LINEAR INTEGRATED CIRCUITS LAB

The broad objective of this lab is to give the students taking the course EL-202/EE-313 some
hands-on experience in designing signal processing circuits using general purpose Linear and
timer ICs

The specific objectives set for this lab are given below

1.0. To characterize the IC Op-amp-µA 741

1.1. To design and implement the following types of amplifiers using µA 741

a. Inverting

b. Non-inverting

c. Buffer

2. To design and implement, following Circuits using µA 741,

a. Integrator

b. Differentiator

3. To design and implement an Astable multi vibrator using µA 741.

4. To design and implement a Log/Antilog amplifier using µA 741.

5. To design and implement a Schmitt Trigger using µA 741.

6. To design and implement a Triangular/Square wave generator using µA 741.

7. To design and implement, following circuits using 555 timer IC.

a. Astable multi vibrator

b. Monostable multi vibrator

8. To design and implement a WBO (Wien Bridge Oscillator) using µA 741.

9. To design and implement a Second order Low pass filter.

10. To design and implement a Second order High pass filter.

11. To design and implement a GIC (Generalized impedance converter) based 2 nd order
band pass filter using µA 741.
 Voltage Operational Amplifiers (popularly pronounced as op amps) are among the most
commonly used components in any instrumentation, communication and process control systems.
They can be used to perform many kinds of signal processing functions namely amplifications,
addition, subtraction, integration, differentiation, filtering, generation of sinusoidal and non-
sinusoidal signal generation.

The most popular IC operational amplifier used for processing dc or low frequency ac signals
(output of most of the transducers fall under these categories) is uA 741. This IC was originally
patented by Fairchild semiconductors in the name of David Fullgar. Many different IC
manufacturers (National Semiconductors (LM prefix), Analog Devices (AD/OP prefix), Texas
Instruments (TI prefix), Fairchild (ua prefix), etc.) manufacture this IC. The industry standard for
IC 741 is a 8-pin DIP IC pack. It is also available in ‘metal can’) package also. The pin
configuration for this IC is shown below in Fig. 1

This IC is very versatile and though it has some major limitations, it is still dominating the low-
frequency non-critical signal processing market.

Fig. 1 Pin-configuration of 741

This IC is an implementation of a very high gain DC amplifier in which the input is a differential stage.
to ensure that the unwanted common-mode signals are rejected at the input stage. The bulk of the gain of
the amplifier is derived from a common-emitter stage which is loaded by a current–source load. It has an
elaborate arrangement for short-circuit protection. The output stage is designed to drive very high load
currents in the range of tens of mAs. A schematic representation of the internal architecture of uA 741 is
given in Fig. 2. The open loop transfer characteristic is given in Fig. 3.
 Fig. 2 Schematic representation of architecture of 741

Fig. 3 Transfer characteristics of 741

Internal frequency compensation has been employed to guarantee stable operation under close-loop
conditions. The internal frequency compensation introduces a dominant-pole around 5Hz in the open-
loop frequency response. The open-loop frequency response of IC-741 is shown below in Fig. 3

Fig. 4 Frequency response of the open-loop gain A 0 of 741

Op - amp characteristics
An ideal op-amp is supposed to have infinite gain, should not draw any current from the
driving sources as well as biasing power supply and its response is also independent of
temperature. However, are al op-amp does not work this way . Its open-loop gain is very high but
not infinite! Still worse, it is frequency-dependent!! Current is taken from the source into op-amp
inputs. Also the two inputs respond differently to current and voltage due to mismatch in
transistors. A real op-amp also shifts its operation with temperature. These non-ideal characteristics
are summarized below:

Input bias current

The op-amp’s input is a differential amplifier, which may be made of.BJT or FET. In either
case the input transistors must be biased into this linear region by supplying currents into the bases.
In an ideal op-amp, no current is drawn from the input terminals. However, practically, input
terminals conduct a small value of dc current to bias the input transistors when base currents flow
through external resistances, they produce a small differential input voltage or unbalance; this
represents a false input signal. When amplified, this small input unbalance produces an offset in the
output voltage.
The input bias current shown on data sheets is the average value of base currents entering into
the terminals of an op-amp. For741, the bias current is500nA or less. The smaller the input bias
current, the smaller the offset at the output voltage.

Input offset current

The input offset current is the difference between the two input currents driven from a common source.
+ -
|IOS|=IB +IB (1-2-17)

It tells you how much larger one current is than the other. Bias current compensation will work if both
+ -
bias currents IB and IB are equal. So, the smaller the input off set current the better the OP amp . The
741 op-amps have input offset current in the range of tens of nA.

Input offset voltage

Ideally, the output voltage should be zero when the voltage between the inverting and non-
inverting inputs is zero. In reality, the output voltage may not be zero with zero input voltage. This is
due to un-avoidable imbalances, mismatches, tolerances, and so on inside the op-amp. In order to
make the output voltage zero, we have to apply a small voltage at the input terminals to make output
voltage zero. This voltage is called input offset voltage .i.e., input offset voltage is the voltage required
to be applied at the input for making output voltage to zero volts. The 741 op-amp has input offset
voltage of 5mV under no signal conditions. Therefore, we may have to apply a differential input of
5mV, to produce an output voltage of exactly zero.
 Thermal drift
Bias current, offset current and offset voltage change with temperature. A circuit carefully
o o
mulled at 25 C may not remain so when the temperature rises to 35 C .This is called drift often, offset
o o
current drift is expressed in n A/ C and offset voltage drift in mV/ C. These indicate the changeis
offset for each degree Celsius change in temperature .There are very few techniques that can be used
to minimize the effect of drift.
Slew rate
Among all specifications affecting the ac operation of the op-amp, slew rate is the most
important because it places a severe limit on a large signals operation. Slew rate is defined as the
maximum rate at which the output voltage can change. The 741 op-amp has a typical slew rate of
0.5volts per microsecond (V/s). This is the ultimate speed of a typical 741; its output voltage can
change no faster than 0.5V/s. If we drive a 741 with large step input, it takes 20s (0.5 V/sX10V)
for the output voltage to change from 0 to 10V.

Full power Bandwidth

Slew rate distortion of a sine wave starts at a point where the initial slope of the sine wave
equals the slew rate of the op-amp. The maximum frequency at which the op-amp can be operated
without distortion is
SR
f max= (1-2-18)
2 πV p

Where SR= slew rate of op-amp, VP=peak voltage of output sine wave. As an example, if the output sine
wave has a peak voltage of 10V and the op-amp slew rate is 0.5V/µs, the maximum frequency for large
signal operation at which the amplifier starts slewing, know as full power bandwidth is given by
6
SR 0.5 ×10
f max= = ≅8 KHz.
2 π V pXk 2 π ×10 ×1

Characteristics of IC-OPAMP

Name of the parameter Ideal value Real value

Open- loop gain ∞ 2X 105 (100-120 dB)

Input impedance ∞ 3-5MΩ

Output impedance 0 50-75Ω

 Unity gain bandwidth ∞ 1MHz

3-db bandwidth of the open-loop gain ∞ 5 Hz (Typical)

Slew rate ∞ 0.5 V/us

Input offset voltage 0 5-10mV

Input bias current 0 50-100nA (max. 500nA)

Input offset current 0 10-20nA

Common-mode rejection ratio ∞ 100-120dB

OP amp applications: Operational amplifiers find numerous use in, electronics, instrumentation,
communication and process control. The most commonly found applications use some of the following
circuits realized with op amps.

A: Op-Amp operating in Linear region

(i) Scale changer (Inverting/Non-inverting amplifier configuration

(ii) Voltage Buffer

(iii) Difference amplifier/Instrumentation Amplifier

(iii) Inverting-Integrator/Differentiator

(iv) RC active filters

(v) Logrithmic /exponential converter

(vi) Immittace simulators

B: Op-amp operating in non-linear mode

(i) Zero-crossing detector

(ii) Multi vibrator ( Bi stable/ Mono stable /As table)

(iii) Triangular wave generator/ Saw tooth wave generator

 EXPERIMENT 1.0
AIM: To measure the input bias current, input offset current, input offset voltage, input and
output voltage ranges, the slew rate and band width of op–amp.

INSTRUMENTS AND COMPONENTS TO BE USED

1. DC Power supply (0 -30 V, 5A dual mode power supply)
2. Dual channel DSO
3. Function generator
4. IC -741
5. Resistors (1/4 watts of suitable values such that ratio of 1, 5 and 10 can be realized)
6. Bread board
7. Connecting wires
The power supply arrangement for biasing the op amp in all the experiments where 741 is to be used is
shown below. Unless otherwise stated, use the voltage of ±15V for biasing.

Fig.1. 0. 1
1. Input bias current and input offset current

Fig1. 0. 2Inputbiasandinputoffsetcurrent

1. Connect the circuit of figure 1. 0 .2.

2. Using a DMM, measure the dc voltage at the (-) terminal & record the values in Table1-2-1.
+ -
3. By ohm’ slaw, calculate the input currents; IB and IB . Average these values to find out the
input Bias current. Also, find the difference between these two currents to know the input
 Offset current. Record these values in Table 1-2-1.
Table1. 0.1
DC voltage at the DC voltage at Input bias Input offset
+¿
V
non-inverting the inverting +¿= ¿¿
220 K
IB −¿=
V
−¿
¿¿ Current Current
220 K
terminal terminal IB
¿

V+ V-
+¿+I B
IB I OS=¿
I B= ¿
2

2. Input off set voltage

1 Connect the circuit of Figure1. 0. 3
2 Measure the DC output voltage at pin 6using multi meter and record the result inTable2.
3Calculatethe input offset voltage using the formula, Vi (offset) = V out / 1000 and record the
value in table 1. 0. 2

Fig1. 0. 3Inputoffsetvoltage

Table 1.0.2

Vout = ¿)Vi Vi(offset)

2. Slew rate
1. Connect the circuit of Figure1-0-4
2. Using an AFO, provide a 1V peak to peak square wave with a frequency of 25 KHz.
3. With an oscilloscope, observe the output of OPAMP. Adjust the oscilloscope timing the
get a couple of cycles.
 4. Measure the voltage change V and time change T of the output wave form. Record the
results in Table 1. 0. 3.
5. Calculate the slew rate using the formula SR=∆V/∆T

Fig1-0-4 Slew rate

Table 1-2-3

∆V ∆T SR=∆V/∆T BW

Quiz Questions
Check your understanding by answering these questions
1. The input stage of a 741 op-amp is a ---------------
2. The output stage of a 741 op-amp is a --------------
3. The input bias current of an op-amp is the---------------------of the two input base currents under
no-signal condition.
4. The input ----------------- current is the difference of the two input base currents.
5. The input----------------voltage is the differential input voltage needed to null or zero the
quiescent output voltage.
6. The CMRR of an op-amp is the ratio of ------------- voltage gain to ----------
voltagegain.7.A 741 has a slewrate of ------------- V/µs.
8. The band width is the-----------------undistorted frequency out of an op-amp It depends on the-
----------- rate of the op-amp and the ---------------------- of the output signal.
9. Identify the type of input mode for each op-amp in fig
 EXPERIMENT NO. 1.1

AIM:- To design and implement the following types of amplifiers using IC 741
a. Inverting
b. Non-inverting
c. Voltage follower

INSTRUMENTS AND COMPONENTS TO BE USED

1. DC Power supply (0 -30 V, 5A dual mode power supply)

2. Dual channel DSO
3. Function generator
4. IC -741
5. Resistors (1/4 watts of suitable values such that ratio of 1, 5 and 10 can be realized)
6. Bread board
7. Connecting wires

A. Inverting amplifier:
An inverting amplifier realization is given below in fig. 1.1 The gain of this amplifier (assuming
ideal behavior of IC 741) is given by

Fig.1.1 Inverting Amplifier

The gain of this amplifier (assuming ideal behavior of IC 741) is given by

Vo Rf
A= =−
Vi Ri
PROCEDURE:-

1. On a bread-board make a neat circuit of the inverting amplifier as shown in fig. 1.1.
2. Use dual power supply to make available a voltage of ±13V fig. 1.2). This choice is not
unique!! You can bias the amplifier with lower / higher or even unsymmetrical voltages.
The maximum value will depend upon the rating of the IC, where as the minimum will be
dictated by the signal swing required. If you bias the IC with unsymmetrical bias voltages
(unequal values of positive and negative bias voltages), then the maximum signal swing
available in positive and negative directions will be different. If you don’t believe this try
out the second and the last variation.

FIG. 1.2 Power Supply for IC 741

3. After biasing the IC 741 (+V cc to Pin-7 and -Vcc to Pin-4), connect the input to Pin-2
through the resistor R1 . You should try out for the following inputs.
(i) Triangular wave with a p-p amplitude of 200mV at 1 KHz frequency.
(ii) Square wave with a p-p amplitude of 200mv at 1 KHz frequency.
(iii) Sinusoidal wave with p-p amplitude of 200mv at 1 KHz frequency.
4. Observe the transfer characteristic of the circuit (V o - Vi ) on the dual channel
oscilloscope. The transfer characteristics will be observed in the X-Y mode of operation
of the DSO. Calculate the slope of the transfer characteristic (It is given by the gain
expression). Verify the results for all the three values of the gain realized (-1, -5, -10).
Save the trace in your removable disc.
5. Now to study the behavior of the inverting amplifier when a sinusoidal input of 1 V( p-p)
amplitude is applied and Rf /R1 is 1 :
(i) operate the DSO in y-t mode (In this mode the output sis displayed as a function of
time).
(ii) Change the frequency of the input sinusoidal signal using the function generator and
note down the corresponding output sinusoidal voltage amplitude starting from a
 frequency of 10 Hz. Note down the frequency where you start observing
distortion in the output sinusoid (try to observe the nature of the distortion!!).
Continue the variation up to a frequency where the output magnitude has become
indistinguishable from noise. (you should take at least 20 observations to plot the
frequency response).
6. Plot the magnitude frequency response and there from calculate the 3-dB frequency of the
amplifier.

Theoretically the 3-dB frequency should be approximately equal to 1MHz because your
amplifier is being operated in the unity gain mode and the GBP (Gain bandwidth product
of IC-741 is nearly 1MHz).

7. Comment on (i) the type of distortion observed at high frequency and the reasons for the
same. (ii) reasons for discrepancy (if any) in the experimentally observed value of 3-dB
frequency and the theoretical value of 1 MHz.

B). Non-inverting amplifier:

Gain of this amplifier (assuming ideal behavior of IC 741) is given by

Procedure:
1. On a bread-board make a neat circuit of the non-inverting amplifier as shown in fig. 1.4

Fig. 1.3 Non-Inverting Amplifier

2. Repeat part 2-7 for the non-inverting amplifier circuit also (in part 4, choose the values of
R1 and Rf such that a gain of, 2, 6 and 11 are realized).
C). Voltage follower:
A voltage follower is a unity gain non-inverting amplifier. Its main use in instrumentation system
is to avoid loading of the signal source by the amplifier (How it is done??)

1. On a bread-board make a neat circuit of the buffer amplifier as shown in fig.1. 4

2. Repeat part 2-7 for the buffer also (You do not have to use R i and Rf as the gain required
is 1 and because of the virtual short appearing between non-inverting and inverting
terminal as there is a negative feedback between output and the inverting input) output
simply follows the input.

Fig. 1.4 Voltage Follower

Precautions:

1. Never apply the input signal before biasing the IC.

2. Place the components neatly on the bread-board.
3. Do not make criss-cross connections across the DIP IC.
4. All voltages must be measured w. r. t the common ground of the circuit. (This is the
common point of the dual power supply).

Observation table for single frequency measurement at (1 KHz)

Mode Vi Vo Gain

Inverting

Non-inverting

Voltage follower

Observation table for the frequency response

 Frequency Vi (p-p) Vo (p-p) Gain

10 Hz

Quiz Questions:

1. How is the virtual ground different from actual ground?

2. What will happen if in the circuit of fig. 1 connections at Pin-2 and Pin-3 were to be
interchanged?
3. Which of the two configurations (Inverting/Non-inverting) has higher input impedance?
4. How does the voltage follower avoid loading of the signal source?
5. How does the slew rate of IC 741 affect the performance of the realized amplifiers in
terms of input amplitude and frequency?

Computer Problems:
Use PSPICE simulations to test the operations of the circuits which you have implemented.

EXPERIMENT NO. 2
AIM:- To design and implement using IC 741
1) Integrator
2) Differentiator

INSTRUMENTS AND COMPONENTS TO BE USED

1. IC-741 op-amp.
2. Resistances (1k ,10k) and (470Ω , 20k).
3. Capacitor (10nf).
4. Signal generator with variable frequency.
5. DSO.
6. Bread board.
7. DC power supply (±15v)

IDEAL INTEGRATOR :
By placing a capacitor in the feedback path (in place of the resistor of the inverting amplifier
circuit given in fig. 1.1) we obtain the circuit fig.2.1.

Fig. 2.1 Ideal Integrator

Let the input be a time-varying function V i (t). The virtual ground at the inverting op-amp input
causes Vi (t) to appear in effect across R, and the input current will be V 1(t)/R. This current flows
through the capacitor C, (because the amplifier being ideal it can’t go into it, ?? ) causing charge
to accumulate on C.
If we assume that the circuit begins operation at time t = 0 then at an arbitrary time t if the initial
voltage on C is denoted Vc then
t
v c=V c +∫ I i dt
0
Now the output voltage V0(t) = -Vc(t) ,thus
 t
1
V 0 (t )=− ∫ v i(t ) dt−V c
CR 0
Vo 1
( s )=−
V
which results in the following transfer function i RCs

Thus it is obvious that the integrator behaves as a low pass filter with a corner frequency at zero.
Observe that at ω=0 (for s=jω), the magnitude of the integrator transfer function is infinite. This
should also be obvious from the integrator circuit itself. Reference to fig.2.1 shows that the
feedback element is a capacitor, and thus at dc where the capacitor behaves as an open circuit
there is no negative feedback. This is a very significant observation and one that indicates a
source of problem with the integrator circuit. Any tiny dc component in input signal will
theoretically produce an infinite output. Of course no infinite output voltage results in
practice.

Design:
From the time domain relation given in equation it is seen that if we apply a square wave input to
the integrator we should get a triangular wave form as output. To obtain a perfect triangular wave
output the following points must be taken into consideration.

(i) The RC time constant of the integrator must be very small compared to the time period of
the input waveform. The ratio should be not less than 10. Higher this ratio is, better will
be the triangular waveform to look at (Thumb rule)!!
(ii) The input amplitude and the frequency should be selected in such a way that the output
should not saturate.

If R= 2 KΩ and C= 10nF then RC= 0.02 ms. Thus with these values the time period of the square
wave to be integrated should be at least 0.2 ms.
PROCEDURE:-
1.On a bread-board make a neat circuit as shown in fig.2.1.
2. Use dual power supply to make available a voltage of ±15V (refer to fig. 1.2). This choice
is not unique!! You can bias the amplifier with lower / higher or even unsymmetrical
voltages. The maximum value will depend upon the rating of the IC, where as the
minimum will be dictated by the input amplitude and the frequency of the input so that
output signal does not get clipped.
3. After biasing the IC 741 (+15Vto Pin-7 and -15Vto Pin-4), connect the input (square wave
with a p-p amplitude of 500mv at 1 KHz (time period = 1ms) frequency to pin-2 through
the resistor R.
 4. Observe the output wave form of integrator on the dual channel oscilloscope (operating in
y-t mode). Save the trace in your removable disc. The output waveform (taken at pin-6
of IC 741) should resemble the following waveforms.
500mV

0V

-500mV
V(1)
20V

10V

0V

-10V

SEL>>
-20V
0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms 11ms 12ms 13ms 14ms 15ms 16ms
V(3)
Time

Fig. 2.2

RESULT AND DISCUSSIONS:-

Integrators are very useful building blocks in Instrumentation and control systems. Since the
above design has been carried out assuming that IC-741 behaves ideally (Particularly w. r. t its
open loop gain), the design has been tested at low frequency only. The design of integrator
should be carried out keeping in mind the intended frequency of operation (Since the amplifier
does not behave ideally at all the frequencies).

In report mention at least three abnormal behavior of this circuit ( you make the circuit behave
abnormally) and suggest remedial measures to make the circuit behave normally.

Afterthought:
Let us consider the step response of a RC network shown below.

The step response is given by (1 – e-t/RC ). If we expand the exponential term in an infinite series
under the assumption that RC product is very large then the step response can be approximated
by a linear expression as follows: V 0(t) = t/RC( the higher order terms in the exponential term
expansion have been neglected. if RC value is much higher then this circuit behaves as closer to
an Integrator circuit, i.e, for step input output appears to be close to a ramp which may be called
as integral of the step. Now for making RC product very large, either R or C value should be very
high. If value of R is much higher then the connect between input and output is lost and the
circuit behaves like an open circuit. Real capacitor cannot be infinitely large. To realize very high
capacitance value, an active devices such as an OP-AMP as in the circuit of figure 2.1.is used. If
we use Miller’s theorem to find out the effective capacitance at the input of the opamp then this
value becomes very large(the value C gets multiplied by the open loop gain of the opamp). This
is the reason that the integrator circuit given in Fig. 2.1 i also known as Miller’s integrator

LOSSY INTEGRATOR:

The problem of infinite or very high dc gain of the integrator is solved by connecting a resistor R f
in parallel with the integrator capacitor, as shown in fig.2.3.

Fig. 2.3 Lossy Integrator

The transfer function of the circuit is given by
1
Vo R1 C f
( s )=−
( )
Vi 1
s+
Rf Cf
 1
R C
From this equation it is clear that for frequencies much higher than f f the circuit behaves like
the ideal integrator circuit of Fig. 2.1. The addition of the additional feedback resistor is thus seen to limit
the lowest frequency input which will be integrated satisfactorily. It is also observed from the ideal
integrator transfer function that there is a pole at origin whereas the lossy integrator has a non-origin pole.

PROCEDURE:
1. Re-breadboard the circuit given below in Fig. 2.3.
2.Use dual power supply to make available a voltage of ±15V (refer to fig. 1.2).
3. Select R1= 2 KΩ, Cf = 10 Nf and Rf = 10 KΩ. (This gives a pole frequency at 15.9 KHz).
4. Apply a sinusoidal input of 500Mv (p-p) and perform a frequency response test (you have
not forgotten to conduct a frequency response test. For a quick reminder, apply a constant
amplitude- 500Mv varying frequency- 10Hz-500kHz in this case, and note down the
corresponding output amplitude at all the frequencies). Phase will have to be determined
with the help of Lissajious pattern obtained at each frequency to be observed on the DSO
in the X-Y mode of display.
Observation table for frequency response

Frequency Vi (p-p) Vo (p-p) Gain Phase

10 Hz

5. Now apply a square wave input 500mV (p-p) and vary its frequency starting from 10 Hz.
Observe the output of the circuit in the y-t mode of operation of DSO and note down the
frequency at which you get a triangular waveform. Try to relate this frequency with the
pole frequency of the lossy integrator.

RESULT AND DISCUSSIONS:-

Justify the name lossy integrator given to the circuit of Fig. 2.3. Try to correlate the behavior of
a low pass filter with that of an integrator.

DIFFERENTIATOR:-
Interchanging the location of the capacitor and the resistor of the integrator circuit result in the
circuit fig.2.3 gives the circuit of the differentiator as shown in Fig. 2.4
 FIG.2.4. Differentiator

Let the input be the time-varying function vi(t) and note that the virtual ground at the inverting
input terminal of the op-amp causes vi(t) to appear in effect across the capacitor C .thus the
current through C will be C(dvi/dt) ,and this current flows through the feedback resistor R
providing at the op-amp output a voltage v0((t),
dv (t )
v 0 (t )=−CR i
dt

the frequency response of the differentiator can be thought of as that of an high-pass filter with a
corner frequency at infinity.
PROCEDURE:-
1. Breadboard the circuit shown in Fig. 2.4 with the same component values as chosen in the
ideal integrator design (R = 2KΩ, C = 10nf).
2.Use dual power supply to make available a voltage of ±15V (refer to fig. 1.2).
3. Apply an input triangular wave of 500mV (p-p) amplitude at a frequency of 1KHz and
observe the output on the DSO in the y-t mode and save the output trace in your
removable disc.

We will not conduct the frequency response test on the differentiator as differentiators are not
used in instrumentation systems because of very high gain at high frequency (as noise signals
also get amplified).
 600mV

400mV

200mV

0V

-200mV

-400mV

-600mV
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
V(1) V(6)
Time

PRECAUTIONS:-

1. Test the components (active as well as passive) before bread boarding.

2. Carry out the design calculations before selecting the component values. The typical
values selected for implementations are exemplary. You may not get the desired value
components thus based upon the design criteria select alternative values.
3. Never apply input signal to the IC before biasing.

Quiz Questions :

1. What are the non-idealities associated with IC-741?

2. How do these non-idealities affect the performance of the realized integrator?
3. It is claimed that IC 741 can act as an integrator without using external capacitor? Do you
agree with this statement? Justify your answer in terms of the integrator model of IC 741
 EXPERIMENT NO. 3
AIM:-To design and implement a square wave generator using IC-741 (as table multi vibrator).

INSTRUMENTS AND COMPONENTS TO BE USED

1) dc supply.
2) DSO.
3) IC-741
4) Bread board
5) Resistors and capacitors.

Multi-vibrators are timing circuits used for generating various types of pulses of controlled
duration (periodic / non-periodic). Astable multi-vibrators are circuit used in pulse systems. IC
operational amplifiers can be used to implement various types of multi-vibrators. In the astable
multi vibrator the op-amp runs from one quasi stable to another on its own (without requiring any
external trigger). The output is a square wave whose frequency depends upon R and C. Feedback
resistors R1 and R2 serve for regenerative comparison. Output of op-amp is limited by saturation
levels of op-amp (±Vsat). Time period of wave is-

1 1
R2 ≈1 .164 R 1 , f = =
; for T 2 RC
DESIGN:
To design a square wave generator with 1.5 KHz output frequency select R 1 = 10 KΩ. To
simplify the design choose R2 = 1.164R1; This gives the value of R2 as 11.64 KΩ. (This value can
be realized with a potentiometer of 10 KΩ in series with a fixed resistance of 4.7 KΩ). Choose
C= 10 nf which gives a value of 33 KΩ for R.

PROCEDURE :-

1. Breadboard the circuit shown below in fig. 3.1.

2. Use dual power supply to make available a voltage of ±15 V (refer to fig. 1.2) and bias the
IC 741 with it.
3. Observe output waveform (pin -6 )and voltage waveform across the capacitor (pin -2)
simultaneously using DSO and save these waveforms in your removable drive.
4. Note down the time period and amplitude of the square wave.
5.For a given design frequency, note down the effect of change in the bias voltage,by
changing the bias voltage in steps of ±1V between ±15V to ±5V.Comment on the error ,it
any,between the designed frequency and the experimentally observed frequency.
 FIG.3.1 Astable Multivibrator Using IC 741

RESULT AND DISCUSSIONS:-

Comment on the suitability of IC 741 for comparator applications.

COMPUTER ASSIGNEMENT:
Simulate the astable multivibrator circuit using some other IC operational amplifier (LM 111).

QUIZ QUESTIONS :
(i) What is the duty cycle of the output waveform?
(ii) List out the differences between a comparator and an op-amp.
(iii) What is the principle of operation of a zero crossing detector?
(iv) What is saturation in an op-amp?
(v) Why is a square wave generator called an astable multivibrator?
(vi) What parameters determine the frequency of a square wave?
(vi) How can the circuit given in Fig. 3.1 be modified to have an output waveform with a
duty cycle of 10 percent and 70 percent?

PRECAUTIONS:-
List out the things which helped you in getting the output waveform when you were not getting it
on the DSO (it is very rare that you will get the output in the first instant.

EXPERIMENT NO. 5
AIM :- To design and implement the following types of relaxation oscillators
1) Triangular
2) Rectangular

INSTRUMENTS AND COMPONENTS TO BE USED

1. DC power supply
2. DSO
3. Bread board
4. IC-741 (02)
5. Potentiometer (11.6k in 20k pot)
6. Resistors (5×10k , 1×100k)

Non-sinusoidal oscillators are also referred to as relaxation oscillators. The output waveform in
case of non-sinusoidal oscillators can either be a periodic rectangular/square waveform,
triangular/ saw tooth waveform etc. Operational amplifiers running in the comparator mode are
used to generate non-sinusoidal waveforms.
A triangular/rectangular waveform generator shown below in fig. 4.1 consists of a comparator
and an integrator. The comparator compares the voltage at point P continuously with the
inverting input that is at 0V, when the voltage at P goes slightly below or above 0v, the output of
comparator is at the negative or positive saturation level, respectively.

DESIGN:
The peak to peak output amplitude of the triangular wave is given by
R2
v
0
( p− p )=2 (V )
R3 sat ------- (1)
And frequency of oscillation is given by
R3
f =
0 4 R 1 C 1 R2 ---------- (2)

To design the triangular wave generator for f0=2 KHz and v0 (p-p) = 7 V use equation (1) to
R
R2 = 3
calculate 4 , if R2 = 10 KΩ then R3 = 40 KΩ (use a 47 KΩ potentiometer) now from
equation 2 R1 C 1=0. 5 ms ; if C1=0.05 µF, then R1=10 KΩ.
 FIG. 5.1 Triangular Wave Generator

PROCEDURE:-
1. Breadboard the circuit shown below in fig. 5.1 using the component values obtained from
the design procedure given above.
2. Bias both the op-amps with bias voltages of ±15V (you can bias the amplifier with lower
bias voltage also because the output amplitude required is ±7 V only).
3. Observe the output waveforms available at the output pins of the comparator op-amp and
the integrator op-amp. Save both the outputs on your removable drive. Measure the p-p
amplitude and the frequency of both the waveforms.

Conversion of the triangular waveform generator into a saw tooth waveform generator:

The circuit shown above in Fig. 5.1 can very easily be converted into a saw tooth waveform
generator (a saw tooth waveform is different from a triangular waveform because it has unequal
rise time and fall time whereas a triangular waveform has equal rise time and fall time) if the
non-inverting input terminal of the integrator op-amp is kept at some non-zero potential V ref. The
rise time and fall time of the saw tooth waveform are given by

R1 R1
RC V RC V
t r =2
Rf sat
V sat−V ref
and t f =2
Rf sat
V sat+V ref
k=dutycycle =
tr 1
[
V
= 1+ ref
t r +t f 2 V sat ]
4. To generate a saw tooth waveform with k= 0.25 apply a suitable value of V ref (obtained
from the above equations). For obtaining a saw tooth waveform with k=0.25, if Vsat =
14 V , Vref = 7V.
The reference voltage can be applied with the help of a separate power supply.
5. Observe the saw tooth output on the output terminal (pin-6) of the integrator opamp. Save
the output in your removable drive and note down the values of tr, tf and calculate the
value of k there from.
 R1 Rf R C Vref Vsat tr tf

Triangular

Square

Saw tooth

Assignment:

1. Derive all the design equations used in this experiment

2. Study the performance of the circuits using PSPICE simulations. (Use other IC opamps
(LM 111) to simulate the triangular and square wave generators.

3. Study the effect of variation of Vref on the output of the comparator opamp.
 EXPERIMENT NO. 6

AIM :- To design and implement a Wein Bridge Oscillator (WBO).

INSTRUMENTS AND COMPONENTS TO BE USED

1. DC power supply (±13v)

2. DSO
3. IC-741 op-amp
4. Bread board
5. Resistors
6. Capacitor

One of the most commonly used audio frequency oscillators is the WBO (Wien bridge
Oscillator). The circuit is shown in fig.5.1

FIG. 6.1 Wein Bridge Oscillator

The bridge is embedded in an amplifier whose gain is determined by R1 and Rf, and has a series
RC network in one arm and a parallel RC network in the adjoining arm. The feedback signal in
this circuit is connected to (+) terminal so that op-amp works as a non-inverting amplifier. The
network will have oscillations with the frequency given by
 1
f o=
2 π √ R 2 R3 C 1 C 2 6.1

under the condition,

( )
1+
Rf

R1
=3. 6.2
if R2 = R3 and C1= C2.

DESIGN:-
Choose the value of Rf and R1 such that Rf / R1 is slightly more than 2 ( according to the

condition of oscillation
( )
1+
Rf

R
1 =3). But to start oscillations this ratio must be brought to 2

from a higher value (why ?). To generate an audio frequency sinusoidal output the values of R 2,
R3, C1 and C2 are selected using equation 6.1. If the desired frequency is 1.59 KHz and we
choose C1=C2 1nF then we can select R2 = R3 = 100KΩ. To satisfy the condition of oscillation
(equation 5.2) any one of the two resistors (R1 and Rf) should be taken as a variable resistor (Pot
of suitable range) while the other resistor can be the usual ¼ watt, carbon resistor. If we select
R1 = 10KΩ, then Rf should be implemented with a 47 KΩ Pot in series with a fixed resistance
of 100Ω (This will ensure that you are able to get a sinusoidal output with very little distortion.

PROCEDURE :-

1. On a bread-board make a neat circuit of the Wein bridge oscillator as shown in fig. 6.1
2. Bias the IC 741 (pin4 with -15V and pin7 with +15Vobtained from the dual power supply.
By now you must have remembered the power supply connections!!).
3. Since oscillators are autonomous circuits (they do not require any external input other than
the power supply) no external input is applied to the circuit. You may not observe any
output at the pin 6 of IC 741. Change the value of R f by adjusting the Pot (the direction of
change will depend upon initial value of the variable position of the Pot) till you start
getting any output. At this stage do not expect a sinusoidal output. You should expect a
distorted sinusoidal waveform (clipped) or square wave. This indicates that the poles of
the circuit are in the right half of the s-plane, and they need to be brought to the imaginary
axis of the s-plane. Continue the Pot variation till you obtain a nearly sinusoidal wave
form. At this point if you further vary the pot in the same direction then the oscillations
may start decaying indicating the movement of the poles in the left half of the s-plane
(damped oscillations).
4. Note down the frequency of the sinusoidal output and also note down the amplitude of the
waveform. Save the output wave form on your removable drive. Note down the value of
 the Pot resistance including the 100Ω resistance in series with the pot as suggested by the
design procedure (Is it satisfying the equation 6.2?)
5. To change the frequency of the output sinusoidal signal the values of C 1 and/or C2 may be
changed. Alternatively R2 and/or R3 may be changed. Obtain another sinusoidal
waveform with a different frequency. Note down the amplitude and the value of pot
resistance.

OBSERVATION TABLE

S.NO. R2 R3 C1 C2 R1 Pot Amplitud Frequency

e

1.

2.

RESULTS AND DISCUSSION:-

Wein bridge oscillator is a classical audio frequency oscillator which can be implemented very
easily with the help of a adjustable gain voltage amplifier. In the implementation used in this
experiment no external adjustment has been provided for the amplitude control of the sinusoidal
output. The amplitude of the output is limited by the saturation characteristics of the op-amp.

Quiz Questions :

(i) What happened if we choose values of R1 and Rf such that the gain is exactly equal 3.
(ii) Draw two circuits for the amplitude control of the sinusoidal output.
(iii) Once the output oscillations have stabilized (it means that R f /R1 =2) if we change the value
of C1 and /C2 sinusoidal output at a different frequency should appear in the circuit; no
further adjustment of the Pot should be required. Does this happen? Report this with
reference to step 5 of the experimental procedure.
(iv) What are the limitations of the classical Wein bridge oscillator ?
 EXPERIMENT NO. 7
AIM :- To design and implement a Schmitt trigger with inverting and non-inverting transfer
characteristics using IC-741

INSTRUMENTS AND COMPONENTS TO BE USED

1. IC-741 op-amp
2. DC Power supply
3. DSO
4. Bread board
5. Resistors (1/4 watts of suitable values)

A Schmitt trigger circuit compares a regular or irregular waveform with reference signal and
coverts the waveform to a square or pulse wave. A Schmitt trigger is often known as a squaring
circuit also. It is also known as a bistable multivibrator, because it has two stable states, low and
high (by stable states we mean possible value of the output of the circuit). It can remain in one
state indefinitely; it moves to the other stable state only when a triggering signal is applied.
Schmitt triggers can be classified into two types depending on the type of op-amp configuration
used: inverting or no inverting.

FIG. 7.1 Schmitt Trigger (INVERTING MODE)

If an input voltage (time varying) is applied to inverting input terminal the out voltage changes
its level (from +Vsat to -Vsat or -Vsat to +Vsat)the instant input voltage Vin exceeds every time a
certain voltage level. These voltage levels are calledVUT and VLT. Suppose output Vo = ±Vsat, then
voltage at (+) input terminal can be obtained as -
 ( )( )
V ref . R 1 V sat R2
V UT = +
R1+ R 2 R1 + R2

)( )
V sat . R
(
V ref . R1 2
V LT = −
R2+ R 1 R1+ R 2
Similarly,

These are called upper and lower threshold voltages.

Hysteresis width
V h =V UT −V LT
If Vref = 0, then VUT = - VLT
The most important application of Schmitt trigger is to convert a very slowly varying signal into
a square wave.

PROCEDURE :-
1.On a bread-board make a neat circuit of the schmit trigger as shown in fig.7. 1.
2. Use dual power supply to make available a voltage of ±8V. This choice is not unique!! You
can bias the amplifier with lower / higher or even unsymmetrical voltages.
3. After biasing the IC 741 (+Vcc to Pin-7 and -Vcc to Pin-4), connect the following input to pin-2
(i) Sinusoidal wave with 10Hz frequency (amplitude = 4V)
(ii) Triangular wave with 10Hz frequency (amplitude = 4V)
4. Select R1 = 20 KΩ and R2 = 10 KΩ and Vref = 0V so that
10
|V UT|=|V LT|=V sat ≈2. 66 V
30
5. Observe the output waveform (pin-6) and the input waveform (pin-2) on the DSO in y-t mode.
Apply both the inputs in turn and measure the values of V UT and VLT. As is evident from the
expression for these threshold voltages they are independent of the type and amplitude of
input, you should obtain same values for VUT and VLT for both the inputs.
6. Operate the DSO in XY mode and observe the hysteresis loop and measure the width of the
hysteresis loop. Save the transfer characteristics in your removable disc.
7. Select a different set of R1 and R2 and repeat step 5-6 and complete the table 6.1

Table 6.1

R1 R2 Vref VUT VLT Vh Input waveform

Type Amplitude Frequency

Schmitt trigger with non-inverting transfer characteristics :
The bistable multivibrator shown below in fig. 6.2 has non-inverting transfer characteristics (with
increasing value of input whenever the output level changes the change is from -Vsat to +Vsat .

( )
V sat R2
|V UT|=|V LT|=
R1
The expression for the threshold voltages is given by

FIG. 7.2 Schmitt Trigger (NONINVERTING MODE)

PROCEDURE:-
1.On a bread-board make a neat circuit of the schmit trigger as shown in fig. 6. 2
2. Use dual power supply to make available a voltage of ±8V. This choice is not unique!!
You can bias the amplifier with lower / higher or even unsymmetrical voltages.
3. After biasing the IC 741 (+Vcc to Pin-7 and -Vcc to Pin-4), connect the following input to
pin 2:
(i) Sinusoidal wave with 10Hz frequency (amplitude = 5V)
(ii) Triangular wave with 10Hz frequency (amplitude = 5V)
4. Select R1 = 20 KΩ and R2 = 10 KΩ so that
10
|V UT|=|V LT|=V sat ≈4 V
20
5. Observe the output waveform (pin-6) and the input waveform (pin-2) on the DSO in y-t
mode. Apply both the inputs in turn and measure the values of V UT and VLT. As is evident
from the expression for these threshold voltages they are independent of the type and
amplitude of input, you should obtain same values for VUT and VLT for both the inputs.
6. Operate the DSO in XY mode and observe the hysteresis loop and measure the width of
the hysteresis loop. Save the transfer characteristics in your removable disc.
7. Select a different set of R1 and R2 and repeat step 5-6 and complete the table 6.2
Table 6.2

R1 R2 Vref VUT VLT Vh Input waveform

 Type Amplitud Frequency
e

RESULTS AND DISCUSSION:- In comparator type amplifiers the state change should ideally
be instantaneous. Does this happen in the case of IC 741? Discuss the suitability of IC 741 for
comparator type application? Discuss the possible reasons for observing unequal values for upper
threshold and lower threshold voltages.

Quiz questions:

(i) Can a Schmitt trigger be called a zero crossing detector?

(ii) List out some popular ICs which are used in comparator type applications.
(iii) List out some possible use of a Schmitt trigger.
(iv) What is the difference between the transfer characteristics of a non-inverting Schmitt
trigger and an inverting Schmitt trigger?
 EXPERIMENT NO. 8

AIM :- To design and implement, using IC 555

a. (i) Astable multivibrator with a duty cycle > 50%.

(ii) Astable multivibrator with a 0 < duty cycle ≤ 100%.
b. Monostable multivibrator.
INSTRUMENTS AND COMPONENTS TO BE USED:-

1. Power supply (0 -30 V , 5A dual mode power supply)

2. Dual channel CRO (TDX 1510)
3.IC -555
4. Resistors
5. Bread board
6. Connecting wires

Square waves are the simplest waveforms to produce. They are used in system control, tone
generation and instrumentation. They can be used to produce both rams as well as sine waves.
IC-555 is an integrated circuit specifically designed to perform signal generation and timing
function.
An astable multivibrator (In this mode of operation output does not remain in any of the two
possible states permanently thus the name Astable!!) can be produced by adding two resistor and
a capacitor to the IC-555 as shown below in fig.8.1.
 Fig.8.1 Astable Multivibrator Using IC 555
A typical output waveform available at the output terminals (pin no.3) is shown below.

TON TOFF

Fig.8.2 Output Waveform

DESIGN PROCEDURE :-
T on=0 . 69 ( R A + R B ) C T off =0 . 69 RB C
, .

Duty cycle of the output waveform generated is given by

T on R A+ RB
% Dutycyle= = ×100
T on+T off R A +2 R B --------- (1)

To generate an output waveform with a free running frequency of 1.45 kHz and on time Ton
=0.421ms and hence Toff = 0.269 ms which gives a duty cycle of 61% , we begin the design by
selecting a capacitor of value 0.1µF and R A=2.2 KΩ. This gives RB=3.9 KΩ to meet
simultaneously the specification on Ton , Toff and duty cycle as given in equation (1) .

PROCEDURE:-

1. Bread board the circuit given in fig. 10.1 with the component values obtained by the design
procedure explained above.
2. Bias the circuit with Vcc =5V (be careful you are biasing IC-555 not IC-741!! IC-555 requires
unipolar (+ve) bias of 5V at pin -8).
3. Observe the output at pin-3 and pin-6 and save them in your removable disk and note down the
values of Ton and Toff there from. Compare these values with the designed values of the same.
 6.0V

5.0V

4.0V

3.0V

2.0V

1.0V

0V

-1.0V
0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms
V(3) V(2)
Time

Fig.8.3 sample output waveform available at pin-6 and pin-3

ASTABLE MULTIVIBRATOR WITH DUTY CYCLE OF 50% OR LESS:

With the circuit configuration shown in fig equation (1) dictates that the duty cycle will never be
less than 50%. A simple modification as shown below in fig.7.4 makes possible the generation of
output waveforms with duty cycle equal to or less than 50%.

FIG. 8.4
PROCEDURE:-

1. Bread board the circuit given in fig.10.3 with the following component values: C= 0.1µF ,
RA=2.2 KΩ , RB=3.9 KΩ and R=20 KΩ.
2. Bias the circuit with Vcc =5V.
3. Observe the output at pin -3.and pin-6 and save them in your removable disk and note
down the values of Ton and Toff . Compare the value of duty cycle with the duty cycle
obtained from the circuit given in fig.10.1. Figure 10.5 gives a sample output wave form
and the capacitor charging and discharging waveforms (pin-6).
6.0V

5.0V

4.0V

3.0V

2.0V

1.0V

0V

-1.0V
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
V(3) V(2)
Time

Fig. 8.5 Sample output Waveform

RESULTS AND DISSCUSION:-

Use the internal diagram of IC-555 to obtain expression Ton , Toffand duty cycle for the circuit
shown in fig. 7.4.

MONOSTABLE MULTIVIBRATOR:

A Monostable multivibrator is often called a one-shot and is mostly used in a pulse generating
circuit in which the duration of the pulse is determined by an external RC network connected to
the timer IC as shown in Fig. 7.6 shown below.
 Fig. 8.6 555-TIMER COPNNECTED AS A MONOSTABLE MULTIVIBRATOR

In a stable or standby state the output the output of the circuit is approximately zero or at logic
low level (what is the range of logic level for CMOS logic ?). When an external trigger pulse is
applied then the output (pin-3) is forced to go high (very near to Vcc). The time the output
remains high is determined by the external RC network. At the end of the timing interval the
output automatically reverts back to its logic low state.

Design:

The time duration (sec) for which the output remains high is given by t p = 1.1 RAC. If a pulse of
duration 10 ms is to be generated and we select RA = 10KΩ, then C= 1 µF.

Procedure:

1. Bread board the circuit given in fig.8.6 with the following component values . values C=
1µF , RA=10 KΩ .
2. Bias the circuit with Vcc =5V.
3. Apply a trigger (use the negative pulse output from the function generator) to pin-2 of IC-555.
4. Observe the output at pin -3.and pin- 6 and save them in your removable disk and note down
the value of the pulse duration. Compare the value of duty cycle with the duty cycle obtained
from the circuit given in fig.8.1. Figure 7.5 gives a sample output wave form and the capacitor
charging and discharging waveforms (pin-6).
 EXPERIMENT NO. 9

AIM :- Implementation of a 2nd order low pass filter

INSTRUMENTS AND COMPONENTS TO BE USED:-

1. IC-741 op-amp
2. CRO
3. Bread board
4. Resistors
5. Capacitors

THEORY:-
Filters are frequency selective circuits used in various signal processing circuits used in
instrumentation, communication and control systems. Active filters reshape the frequency
spectrum of an input signal and can provide gain also (in contrast to passive filters). Based upon
the shape of the magnitude frequency response filters can be characterized into the following
categories :
(i) High pass (infinite attenuation in the stop band (fh), and zero attenuation in the pass
band (>fh)
(ii) Low pass (infinite attenuation in the stop band (>fl )and zero attenuation in the pass
band (<fl))
(iii) Band pass (infinite attenuation in the stop band ( fl1<, >fl2) and zero attenuation in the
pass band (<fl2 , > fl1)
(iv) Band elimination / notch/ (infinite attenuation in the stop band (<fl2 , > fl1) and zero
attenuation in the pass band ( fl1<, >fl2))
(v) All pass (equal magnitude at all the frequencies)

Ideal magnitude frequency response of these filters is of the form of brick walls which can’t be
realized physically. The practical approach is to realize these filters which approximate the brick
wall characteristics. Higher the order of the filter is, more near is its approximation of the brick
wall.
One of the very popular methods of designing higher order filters is to cascade many 1st order
and second order filters to approximate a higher order filter. In the following we implement a
2nd order low pass filter using IC 741.
LOW-PASS FILTER:-
FILTER DESIGN:- A circuit which implements a second order low pass filter is given in Fig.
9.1.

Fig. 9.1 2nd Order low Pass Filter

Kω
o2
Vo ω
= s2+ s o + ω
The transfer function of the circuit is given by Vin Q o2

K=1+
Rf
; ω 2=
1
; Q=
√G1 G2
Where
R1 o R1 R2 C 1 C 2 G 1 +G 2 ( 2−K )
To design a 2nd order low pass filter with a cut-off frequency = 1 KHz , simply follow the
following steps:

1. Let C2=C3=4.7 nF
2. If we choose (for simplicity) R2 = R3 then the expression for the cut-off frequency gives
yields R2=R3=33.8 KΩ (In this expression the unit of frequency is in radians/s, be careful)
3. The value of R1 and Rf will depend upon gain K (which in turn will be decided by the
required value of pole Q of the filter. For a Butterworth type of response the value of Q
should be 0.707 which yields a value of K= 1.586, this gives the following relation between
Rf and R1 :

Rf = 0.586R1
If R1=27 KΩ,therefore Rf=15.82kΩ The required components are thus selected as given above:
R2=R3=33 KΩ, C2=C3=4.7nF
PROCEDURE:
1. Using the procedure described above select the value of the passive components to give
the desired cut-off frequency (ωo) and pole quality factor (Q).
2. Breadboard the circuit for the low pass filter shown in fig. 8.1b.
3. Bias the IC 741 with ±15 V using the dual power supply as shown in fig. 1.2
4. Using the function generator apply a sinusoidal amplitude of 2 V (p-p) and measure the
output amplitude and phase using both the channels of the DSO for frequency in the
range of 10 Hz – 100 KHz (the range will depend upon the value of the designed cut-off
frequency; for a second order filter the gain starts falling at the rate of 40dB per decades
so even with an input of 2V (p-p amplitude) and a DC gain of 1.5 you may not go beyond
two decades of the cut-off frequency). The choice of input amplitude is for convenience,
because with this choice (provided the amplifier can take this amplitude) the amplitude of
the output gives the value of gain directly.
5. To measure the phase difference between the input and output at a given frequency operate
the DSO in X-Y mode and use the Lissajous patterns to calculate the phase difference.
B
Sinθ=
Use the relationship A where 2A is the length of total intercept of the ellipse on
the y-axis and 2B is the length of total intercept of the intercepts made by the extrma of
the ellipse on the y-axis.
6. Plot the magnitude frequency response and phase frequency response on a semi log graph
paper or you may use MATLAB to do the plotting for you.
7. Compare the value of the cut-off frequency (it is that frequency where the gain becomes
0.707 times or falls by 3dB from its DC value) as obtained from the graph with the
designed value.
 10

-10

-20

-30

-40

-50

-60

-70

-80
10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHz
DB(V(6))
Frequency

Fig. 9.2 PSPICE simulated frequency response for LPF

OBSERVATIONS TABLE 9.1

S.NO. FREQUENCY OUTPUT INPUT Vo/Vi 20LOG(Vo/Vi)

(HZ) VOLTAGE VOLTAGE (DB)
Vo(V) Vi(V)

1.

2.

3.

4.

5.

6.

7.

8
 9.

10.

11.

12.

13.

14.

15.

Results and Discussions - Derive the transfer function expression. Try to find out other
structures of second order filters and compare their advantages/disadvantages over the Sallen and
Kay structure.
Precautions :
(i). Do not apply the input before biasing the IC.
(ii). If you find the output slewing at higher frequency then reduce the input amplitude and
measure the gain when the output becomes sinusoidal.
 EXPERIMENT NO. 10

AIM :- Implementation of a 2nd order high pass filter

INSTRUMENTS AND COMPONENTS TO BE USED:-

1. IC-741 op-amp
2. CRO
3. Bread board
4. Resistors
5. Capacitors

THEORY:- HIGH PASS FILTER:-

FILTER DESIGN :- A circuit which implements a second order high pass filter is given in Fig.
10.1.

Fig. 10.1 2nd Order High Pass Filter

KS 2
Vo ω
= s2+ s o + ω 2
The transfer function of the circuit is given by Vin Q o
 Rf 1
K=1+ ; ω 2=
Where K= R1 o R1 R2 C 1 C 2

1
Q=
R1 C 1 + R1 C 2 + R 2 C 2 ( 1−K )
To design a 2nd order high pass filter with a cut-off frequency = 1 KHz , simply follow the
following steps:

1. Let C2=C3=4.7 nF
2. If we choose (for simplicity) R2 = R3 then the expression for the cut-off frequency gives
yields R2=R3=33.8 KΩ (In this expression the unit of frequency is in radians/s, be careful)
3. The value of R1 and Rf will depend upon gain K (which in turn will be decided by the
required value of pole Q of the filter. For a Butterworth type of response the value of Q
should be 0.707 which yields a value of K= 1.586, this gives the following relation
between Rf and R1

Rf = 0.586 * R1
If R1=27 KΩ, therefore Rf=15.82kΩ The required components are thus selected as given above:

PROCEDURE:
1. Using the procedure described above select the value of the passive components to give
the desired cut-off frequency (ωo and pole quality factor (Q).
2. Breadboard the circuit for the high pass filter shown in fig. 8.2b.
3. Bias the IC 741 with ±15 V using the dual power supply as shown in fig. 1.2
4. Using the function generator apply a sinusoidal amplitude of 2 V (p-p) and measure the
output amplitude and phase using both the channels of the DSO for frequency in the range
of 10 Hz – 100 KHz (the range will depend upon the value of the designed cut-off
frequency; for a second order filter the gain starts falling at the rate of 40dB per decades
so even with an input of 2V (p-p amplitude) and a DC gain of 1.5 you may not go beyond
two decades of the cut-off frequency). The choice of input amplitude is for convenience,
because with this choice (provided the amplifier can take this amplitude) the amplitude of
the output gives the value of gain directly.
5. To measure the phase difference between the input and output at a given frequency
operate the DSO in X-Y mode and use the Lissajous patterns to calculate the phase
B
Sin θ=
difference. Use the relationship A where 2A is the length of total intercept of the
ellipse on the y-axis and 2B is the length of total intercept of the intercepts made by the
extrma of the ellipse on the y-axis.
6. Plot the magnitude frequency response and phase frequency response on a semi log graph
paper or you may use MATLAB to do the plotting for you.
 7. Compare the value of the cut-off frequency (it is that frequency where the gain becomes
0.707 times or falls by 3dB from its DC value) as obtained from the graph with the
designed value.

10

-10

-20

-30

-40

-50

-60

-70

-80
10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHz
DB(V(6))
Frequency

Fig. 10.2 PSPICE simulated frequency response for HPF

OBSERVATIONS TABLE 9.1

S.NO. FREQUENCY OUTPUT INPUT Vo/Vi 20LOG(Vo/Vi)

(HZ) VOLTAGE VOLTAGE (DB)
Vo(V) Vi(V)

1.

2.

3.

4.

5.

6.
 7.

9.

10.

11.

12.

13.

14.

15.

Precautions :
(i). Do not apply the input before biasing the IC.
(ii). If you find the output slewing at higher frequency then reduce the input amplitude and
measure the gain when the output becomes sinusoidal.
Quiz Questions: (i)
 EXPERIMENT NO.-11

AIM :- Implementation of a 2nd order band pass filter

INSTRUMENTS AND COMPONENTS TO BE USED:-

1. IC-741 op-amp
2. CRO
3. Bread board
4. Resistors
5. Capacitors

THEORY:-

FILTER DESIGN:- A circuit which implements a second order band pass filter is given in
Fig.10.1.

Fig 11.1 Band Pass Filter

The transfer function of wide band pass filter can be given as below.

The value of L can be taken as

 R 1 R 3 R5 C 4
⇒ L=
R2
With the help of value of L ,W0 can be calculated hence f0(center frequency) is known.
Band width of the filter can be calculated by the formula,
R
B. W .=
L
The quality factor can be calculated.
W
Q= 0
ΔW
CALCULATION:-
R1=R2=R3=R5=15kΩ, R6=270kΩ, C4=C6=1.1nf
Then , L=247.5×10-3 (using the expression for L) And f0=9.64 kHz (using
equation no.)

PROCEDURE :-
1.On a bread-board make a neat circuit as shown in fig. 11.1.
2. After biasing the IC 741 (+Vcc to Pin-7 and -Vcc to Pin-4), connect the input through the
resistor R6.
3. Now to study the behavior of the band pass filter when a sinusoidal input of 1 V p-p
amplitude is applied and choose band of frequency just like above calculations.
(i) Operate the DSO in y-t mode (In this mode the output is displayed as a function of
time).
(ii) Change the frequency of the input sinusoidal signal using the function generator and
note down the corresponding output sinusoidal voltage amplitude starting from a
frequency of 10 Hz. Note down the frequency where you start observing
distortion in the output sinusoid (try to observe the nature of the distortion!!).
Continue the variation up to a frequency where the output magnitude has become
indistinguishable from noise. (you should take at least 20 observations to plot the
frequency response).
4. Plot the magnitude frequency response and there from calculate the 3-dB frequency of the
amplifier. There are two 3-dB frequency in which signal can pass.
5.Compare practical implementation with theoretical calculation.
 0

-10

-20

-30

-40

-50

-60

-70

-80

-90
10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHz
DB(V(6))
Frequency

Fig. PSPICE simulated frequency response for BPF

OBSERVATIONS : 11.1 :-

S.NO. FREQUENCY OUTPUT INPUT Vo/Vi 20LOG(Vo/Vi)

(HZ) VOLTAGE VOLTAGE (DB)
Vo(V) Vi(V)

1.

2.

3.

4.

5.

7.

Precautions :
(i). Do not apply the input before biasing the IC.
(ii). If you find the output slewing at higher frequency then reduce the input amplitude and
measure the gain when the output becomes sinusoidal.