17.6.

1 Input Capture Trigger Source

The main trigger source for the input capture unit is the Input Capture Pin (ICPn). Timer/Counter1 can alternatively
use the analog comparator output as trigger source for the input capture unit. The Analog Comparator is selected
as trigger source by setting the analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and
Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The input capture flag must
therefore be cleared after the change.
Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled using the same
technique as for the Tn pin (Figure 18-1 on page 164). The edge detector is also identical. However, when the
noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four
system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the
Timer/Counter is set in a Waveform Generation mode that uses ICRn to define TOP.
An input capture can be triggered by software by controlling the port of the ICPn pin.
17.6.2 Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is
monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge
detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter Control
Register B (TCCRnB). When enabled the noise canceler introduces additional four system clock cycles of delay
from a change applied to the input, to the update of the ICRn Register. The noise canceler uses the system clock
and is therefore not affected by the prescaler.
17.6.3 Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the
incoming events. The time between two events is critical. If the processor has not read the captured value in the
ICRn Register before the next event occurs, the ICRn will be overwritten with a new value. In this case the result of
the capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the interrupt handler routine
as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response
time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during
operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture.
Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a
change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is
used).

17.7 Output Compare Units

The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals
OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock
cycle. If enabled (OCIEnx = 1), the Output Compare Flag generates an Output Compare interrupt. The OCFnx Flag
is automatically cleared when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software
by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output
according to operating mode set by the Waveform Generation mode (WGMn3:0) bits and Compare Output mode
(COMnx1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation. See “Modes of Operation” on page 144.

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A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that is, counter reso-
lution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the
Waveform Generator.
Figure 17-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indi-
cates the device number (n = n for Timer/Counter n), and the “x” indicates Output Compare unit (A/B/C). The
elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded.

Figure 17-4. Output Compare Unit, Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) TCNTnL (8-bit)

OCRnx Buffer (16-bit Register) TCNTn (16-bit Counter)

OCRnxH (8-bit) OCRnxL (8-bit)

OCRnx (16-bit Register)

= (16-bit Comparator )
OCFnx (Int.Req.)

TOP
Waveform Generator OCnx
BOTTOM

WGMn3:0 COMnx1:0

The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For
the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx
directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the
Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is
not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as
when accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Register since the
compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first. When the high byte I/O
location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte
(OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCRnx
buffer or OCRnx Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 135.

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17.7.1 Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOCnx) bit. Forcing compare match will not set the OCFnx Flag or reload/clear the
timer, but the OCnx pin will be updated as if a real compare match had occurred (the COMn1:0 bits settings define
whether the OCnx pin is set, cleared or toggled).
17.7.2 Compare Match Blocking by TCNTn Write

All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer clock cycle, even
when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without trigger-
ing an interrupt when the Timer/Counter clock is enabled.
17.7.3 Using the Output Compare Unit

Since writing TCNTn in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNTn when using any of the Output Compare channels, independent of whether
the Timer/Counter is running or not. If the value written to TCNTn equals the OCRnx value, the compare match will
be missed, resulting in incorrect waveform generation. Do not write the TCNTn equal to TOP in PWM modes with
variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting.
The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OCnx value is to use the Force Output Compare (FOCnx) strobe bits in Normal
mode. The OCnx Register keeps its value even when changing between Waveform Generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the
COMnx1:0 bits will take effect immediately.

17.8 Compare Match Output Unit

The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0
bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control
the OCnx pin output source. Figure 17-5 on page 144 shows a simplified schematic of the logic affected by the
COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the
general I/O Port Control Registers (DDR and PORT) that are affected by the COMnx1:0 bits are shown. When
referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset
occur, the OCnx Register is reset to “0”.

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 Figure 17-5. Compare Match Output Unit, Schematic

COMnx1
COMnx0 Waveform
D Q
FOCnx Generator
1
OCnx
OCnx Pin
0

D Q

DATA BUS
PORT

D Q

DDR
clk I/O

The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either
of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direc-
tion Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as
output before the OCnx value is visible on the pin. The port override function is generally independent of the Wave-
form Generation mode, but there are some exceptions. Refer to Table 17-3 on page 155, Table 17-4 on page 155
and Table 17-5 on page 155 for details.
The design of the Output Compare pin logic allows initialization of the OCnx state before the output is enabled.
Note that some COMnx1:0 bit settings are reserved for certain modes of operation. See “Register Description” on
page 154.
The COMnx1:0 bits have no effect on the Input Capture unit.
17.8.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes,
setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on
the next compare match. For compare output actions in the non-PWM modes refer to Table 17-3 on page 155. For
fast PWM mode refer to Table 17-4 on page 155, and for phase correct and phase and frequency correct PWM
refer to Table 17-5 on page 155.
A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-
PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits.

17.9 Modes of Operation

The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a
compare match. See “Compare Match Output Unit” on page 143.

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Table 17-2. Waveform Generation Mode Bit Description(1)
WGMn2 WGMn1 WGMn0 Timer/Counter Update of TOVn Flag
Mode WGMn3 (CTCn) (PWMn1) (PWMn0) Mode of Operation TOP OCRnx at Set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCRnA Immediate MAX
5 0 1 0 1 Fast PWM, 8-bit 0x00FF BOTTOM TOP
6 0 1 1 0 Fast PWM, 9-bit 0x01FF BOTTOM TOP
7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP
PWM, Phase and Frequency
8 1 0 0 0 ICRn BOTTOM BOTTOM
Correct
PWM,Phase and Frequency
9 1 0 0 1 OCRnA BOTTOM BOTTOM
Correct
10 1 0 1 0 PWM, Phase Correct ICRn TOP BOTTOM
11 1 0 1 1 PWM, Phase Correct OCRnA TOP BOTTOM
12 1 1 0 0 CTC ICRn Immediate MAX
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWM ICRn BOTTOM TOP
15 1 1 1 1 Fast PWM OCRnA BOTTOM TOP
Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functional-
ity and location of these bits are compatible with previous versions of the timer.
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 152.
17.9.1 Normal Mode

The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum
16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Coun-
ter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in
this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by software. There are no
special cases to consider in the Normal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the
external events must not exceed the resolution of the counter. If the interval between events are too long, the timer
overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
17.9.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register are used to manipu-
late the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches
either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the

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 counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also
simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 17-6. The counter value (TCNTn) increases until a com-
pare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared.

Figure 17-6. CTC Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set
(Interrupt on TOP)

TCNTn

OCnA
(COMnA1:0 = 1)
(Toggle)

Period 1 2 3 4

An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or
ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler
routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when
the counter is running with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCRnA or ICRn is lower than the current value of
TCNTn, the counter will miss the compare match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is
not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP (WGMn3:0 =
15) since the OCRnA then will be double buffered.
For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will
not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCnA = 1). The waveform
generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform
frequency is defined by the following equation:
f clk_I/O
f OCnA = --------------------------------------------------
-
2  N   1 + OCRnA 

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x0000.
17.9.3 Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation.
The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode,
the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx, and set at BOTTOM.
In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-
slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and
phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM

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mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICRn or OCRnA. The
minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or
OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation:
log  TOP + 1 
R FPWM = ----------------------------------
-
log  2 

In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA
(WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 17-7 on page 147. The figure shows fast PWM mode when OCRnA or ICRn is used
to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the
TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when
a compare match occurs.

Figure 17-7. Fast PWM Mode, Timing Diagram

OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set
(Interrupt on TOP)

TCNTn

OCnx (COMnx1:0 = 2)

OCnx (COMnx1:0 = 3)

Period 1 2 3 4 5 6 7 8

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn
Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP
value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and com-
pare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are
masked to zero when any of the OCRnx Registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn
Register is not double buffered. This means that if ICRn is changed to a low value when the counter is running with
none or a low prescaler value, there is a risk that the new ICRn value written is lower than the current value of
TCNTn. The result will then be that the counter will miss the compare match at the TOP value. The counter will
then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can
occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location to be written
anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The
OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle

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 the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the
TOVn Flag is set.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA
Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively
changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer
feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the
COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COMnx1:0 to three (see Table on page 155). The actual OCnx value will only be visible on the port pin if the
data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clear-
ing) the OCnx Register at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx
Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ----------------------------------
-
N   1 + TOP 

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each
TOP+1 timer clock cycle. Setting the OCRnx equal to TOP will result in a constant high or low output (depending
on the polarity of the output set by the COMnx1:0 bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCnA to toggle
its logical level on each compare match (COMnA1:0 = 1). This applies only if OCR1A is used to define the TOP
value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA
is set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer feature of
the Output Compare unit is enabled in the fast PWM mode.
17.9.4 Phase Correct PWM Mode

The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3, 10, or 11) provides a
high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase
and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOT-
TOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either
ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum res-
olution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following
equation:

 TOP + 1 -
R PCPWM = log
----------------------------------
log  2 

In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed val-
ues 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in
OCRnA (WGMn3:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNTn
value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

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on Figure 17-8 on page 149. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define
TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes
represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare
match occurs.

Figure 17-8. Phase Correct PWM Mode, Timing Diagram

OCRnx/TOP Update and

OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

OCnx (COMnx1:0 = 2)

OCnx (COMnx1:0 = 3)

Period 1 2 3 4

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or
ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly at the same timer clock cycle as
the OCRnx Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to gener-
ate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are
masked to zero when any of the OCRnx Registers are written. As the third period shown in Figure 17-8 illustrates,
changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsym-
metrical output. The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx
update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is
determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value.
When these two values differ the two slopes of the period will differ in length. The difference in length gives the
unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when chang-
ing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no
differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting
the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by set-
ting the COMnx1:0 to three (see Table 17-5 on page 155). The actual OCnx value will only be visible on the port
pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting
(or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments,
and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the counter dec-

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 rements. The PWM frequency for the output when using phase correct PWM can be calculated by the following
equation:
f clk_I/O
f OCnxPCPWM = ---------------------------
-
2  N  TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set
equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the
OC1A output will toggle with a 50% duty cycle.
17.9.5 Phase and Frequency Correct PWM Mode

The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGMn3:0
= 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase
and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The
counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Com-
pare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx
while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the
operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the sin-
gle-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the
OCRnx Register is updated by the OCRnx Buffer Register, see Figure 17-8 on page 149 and Figure 17-9 on page
151.
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA.
The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit
(ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation:

log  TOP + 1 
R PFCPWM = -----------------------------------
log  2 

In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the
value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and
changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram
for the phase correct and frequency correct PWM mode is shown on Figure 17-9 on page 151. The figure shows
phase and frequency correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the
timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches
between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare match occurs.

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Figure 17-9. Phase and Frequency Correct PWM Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)

OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)

TCNTn

OCnx (COMnx1:0 = 2)

OCnx (COMnx1:0 = 3)

Period 1 2 3 4

The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated
with the double buffer value (at BOTTOM). When either OCRnA or ICRn is used for defining the TOP value, the
OCnA or ICFn Flag set when TCNTn has reached TOP. The Interrupt Flags can then be used to generate an inter-
rupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNTn and the OCRnx.
As Figure 17-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods.
Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be
equal. This gives symmetrical output pulses and is therefore frequency correct.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA
Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively
changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx
pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be gen-
erated by setting the COMnx1:0 to three (see Table 17-5 on page 155). The actual OCnx value will only be visible
on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated
by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter
increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the
counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be cal-
culated by the following equation:
f clk_I/O
f OCnxPFCPWM = ---------------------------
-
2  N  TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set
equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A
output will toggle with a 50% duty cycle.

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17.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal
in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Reg-
ister is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 17-10 shows a
timing diagram for the setting of OCFnx.

Figure 17-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling

clkI/O

clkTn
(clkI/O /1)

TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

OCRnx OCRnx Value

OCFnx

Figure 17-11 shows the same timing data, but with the prescaler enabled.

Figure 17-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)

clkI/O

clkTn
(clkI/O /8)

TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

OCRnx OCRnx Value

OCFnx

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Figure 17-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct
PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should
be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the
TOVn Flag at BOTTOM.

Figure 17-12. Timer/Counter Timing Diagram, no Prescaling

clkI/O

clkTn
(clkI/O /1)

TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC and FPWM)

TCNTn
TOP - 1 TOP TOP - 1 TOP - 2
(PC and PFC PWM)

TOVn (FPWM)
and ICFn (if used
as TOP)

OCRnx
Old OCRnx Value New OCRnx Value
(Update at TOP)

Figure 17-13 shows the same timing data, but with the prescaler enabled.

Figure 17-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

clkI/O

clkTn
(clkI/O/8)

TCNTn
TOP - 1 TOP BOTTOM BOTTOM + 1
(CTC and FPWM)

TCNTn TOP - 1 TOP TOP - 1 TOP - 2

(PC and PFC PWM)

TOVn (FPWM)
and ICF n (if used
as TOP)

OCRnx
Old OCRnx Value New OCRnx Value
(Update at TOP)

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17.11 Register Description
17.11.1 TCCR1A – Timer/Counter 1 Control Register A

Bit 7 6 5 4 3 2 1 0
(0x80) COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 TCCR1A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.2 TCCR3A – Timer/Counter 3 Control Register A

Bit 7 6 5 4 3 2 1 0
(0x90) COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 TCCR3A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.3 TCCR4A – Timer/Counter 4 Control Register A

Bit 7 6 5 4 3 2 1 0
(0xA0) COM4A1 COM4A0 COM4B1 COM4B0 COM4C1 COM4C0 WGM41 WGM40 TCCR4A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.4 TCCR5A – Timer/Counter 5 Control Register A

Bit 7 6 5 4 3 2 1 0
(0x120) COM5A1 COM5A0 COM5B1 COM5B0 COM5C1 COM5C0 WGM51 WGM50 TCCR5A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A

• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB, and OCnC respec-
tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port
functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bits are written to one, the OCnB out-
put overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are
written to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected to. However,
note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or OCnC pin must be set in
order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the
WGMn3:0 bits setting. Table 17-3 on page 155 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are
set to a normal or a CTC mode (non-PWM).

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• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 17-2 on page 145. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter),
Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more
information on the different modes, see “Modes of Operation” on page 144.

Table 17-3. Compare Output Mode, non-PWM

COMnA1 COMnA0
COMnB1 COMnB0
COMnC1 COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC disconnected
0 1 Toggle OCnA/OCnB/OCnC on compare match
1 0 Clear OCnA/OCnB/OCnC on compare match (set output to low level)
1 1 Set OCnA/OCnB/OCnC on compare match (set output to high level)

Table 17-4 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode.

Table 17-4. Compare Output Mode, Fast PWM

COMnA1 COMnA0
COMnB1 COMnB0
COMnC1 COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC disconnected
WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal
0 1 port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C
disconnected
Clear OCnA/OCnB/OCnC on compare match, set OCnA/OCnB/OCnC at BOTTOM (non-inverting
1 0
mode)
1 1 Set OCnA/OCnB/OCnC on compare match, clear OCnA/OCnB/OCnC at BOTTOM (inverting mode)

Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and COMnA1/COMnB1/COMnC1 is set. In this
case the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 146. for
more details.
Table 17-5 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct and fre-
quency correct PWM mode.

Table 17-5. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
COMnA1 COMnA0
COMnB1 COMnB0
COMnC1 COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC disconnected
WGM13:0 =9 or 11: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal port
0 1
operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C disconnected
Clear OCnA/OCnB/OCnC on compare match when up-counting
1 0
Set OCnA/OCnB/OCnC on compare match when downcounting
Set OCnA/OCnB/OCnC on compare match when up-counting
1 1
Clear OCnA/OCnB/OCnC on compare match when downcounting

Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and COMnA1/COMnB1//COMnC1 is set. See
“Phase Correct PWM Mode” on page 148. for more details.

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17.11.5 TCCR1B – Timer/Counter 1 Control Register B

Bit 7 6 5 4 3 2 1 0
(0x81) ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.6 TCCR3B – Timer/Counter 3 Control Register B

Bit 7 6 5 4 3 2 1 0
(0x91) ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.7 TCCR4B – Timer/Counter 4 Control Register B

Bit 7 6 5 4 3 2 1 0
(0xA1) ICNC4 ICES4 – WGM43 WGM42 CS42 CS41 CS40 TCCR4B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.8 TCCR5B – Timer/Counter 5 Control Register B

Bit 7 6 5 4 3 2 1 0
(0x121) ICNC5 ICES5 – WGM53 WGM52 CS52 CS51 CS50 TCCR5B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – ICNCn: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the
input from the Input Capture Pin (ICPn) is filtered. The filter function requires four successive equal valued samples
of the ICPn pin for changing its output. The input capture is therefore delayed by four Oscillator cycles when the
noise canceler is enabled.

• Bit 6 – ICESn: Input Capture Edge Select

This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture event. When the
ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a
rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Reg-
ister (ICRn). The event will also set the Input Capture Flag (ICFn), and this can be used to cause an Input Capture
Interrupt, if this interrupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the
TCCRnB Register), the ICPn is disconnected and consequently the input capture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero
when TCCRnB is written.

• Bit 4:3 – WGMn3:2: Waveform Generation Mode

See TCCRnA Register description.

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 • Bit 2:0 – CSn2:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 17-10 and Figure
17-11 on page 152.

Table 17-6. Clock Select Bit Description

CSn2 CSn1 CSn0 Description
0 0 0 No clock source. (Timer/Counter stopped)
0 0 1 clkI/O/1 (No prescaling
0 1 0 clkI/O/8 (From prescaler)
0 1 1 clkI/O/64 (From prescaler)
1 0 0 clkI/O/256 (From prescaler)
1 0 1 clkI/O/1024 (From prescaler)
1 1 0 External clock source on Tn pin. Clock on falling edge
1 1 1 External clock source on Tn pin. Clock on rising edge

If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
17.11.9 TCCR1C – Timer/Counter 1 Control Register C

Bit 7 6 5 4 3 2 1 0
(0x82) FOC1A FOC1B FOC1C – – – – – TCCR1C
Read/Write W W W R R R R R
Initial Value 0 0 0 0 0 0 0 0

17.11.10 TCCR3C – Timer/Counter 3 Control Register C

Bit 7 6 5 4 3 2 1 0
(0x92) FOC3A FOC3B FOC3C – – – – – TCCR3C
Read/Write W W W R R R R R
Initial Value 0 0 0 0 0 0 0 0

17.11.11 TCCR4C – Timer/Counter 4 Control Register C

Bit 7 6 5 4 3 2 1 0
(0xA2) FOC4A FOC4B FOC4C – – – – – TCCR4C
Read/Write W W W R R R R R
Initial Value 0 0 0 0 0 0 0 0

17.11.12 TCCR5C – Timer/Counter 5 Control Register C

Bit 7 6 5 4 3 2 1 0
(0x122) FOC5A FOC5B FOC3C – – – – – TCCR5C
Read/Write W W W R R R R R
Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – FOCnA: Force Output Compare for Channel A

• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writ-
ing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare match is forced on the waveform
generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the

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 FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits
that determine the effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Com-
pare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.

• Bit 4:0 – Reserved Bits

These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to
zero when TCCRnC is written.
17.11.13 TCNT1H and TCNT1L – Timer/Counter 1

Bit 7 6 5 4 3 2 1 0
(0x85) TCNT1[15:8] TCNT1H
(0x84) TCNT1[7:0] TCNT1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.14 TCNT3H and TCNT3L – Timer/Counter 3

Bit 7 6 5 4 3 2 1 0
(0x95) TCNT3[15:8] TCNT3H
(0x94) TCNT3[7:0] TCNT3L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.15 TCNT4H and TCNT4L –Timer/Counter 4

Bit 7 6 5 4 3 2 1 0
(0xA5) TCNT4[15:8] TCNT4H
(0xA4) TCNT4[7:0] TCNT4L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.16 TCNT5H and TCNT5L –Timer/Counter 5

Bit 7 6 5 4 3 2 1 0
(0x125) TCNT5[15:8] TCNT5H
(0x124) TCNT5[7:0] TCNT5L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read
and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are
read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See
“Accessing 16-bit Registers” on page 135.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a compare match between
TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare
units.

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17.11.17 OCR1AH and OCR1AL – Output Compare Register 1 A

Bit 7 6 5 4 3 2 1 0
(0x89) OCR1A[15:8] OCR1AH
(0x88) OCR1A[7:0] OCR1AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.18 OCR1BH and OCR1BL – Output Compare Register 1 B

Bit 7 6 5 4 3 2 1 0
(0x8B) OCR1B[15:8] OCR1BH
(0x8A) OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.19 OCR1CH and OCR1CL – Output Compare Register 1 C

Bit 7 6 5 4 3 2 1 0
(0x8D) OCR1C[15:8] OCR1CH
(0x8C) OCR1C[7:0] OCR1CL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.20 OCR3AH and OCR3AL – Output Compare Register 3 A

Bit 7 6 5 4 3 2 1 0
(0x99) OCR3A[15:8] OCR3AH
(0x98) OCR3A[7:0] OCR3AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.21 OCR3BH and OCR3BL – Output Compare Register 3 B

Bit 7 6 5 4 3 2 1 0
(0x9B) OCR3B[15:8] OCR3BH
(0x9A) OCR3B[7:0] OCR3BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.22 OCR3CH and OCR3CL – Output Compare Register 3 C

Bit 7 6 5 4 3 2 1 0
(0x9D) OCR3C[15:8] OCR3CH
(0x9C) OCR3C[7:0] OCR3CL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.23 OCR4AH and OCR4AL – Output Compare Register 4 A

Bit 7 6 5 4 3 2 1 0
(0xA9) OCR4A[15:8] OCR4AH
(0xA8) OCR4A[7:0] OCR4AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

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17.11.24 OCR4BH and OCR4BL – Output Compare Register 4 B

Bit 7 6 5 4 3 2 1 0
(0xAA) OCR4B[15:8] OCR4BH
(0xAB) OCR4B[7:0] OCR4BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.25 OCR4CH and OCR4CL –Output Compare Register 4 C

Bit 7 6 5 4 3 2 1 0
(0xAD) OCR4C[15:8] OCR4CH
(0xAC) OCR4C[7:0] OCR4CL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.26 OCR5AH and OCR5AL – Output Compare Register 5 A

Bit 7 6 5 4 3 2 1 0
(0x129) OCR5A[15:8] OCR5AH
(0x128) OCR5A[7:0] OCR5AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.27 OCR5BH and OCR5BL – Output Compare Register 5 B

Bit 7 6 5 4 3 2 1 0
(0x12B) OCR5B[15:8] OCR5BH
(0x12A) OCR5B[7:0] OCR5BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.28 OCR5CH and OCR5CL –Output Compare Register 5 C

Bit 7 6 5 4 3 2 1 0
(0x12D) OCR5C[15:8] OCR5CH
(0x12C) OCR5C[7:0] OCR5CL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value
(TCNTn). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultane-
ously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on
page 135.
17.11.29 ICR1H and ICR1L – Input Capture Register 1

Bit 7 6 5 4 3 2 1 0
(0x87) ICR1[15:8] ICR1H
(0x86) ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

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17.11.30 ICR3H and ICR3L – Input Capture Register 3

Bit 7 6 5 4 3 2 1 0
(0x97) ICR3[15:8] ICR3H
(0x96) ICR3[7:0] ICR3L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.31 ICR4H and ICR4L – Input Capture Register 4

Bit 7 6 5 4 3 2 1 0
(0xA7) ICR4[15:8] ICR4H
(0xA6) ICR4[7:0] ICR4L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.32 ICR5H and ICR5L – Input Capture Register 5

Bit 7 6 5 4 3 2 1 0
(0x127) ICR5[15:8] ICR5H
(0x126) ICR5[7:0] ICR5L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or
optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the
counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on
page 135.
17.11.33 TIMSK1 – Timer/Counter 1 Interrupt Mask Register

Bit 7 6 5 4 3 2 1 0
(0x6F) – – ICIE1 – OCIE1C OCIE1B OCIE1A TOIE1 TIMSK1
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.34 TIMSK3 – Timer/Counter 3 Interrupt Mask Register

Bit 7 6 5 4 3 2 1 0
(0x71) – – ICIE3 – OCIE3C OCIE3B OCIE3A TOIE3 TIMSK3
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.35 TIMSK4 – Timer/Counter 4 Interrupt Mask Register

Bit 7 6 5 4 3 2 1 0
(0x72) – – ICIE4 – OCIE4C OCIE4B OCIE4A TOIE4 TIMSK4
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

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17.11.36 TIMSK5 – Timer/Counter 5 Interrupt Mask Register

Bit 7 6 5 4 3 2 1 0
(0x73) – – ICIE5 – OCIE5C OCIE5B OCIE5A TOIE5 TIMSK5
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page
101) is executed when the ICFn Flag, located in TIFRn, is set.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Countern Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector (see “Inter-
rupts” on page 101) is executed when the OCFnC Flag, located in TIFRn, is set.

• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Countern Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see “Inter-
rupts” on page 101) is executed when the OCFnB Flag, located in TIFRn, is set.

• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Countern Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Inter-
rupts” on page 101) is executed when the OCFnA Flag, located in TIFRn, is set.

• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 101) is
executed when the TOVn Flag, located in TIFRn, is set.
17.11.37 TIFR1 – Timer/Counter1 Interrupt Flag Register

Bit 7 6 5 4 3 2 1 0
0x16 (0x36) – – ICF1 – OCF1C OCF1B OCF1A TOV1 TIFR1
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.38 TIFR3 – Timer/Counter3 Interrupt Flag Register

Bit 7 6 5 4 3 2 1 0
0x18 (0x38) – – ICF3 – OCF3C OCF3B OCF3A TOV3 TIFR3
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

17.11.39 TIFR4 – Timer/Counter4 Interrupt Flag Register

Bit 7 6 5 4 3 2 1 0
0x19 (0x39) – – ICF4 – OCF4C OCF4B OCF4A TOV4 TIFR4
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

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17.11.40 TIFR5 – Timer/Counter5 Interrupt Flag Register

Bit 7 6 5 4 3 2 1 0
0x1A (0x3A) – – ICF5 – OCF5C OCF5B OCF5A TOV5 TIFR5
Read/Write R R R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 5 – ICFn: Timer/Countern, Input Capture Flag

This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register (ICRn) is set by the
WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the counter reaches the TOP value.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICFn can be
cleared by writing a logic one to its bit location.

• Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register C
(OCRnC).
Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.
OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is executed. Alternatively,
OCFnC can be cleared by writing a logic one to its bit location.

• Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B
(OCRnB).
Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag.
OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively,
OCFnB can be cleared by writing a logic one to its bit location.

• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNTn value matches the Output Compare Register A
(OCRnA).
Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA Flag.
OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively,
OCFnA can be cleared by writing a logic one to its bit location.

• Bit 0 – TOVn: Timer/Countern, Overflow Flag

The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOVn Flag is set
when the timer overflows. Refer to Table 17-2 on page 145 for the TOVn Flag behavior when using another
WGMn3:0 bit setting.
TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed. Alternatively, TOVn
can be cleared by writing a logic one to its bit location.

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18. Timer/Counter 0, 1, 3, 4, and 5 Prescaler
Timer/Counter 0, 1, 3, 4, and 5 share the same prescaler module, but the Timer/Counters can have different pres-
caler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1, 3, 4, or
5.

18.1 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fast-
est operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f CLK_I/O ).
Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a fre-
quency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.

18.2 Prescaler Reset

The prescaler is free running, that is, operates independently of the Clock Select logic of the Timer/Counter, and it
is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counter’s clock select, the
state of the prescaler will have implications for situations where a prescaled clock is used. One example of presca-
ling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of
system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care
must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset
will affect the prescaler period for all Timer/Counters it is connected to.

18.3 External Clock Source

An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled
once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed
through the edge detector. Figure 18-1 shows a functional equivalent block diagram of the Tn synchronization and
edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is
transparent in the high period of the internal system clock.
The edge detector generates one clkTn pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it
detects.

Figure 18-1. Tn/T0 Pin Sampling

Tn D Q D Q D Q Tn_sync
(To Clock
Select Logic)
LE

clk I/O

Synchronization Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has
been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock
cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

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Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sam-
pling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2)
given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it
can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system
clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is rec-
ommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.

Figure 18-2. Prescaler for synchronous Timer/Counters

clk I/O
Clear

PSR10

Tn
Synchronization

Tn
Synchronization

CSn0 CSn0
CSn1 CSn1
CSn2 CSn2

TIMER/COUNTERn CLOCK SOURCE TIMER/COUNTERn CLOCK SOURCE

clkTn clkTn

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18.4 Register Description
18.4.1 GTCCR – General Timer/Counter Control Register

Bit 7 6 5 4 3 2 1 0
0x23 (0x43) TSM – – – – – PSRASY PSRSYNC GTCCR
Read/Write R/W R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is writ-
ten to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted.
This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without
the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and
PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously.

• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters

When this bit is one, Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 pres-
caler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that
Timer/Counter0, Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 share the same prescaler
and a reset of this prescaler will affect all timers.

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19. Output Compare Modulator (OCM1C0A)
19.1 Overview
The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The
modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare
Unit of the 8-bit Timer/Counter0. For more details about these Timer/Counters see “Timer/Counter 0, 1, 3, 4, and 5
Prescaler” on page 164 and “8-bit Timer/Counter2 with PWM and Asynchronous Operation” on page 169.

Figure 19-1. Output Compare Modulator, Block Diagram

Timer/Counter 1 OC1C

Pin

OC1C /
Timer/Counter 0 OC0A OC0A / PB7

When the modulator is enabled, the two output compare channels are modulated together as shown in the block
diagram (see Figure 19-1).

19.2 Description
The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The outputs of the
Output Compare units (OC1C and OC0A) overrides the normal PORTB7 Register when one of them is enabled
(that is, when COMnx1:0 is not equal to zero). When both OC1C and OC0A are enabled at the same time, the
modulator is automatically enabled.
The functional equivalent schematic of the modulator is shown on Figure 19-2. The schematic includes part of the
Timer/Counter units and the port B pin 7 output driver circuit.

Figure 19-2. Output Compare Modulator, Schematic

COMA01 Vcc
COMA00

COM1C1 Modulator
COM1C0
0

1
( From Waveform Generator ) D Q

1
OC1C
Pin
0
OC1C /
( From Waveform Generator ) D Q OC0A/ PB7

OC0A

D Q D Q

PORTB7 DDRB7
DATABUS

When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Reg-
ister. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting.

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19.2.1 Timing example

Figure 19-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM
mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode
(COMnx1:0 = 1).

Figure 19-3. Output Compare Modulator, Timing Diagram

clk I/O

OC1C
(FPWM Mode)

OC0A
(CTC Mode)

PB7
(PORTB7 = 0)

PB7
(PORTB7 = 1)

1 2 3
(Period)

In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated by the Output Com-
pare unit C of the Timer/Counter1.
The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is equal to the num-
ber of system clock cycles of one period of the carrier (OC0A). In this example the resolution is reduced by a factor
of two. The reason for the reduction is illustrated in Figure 19-3 at the second and third period of the PB7 output
when PORTB7 equals zero. The period 2 high time is one cycle longer than the period 3 high time, but the result on
the PB7 output is equal in both periods.

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20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are:
• Single Channel Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
• Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock

20.1 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 17-12 on page 153 For the actual place-
ment of I/O pins, see “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins,
are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on
page 182.
The Power Reduction Timer/Counter2 bit, PRTIM2, in “PRR0 – Power Reduction Register 0” on page 55 must be
written to zero to enable Timer/Counter2 module.

Figure 20-1. 8-bit Timer/Counter Block Diagram

Count TOVn
Clear (Int.Req.)
Control Logic
Direction clkTn TOSC1
T/C
Oscillator
Prescaler TOSC2
TOP BOTTOM
clkI/O

Timer/Counter
TCNTn
= =0
OCnA
(Int.Req.)

Waveform
= Generation
OCnA

OCRnA
Fixed
OCnB
TOP
(Int.Req.)
Value
DATA BUS

Waveform
= Generation
OCnB

OCRnB clkI/O
Synchronized Status flags
Synchronization Unit
clkASY

asynchronous mode
Status flags select (ASn)
ASSRn

TCCRnA TCCRnB

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20.1.1 Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt
request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts
are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the
figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins,
as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register
(ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decre-
ment) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select
logic is referred to as the timer clock (clkT2).
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the Timer/Counter value
at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable fre-
quency output on the Output Compare pins (OC2A and OC2B). See “Output Compare Unit” on page 175 for
details. The compare match event will also set the Compare Flag (OCF2A or OCF2B) which can be used to gener-
ate an Output Compare interrupt request.
20.1.2 Definitions

Many register and bit references in this document are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise
form must be used, that is, TCNT2 for accessing Timer/Counter2 counter value and so on.
The definitions in Table 20-1 are also used extensively throughout the section.
Table 20-1. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00)
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255)
TOP The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored
in the OCR2A Register. The assignment is dependent on the mode of operation

20.2 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The
clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to
logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For
details on asynchronous operation, see “Asynchronous Operation of Timer/Counter2” on page 179. For details on
clock sources and prescaler, see “Timer/Counter Prescaler” on page 180.

20.3 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 20-2 on page 171
shows a block diagram of the counter and its surrounding environment.

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 Figure 20-2. Counter Unit Block Diagram

TOVn
DATA BUS (Int.Req.)

TOSC1
count
T/C
clear clk Tn
TCNTn Control Logic Prescaler Oscillator
direction
TOSC2

bottom top clkI/O

Signal description (internal signals):

count Increment or decrement TCNT2 by 1.
direction Selects between increment and decrement.
clear Clear TCNT2 (set all bits to zero).
clkTn Timer/Counter clock, referred to as clkT2 in the following.
top Signalizes that TCNT2 has reached maximum value.
bottom Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be
accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter
Control Register (TCCR2A) and the WGM22 located in the Timer/Counter Control Register B (TCCR2B). There
are close connections between how the counter behaves (counts) and how waveforms are generated on the Out-
put Compare outputs OC2A and OC2B. For more details about advanced counting sequences and waveform
generation, see “Modes of Operation” .
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits.
TOV2 can be used for generating a CPU interrupt.

20.4 Modes of Operation

The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a
compare match. See “Compare Match Output Unit” on page 176.
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 177.

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