TRANSISTOR BASE BIASING PURPOSE AND BACKGROUND ‘The purpose of this experiment is to verify the voltages and cur- rents in a base-biased circuit as well as to construct its de load line. In spite of its simplicity, a base-biased cireuit does not effectively stabilize a transistor’s quiescent point. Consequently, the Q point is, affected by the transistor’s current gain (8). Text References: 5-1, The DC Operating Point; 5-2, Base Bias. REQUIRED PARTS AND EQUIPMENT Resistors (1/4 W): 1 0-45 V de power supply O1ka (VOM or DMM (preferred) 0 560 ko 1 Breadboarding socket (D1 MO potentiometer 1B Two 2N3904 npn silicon transistors 89USEFUL FORMULAS Quiescent de base voltage (1) Va = Veo ~ IaRe = Var Quiescent de collector (emitter) current Quiescent de base current (8) Ip = Veo = Va Ra Quiescent de collector-to-emitter voltage (4) Vor = Vee ~ [eRe de load line (©) Tomy = EE (saturation) (8) Vorwm = Veo (cutoff) In general, make © Veo > Var PROCEDURE 1 Wire the circuit shown in the schematic diagram of Figure 9-1, and apply power to the breadboard. With your VOM or DMM, measure the voltage across the base and collector resistors, and, using Ohm's law, determine the corresponding currents, recording your values in Table 9-1. From these two sets of values, determine the de current gain or beta (Bye) for this transistor so that alc Pu= Record this value of beta in Table 9-1. Use your VOM or DMM to measure individually Vp and Vor. Record your results in Table 9-1 Compare the values of Step 3 with the expected values, using the value of Bye determined in Step 2 and a typical base-emitter voltage of 0.7 V. Record these values in Table 9-1. Now use @ hand-held hair dryer to blow hot air against the transistors case for a few seconds while measuring thesisv re 00 Ko. ve 204 FIGURE9-1 Schematic diagram of cireuit. 10. collector current using your VOM or DMM. Does the collector current increase or decrease? ‘You should find that the collector current increases, which turn causes the circuit's @ point to change. ‘Using Equations 5 and 6 in the “Useful Formulas” section of this experiment, determine the saturation and cutoff points on ‘the de load line for this circuit, and record these values in Table 9-2. On the blank graph provided, plot the de load line, using the calculated values of Zcjas) and Vosian as the endpoints of tthe load line. Now plot the Q point based on the measured values of Ic and Vog on the same graph. What do you notice about the Q point? ‘You should find that the measured Q point lies essentially ‘on the de load line. Using a different 2N3904 transistor, repeat Steps 2 through 5, and record your results in Table 9-1. Do you find any differ- ences between the two transistors? ‘You will usually find that the two transistors give different values for the quiescent voltages and currents. In addition, you will usually find differences in the de current gains. Disconnect the power ftom the breadboard and replace the 560-0. resistor (Rp) with a 1-MO. potentiometer. Again apply power to the breadboard and connect a voltmeter between the transistor’s collector terminal and ground. Now vary the resistance of the potentiometer until Vos as read by the voltmeter reaches a minimum value, Vogiat). Then mea- sure the corresponding collector current, Icisuy. Record both values in Table 9-2. Continue to vary the resistance of the 1-M2 potentiometer un- til Vop reaches a maximum value, Vosian- Then measure the 1uu. corresponding collector current Icieq If the collector current is not essentially zero, then temporarily disconnect one lead of ‘the potentiometer from the circuit so that the base current is zero. The collector current should also be zero. Measure the corresponding collector-emitter voltage, Vervem. Record both Tem and Ves in Table 9-2. At saturation, Vorisay is ideally zero, while at cutoff, Icom is zero. Plot the values for Jc and Vog at cutoff and saturation on the graph constructed in Step 6. You should find that both points lie essentially on the dc load line very close to the ideal endpoints of cutoff and saturation. If you disconnected the potentiometer in Step 10, reconnect, the potentiometer as in Step 8. Vary the potentiometer so that you are able to measure about five combinations of Tc and Veg over the active region of the de loan line, recording all values, in Table 9-2. Then plot these values on the graph. As in Step 10, each point should lie essentially on the de load line, as the load line is a plot of all possible combinations of Ic and Vor. WHAT YOU HAVE DONE This experiment verified the voltages and currents in a base-biased circuit as well as constructing the de load line for the circuit. In addition, the effect of temperature on the stability of the bias circuit was also demonstrated.Name —_______________ Date TRANSISTOR BASE BIASING OBJECTIVES/PURPOSE: SCHEMATIC DIAGRAM: (©1932 Macmilan Publishing Company. Al rights reserved 93Nere ee Data) DATA FOR EXPERIMENT 9 TABLE 9-1 ‘Transistor 2 Measured | Expected | Measured | Expected Parameter | Value Value Value Value In L Ie | Orv ory (typical) (typical) Ya Vox ‘TABLE 9-2 Calculated Values, ‘Measured Values Condition Te Vor Te Vow Saturation (Step 9) Cutott (Step 10) Active Region (Step 11) (©1992 Macmilan Publishing Company. Al rights reserved.Name —_________________ Date ___ DATA FOR EXPERIMENT 9 (©1992 Macmitan Publishing Company. Al rights reservedName ___________________ Date RESULTS AND CONCLUSIONS: REVIEW QUESTIONS FOR EXPERIMENT 9 1. For the circuit of Figure 9-1, if 8 = 150, then Ip is (@) 10 nA) 15 nA (©) 204A (@) 25 uA 2. If of the transistor in the circuit of Figure 9-1 increases, then (@) Ip decreases (b) Ic increases (©) Vor decreases (d) all of the above 3. If Ry is made smaller in the circuit of Figure 9-1, then (a) [y decreases (b) Ic increases (©) Ver decreases _(€) all of the above 4. The collector saturation current for the circuit of Figure 9-1 is approximately (@)4mA_ (b) 6mA_ (©) 10mA__@) 15 mA 5. At cutoff, the collector-to-emitter voltage for the circuit of Figure 9-1is @5V @)75V @10V (a 15V c ) 96 ©1992 Macmillan Publishing Company. All rights reserved.TRANSISTOR EMITTER BIASING PURPOSE AND BACKGROUND ‘The purpose of this experiment is to verify the voltages and currents in an emitter-biased circuit as well as to construct its de load line. Unlike other biasing schemes, emitter bias uses both a positive and a negative supply voltage. In this manner, the base is approximately at ground while the negative emitter supply voltage forward biases the base-emitter junction. Text References: 5-1, The DC Operating Point; 5-3, Emitter Bias, REQUIRED PARTS AND EQUIPMENT Resistors (1/4 W): Two 0-16 V de power 1 Two 1 ko. supplies O47Ko (VOM or DMM (preferred) (J ‘Two 2N3904 npn silicon 1 Breadboarding socket transistorsUSEFUL FORMULAS Quiescent de emitter voltage () Ve = Ver ~ Vas Quiescent de base voltage (2) Va = Vex — TeRe ~ Vox Quiescent de collector (emitter) current Ver - Var Re + @s/B) Quiescent de base current @ Ic= Uc = Iz for large 8) Vp Ver — Vp Quiescent de collector-to-emitter voltage (5) Ver = Vee — IcRe + Vaz de load line Veo + Veg Ro +Re (D Vexiam = Veo + Vee (cutoff) Iason Re @ Re > Fe eB 6) Towa (saturation) (9) Vex > Vor PROCEDURE 1. Wire the circuit shown in the schematic diagram of Figure 10-1, and apply power to the breadboard. 2. With your VOM or DMM, measure the base, emitter and collec- tor voltages, with respect to ground, and measure the base and collector currents, recording your values in Table 10-1. From these two sets of values, determine the de current gain, or beta (B), for this transistor so that ale Bac Is Record this value of de beta in Table 10-1.Re Tha % % 2N3904 Rs Ve 47a Re ke -v FIGURE 10-1 Schematic diagram of circuit. ‘Then measure Ver, and record your results in Table 10-1, Compare these values and those of Steps 2 and 3 with the ex- pected values, using the value of beta determined in Step 2 and a typical base-emitter voltage of 0.7 V. Record these values in Table 10-1. 5. Now use a hand-held hair dryer to blow hot air against the transistor’s ease for a few seconds while measuring the emitter current using your VOM or DMM. Does the emitter current increase or decrease? ‘You should find that the emitter current increases, which in turn causes the circuit's Q point to change. 6. Using Equations 6 and 7 in the “Useful Formulas” section of this experiment, determine the saturation and cutoff points on the de load line for this circuit, and record these values in Table 10-2. On the blank graph provided, plot the de load line, using the calculated values of Icisay and Voevon as the endpoints of the load line. Now plot the Q point based on the measured values of Ic and Vor on the same graph. What do you notice about the Q point? ‘You should find that the measured Q point lies essentially on the de load line. 7. Using a different 2N3904 transistor, repeat Steps 2 through 5, and record your results in Table 10-1. Do you find any differ- ences between the two transistors? ‘You will usually find that the two transistors give different values for the quiescent voltages and currents. In addition, you will usually find differences in the current gains. 3. 4100 WHAT YOU HAVE DONE ‘This experiment verified the voltages and currents in an emitter- biased circuit using two power supplies as well as constructing the dc load line for the circuit. In addition, the effect of temperature on the stability of the bias circuit was also demonstrated.[Nar ee een E Data) TRANSISTOR EMITTER BIASING OBJECTIVES/PURPOSE: SCHEMATIC DIAGRAM: (© 1992 Macmillan Publishing Company Al rights reserved 101Name — DATA FOR EXPERIMENT 10 TABLE 10-1 Date ‘Transistor 1 ‘Transistor 2 Measured | Expected | Measured | Expected Parameter | Value Value Value Value Ie hn [ uo || | Ye Ve Ve Vee TABLE 10-2 Parameter | Calculated Value Ves v Tovey mA 102 (©1992 Macmitan Publishing Company. Alright reservedName EE Date) DATA FOR EXPERIMENT 10Name —_____ Date RESULTS AND CONCLUSIONS REVIEW QUESTIONS FOR EXPERIMENT 10 1. For the circuit of Figure 10-1, if B = 100, then Ve is @6V @)8V (@)10V @ bv 2. If B increases for the transistor of Figure 10-1, then (a) Ic decreases (b) Vg decreases (©) Voz decreases (d) all of the above 3. If Rp is made smaller in the cireuit of Figure 10-1, then (a) Ig decreases —_(b) Ic increases (©) Vex increases _(d) all of the above 4, The collector saturation current for the circuit of Figure 10-1 is approximately (a) 4mA_(b) 7.5 mA (©) 11.5 mA A) 23. mA 5. At cutoff, the collector-to-emitter voltage for the circuit of Figure 10-1 is @6V )8V (bv @23V ) 104 (©1992 Macmillan Pubishing Company. Al rights reserved.