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OPA1688, OPA1689
Burr-Brown Audio SBOS724 – SEPTEMBER 2015

OPA168x
SoundPlus 36-V, Single-Supply, 10-MHz, Rail-to-Rail Output Operational Amplifiers
1 Features 3 Description
•
1 THD+N, 50 mW, 32 Ω, 1 kHz, –109 dB The OPA1688 and OPA1689 are a family of
SoundPlus™ 36-V, single-supply, low-noise
• Wide Supply Range: operational amplifiers capable of operating on
– 4.5 V to 36 V, ±2.25 V to ±18 V supplies ranging from 4.5 V (±2.25 V) to 36 V
• Low Offset Voltage: ±0.25 mV (±18 V). This latest addition of high-voltage audio
operational amplifiers, in conjunction with the
• Low Offset Drift: ±0.5 µV/°C
OPA16xx devices provide a family of bandwidth,
• Gain Bandwidth: 10 MHz noise, and power options to meet the needs of a wide
• Low Input Bias Current: ±10 pA variety of applications. The OPA168x are available in
• Low Quiescent Current: 1.6 mA per Amplifier micropackages, and offer low offset, drift, and
quiescent current. These devices also offer wide
• Low Noise: 8 nV/√Hz bandwidth, fast slew rate, and high output current
• EMI- and RFI-Filtered Inputs drive capability. The dual and quad versions all have
• Input Range Includes Negative Supply identical specifications for maximum design flexibility.
• Input Range Operates to Positive Supply Unlike most op amps that are specified at only one
• Rail-to-Rail Output supply voltage, the OPA168x family is specified from
4.5 V to 36 V. Input signals beyond the supply rails
• High Common-Mode Rejection: 120 dB
do not cause phase reversal. The input can operate
• Industry-Standard Packages: 100 mV below the negative rail and within 2 V of the
– SOIC-8 and SOIC-14 top rail during normal operation. Note that these
• microPackages: devices can operate with full rail-to-rail input 100 mV
beyond the top rail, but with reduced performance
– Dual in WSON-8, Quad in VQFN-16 within 2 V of the top rail.

2 Applications The OPA168x series of op amps are specified from

–40°C to 85°C.
• Headphone Driver
• Analog and Digital Mixers Device Information(1)
• Audio Effects Processors PART NUMBER PACKAGE BODY SIZE (NOM)

• Transducer Amplifiers SOIC (8) 4.90 mm × 3.91 mm

OPA1688
WSON (8) 3.00 mm × 3.00 mm
• Musical Instruments
SOIC (14) 8.65 mm × 3.91 mm
• A/V Receivers OPA1689(2)
VQFN (16) 3.50 mm × 3.50 mm
• DVD and Blu-Ray™ Players
(1) For all available packages, see the orderable addendum at
• Car Audio Systems the end of the datasheet.
(2) Product-preview device.

Headphone Amplifier Circuit Configuration Superior THD Performance

C1
(f = 1 kHz, BW = 80 kHz, VS = ±5 V)
47pF
1 -40
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)

R1 R2
ROUT 768 750
0.1 -60
VAC -5 V
Inverting
- Headphone
++ Output
+

VDC OPA1688 0.01 -80

VAC R3 5V Noninverting
ROUT 768
0.001 16- Load -100
R4 C2 32- Load
Audio DAC 750 47pF
128- Load
0.0001 -120
0.001 0.01 0.1 1 10

1
Amplitude (VRMS) C004

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
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Table of Contents
1 Features .................................................................. 1 9.3 Feature Description................................................. 19
2 Applications ........................................................... 1 9.4 Device Functional Modes........................................ 21
3 Description ............................................................. 1 10 Applications and Implementation...................... 24
4 Revision History..................................................... 2 10.1 Application Information.......................................... 24
10.2 Typical Application ................................................ 24
5 Device Comparison Table..................................... 3
6 Device Family Comparison Table ........................ 3 11 Power Supply Recommendations ..................... 28
7 Pin Configuration and Functions ......................... 3 12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
8 Specifications......................................................... 5
12.2 Layout Example .................................................... 29
8.1 Absolute Maximum Ratings ...................................... 5
8.2 ESD Ratings.............................................................. 5 13 Device and Documentation Support ................. 30
13.1 Device Support...................................................... 30
8.3 Recommended Operating Conditions....................... 5
13.2 Documentation Support ........................................ 30
8.4 Thermal Information: OPA1688 ................................ 6
13.3 Related Links ........................................................ 30
8.5 Thermal Information: OPA1689 ................................ 6
13.4 Community Resources.......................................... 30
8.6 Electrical Characteristics........................................... 7
13.5 Trademarks ........................................................... 31
8.7 Typical Characteristics: Table of Graphs .................. 9
13.6 Electrostatic Discharge Caution ............................ 31
8.8 Typical Characteristics ............................................ 10
13.7 Glossary ................................................................ 31
9 Detailed Description ............................................ 18
9.1 Overview ................................................................. 18 14 Mechanical, Packaging, and Orderable
Information ........................................................... 31
9.2 Functional Block Diagram ....................................... 18

4 Revision History
DATE REVISION NOTES
September 2015 * Initial release.

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5 Device Comparison Table

DEVICE (1) PACKAGE

OPA1688 (dual) SOIC-8, WSON-8
OPA1689 (quad) SOIC-14, VQFN-16

(1) The OPA1688 SOIC-8 and WSON-8 packages are production data. The OPA1689 SOIC-14 and VQFN-16 packages are product
preview.

6 Device Family Comparison Table

QUIESCENT CURRENT GAIN BANDWIDTH PRODUCT VOLTAGE NOISE DENSITY

DEVICE (IQ) (GBP) (en)
OPA168x 1650 µA 10 MHz 8 nV/√Hz
OPA165x 2000 µA 18 MHz 4.5 nV/√Hz
OPA166x 1500 µA 22 MHz 3.3 nV/√Hz

7 Pin Configuration and Functions

D Package: OPA1688 DRG Package: OPA1688

SOIC-8 WSON-8
Top View Top View

OUT A 1 8 V+ +IN A 1 8 -IN A

A
-IN A 2 7 OUT B V+ 2 7 OUT A
+IN A 3 6 -IN B
V- 3 6 OUT B
B
V- 4 5 +IN B
+IN B 4 5 -IN B

D Package: OPA1689
SOIC-14 RVA Package: OPA1689
Top View VQFN-16
Top View
14 OUT D
15 OUT A

13 -IN D

OUT A 1 14 OUT D
16 -IN A

-IN A 2 13 -IN D

+IN A 3 12 +IN D

V+ 4 11 V- +IN A 1 12 +IN D
A D
+IN B 5 10 +IN C V+ 2 11 V-

-IN B 6 9 -IN C NC 3 10 NC
B C
OUT B 7 8 OUT C +IN B 4 9 +IN C
5

8
-IN B

OUT B

OUT C

-IN C

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Pin Functions: OPA1688

PIN
OPA1688
DRG
NAME D (SOIC) (WSON) I/O DESCRIPTION
+IN A 3 1 I Noninverting input, channel A
+IN B 5 4 I Noninverting input, channel B
–IN A 2 8 I Inverting input, channel A
–IN B 6 5 I Inverting input, channel B
OUT A 1 7 O Output, channel A
OUT B 7 6 O Output, channel B
V+ 8 2 — Positive (highest) power supply
V– 4 3 — Negative (lowest) power supply

Pin Functions: OPA1689

PIN
OPA1689
NAME D RVA I/O DESCRIPTION
+IN A 3 1 I Noninverting input, channel A
+IN B 5 4 I Noninverting input, channel B
+IN C 10 9 I Noninverting input, channel C
+IN D 12 12 I Noninverting input, channel D
–IN A 2 16 I Inverting input, channel A
–IN B 6 5 I Inverting input, channel B
–IN C 9 8 I Inverting input, channel C
–IN D 13 13 I Inverting input, channel D
OUT A 1 15 O Output, channel A
OUT B 7 6 O Output, channel B
OUT C 8 7 O Output, channel C
OUT D 14 14 O Output, channel D
V+ 4 2 — Positive (highest) power supply
V– 11 11 — Negative (lowest) power supply
NC — 3, 10 — No connection

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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VS ±20 (40, single supply) V
Common-mode (V–) – 0.5 (V+) + 0.5 V
Voltage (2)
Signal input pins Differential (3) ±0.5 V
Current ±10 mA
Output short circuit (4) Continuous
Temperature range –55 150 °C
Temperature Junction temperature 150 °C
Storage, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transient conditions that exceed these voltage ratings should be current limited to 10 mA or less.
(3) See the Electrical Overstress section for more information.
(4) Short-circuit to ground, one amplifier per package.

8.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage (V+ – V–) 4.5 (±2.25) 36 (±18) V
Specified temperature –40 85 °C

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8.4 Thermal Information: OPA1688

OPA1688
THERMAL METRIC (1) D (SOIC) DRG (WSON) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 116.1 63.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 69.8 63.5 °C/W
RθJB Junction-to-board thermal resistance 56.6 36.5 °C/W
ψJT Junction-to-top characterization parameter 22.5 1.4 °C/W
ψJB Junction-to-board characterization parameter 56.1 36.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 6.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

8.5 Thermal Information: OPA1689

OPA1689
(1)
THERMAL METRIC D (SOIC) RVA (VQFN) UNIT
14 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 82.7 TBD °C/W
RθJC(top) Junction-to-case (top) thermal resistance 42.3 TBD °C/W
RθJB Junction-to-board thermal resistance 37.3 TBD °C/W
ψJT Junction-to-top characterization parameter 8.9 TBD °C/W
ψJB Junction-to-board characterization parameter 37 TBD °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A TBD °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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8.6 Electrical Characteristics

At TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO PERFORMANCE
0.00005%
G = 1, f = 1 kHz, VO = 3.5 VRMS , RL = 2 kΩ
–126 dB
0.000051%
G = 1, f = 1 kHz, VO = 3.5 VRMS , RL = 600 Ω
–126 dB

Total harmonic distortion 0.000153%

THD+N G = 1, f = 1 kHz, PO = 10 mW, RL = 128 Ω
+ noise –116 dB
0.000357%
G = 1, f = 1 kHz, PO = 10 mW, RL = 32 Ω
–109 dB
0.000616%
G = 1, f = 1 kHz, PO = 10 mW, RL = 16 Ω
–104 dB
FREQUENCY RESPONSE
GBP Gain bandwidth product G=1 10 MHz
SR Slew rate G=1 8 V/µs
Full-power bandwidth (1) VO = 1 VPP 1.3 MHz
Overload recovery time VIN × gain > VS 200 ns
Channel separation
f = 1 kHz –120 dB
(dual)
tS Settling time To 0.1%, VS = ±18 V, G = 1, 10-V step 3 µs
NOISE
En Input voltage noise f = 0.1 Hz to 10 Hz 2.5 µVPP

Input voltage noise f = 100 Hz 14

en nV/√Hz
density (2) f = 1 kHz 8
Input current noise
in f = 1 kHz 1.8 fA/√Hz
density
OFFSET VOLTAGE
TA = 25°C ±0.25 ±1.5
VOS Input offset voltage mV
TA = –40°C to 85°C ±1.6
dVOS/dT VOS over temperature (2) TA = –40°C to 85°C ±0.5 ±2 µV/°C
Power-supply rejection
PSRR TA = –40°C to 85°C ±1 ±2.5 µV/V
ratio
Channel separation, dc At dc 0.1 µV/V
INPUT BIAS CURRENT
TA = 25°C ±10 ±20 pA
IB Input bias current
TA = –40°C to 85°C ±1.5 nA
TA = 25°C ±3 ±7 pA
IOS Input offset current
TA = –40°C to 85°C ±250 pA
INPUT VOLTAGE RANGE
Common-mode voltage
VCM (V–) – 0.1 V (V+) – 2 V V
range (3)
VS = ±2.25 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
90 104
Common-mode rejection TA = –40°C to 85°C
CMRR dB
ratio VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
104 120
TA = –40°C to 85°C
INPUT IMPEDANCE
Differential 100 || 7 MΩ || pF
Common-mode 6 || 1.5 1012Ω || pF

(1) Full-power bandwidth = SR / (2π × VP), where SR = slew rate.

(2) Specified by design and characterization.
(3) Common-mode range can extend to the top rail with reduced performance.

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Electrical Characteristics (continued)

At TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPEN-LOOP GAIN
(V–) + 0.35 V < VO < (V+) – 0.35 V, RL = 10 kΩ,
108 130
TA = –40°C to 85°C
AOL Open-loop voltage gain dB
(V–) + 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ,
118
TA = –40°C to 85°C
OUTPUT
IL = ±1 mA (V–) + 0.1 V (V+) – 0.1 V
Voltage output swing
VO VS = 36 V, RL = 10 kΩ 70 90 mV
from rail
VS = 36 V, RL = 2 kΩ 330 400
Open-loop output
ZO f = 1 MHz, IO = 0 A 60 Ω
impedance
ISC Short-circuit current ±75 mA
CLOAD Capacitive load drive See the Typical Characteristics pF
POWER SUPPLY
VS Specified voltage range 4.5 36 V

Quiescent current per IO = 0 A 1.6 1.8

IQ mA
amplifier IO = 0 A, TA = –40°C to 85°C 2
TEMPERATURE RANGE
Specified range –40 85 °C
Operating range –55 125 °C

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8.7 Typical Characteristics: Table of Graphs

Table 1. List of Typical Characteristics
DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 1
Offset Voltage Drift Distribution Figure 2
Offset Voltage vs Temperature (VS = ±18 V) Figure 3
Offset Voltage vs Common-Mode Voltage (VS = ±18 V) Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5
Offset Voltage vs Power Supply Figure 6
Input Bias Current vs Common-Mode Voltage Figure 7
Input Bias Current vs Temperature Figure 8
Output Voltage Swing vs Output Current (Maximum Supply) Figure 9
CMRR and PSRR vs Frequency (Referred-to-Input) Figure 10
CMRR vs Temperature Figure 11
PSRR vs Temperature Figure 12
0.1-Hz to 10-Hz Noise Figure 13
Input Voltage Noise Spectral Density vs Frequency Figure 14
THD+N Ratio vs Frequency Figure 15
THD+N vs Output Amplitude Figure 16
THD+N vs Frequency Figure 17
THD+N vs Amplitude Figure 18
Quiescent Current vs Temperature Figure 19
Quiescent Current vs Supply Voltage Figure 20
Open-Loop Gain and Phase vs Frequency Figure 21
Closed-Loop Gain vs Frequency Figure 22
Open-Loop Gain vs Temperature Figure 23
Open-Loop Output Impedance vs Frequency Figure 24
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 25, Figure 26
Positive Overload Recovery Figure 27, Figure 28
Negative Overload Recovery Figure 29, Figure 30
Small-Signal Step Response (10 mV, G = –1) Figure 31
Small-Signal Step Response (10 mV, G = 1) Figure 32
Small-Signal Step Response (100 mV, G = –1) Figure 33
Small-Signal Step Response (100 mV, G = 1) Figure 34
Large-Signal Step Response (10 V, G = –1) Figure 35
Large-Signal Step Response (10 V, G = 1) Figure 36
Large-Signal Settling Time (10-V Positive Step) Figure 37
Large-Signal Settling Time (10-V Negative Step) Figure 38
No Phase Reversal Figure 39
Short-Circuit Current vs Temperature Figure 40
Maximum Output Voltage vs Frequency Figure 41
EMIRR vs Frequency Figure 42
Channel Separation vs Frequency Figure 43

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8.8 Typical Characteristics

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.

25 25
Percentage of Amplifiers (%)

Percentage of Amplifiers (%)

20 20

15 15

10 10

5 5

0 0
0

1
0.2

0.4

0.6

0.8

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9
-1

-0.8

-0.6

-0.4

-0.2

Offset Voltage (mV) Offset Voltage Drift (µV/ƒC)

C013 C013

Distribution taken from 5185 amplifiers Distribution taken from 47 amplifiers,

temperature = –40°C to 125°C

Figure 1. Offset Voltage Production Distribution Figure 2. Offset Voltage Drift Production Distribution
250 225
200
150 150 VCM = 16 V

100 VCM = -18.1 V

75
50
VOS ( V)

VOS ( V)

0 0
±50
±100 ±75

±150
±150
±200
±250 ±225
±75 ±50 ±25 0 25 50 75 100 125 150 ±20 ±15 ±10 ±5 0 5 10 15 20
Temperature (ƒC) C001 VCM (V) C001

5 typical units shown, VS = ±18 V 5 typical units shown, VS = ±18 V

Figure 3. Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Voltage

(VS = ±18 V) (VS = ±18 V)
20 500
400
10 Vs = ± 2.25 V
300
0 200
100
VOS ( V)
VOS (mV)

-10
0
-20 ±100

-30 ±200
±300
-40
±400
-50 ±500
14 15 16 17 18 0 2 4 6 8 10 12 14 16 18
VCM (V) C001
VSUPPLY (V) C001

5 typical units shown, VS = ±18 V 5 typical units shown, VS = ±2.25 V to ±18 V

Figure 5. Offset Voltage vs Common-Mode Voltage Figure 6. Offset Voltage vs Power Supply
(Upper Stage)

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Typical Characteristics (continued)

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
12 8000
IB+
10 IbP IB -
Ios
Input Bias Current (pA)

Input Bias Current (pA)

8 5500

6
IbN
4 3000

0 500

±2 Ios

±4 ±2000
-18 -13.5 -9 -4.5 0 4.5 9 13.5 18 ±50 ±25 0 25 50 75 100 125 150
VCM (V) C001 Temperature (ƒC) C001

TA = 25°C

Figure 7. Input Bias Current vs Common-Mode Voltage Figure 8. Input Bias Current vs Temperature
(V+) +1 140

Common-Mode Rejection Ratio (dB)

(V+) 25°C CMRR

Power-Supply Rejection Ratio (dB)

(V+) -1 ±40°C 120
(V+) -2 PSRR+
100
Output Voltage (V)

(V+) -3
125°C
(V+) -4 85°C
80
(V+) -5
(V-) +5 PSRR-
60
(V-) +4 85°C
(V-) +3 125°C 40
(V-) +2
(V-) +1 ±40°C 20
(V-) 25°C
(V-) -1 0
0 10 20 30 40 50 60 70 80 90 100 1 10 100 1k 10k 100k 1M
Output Current (mA) C011 Frequency (Hz) C006

Figure 9. Output Voltage Swing vs Output Current Figure 10. CMRR and PSRR vs Frequency
(Maximum Supply) (Referred-to-Input)
30 10
Common-Mode Rejection Ratio (µV/V)

Power-Supply Rejection Ratio (µV/V)

8
20
VS = ± 2.25 V, - 9 ” 9CM ” 9
6

10 4

2
0
0
VS = “18 V, - 9 ” 9CM ” 9

±10 ±2
±75 ±50 ±25 0 25 50 75 100 125 150 ±75 ±50 ±25 0 25 50 75 100 125 150
Temperature (ƒC) C001 Temperature (ƒC) C001

Figure 11. CMRR vs Temperature Figure 12. PSRR vs Temperature

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Typical Characteristics (continued)

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
1000

9ROWDJH 1RLVH 'HQVLW\ Q9 ¥+]

100
500 nV/div

10

1
Time (1 s/div) 0.1 1 10 100 1k 10k 100k
C001 Frequency (Hz) C002

Peak-to-peak noise = 1.70 µVPP

Figure 13. 0.1-Hz to 10-Hz Noise Figure 14. Input Voltage Noise Spectral Density vs
Frequency
0.01 -80 1. -40
G = +1 V/V, 10-k Load G = +1 V/V, 10-k Load
Total Harmonic Distortion + Noise (dB)

Total Harmonic Distortion + Noise (dB)

Total Harmonic Distortion + Noise (%)

G = +1 V/V, 2-k Load Total Harmonic Distortion + Noise (%) G = +1 V/V, 2-k Load
G = +1 V/V, 600- Load 0.1 G = -1 V/V, 10-k Load -60
G = -1 V/V, 10-k Load G = -1 V/V, 2-k Load
0.001 -100 G = -1 V/V, 600- Load
G = -1 V/V, 2-k Load
0.01 G = +1 V/V, 600- Load -80
G = -1 V/V, 600- Load

0.001 -100
0.0001 -120

0.0001 -120

0.00001 -140 0.00001 -140

10 100 1k 10k 0.01 0.1 1 10
Frequency (Hz) C007 Output Amplitude (VRMS) C008

VOUT = 3.5 VRMS, BW = 50 kHz f = 1 kHz, BW = 80 kHz

Figure 15. THD+N Ratio vs Frequency Figure 16. THD+N vs Output Amplitude
0.1 -60 1 -40

Total Harmonic Distortion + Noise (dB)

Total Harmonic Distortion + Noise (dB)

Total Harmonic Distortion + Noise (%)

G = -1, 16- Load

Total Harmonic Distortion + Noise (%)

G = -1, 32- Load

G = -1, 128- Load
0.1 -60
G = +1, 16- Load
0.01 -80
G = +1, 32- Load Inverting
G = +1, 128- Load
0.01 -80

Noninverting
0.001 -100
0.001 16- Load -100
32- Load
128- Load
0.0001 -120 0.0001 -120
10 100 1000 10000 0.001 0.01 0.1 1 10
Frequency (Hz) C003 Amplitude (VRMS) C004

POUT = 10 mW, BW = 80 kHz, VS = ±5 V f = 1 kHz, BW = 80 kHz, VS = ±5 V

Figure 17. THD+N vs Frequency Figure 18. THD+N vs Amplitude

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Typical Characteristics (continued)

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
2 2
1.9
1.8 1.8
1.7
Vs = ± 18 V
1.6 1.6
IQ (mA)

IQ (mA)
Vs = ± 2.25 V 1.5
1.4 1.4
1.3
1.2 1.2
1.1
1 1
±75 ±50 ±25 0 25 50 75 100 125 150 0 4 8 12 16 20 24 28 32 36
Temperature (ƒC) C001 Supply Voltage (V) C001

Figure 19. Quiescent Current vs Temperature Figure 20. Quiescent Current vs Supply Voltage
140 180 25

120 20

100 135 15
Open-loop Gain
10
80
Gain (dB)

Gain (dB)
Phase (º)

Phase 5
60 90
0
40
-5
20 45
-10
G = +1
0 -15 G = -10
G = -1
±20 0 -20
1 10 100 1k 10k 100k 1M 10M 1000 10k 100k 1M 10M
Frequency (Hz) C004 Frequency (Hz) C003

CLOAD = 15 pF

Figure 21. Open-Loop Gain and Phase vs Frequency Figure 22. Closed-Loop Gain vs Frequency
2 1000

1.5
100
1
Vs = 4.5 V
AOL (µV/V)

ZO ( )

0.5 10
Vs = 36 V
0
1
-0.5

-1 0
±75 ±50 ±25 0 25 50 75 100 125 150 10 100 1k 10k 100k 1M 10M 100M
Temperature (ƒC) C001 Frequency (Hz) C016

RL = 10 kΩ

Figure 23. Open-Loop Gain vs Temperature Figure 24. Open-Loop Output Impedance vs Frequency

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Typical Characteristics (continued)

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
60 50

50
40

40
Overshoot (%)

Overshoot (%)
30
30
20
20
ROUT = 0 ROUT= 0
10
10 ROUT
RO = 25
= 25 RO ==25
ROUT 25

ROUT
RO = 50
= 50 RO ==50
ROUT 50
0 0
0 100 200 300 400 500 0 100 200 300 400 500
Capacitive Load (pF) C013 Capacitive Load (pF) C013

G = –1 G=1

Figure 25. Small-Signal Overshoot vs Capacitive Load Figure 26. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step) (100-mV Output Step)

VOUT
5 V/div
5V/div

VOUT

VIN

VIN

Time (1 s/div) Time (1 s/div)

C011 C009

Figure 27. Positive Overload Recovery Figure 28. Positive Overload Recovery (Zoomed In)

VIN VIN
5 V/div

5 V/div

VOUT

VOUT

Time (1 s/div) Time (1 s/div)

C010 C010

Figure 29. Negative Overload Recovery Figure 30. Negative Overload Recovery (Zoomed In)

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Typical Characteristics (continued)

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
2 mV/div

2 mV/div
Time (200 ns/div) Time (200 ns/div)
C006 C014

RL = 1 kΩ, CL = 10 pF CL = 10 pF

Figure 31. Small-Signal Step Response (10 mV, G = –1) Figure 32. Small-Signal Step Response (10 mV, G = 1)
20 mV/div

20 mV/div

Time (200 ns/div) Time (200 ns/div)

C006 C014

RL = 1 kΩ, CL = 10 pF CL = 10 pF

Figure 33. Small-Signal Step Response (100 mV, G = –1) Figure 34. Small-Signal Step Response (100 mV, G = 1)
2 V/div

2 V/div

Time (500 ns/div) Time (500 ns/div)

C005 C014

RL = 1 kΩ, CL = 10 pF CL = 10 pF

Figure 35. Large-Signal Step Response (10 V, G = –1) Figure 36. Large-Signal Step Response (10 V, G = 1)

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Typical Characteristics (continued)

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
20 20
Output Delta from Final Value (mV)

Output Delta from Final Value (mV)

15 15

10 10

5 5

0 0

-5 ±5

-10 ±10

-15 ±15

-20 ±20
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time ( s) C034 Time ( s) C030

G = 1, CL = 10 pF, 0.1% settling = ±10 mV G = 1, CL = 10 pF, 0.1% settling = ±10 mV

Figure 37. Large-Signal Settling Time (10-V Positive Step) Figure 38. Large-Signal Settling Time (10-V Negative Step)
100

VOUT
75
ISC, Sink “ 18 V
5 V/div

ISC (mA)

50

ISC, Source ± 18 V
VIN 25

0
Time (200 s/div) ±75 ±50 ±25 0 25 50 75 100 125 150
C011 Temperature (ƒC) C001

Figure 39. No Phase Reversal Figure 40. Short-Circuit Current vs Temperature

160
30
VS = ±15 V
Maximum output voltage without 140
25 slew-rate induced distortion.
120
Output Voltage (VPP)

20
EMIRR (dB)

100

15 80

VS = ±5 V 60
10
40
VS = ±2.25 V
5
20

0 0
10k 100k 1M 10M 10M 100M 1G 10G
Frequency (Hz) C033 Frequency (Hz) C017

PRF = –10 dBm, VSUPPLY = ±18 V, VCM = 0 V

Figure 41. Maximum Output Voltage vs Frequency Figure 42. EMIRR vs Frequency

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Typical Characteristics (continued)

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
0

±20

Channel Separation (dB)

±40

±60

±80

±100

±120

±140

±160
100 1k 10k 100k 1M 10M
Frequency (Hz) C027

Figure 43. Channel Separation vs Frequency

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9 Detailed Description

9.1 Overview
The OPA168x family of operational amplifiers provide high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 1.5 µV/°C (max) provides excellent stability over
the entire temperature range. In addition, the device offers very good overall performance with high CMRR,
PSRR, AOL, and superior THD.
The Functional Block Diagram section shows the simplified diagram of the OPA168x design. The design
topology is a highly-optimized, three-stage amplifier with an active-feedforward gain stage.

9.2 Functional Block Diagram

PCH
FF Stage

Ca

Cb

+IN
PCH Output
2nd Stage OUT
Input Stage Stage
-IN

NCH
Input Stage

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9.3 Feature Description

9.3.1 EMI Rejection
The OPA168x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPA168x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 44 shows the results of this testing on the OPA168x. Table 2 shows the EMIRR IN+ values for the
OPA168x at particular frequencies commonly encountered in real-world applications. Applications listed in
Table 2 can be centered on or operated near the particular frequency shown. Detailed information can also be
found in application report SBOA128, EMI Rejection Ratio of Operational Amplifiers, available for download from
www.ti.com.
160

140

120
EMIRR (dB)

100

80

60

40

20

0
10M 100M 1G 10G
Frequency (Hz) C017

PRF = –10 dBm, VSUPPLY = ±18 V, VCM = 0 V

Figure 44. EMIRR Testing

Table 2. OPAx168x EMIRR IN+ for Frequencies of Interest

FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, and ultrahigh
400 MHz 47.6 dB
frequency (UHF) applications
Global system for mobile communications (GSM) applications, radio
900 MHz communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, and 58.5 dB
UHF applications
GSM applications, mobile personal communications, broadband, satellite, and L-
1.8 GHz 68 dB
band (1 GHz to 2 GHz)
®
802.11b, 802.11g, 802.11n, Bluetooth , mobile personal communications,
2.4 GHz industrial, scientific and medical (ISM) radio band, amateur radio and satellite, and 69.2 dB
S-band (2 GHz to 4 GHz)
3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, and S-band 82.9 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
5.0 GHz 114 dB
space and satellite operation, and C-band (4 GHz to 8 GHz)

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9.3.2 Phase-Reversal Protection

The OPA168x family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPA168x prevents phase reversal with excessive common-mode
voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 45.

VOUT

5 V/div

VIN

Time (200 s/div)

C011

Figure 45. No Phase Reversal

9.3.3 Capacitive Load and Stability

The dynamic characteristics of the OPA168x are optimized for commonly-used operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and
may lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.
The simplest way to achieve this isolation is to add a small resistor (for example, ROUT = 50 Ω) in series with the
output. Figure 46 and Figure 47 show graphs of small-signal overshoot versus capacitive load for several values
of ROUT; see application bulletin SBOA015 (AB-028), Feedback Plots Define Op Amp AC Performance, available
for download from www.ti.com, for details of analysis techniques and application circuits.

60 50

50
40

40
Overshoot (%)

Overshoot (%)

30
30
20
20
ROUT = 0 ROUT= 0
10
10 ROUT
RO = 25
= 25 RO ==25
ROUT 25

ROUT
RO = 50
= 50 RO ==50
ROUT 50
0 0
0 100 200 300 400 500 0 100 200 300 400 500
Capacitive Load (pF) C013 Capacitive Load (pF) C013

G = –1 G=1

Figure 46. Small-Signal Overshoot vs Capacitive Load Figure 47. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step) (100-mV Output Step)

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9.4 Device Functional Modes

9.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPA168x series extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in Table 3.

Table 3. Typical Performance Range (VS = ±18 V)

PARAMETER MIN TYP MAX UNIT
Input common-mode voltage (V+) – 2 (V+) + 0.1 V
Offset voltage 5 mV
Offset voltage vs temperature (TA = –40°C to 85°C) 10 µV/°C
Common-mode rejection 70 dB
Open-loop gain 60 dB
Gain bandwidth product (GBP) 4 MHz
Slew rate 4 V/µs
Noise at f = 1 kHz 22 nV/√Hz

9.4.2 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful.
Figure 48 illustrates the ESD circuits contained in the OPA168x (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.

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TVS

RF

+
±
+VS

R1 IN± 250 Ÿ

RS IN+ 250 Ÿ
+
Power-Supply
ID ESD Cell RL
+
VIN ±

+
±
±VS

TVS

Figure 48. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA168x but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (Figure 48), the ESD protection components are intended
to remain inactive and do not become involved in the application circuit operation. However, circumstances may
arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there
is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs
through steering-diode paths and rarely involves the absorption device.
Figure 48 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.

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Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (+VS or –VS) are at 0 V. Again, this question depends on the supply characteristic when at
0 V, or at a level below the input-signal amplitude. If the supplies appear as high impedance, then the input
source supplies the operational amplifier current through the current-steering diodes. This state is not a normal
bias condition; most likely, the amplifier will not operate normally. If the supplies are low impedance, then the
current through the steering diodes can become quite high. The current level depends on the ability of the input
source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external zener diodes to the
supply pins; see Figure 48. Select the zener voltage so that the diode does not turn on during normal operation.
However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The OPA168x input pins are protected from excessive differential voltage with back-to-back diodes; see
Figure 48. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1
circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition,
limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series
resistor can be used to limit the input signal current. This input series resistor degrades the low-noise
performance of the OPA168x. Figure 48 illustrates an example configuration that implements a current-limiting
feedback resistor.

9.4.3 Overload Recovery

Overload recovery is defined as the time required for the op amp output to recover from the saturated state to
the linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds
the rated operating voltage, either resulting from the high input voltage or the high gain. After the device enters
the saturation region, the charge carriers in the output devices need time to return back to the normal state. After
the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. Thus,
the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew
time. The overload recovery time for the OPA168x is approximately 200 ns.

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10 Applications and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

The OPA168x family of amplifiers is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the
specifications apply from –40°C to 85°C. Parameters that can exhibit significant variance with regard to operating
voltage or temperature are presented in the Typical Characteristics.

10.2 Typical Application

This application example highlights only a few of the circuits where the OPA168x can be used.
C1
47pF

R1 R2
ROUT 768 750

VAC -5 V

- Headphone
++ Output
+

VDC OPA1688
VAC R3 5V
ROUT 768

R4 C2
Audio DAC 750 47pF

Figure 49. Headphone Amplifier Circuit Configuration for Audio DACs that Output a Differential Voltage
(Single Channel Shown)

10.2.1 Design Requirements

The design requirements are:
• Supply voltage: 10 V (±5 V)
• Headphone loads: 16 Ω to 600 Ω
• THD+N: > 100 dB (1-kHz fundamental, 1 VRMS in 32 Ω, 22.4-kHz measurement bandwidth)
• Output power (before clipping): 50 mW into 32 Ω

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Typical Application (continued)

10.2.2 Detailed Design Procedure
The OPA168x family offers an excellent combination of specifications for headphone amplifier circuits (such as
low noise, low distortion, capacitive load stability, and relatively high output current). Furthermore, the low-power
supply current and small package options make the OPA1688 an exceptionally good choice for headphone
amplifiers in portable devices. A common headphone amplifier circuit for audio digital-to-analog converters
(DACs) with differential voltage outputs is illustrated in Figure 49. This circuit converts the differential voltage
output of the DAC to a single-ended, ground-referenced signal and provides the additional current necessary for
low-impedance headphones. For R2 = R4 and R1 = R3, the output voltage of the circuit is given by Equation 1:
R2
VOUT = 2 u VAC
R 1 + R OUT
where
• ROUT is the output impedance of the DAC and
• 2 × VAC is the unloaded differential output voltage (1)
The output voltage required for headphones depends on the headphone impedance as well as the headphone
efficiency. Both values can be provided by the headphone manufacturer, with headphone efficiency usually given
as a sound pressure level (SPL) produced with 1 mW of input power and denoted by the Greek letter η. The SPL
at other input power levels can be calculated from the efficiency specification using Equation 2:
§ P ·
SPL (dB) K 10 log ¨ IN ¸
© 1 mW ¹ (2)
Note that at extremely high power levels, the accuracy of this calculation decreases as a result of secondary
effects in the headphone drivers. Figure 50 allows the SPL produced by a pair of headphones of a known
sensitivity to be estimated for a given input power.
10000
90-dB SPL 95-dB SPL
100-dB SPL 105-dB SPL
1000 110-dB SPL 115-dB SPL
120-dB SPL

100
Power (mW)

10

0.1

0.01
90 95 100 105 110 115
Headphone Efficiency (dB/mW)
C001

Figure 50. SPLs Produced for Various Headphone Efficiencies and Input Power Levels

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Typical Application (continued)

For example, a pair of headphones with a 95-dB/mW sensitivity given a 3-mW input signal produces a 100-dB
SPL. If these headphones have a nominal impedance of 32 Ω, then the voltage and current from the headphone
amplifier is as described in Equation 3 and Equation 4, respectively:
V PIN u RHP 3 mW u 32 : 310 mVRMS (3)
PIN 3 mW
I 9.68 mARMS
RHP 32 : (4)
Headphones can present a capacitive load at high frequencies that can destabilize the headphone amplifier
circuit. Many headphone amplifiers use a resistor in series with the output to maintain stability; however this
solution also compromises audio quality. The OPA168x family is able to maintain stability into large capacitive
loads; therefore, a series output resistor is not necessary in the headphone amplifier circuit. TINA-TI™
simulations illustrate that the circuit in Figure 49 has a phase margin of approximately 50 degrees with a 400-pF
load connected directly to the amplifier output.

10.2.3 Application Curves

The headphone amplifier circuit in Figure 49 is tested with three common headphone impedances: 16 Ω, 32 Ω,
and 600 Ω. The total harmonic distortion and noise (THD+N) for increasing output voltages is given in Figure 51.
This measurement is performed with a 1-kHz input signal and a measurement bandwidth of 22.4 kHz. The
maximum output power and THD+N before clipping are given in Table 4. The maximum output power into low-
impedance headphones is limited by the output current capabilities of the amplifier. For high-impedance
headphones (600 Ω), the output voltage capabilities of the amplifier are the limiting factor. The circuit in Figure 49
is tested using ±5-V supplies that are common in many portable systems. However, using higher supply voltages
increases the output power into 600-Ω headphones.
0

-20
Total Harmonic Distortion + Noise (dB)

-40

-60

-80

-100

-120
0.001 0.01 0.1 1 10
Amplitude (VRMS)
C002

Figure 51. THD+N for Increasing Output Voltages Into Three Load Impedances
(Input Signal = 1 kHz, Measurement Bandwidth = 22.4 kHz)

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Typical Application (continued)

Table 4. Maximum Output Power and THD+N Before Clipping for Different Load Impedances
MAXIMUM OUTPUT POWER BEFORE THD+N AT MAXIMUM OUTPUT POWER
LOAD IMPEDANCE (Ω)
CLIPPING (mW) (dB)
16 32 –104.1
32 50 –109.5
600 16 –117.8

Figure 52, Figure 53, and Figure 54 further illustrate the exceptional performance of the OPA1688 as a
headphone amplifier.
Figure 52 shows the THD+N over frequency for a 500-mVRMS output signal into the same three load impedances
previously tested.
Figure 53 and Figure 54 show the output spectrum of the OPA1688 at low (1 mW) and high (50 mW) output
power levels into a 32-Ω load. The distortion harmonics in both cases are approximately 120 dB below the
fundamental.

0 0
Total Harmonic Distortion + Noise (dB)

±20
±20
±40
±40 Amplitude (dBc)
±60

±60 ±80

±100
±80
±120
±100
±140

±120 ±160
10 100 1000 10000 0 5000 10000 15000 20000
Frequency (Hz) C003 Frequency (Hz) C001

Figure 52. THD+N Measured over Frequency (90-kHz Figure 53. Output Spectrum of a
Measurement Bandwidth) for a 500-mVRMS Output Level 1-mW, 1-kHz Tone into a 32-Ω Load
(The third harmonic is dominant at a level of –117.6 dB
relative to the fundamental.)

±20

±40
Amplitude (dBc)

±60

±80

±100

±120

±140

±160
0 5000 10000 15000 20000
Frequency (Hz) C001

Figure 54. Output Spectrum of a 50-mW, 1-kHz Tone Into a

32-Ω Load, Immediately Below the Onset of Clipping
(The highest harmonic is the second harmonic at
–119 dB below the fundamental.)

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11 Power Supply Recommendations

The OPA168x is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to 85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.

CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.

12 Layout

12.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed
information, see SLOA089, Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 55, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.

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12.2 Layout Example

RIN
VIN +
RG VOUT

RF

(Schematic Representation)

Place components
Run the input traces close to device and to
as far away from each other to reduce
the supply lines parasitic errors VS+
as possible RF

NC NC
RG
GND ±IN V+ GND

VIN +IN OUT

RIN
Use low-ESR, ceramic
V± NC
bypass capacitor

Only needed for

dual-supply GND VS± VOUT
operation (or GND for single supply) Ground (GND) plane on another layer

Figure 55. Operational Amplifier Board Layout for a Noninverting Configuration

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Links: OPA1688 OPA1689
OPA1688, OPA1689
SBOS724 – SEPTEMBER 2015 www.ti.com

13 Device and Documentation Support

13.1 Device Support

13.1.1 Development Support

13.1.1.1 TINA-TI™ (Free Software Download)

TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.

13.2 Documentation Support

13.2.1 Related Documentation
SBOA015 (AB-028) — Feedback Plots Define Op Amp AC Performance
SBOA128 — EMI Rejection Ratio of Operational Amplifiers
SLOA089 — Circuit Board Layout Techniques
SLOD006 — Op Amps for Everyone
TIPD128 — Capacitive Load Drive Solution using an Isolation Resistor

13.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 5. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
OPA1688 Click here Click here Click here Click here Click here
OPA1689 Click here Click here Click here Click here Click here

13.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

30 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: OPA1688 OPA1689

 OPA1688, OPA1689
www.ti.com SBOS724 – SEPTEMBER 2015

13.5 Trademarks
E2E is a trademark of Texas Instruments.
SoundPlus is a trademark of Texas Instruments, Inc.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Blu-Ray is a trademark of Blu-ray Disc Association (BDA).
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 31

Product Folder Links: OPA1688 OPA1689
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA1688ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 O1688A

OPA1688IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 O1688A

OPA1688IDRGR ACTIVE SON DRG 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OP1688

OPA1688IDRGT ACTIVE SON DRG 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OP1688

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Oct-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1688IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA1688IDRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA1688IDRGT SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Oct-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA1688IDR SOIC D 8 2500 853.0 449.0 35.0
OPA1688IDRGR SON DRG 8 3000 367.0 367.0 35.0
OPA1688IDRGT SON DRG 8 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DRG0008A SCALE 5.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

3.1 B
A
2.9

3.1
PIN 1 INDEX AREA 2.9

0.8
0.7
C

SEATING PLANE
0.05
0.00 0.08 C

(0.2) TYP
EXPOSED 1.2 0.1
THERMAL PAD

4
5

2X
1.5 2 0.1

8
1
6X 0.5
0.3
8X
0.2
PIN 1 ID 0.6
8X 0.1 C A B
0.4
0.08 C

4218885/A 03/2020
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRG0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(1.2)

8X (0.7) SYMM

1 8

8X (0.25)

SYMM (2)

(0.75)
6X (0.5)
4 5

(R0.05) TYP
( 0.2) VIA (0.35)
TYP
(2.7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

EXPOSED EXPOSED
METAL METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4218885/A 03/2020
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRG0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM METAL
8X (0.7)
TYP

8X (0.25) 1 8

SYMM
(1.79)

6X (0.5)
4
5

(R0.05) TYP
(1.13)

(2.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4218885/A 03/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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