OPA863, OPA2863, OPA4863

SBOS982J – JUNE 2020 – REVISED JUNE 2023

OPAx863 Low-Power, 110-MHz, Rail-to-Rail Input/Output Voltage-Feedback Op Amps

1 Features 3 Description
• Wide-bandwidth The OPAx863 devices are low-power, unity-gain
– Unity-gain bandwidth: 110-MHz (AV= 1 V/V) stable, rail-to-rail input and output, voltage-feedback
– Gain-bandwidth product: 50-MHz operational amplifiers designed to operate over a
• Low power power-supply range of 2.7 V to 12.6 V. Consuming
– Quiescent current: 700-µA/ch (typical) only 700 µA per channel, the OPAx863 offers a gain-
– Power down mode: 1.5-µA (maximum, VS= 3 V) bandwidth product of 50 MHz, slew rate of 105 V/µs
– Supply voltage: 2.7-V to 12.6-V with a voltage noise density of 5.9 nV/√Hz.
• Input voltage noise: 5.9-nV/√Hz The rail-to-rail input stage with 2.7-V supply operation
• Slew rate: 105-V/µs is useful in portable, battery-powered applications.
• Rail-to-rail input and output The rail-to-rail input stage is well-matched for gain-
• HD2/HD3: –129 dBc/–138 dBc at 20 kHz (2-VPP) bandwidth product and noise across the full input
• Operating temperature range: common‑mode voltage range, enabling excellent
–40°C to +125°C performance with wide-input dynamic range. The
• Additional features: OPAx863 feature a power-down (PD) mode with a
– Overload power limit PD quiescent current (IQ) of 1.5-µA (maximum) and
– Output short-circuit protection a turn-on or turn-off time within 6.5-µs using a 3-V
• High-precision version: OPAx863A supply.
2 Applications The OPAx863 includes overload power limiting to limit
• Low-power SAR and ΔΣ ADC driver the increase in IQ with saturated outputs, thereby
• ADC reference buffer preventing excessive power dissipation in power-
• Low-side current sensing conscious, battery-operated systems. The output
• Photodiode TIA interface stage is short-circuit protected, making these devices
• Inductive sensing conducive to ruggedized environments.
• Ultrasonic flow meter Device Information(1)(2)
• Multifunction printer PART NUMBER CHANNEL COUNT PACKAGE
• MDAC output buffer DBV (SOT-23, 5)
• Gain and active filter stages OPA863 Single
DBV (SOT-23, 6)
LED CF DGK (VSSOP, 8)
Driver
RF
OPA2863 Dual RUN (WQFN, 10)
D (SOIC, 8)
VCC
ID OPA4863 Quad PW (TSSOP, 14)
LED ±
± OPA x863
To
Photo-
Diode ADC
+ VOUT
(1) For all available packages, see the orderable addendum at
GND VEE the end of the data sheet.
VOUT = ID.RF (2) For related products, see Device Comparison
±VBIAS
Transimpedance Amplifier Circuit -20
HD2, VOUT = 2 VPP
Switchi ng HD3, VOUT = 2 VPP
Circuit -40
HD2, VOUT = 4 VPP
Harmonic Distortion (dBc)

RF HD3, VOUT = 4 VPP

-60
ISH To compar ato r
VCC for faul t detection
RG -80
± OPA x863
RSH
+ VOUT -100
To MCU/
RG GND ADC
-120
RF

GND
-140
VREF
Low-side Current Sensing -160
1k 10k 100k 1M 10M
Application Circuits Using OPAx863 Frequency (Hz)

Distortion Performance in G = 1 V/V

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.1 Overview................................................................... 21
2 Applications..................................................................... 1 8.2 Functional Block Diagram......................................... 21
3 Description.......................................................................1 8.3 Feature Description...................................................22
4 Revision History.............................................................. 2 8.4 Device Functional Modes..........................................23
5 Device Comparison Table...............................................3 9 Application and Implementation.................................. 24
6 Pin Configuration and Functions...................................3 9.1 Application Information............................................. 24
7 Specifications.................................................................. 6 9.2 Typical Applications.................................................. 24
7.1 Absolute Maximum Ratings........................................ 6 9.3 Power Supply Recommendations.............................28
7.2 ESD Ratings............................................................... 6 9.4 Layout....................................................................... 28
7.3 Recommended Operating Conditions.........................6 10 Device and Documentation Support..........................30
7.4 Thermal Information: OPA863.................................... 7 10.1 Documentation Support.......................................... 30
7.5 Thermal Information: OPA2863.................................. 7 10.2 Receiving Notification of Documentation Updates..30
7.6 Thermal Information: OPA4863.................................. 7 10.3 Support Resources................................................. 30
7.7 Electrical Characteristics: VS = 10 V .......................... 8 10.4 Trademarks............................................................. 30
7.8 Electrical Characteristics: VS = 3 V........................... 10 10.5 Electrostatic Discharge Caution..............................30
7.9 Typical Characteristics: VS = 10 V............................ 12 10.6 Glossary..................................................................30
7.10 Typical Characteristics: VS = 3 V............................ 17 11 Mechanical, Packaging, and Orderable
7.11 Typical Characteristics: VS = 3 V to 10 V................ 19 Information.................................................................... 30
8 Detailed Description......................................................21

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (December 2022) to Revision J (June 2023) Page
• Changed the status of OPA4863 PW package, 14-pin TSSOP from: preview to: production and added
associated content..............................................................................................................................................1

Changes from Revision H (August 2022) to Revision I (December 2022) Page

• Changed the status of the DBV package, 5-pin SOT23 from: preview to: production ...................................... 1

Changes from Revision G (July 2022) to Revision H (August 2022) Page

• Changed the status of the RUN Package, from: preview to: production ........................................................... 3

Changes from Revision F (April 2022) to Revision G (July 2022) Page

• Added OPAx863A information to the Features section...................................................................................... 1
• Added the DBV package, 5-pin SOT23 to the data sheet..................................................................................1
• Changed the status of the D Package, from: preview to: production .................................................................3
• Updated the Output Voltage vs Load Current and Output Voltage vs Load Current figures to show typical
device performance.......................................................................................................................................... 12

Changes from Revision E (November 2021) to Revision F (April 2022) Page

• Added the D package, 8-pin SOIC and RUN package, 10-pin WQFN to the data sheet...................................1

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5 Device Comparison Table

IQ / CHANNEL GBWP SLEW RATE VOLTAGE NOISE
DEVICE ±VS (V) AMPLIFIER DESCRIPTION
(mA) (MHz) (V/µs) (nV/√ Hz)
OPA2863 ±6.3 0.70 50 105 5.9 Unity-gain stable RRIO Bipolar Amplifier
LMH6643 ±6.4 2.7 65 130 17 Unity-gain stable NRI/RRO Bipolar Amplifier
OPAx810 ±13.5 3.6 70 200 6.3 Unity-gain stable RRIO FET-Input Amplifier
OPAx837 ±2.7 0.6 50 105 4.7 Unity-gain stable NRI/RRO Bipolar Amplifier
Decompensated Gain of 6 V/V stable CMOS
OPAx607 ±2.75 0.9 50 24 3.8
Amplifier

6 Pin Configuration and Functions

VOUT 1 6 VS+ VOUT 1 5 VS+

VS- 2 5 PD VS- 2

VIN+ 3 4 VIN- VIN+ 3 4 VIN-

Figure 6-1. OPA863 DBV Package, Figure 6-2. OPA863 DBV Package,
6-Pin SOT-23 5-Pin SOT-23
(Top View) (Top View)

Table 6-1. Pin Functions: OPA863

PIN
NO.
TYPE(1) DESCRIPTION
NAME DBV DBV
(SOT-23, 5) (SOT-23, 6)
Power down.
PD — 5 I
Low = disabled, high = normal operation (pin must be driven).
VIN+ 3 3 I Noninverting input pin
VIN– 4 4 I Inverting input pin
VOUT 1 1 O Output pin
VS– 2 2 P Negative power-supply pin
VS+ 5 6 P Positive power-supply pin

(1) I = input, O = output, and P = power.

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VS+

VOUT1 VS+ 10
1 8
VOUT1 1 9 VOUT2
VIN1- 2 7 VOUT2
VIN1- 2 8 VIN2-
VIN1+ 3 6 VIN2- VIN1+ 3
7 VIN2+

VS- 4 5 VIN2+ PD1 4 6 PD2

5
VS-
Figure 6-3. OPA2863 D Package, 8-Pin SOIC
Figure 6-4. OPA2863 RUN Package,
and DGK Package, 8-Pin VSSOP,
10-Pin WQFN
(Top View)
(Top View)

Table 6-2. Pin Functions: OPA2863

PIN
NO.
TYPE(1) DESCRIPTION
NAME D (SOIC),
RUN
DGK
(WQFN)
(VSSOP)
Amplifier 1 power down.
PD1 — 4 I
Low = disabled, high = normal operation (pin must be driven).
Amplifier 2 power down.
PD2 — 6 I
Low = disabled, high = normal operation (pin must be driven).
VIN1– 2 2 I Amplifier 1 inverting input pin
VIN1+ 3 3 I Amplifier 1 noninverting input pin
VIN2– 6 8 I Amplifier 2 inverting input pin
VIN2+ 5 7 I Amplifier 2 noninverting input pin
VOUT1 1 1 O Amplifier 1 output pin
VOUT2 7 9 O Amplifier 2 output pin
VS– 4 5 P Negative power-supply pin
VS+ 8 10 P Positive power-supply pin

(1) I = input, O = output, and P = power.

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VOUT1 1 14 VOUT4
VIN1- 2 13 VIN4-
VIN1+ 3 12 VIN4+
VS+ 4 11 VS-
VIN2+ 5 10 VIN3+
VIN2- 6 9 VIN3-

VOUT2 7 8 VOUT3

Figure 6-5. OPA4863 PW Package,

14-Pin TSSOP
(Top View)

Table 6-3. Pin Functions: OPA4863

PIN
TYPE(1) DESCRIPTION
NAME NO.
VIN1– 2 I Amplifier 1 inverting input pin
VIN1+ 3 I Amplifier 1 noninverting input pin
VIN2– 6 I Amplifier 2 inverting input pin
VIN2+ 5 I Amplifier 2 noninverting input pin
VIN3– 9 I Amplifier 3 inverting input pin
VIN3+ 10 I Amplifier 3 noninverting input pin
VIN4– 13 I Amplifier 4 inverting input pin
VIN4+ 12 I Amplifier 4 noninverting input pin
VOUT1 1 O Amplifier 1 output pin
VOUT2 7 O Amplifier 2 output pin
VOUT3 8 O Amplifier 3 output pin
VOUT4 14 O Amplifier 4 output pin
VS– 11 P Negative power-supply pin
VS+ 4 P Positive power-supply pin

(1) I = input, O = output, and P = power.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage 13 V
VS– to VS+
Supply turn-on/off maximum dV/dt, DBV-6 and D packages 0.1 V/µs
VI Input voltage VS– – 0.5 VS+ + 0.5 V
VID Differential input voltage ±1 V
II Continuous input current(2) ±10 mA
IO Continuous output current(3) ±30 mA
Continuous power dissipation See Thermal Information
TJ Maximum junction temperature 150 °C
TA Operating free-air temperature –40 125 °C
Tstg Storage temperature –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Continuous input current limit for both the ESD diodes to supply pins and amplifier differential input clamp diode. The differential input
clamp diode limits the voltage across it to 1 V with this continuous input current flowing through it.
(3) Long-term continuous current for electromigration limits.

7.2 ESD Ratings

VALUE UNIT

Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

V(ESD) V
discharge Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS+ – VS– Total supply voltage 2.7 10 12.6 V
TA Ambient temperature –40 25 125 °C

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7.4 Thermal Information: OPA863

OPA863
THERMAL METRIC(1) DBV (SOT-23) UNIT
5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 168.3 161.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 64.3 73.9 °C/W
RθJB Junction-to-board thermal resistance 40.6 42.6 °C/W
ΨJT Junction-to-top characterization parameter 14.2 21.2 °C/W
YJB Junction-to-board characterization parameter 40.3 42.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Thermal Information: OPA2863

OPA2863
THERMAL METRIC(1) DGK (VSSOP) D (SOIC) RUN (WQFN) UNIT
8 PINS 8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 180.3 120.0 110.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 67.5 63.3 66.8 °C/W
RθJB Junction-to-board thermal resistance 101.9 63.2 43.6 °C/W
ΨJT Junction-to-top characterization parameter 9.8 17.2 2.9 °C/W
YJB Junction-to-board characterization parameter 100.1 62.5 43.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.6 Thermal Information: OPA4863

OPA4863
THERMAL METRIC(1) PW (TSSOP) UNIT
14 PINS
RθJA Junction-to-ambient thermal resistance 99.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.6 °C/W
RθJB Junction-to-board thermal resistance 56.1 °C/W
ΨJT Junction-to-top characterization parameter 4.4 °C/W
YJB Junction-to-board characterization parameter 55.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.7 Electrical Characteristics: VS = 10 V

at VS+ = 5 V, VS– = –5 V, G = 1 V/V, RF = 0 Ω for G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ
referenced to mid-supply, input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 20 mVPP, G = 1, < 1 dB peaking 110 MHz
GBWP Gain-bandwidth product 50 MHz
LSBW Large-signal bandwidth VOUT = 2 VPP 17 MHz
Bandwidth for 0.1-dB flatness VOUT = 20 mVPP 15 MHz
SR Slew rate VOUT = 2–V step, G = –1 105 V/µs
Rise, fall time VOUT = 200–mV step 9 ns
Settling time to 0.1% 57
VOUT = 2–V step ns
Settling time to 0.01% 70
Overshoot/undershoot VOUT = 2–V step 1 %
G = –1, 0.5 V overdrive beyond supplies 70
Overdrive recovery time ns
G = 1, 0.5 V overdrive beyond supplies 100
HD2 Second-order harmonic distortion –129
f = 20 kHz, VOUT = 2 VPP dBc
HD3 Third-order harmonic distortion –138
HD2 Second-order harmonic distortion –107
f = 100 kHz, VOUT = 2 VPP dBc
HD3 Third-order harmonic distortion –125
eN Input voltage noise Flatband, 1/f corner at 25 Hz 5.9 nV/√Hz
iN Input current noise Flatband, 1/f corner at 2 kHz 0.4 pA/√Hz
Closed-loop output impedance f = 1 MHz 0.2 Ω
Channel-to-channel crosstalk f = 1 MHz, VOUT = 2 VPP, OPA2863 –124 dBc
DC PERFORMANCE
AOL Open-loop voltage gain VOUT = ±2.5 V 110 128 dB
VOS Input-referred offset voltage –1.3 ±0.4 1.3 mV
TA = –40°C to +125°C,
–3.5 ±1 3.5
D, DBV-5, RUN and DGK packages

Input offset voltage drift TA = –40°C to +125°C, PW package –4 ±1 4 µV/°C

TA = 0°C to +85°C, DBV-6 package –4.4 ±1 4.4
TA = –40°C to +125°C, DBV-6 package –4.9 ±1 4.9
TA ≅ 25°C 0.3 0.73
Input bias current TA = –40°C to +85°C 1.2 µA
TA = –40°C to +125°C 1.6
Input bias current drift TA = –40°C to +125°C ±3 7.6 nA/°C
Input offset current –30 ±10 30 nA
INPUT
Input common-mode voltage range VS––0.2 VS++0.2 V
CMRR Common-mode rejection ratio VCM = VS– – 0.2 V to VS+ – 1.6 V 100 120 dB
Input impedance common-mode 650 || 0.8 MΩ || pF
Input impedance differential mode 200 || 0.5 kΩ || pF
OUTPUT
TA ≅ 25°C VS–+0.14 VS–+0.2
VOL Output voltage, low V
TA = –40°C to +125°C VS–+0.15 VS–+0.22
TA ≅ 25°C VS+–0.2 VS+–0.14
VOH Output voltage, high V
TA = –40°C to +125°C VS+–0.2 VS+–0.15

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7.7 Electrical Characteristics: VS = 10 V (continued)

at VS+ = 5 V, VS– = –5 V, G = 1 V/V, RF = 0 Ω for G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ
referenced to mid-supply, input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Linear output drive (sourcing/ VOUT = ±2.5 V, ΔVOS < 1 mV
25 30 mA
sinking) OPA863 and OPA2863(1)
Short-circuit current 45 mA
POWER SUPPLY
TA ≅ 25°C 700 970
IQ Quiescent current per amplifier µA
TA = –40°C to +125°C 1280
PSRR Power-supply rejection ratio ΔVS = ±2 V(2) 100 120 dB
POWER DOWN (Pin Must be Driven)
Enable voltage threshold Specified on above VS+ – 0.5 V 4.5 V
Disable voltage threshold Specified off below VS+ – 1.5 V 3.5 V
Power-down quiescent current per
PD ≤ VS+ – 1.5 V 2 3.3 µA
channel
Power-down pin bias current 2 50 nA
Turn-on time delay 6 µs
Turn-off time delay 4.5 µs
AUXILIARY INPUT STAGE
Gain-bandwidth product 50 MHz
Input voltage noise Flatband, 1/f corner at 25 Hz 6 nV/√Hz
Input current noise Flatband, 1/f corner at 100 Hz 0.4 pA/√Hz
Input-referred offset voltage –1.3 ±0.15 1.3 mV
TA ≅ 25°C 0.2 0.6
Input bias current µA
TA = –40°C to +125°C 0.2 1.3
Common-mode rejection ratio VCM = 4.1 V to 5.2 V 100 120 dB
Power supply rejection ratio ΔVS = ±0.6 V 100 120 dB

(1) Change in input offset voltage from no-load condition.

(2) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.

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7.8 Electrical Characteristics: VS = 3 V

at VS+ = 3 V, VS– = 0 V, G = 1, RF = 0 Ω for G =1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ connected to
1 V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 20 mVPP, G = 1 97 MHz
GBWP Gain-bandwidth product 50 MHz
LSBW Large-signal bandwidth VOUT = 1 VPP 26 MHz
Bandwidth for 0.1-dB flatness VOUT = 20 mVPP 10 MHz
SR Slew rate VOUT = 1–V step, Gain = –1 105 V/µs
Rise, fall time VOUT = 200–mV step 10 ns
Settling time to 0.1% 58
VOUT = 1–V step ns
Settling time to 0.01% 90
Overshoot 2
VOUT = 1–V step %
Undershoot 16
G = –1, 0.5V overdrive beyond supplies 95
Overdrive recovery time ns
G = 1, 0.5V overdrive beyond supplies 100
HD2 Second-order harmonic distortion –123
f = 20 kHz, VOUT = 1 VPP dBc
HD3 Third-order harmonic distortion –132
HD2 Second-order harmonic distortion –109
f = 100 kHz, VOUT = 1 VPP dBc
HD3 Third-order harmonic distortion –129
eN Input voltage noise Flatband, 1/f corner at 25 Hz 6 nV/√Hz
iN Input current noise Flatband, 1/f corner at 2 kHz 0.4 pA/√Hz
Closed-loop output impedance f = 1 MHz 0.2 Ω
Channel-to-channel crosstalk f = 1 MHz, VOUT = 1 VPP, OPA2863 –127 dBc
DC PERFORMANCE
AOL Open-loop voltage gain VOUT = 1 V to 2 V 104 123 dB
VOS Input-referred offset voltage –1.3 ±0.4 1.3 mV
TA = –40°C to +125°C,
–3.5 ±1 3.5
D, DBV-5, RUN, and DGK packages

Input offset voltage drift TA = –40°C to +125°C, PW package –4 ±1 4 μV/°C

TA = 0°C to +85°C, DBV-6 package –4.4 ±1 4.4
TA = –40°C to +125°C, DBV-6 package –5 ±1 5
TA ≅ 25°C 0.3 0.73
Input bias current TA = –40°C to +85°C 1.2 µA
TA = –40°C to +125°C 1.56
Input bias current drift TA = –40°C to +125°C ±3 7.4 nA/°C
Input offset current –30 ±10 30 nA
INPUT
Input common-mode voltage range VS––0.2 VS++0.2 V
CMRR Common-mode rejection ratio VCM = VS– – 0.2 V to VS+ – 1.6 V 94 115 dB
Input impedance common-mode 360 || 0.9 MΩ || pF
Input impedance differential mode 200 || 0.5 kΩ || pF

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7.8 Electrical Characteristics: VS = 3 V (continued)

at VS+ = 3 V, VS– = 0 V, G = 1, RF = 0 Ω for G =1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ connected to
1 V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
TA ≅ 25°C VS–+ 0.13 VS–+ 0.15
VOL Output voltage, low V
TA = –40°C to +125°C VS–+ 0.13 VS–+ 0.16
TA ≅ 25°C VS+–0.15 VS+–0.13
VOH Output voltage, high V
TA = –40°C to +125°C VS+–0.15 VS+–0.13
Linear output drive (sourcing/ VOUT = ±0.7 V, ΔVOS < 1 mV
23 33 mA
sinking) OPA863 and OPA2863(1)
Short-circuit current 45 mA
POWER SUPPLY
TA ≅ 25°C 690 910
IQ Quiescent current per amplifier µA
TA = –40°C to +125°C 1180
PSRR Power-supply rejection ratio ΔVS = ±1 V(2) 100 120 dB
POWER DOWN (Pin Must be Driven)
Enable voltage threshold Specified on above VS+ – 0.5 V 2.5 V
Disable voltage threshold Specified off below VS+ – 1.5 V 1.5 V
Power-down quiescent current per
PD ≤ VS+ – 1.5 V 0.8 1.5 µA
channel
Power-down pin bias current 1 50 nA
Turn-on time delay 6.5 µs
Turn-off time delay 5 µs
AUXILIARY INPUT STAGE
Gain-bandwidth product 50 MHz
Input voltage noise Flatband, 1/f corner at 25 Hz 6 nV/√Hz
Input current noise Flatband, 1/f corner at 100 Hz 0.4 pA/√Hz
Input-referred offset voltage –1.3 ±0.15 1.3 mV
TA ≅ 25°C 0.2 0.6
Input bias current µA
TA = –40°C to +125°C 0.4 1.2
Common-mode rejection ratio VCM = 2.1 V to 3.2 V 100 120 dB
Power supply rejection ratio ΔVS = ±0.6 V 100 115 dB

(1) Change in input offset voltage from no-load condition.

(2) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.

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7.9 Typical Characteristics: VS = 10 V

at VS+ = 5 V, VS– = –5 V, RF = 0 Ω for Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ referenced to
mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)

3 3

0 0

-3 -3
Normalized Gain (dB)

Normalized Gain (dB)

-6 -6

-9 -9

-12 -12
G = 1 V/V
-15 G = -1 V/V -15
G = 2 V/V
-18 G = 5 V/V -18 RL = 2 k
G = 10 V/V RL = 500 
-21 -21
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)
VOUT = 20 mVPP VOUT = 20 mVPP
Figure 7-1. Small-Signal Frequency Response vs Gain Figure 7-2. Small-Signal Frequency Response vs Output Load
6 1

3
0.5
Normalized Gain (dB)

Normalized Gain (dB)

0
0
-3
No CL
CL = 2.2 pF -0.5
-6 CL =4.7 pF
CL = 10 pF, Rs = 200  G = 1 V/V
CL = 10 pF, G = 2 V/V G = 2 V/V
-9 -1
1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)
VOUT = 20 mVPP VOUT = 20 mVPP
Figure 7-3. Frequency Response vs Load Capacitance Figure 7-4. Small-Signal Response Flatness vs Gain
6 3

3
0
Normalized Gain (dB)
Normalized Gain (dB)

-3 -3
VOUT = 20 mVPP
VOUT = 200 mVPP
-6
VOUT = 500 mVPP
-6 VOUT = 1 VPP
-9 TA = 25 °C VOUT = 2 VPP
TA = 125°C VOUT = 4 VPP
TA = −45 °C VOUT = 8 VPP
-12 -9
1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)
VOUT = 20 mVPP .
Figure 7-5. Frequency Response vs Ambient Temperature Figure 7-6. Frequency Response vs Output Voltage

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7.9 Typical Characteristics: VS = 10 V (continued)

at VS+ = 5 V, VS– = –5 V, RF = 0 Ω for Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ referenced to
mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)

3 3

0
0
Normalized Gain (dB)

Normalized Gain (dB)

-3
-3

-6

-6 G = 1 V/V
G = 2 V/V -9 TA = 25 °C
G = 5 V/V TA = 125 °C
G = 10 V/V TA = −45 °C
-9 -12
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)
VOUT = 2 VPP VOUT = 2 VPP
Figure 7-7. Large-Signal Frequency Response vs Gain Figure 7-8. Frequency Response vs Ambient Temperature
-20 -20
HD2, VOUT = 2 VPP HD2, G = 1 V/V
-40 HD3, VOUT = 2 VPP -40
HD3, G = 1 V/V
HD2, VOUT = 4 VPP HD2, G = 2 V/V
Harmonic Distortion (dBc)

Harmonic Distortion (dBc)

HD3, VOUT = 4 VPP HD3, G = 2 V/V

-60 -60

-80 -80

-100 -100

-120 -120

-140 -140

-160 -160
1k 10k 100k 1M 10M 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)
G = 1 V/V VOUT = 2 VPP
Figure 7-9. Harmonic Distortion vs Frequency Figure 7-10. Harmonic Distortion vs Gain
0.15 6

0.1 4
Output Voltage (V)

Output Voltage (V)

0.05 2

0 0

-0.05 -2

-0.1 -4

-0.15 -6
Time (200 ns/div) Time (50 ns/div)

. .
Figure 7-11. Small-Signal Transient Response Figure 7-12. Large-Signal Transient Response

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7.9 Typical Characteristics: VS = 10 V (continued)

at VS+ = 5 V, VS– = –5 V, RF = 0 Ω for Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ referenced to
mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)

6 6

4 4
Input and Output Voltage (V)

Input and Output Voltage (V)

2 2

0 0

-2 -2

-4 -4
Input Input x -1 V/V
Output Output
-6 -6
Time (100 ns/div) Time (100 ns/div)

Gain = 1 V/V Gain = –1 V/V

Figure 7-13. Input Overdrive Recovery Figure 7-14. Output Overdrive Recovery
1200 1000

750
900
Input Offset Voltage (μ V)

Input Bias Current (nA) 500

600
250

300 0

-250
0
-500
-300
-750

-600 -1000
-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 -5.5 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
Input Common-Mode Voltage (V) Input Common-Mode Voltage (V)

Measured for 10 units

Figure 7-15. Input Offset Voltage vs Input Common-Mode Figure 7-16. Input Bias Current vs Input Common-Mode Voltage
Voltage
6 50
40
Output Short-Circuit Current (mA)

4
30
Output Voltage (V)

20
2
10
Sourcing
Sourcing
0 Sinking 0 Sinking

-10
-2
-20
-30
-4
-40
-6 -50
0 5 10 15 20 25 30 35 -40 -20 0 20 40 60 80 100 120 140
Output Current (mA) Ambient Temperature (°C)

Output saturated and then short-circuited to opposite supply

Figure 7-17. Output Voltage vs Load Current Figure 7-18. Output Short-Circuit Current vs Ambient
Temperature

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7.9 Typical Characteristics: VS = 10 V (continued)

at VS+ = 5 V, VS– = –5 V, RF = 0 Ω for Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ referenced to
mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)

20000
9000
18000
8000

Number of Units in Each Bin

16000
No. of Units in Each Bin

7000
14000
6000
12000
5000
10000
4000
8000
3000
6000
2000 4000
1000 2000
0 0

1000
600
625
650
675
700
725
750
775
800
825
850
875
900

175

200

225

250

275

300

325

350

375
Quiescent Current per Channel (A) Input Bias Current (nA)

μ = 678 μA, σ = 13 μA μ = 251 nA, σ = 5.6 nA

Figure 7-19. Quiescent Current Distribution Figure 7-20. Input Bias Current Distribution
12000 6
11000
10000 Number of Units in Each Bin 5
Number of Units in Each Bin

9000
8000 4
7000
6000 3
5000
4000 2
3000
2000 1
1000
0 0
-1.5
-1.3
-1.1
-0.9
-0.7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
-600

-400

-400

-200

200

400

600

800

1000

1200
0

Input Offset Voltage (μV) Input Offset Drift (μV/°C)

μ = 209 μV, σ = 193 μV 35 units, μ =-0.26 μV/°C, σ = 0.49 μV/°C, DGK package
Figure 7-21. Input Offset Voltage Distribution Figure 7-22. Input Offset Voltage Drift Distribution
7 0.9
Quiescent Current per Channel (mA)

6 0.85
Number of Units in Each Bin

5 0.8

4 0.75

3 0.7

2 0.65

1 0.6

0 0.55
-2.5

-1.5

-0.5

0.5

1.5
-3

-2

-1

-40 -20 0 20 40 60 80 100 120 140

Input Offset Drift (V/C) Ambient Temperature (°C)

32 units, μ = −0.02 μV/°C, σ = 0.98 μV/°C, DBV-6 package 35 units

Figure 7-23. Input Offset Voltage Drift Distribution Figure 7-24. Quiescent Current vs Ambient Temperature

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7.9 Typical Characteristics: VS = 10 V (continued)

at VS+ = 5 V, VS– = –5 V, RF = 0 Ω for Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ referenced to
mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)

700 100
650 75

Normalized Input Offset Voltage (μV)

600
50
550
Input Bias Current (nA)

500 25
450 0
400
-25
350
300 -50
250 -75
200
-100
150
100 -125
50 -150
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C) Ambient Temperature (°C)

35 units Normalized to 25°C values, 35 units, DGK package

Figure 7-25. Input Bias Current vs Ambient Temperature Figure 7-26. Input Offset Voltage vs Ambient Temperature
8 8
VPD
Power-Down and Output Voltages (V)

Power-Down and Output Voltages (V)

6 6 VOUTx10

4 4

2 2

0 0

-2 -2

-4 -4

-6 VPD -6
VOUTx10
-8 -8
Time (2.5 s/div) Time (2.5 s/div)

. .
Figure 7-27. Turn-On Time to DC Input Figure 7-28. Turn-Off Time to DC Input
8000 2.8
Power-Down Quiescent Current (A)

2.4
Number of Units in Each Bin

6000
2

1.6
4000
1.2

0.8
2000

0.4

0 0
1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 -60 -40 -20 0 20 40 60 80 100 120 140
Power-Down Quiescent Current (A) Ambient Temperature (C)
μ = 1.86 μA, σ = 0.076 μA .
Figure 7-29. Power-Down Quiescent Current Distribution Figure 7-30. Power-Down IQ vs Ambient Temperature

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7.10 Typical Characteristics: VS = 3 V

at VS+ = 3 V, VS– = 0 V, RF = 0 Ω for Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ connected to 1
V, G = 1 V/V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)

-3
Normalized Gain (dB)

-6

-9

-12
G = 1 V/V
-15 G = -1 V/V
G = 2 V/V
-18 G = 5 V/V
G = 10 V/V
-21
100k 1M 10M 100M
Frequency (Hz)
VOUT = 20 mVPP VOUT = 1 VPP
Figure 7-31. Small-Signal Frequency Response vs Gain Figure 7-32. Harmonic Distortion vs Frequency
0.15 1

0.1
0.5
Output Voltage (V)

Output Voltage (V)

0.05

0 0

-0.05
-0.5
-0.1

-0.15 -1
Time (200 ns/div) Time (50 ns/div)

. .
Figure 7-33. Small-Signal Transient Response Figure 7-34. Large-Signal Transient Response
1000 1000

800 750
Input Offset Voltage (μV)

500
Input Bias Current (nA)

600
250
400
0
200
-250
0
-500

-200 -750

-400 -1000
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Input Common-Mode Voltage (V) Input Common-Mode Voltage (V)

Measured for 10 units .

Figure 7-35. Input Offset Voltage vs Input Common-Mode Figure 7-36. Input Bias Current vs Input Common-Mode Voltage
Voltage

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7.10 Typical Characteristics: VS = 3 V (continued)

at VS+ = 3 V, VS– = 0 V, RF = 0 Ω for Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ connected to 1
V, G = 1 V/V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)

3 60

Output Short-Circuit Current (mA)

2.5 40
Output Voltage (V)

2 20

Sourcing Sourcing
1.5 Sinking 0 Sinking

1 -20

0.5 -40

0 -60
0 5 10 15 20 25 30 35 40 -40 -20 0 20 40 60 80 100 120 140
Output Current (mA) Ambient Temperature (°C)

. Output saturated and then short-circuited to other supply

Figure 7-37. Output Voltage vs Load Current Figure 7-38. Output Short-Circuit Current vs Ambient
Temperature
6 6
Power-Down and Output Voltages (V)

Power-Down and Output Voltages (V)

4 4

2 2

0 0

-2 -2

-4 -4
VPD VPD
VOUTx10 VOUTx10
-6 -6
Time (2.5 s/div) Time (2.5 s/div)

. .
Figure 7-39. Turn-On Time to DC Input Figure 7-40. Turn-Off Time to DC Input
5000 1
Power-Down Quiescent Current (A)

4000
Number of Units in Each Bin

0.8

3000 0.6

2000 0.4

1000 0.2

0 0
0.45

0.55

0.65

0.75

0.85
0.4

0.5

0.6

0.7

0.8

-60 -40 -20 0 20 40 60 80 100 120 140

Power-Down Quiescent Current (A) Ambient Temperature (C)

μ = 0.64 μA, σ = 0.056 μA .

Figure 7-41. Power-Down Quiescent Current Distribution Figure 7-42. Power-Down IQ vs Ambient Temperature

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7.11 Typical Characteristics: VS = 3 V to 10 V

at VOUT = 2 VPP, RF = 0 Ω for Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ referenced to
mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)

3 3

0 0
Normalized Gain (dB)

Normalized Gain (dB)

-3 -3

-6 -6

-9 VS = 10 V -9 VS = 10 V
VS = 5 V VS = 5 V
VS = 3 V VS = 3 V
-12 -12
100k 1M 10M 100M 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)

VOUT = 20 mVPP VOUT = 1 VPP

Figure 7-43. Frequency Response vs Supply Voltage Figure 7-44. Frequency Response vs Supply Voltage
100 10
Main Stage
Auxiliary Stage
Input Voltage Noise (nV/—Hz)

Input Current Noise (pA/Hz)

10
1

1
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
Frequency (Hz) D401 Frequency (Hz)
. .
Figure 7-45. Input Voltage Noise Density vs Frequency Figure 7-46. Input Current Noise Density vs Frequency
140 140
PSRR−
PSRR+
Power Supply Rejection Ratio (dB)
Common-mode rejection ratio (dB)

120
120
100
100
80

80 60

40
60
20
40
0

20 -20
100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

. .
Figure 7-47. Common-Mode Rejection Ratio vs Frequency Figure 7-48. Power Supply Rejection Ratio vs Frequency

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7.11 Typical Characteristics: VS = 3 V to 10 V (continued)

at VOUT = 2 VPP, RF = 0 Ω for Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ referenced to
mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)

100 135 210

Magnitude
120 Phase 180

Open-Loop Gain Magnitude (dB)

80 105 150

Open-Loop Gain Phase (O)

Output Impedance ()

90 120
60 75 90
60 60
40 45 30
30 0
20 15 -30
0 -60
0 -15 -90
1 10 100 1k 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz) Frequency (Hz)

. Small-signal response
Figure 7-49. Open-Loop Output Impedance vs Frequency Figure 7-50. Open-Loop Gain and Phase vs Frequency
-40 -20

-60 -40
Harmonic Distortion (dBc)

-80 -60
Crosstalk (dBc)

-100 -80

-120 -100
HD2, VS = 10 V
-140 HD3, VS = 10 V -120
HD2, VS = 5 V Ch-A to Ch-B
HD3, VS = 5 V Ch-B to Ch-A
-160 -140
1k 10k 100k 1M 10M 100k 1M 10M 100M
Frequency (Hz) Frequency(Hz)

VOUT = 2 VPP DGK package

Figure 7-51. Harmonic Distortion vs Supply Voltage Figure 7-52. Crosstalk vs Frequency

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8 Detailed Description
8.1 Overview
The OPAx863 devices are low-power, 50‑MHz, rail-to-rail input and output (RRIO), bipolar, voltage-feedback
operational amplifiers with a voltage noise density of 5.9 nV/√Hz and 1/f noise corner at 25 Hz. The OPAx863
work with a wide-supply voltage range of 2.7 V to 12.6 V, and consume only 700 μA quiescent current. The
OPAx863 operate with a 2.7 V supply, are RRIO capable, consume low-power, and offer a power-down mode,
which makes them great amplifiers for 3.3‑V or lower-voltage applications that require excellent ac performance.
The main and auxiliary input stages of the amplifier are matched for gain bandwidth product (GBW), noise, and
offset voltage and designed for applications that require wide dynamic input range and good SNR.
The device includes an overload power limit feature which limits the increase in quiescent current with over-
driven and saturated outputs to either of the supply rails. For more details of this overload power limit feature,
see Section 8.3.2.1. The amplifier's output is protected against short-circuit fault conditions.
The OPAx863 feature a power-down mode (PD) with a PD quiescent current of 1.5 µA (maximum) with a 3‑V
supply, with turn-on and turn-off time within less than 6.5 µs.
8.2 Functional Block Diagram

PD
VS+
OPAx863

Auxiliary
NPN-
VIN+ + Stage
–
EN
CC Output
Short-Circuit
Main Protection

PNP-
+ Stage VOUT
–
EN Overload
Power
Limiting

–
–
VIN– +

VS+ –1.6 V

VS–

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8.3 Feature Description

8.3.1 Input Stage
The OPAx863 include a rail-to-rail input stage. The main stage differential pair using PNP bipolar transistors
operates for common-mode input voltages from VS– – 0.2 V to VS+ – 1.6 V. The amplifier inputs transition into
the auxiliary stage using NPN transistors for common-mode input voltages from VS+ – 1.6 V till VS+ + 0.2 V. The
PNP and NPN input stages offer a gain-bandwidth product of 50 MHz and a voltage noise density of 6.3 nV/√Hz.
The offset voltage for the two input stages is matched to lie within the device specifications. The auxiliary NPN
input stage does not use the slew-boost circuit during large-signal transient response. The input bias current for
the PNP and NPN input stages is opposite in polarity, which adds an additional offset based on the values of
the gain-setting and feedback resistors. A common-mode input voltage transition between these input stages
causes a crossover distortion that must be considered in high-frequency applications requiring excellent linearity.
Limit the common-mode input voltage to VS+ – 1.6 V (maximum) for main-stage operation across process and
ambient temperature.
The OPAx863 are bipolar amplifiers; therefore, the two inputs are protected with antiparallel back-to-back diodes
between the inputs, which limits the maximum input differential voltage to 1 V. The amplifier is slew limited,
and the two inputs are pulled apart up to 1 V when the antiparallel diodes begin to conduct in very fast input
or output transient conditions. Make sure to use gain-setting and feedback resistors large enough to limit the
current through these diodes in such conditions.
8.3.2 Output Stage
The OPAx863 feature a rail-to-rail output stage with possible signal swing from VS– + 0.2 V to VS+ – 0.2 V.
Violating the output headroom of either supply causes output signal clipping and introduces distortion.
The OPAx863 integrate an output short-circuit protection circuit that makes the device rugged for use in real-
world applications.
8.3.2.1 Overload Power Limit
The OPAx863 include overload power limiting that limits the increase in device quiescent current with output
saturated to either of the supplies. Typically, when an amplifier output saturates, the two inputs are pulled
apart, which can enable the slew-boost circuit. The input differential voltage is an error voltage in negative
feedback that the amplifier core nullifies by engaging the slew-boost circuit and driving the output stage deeper
into saturation. After the input to an amplifier attains a value large enough to saturate the output, any further
increase in this input excitation results in a finite input differential voltage. As the output stage transistor is
pushed deeper into saturation, the base-to-collector current gain (hFE) drops with an increase in the base and
collector current, and an increase in the device quiescent current. This increase in quiescent current can cause
a catastrophic failure in multichannel, high-gain, high-density front-end designs, and reduce operating lifetime in
portable, battery-powered systems.
The OPAx863 overload power limiting includes an intelligent output saturation-detection circuit that limits the
device quiescent current to 2.2-mA per channel under dc overload conditions. This increase in quiescent current
is smaller with ac input or output and output saturation duration for only a fraction of the overall signal time
period. Table 8-1 compares the increase in quiescent current with 50‑mV input overdrive for OPAx863 devices
and other voltage-feedback amplifiers without overload power limit.
Table 8-1. Quiescent Current With Saturated Outputs
INCREASE IN IQ
INPUT DIFFERENTIAL QUIESCENT CURRENT
DEVICE FROM STEADY-STATE
VOLTAGE DURING OVERLOAD
CONDITION
OPAx863 with overload power limit 50 mV 1.1 mA 1.57 ×
Competitor amplifier without overload power limit 50 mV 1.96 mA 3.43 ×

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8.3.3 ESD Protection

As Figure 8-1 shows, all device pins are protected with internal ESD protection diodes to the power supplies.
These diodes provide moderate protection to input overdrive voltages greater than the supplies. The protection
diodes typically support 10-mA continuous input and output currents. Use series current limiting resistors if input
voltages exceeding the supply voltages occur at the amplifier inputs, which makes sure that the current through
the ESD diodes remains within the rated value. OPAx863 is a bipolar amplifier; therefore, the two inputs are
protected with antiparallel, back-to-back diodes between the inputs that limits the maximum input differential
voltage to approximately 1 V. Make sure to use gain-setting and feedback resistors large enough to limit the
current through these diodes in fast slewing conditions.
VS+

Power Sup ply

VIN+ ESD Cell

PD

± VOUT

VIN-

VS-

Figure 8-1. Internal ESD Protection

8.4 Device Functional Modes

8.4.1 Power-Down Mode
The OPAx863 includes a power-down mode for low-power standby operation with a quiescent current of only
1.5 μA (maximum) with a 3-V supply and high output impedance. Many low-power systems are active for only a
small time interval when the parameters of interest are measured and remain in low-power standby mode for a
majority of the time and an overall small average power consumption. The OPAx863 enables such a low-power
operation with quick turn-on within less than 6.5 μs. See the Electrical Characteristics tables for power-down pin
control thresholds.
Always drive PD pin to avoid false triggering and oscillations. If power-down mode is not used, then connect the
PD pin to VS+. For applications that need power-down mode, use an external pull-up resistor from the PD pin to
VS+ (driven with an open-collector power-down control logic).
VS+

OPAx863 RPU CPU

1 M
1 nF
Control
PD
Logic

VS–

Figure 8-2. Power Down Control

Figure 8-2 shows the choice of value of the pull-up resistor RPU, which impacts the current consumption in
power-down mode. Using a large RPU reduces power consumption, but increases the noise at the PD pin, which
can cause the amplifier to power down. A 1‑nF capacitor can be used in parallel with RPU to avoid coupling of
external noise and false triggering. For the case of the PD pin driven to VS-, the IPU current through RPU is given
as:

− −

(1)

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The OPAx863 are classic voltage-feedback amplifiers with two high-impedance inputs and a low-impedance
output. These devices have a GBW of 50 MHz, 5.9 nV/√Hz of noise, RRIO capability, and precision performance
consuming only 700 µA quiescent current per channel These features make the OPAx863 an excellent choice
for use in low-side current sensing, ADC input driver, and reference buffering with fast settling, buffers, high
gain and filter circuits. The overload power limit makes the OPAx863 truly low-power in high-gain, multichannel
systems limiting any increase in quiescent current during output overload conditions.
9.2 Typical Applications
9.2.1 Low-Side Current Sensing
Power converters use current-mode feedback control for excellent transient response and multiphase load
sharing. Inverter stages control the phase currents for torque control in motor drives. As a result of the simplicity
and low-cost, many of these topologies use difference-amplifier-based, low-side current sensing. Figure 9-1
shows the use of the OPAx863 in a difference amplifier circuit for low-side current sensing.
300V

3.3V
Switchi ng
Circuit TLV320 1
VTH +
12kŸ Interrupt
±
ISH
3.3V 3.3V MCU
600Ÿ
± OPA x863 250Ÿ
RSH ADS705 6 Digital I/O
+ VOUT

600Ÿ 220pF
12kŸ

GND
1.65V

Figure 9-1. Low-Side Current Sensing in Power Converters

9.2.1.1 Design Requirements

Table 9-1. Design Requirements
PARAMETER DESIGN REQUIREMENT
Shunt resistor 10 mΩ
Input current 15 APP
Output voltage 3 VPP
Switching frequency 50 kHz
Data acquisition 1 MSPS with 0.1% accuracy
Input voltage due to ground bounce 10 Vpk

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9.2.1.2 Detailed Design Procedure

In a difference amplifier circuit, the output voltage is given by:

4(
81 = + 4 + 84'(
4) 5* 5* (2)

For lowest system noise, small values of RF and RG are preferred. The smallest value of RG is limited by the
input transient voltage (10 V here) seen by the circuit, and is given by:

8+0(I=T .) F 8& F 85
4) =
+&(I=T .) (3)

Where,
• VIN(maximum) is the maximum input transient voltage seen by the circuit.
• VD is the forward voltage drop of ESD diodes at the amplifier input.
• ID(maximum) is the maximum current rating of the ESD diodes at the amplifier input.
For a difference amplifier gain of 20 V/V, an RF of 12 kΩ and RG of 600 Ω are used. With a clock frequency of 40
MHz and the ADS7056 sampling at 1 MSPS, the available acquisition time for amplifier output settling is 550 ns.
Figure 9-2 shows the simulation results for the circuit in Figure 9-1. The worst-case peak-to-peak input transient
condition is simulated. The output of the OPAx863 device settles to within 0.1% accuracy within 543 ns. If using
a slower clock frequency with the ADC is desired, then the acquisition time reduces with the same sampling rate,
which degrades measurement accuracy. Alternatively, the sampling rate can be reduced to recover the required
acquisition time and 0.1% accuracy.
9.2.1.3 Application Curves
4 1.2
3.5 1.1
3 1
Input/Output Voltage (V)

2.5 0.9
2 0.8
Error (%)

1.5 0.7
1 0.6
0.5 0.5
0 0.4
-0.5 VIN x 20 0.3
-1 OPAx863 O/P 0.2
S/H Voltage
-1.5 % Error 0.1
-2 0
Time (150 ns/div)
D805

Figure 9-2. 0.1% Settling Performance

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9.2.2 Front-End Gain and Filtering

C2

RBI AS D1
R2 -VBI AS

C1 VS+ D2
R1 VS+ ± RIS O
±
+
+ CSH RP
VS-
VS-

High-Gain Band Pass Filter High-Speed Peak Detector

Figure 9-3. High-Gain Narrow Bandpass Filter and Peak Detector Circuit

Ultrasonic signaling is used for proximity and obstacle detection, level sensing, sonars, and so forth. Such signal
chains detect the amplitude of received ultrasonic signal at a particular center frequency. Figure 9-3 shows a
high-gain narrow bandpass filter and peak detector circuit using any of the OPAx863 devices. The signal at the
frequency of interest is filtered out, gained, and peak detected to report the amplitude at the output of this circuit.
The phase information is lost in this circuit. The OPAx863 devices are used with the 50-MHz GBW to add a
single-stage gain and filtering, and the peak detection capability is easily made with the RRIO capability of these
amplifiers.
9.2.3 Low-Power SAR ADC Driver and Reference Buffer
Figure 9-4 shows the use of the OPAx863 as a SAR ADC input driver and reference buffer driving the ADS7945.
sensors, which are used for interface with the physical environment, exhibit high output impedance, and cannot
drive SAR ADC inputs directly. A wide-GBW amplifier, such as the OPAx863, is needed to charge the switching
capacitors at the SAR ADC input, and quickly settle to the required accuracy within the given acquisition time.
The ADC core draws transient current from the reference input during the conversion (digitization) phase, which
must be driven with a wide-GBW amplifier to offer fast settling and maintain a stable reference voltage for
excellent digitization performance. The OPAx863 reference buffer is used in a composite loop with the OPA378
precision amplifier because of limitations in precision performance of wide-GBW amplifiers. The precision
amplifier maintains low-offset output, whereas the OPAx863 devices provide the output drive and fast-settling
performance.
RF
RG
6V
5V 5V
– RS
AVDD DVDD
Sensor ZOUT OPAx863
+ CCB ADS7945
14-bit
2 MSPS
VREF

5V
12 V
– 6V

REF5050 RFILT OPA378 –

5.0 V + OPAx863
Reference
CFILT +

Figure 9-4. OPAx863 as Low-Power SAR ADC Driver

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9.2.4 Variable Reference Generator Using MDAC

High-speed amplifiers can be used as a voltage buffer at MDAC output to generate a fast-settling variable
reference voltage. Figure 9-5 shows a representative circuit using DAC8801 and OPAx863.
VDD
RFB
+6 V
VREF IOUT
DAC8801 –
VOUT
+ OPAx863

6 V

Figure 9-5. Variable Reference Generator Using MDAC and OPAx863

9.2.5 Clamp-On Ultrasonic Flow Meter

Figure 9-6 shows how ultrasonic flow meters measure the rate of flow of a liquid using transit-time difference
(t12–t21), which depends on the flow rate. Figure 9-6 shows a representative schematic for a non-intrusive
ultrasonic flow meter using the OPAx863 and 12-V transducer excitation. The OPAx863 are used for the forward
path as a unity-gain buffer for 12-V pulsed transducer excitation at NODE 1. At the same time, the receiver
circuit at NODE 2 (which also uses the OPAx863) first provides an ac-gain followed by a dc-level shift to lead to
the PGA, ADC, and processor within the MSP430™ microcontroller.
NODE 2 and NODE 1 use similar transmit and receive circuits (discussed previously) for the reverse path.
The OPAx863 wide GBW of 50 MHz introduces minimal phase-delay and low-noise for excellent flow rate
measurement. The amplifier stays in power-down mode for a majority of the time in battery-powered systems.
This configuration results in very small average system-level power consumption and prolonged battery lifetime
with the 1.5‑µA (maximum) power-down mode quiescent current with a 3-V supply. The transmit and receive
signal chains are connected to the same point at the respective node transducers. Therefore, the OPAx863
12.6-V supply voltage capability enables 12-V transducer excitation without any damage to the front-end, or a
need for external switches, thus enabling a more compact solution. These specifications make the OPAx863 an
excellent choice for flow measurements in large diameter pipes and non-intrusive flow meters. The TIDM-02003
reference design discusses an ultrasonic gas flow sensing subsystem which uses high-speed amplifiers for
front-end amplification.

NODE-1 CFilt NODE-2

CG 3.3 V
12 V RG RF 3.3 V

± RISO
12 V
12 V R¶ MSP430FR6043
VTX + OPAx863 C AC2
12 V R ±
PGA ADC Processor
0V
VRX + OPAx863
t12 CAC1 R R¶

Transmitter

TRX1 TRX2
VTX
12 V Receiver
VRX
0V

Receiver t21 Transmitter

Figure 9-6. Non-Intrusive Ultrasonic Flow Meter

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9.3 Power Supply Recommendations

The OPAx863 is intended to operate on supplies ranging from 2.7 V to 12.6 V. The OPAx863 devices operate
on single-sided supplies, split and balanced bipolar supplies, or unbalanced bipolar supplies. Operating from a
single supply has numerous advantages. The dc errors, due to the –PSRR term, can be minimized with the
negative supply at ground. Typically, ac performance improves slightly at 10-V operation with minimal increase
in supply current. Minimize the distance (< 0.1 in) from the power supply pins to high-frequency, 0.01-µF
decoupling capacitors. A larger capacitor (2.2 µF typical) is used along with a high-frequency, 0.01-µF supply-
decoupling capacitor at the device supply pins. Only the positive supply has these capacitors for single-supply
operation. Use these capacitors from each supply to ground when a split-supply is used. If necessary, place the
larger capacitors further from the device and share these capacitors among several devices in the same area
of the printed circuit board (PCB). An optional supply decoupling capacitor across the two power supplies (for
split-supply operation) reduces second harmonic distortion.
9.4 Layout
9.4.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier (like the OPAx863) requires careful attention to
board layout parasitics and external component types. The OPA2863 DGK Evaluation Module user's guide can
be used as a reference when designing the circuit board. Recommendations that optimize performance includes
the following:
1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause instability on the noninverting input and can react with the
source impedance to cause unintentional band-limiting. Open a window around the signal I/O pins in all of
the ground and power planes around those pins to reduce unwanted capacitance. Otherwise, ground and
power planes must be unbroken elsewhere on the board.
2. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency 0.01-µF decoupling
capacitors. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the
supply pins. These capacitors can be placed somewhat farther from the device and shared among several
devices in the same area of the PCB.
3. Careful selection and placement of external components preserves the high-frequency performance
of the OPAx863. Resistors must be a low reactance type. Surface-mount resistors work best and allow a
tighter overall layout. Other network components, such as noninverting input termination resistors, must also
be placed close to the package. Keep resistor values as low as possible and consistent with load-driving
considerations. Lowering the resistor values keeps the resistor noise terms low and minimizes the effect
of the parasitic capacitance. Lower resistor values, however, increase the dynamic power consumption
because RF and RG become part of the amplifier output load network.

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9.4.1.1 Thermal Considerations

The OPAx863 does not require heat sinking or airflow in most applications. The maximum allowed junction
temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction
temperature to exceed 150°C.
Operating junction temperature (TJ) is given by,

TJ = TA + PD x RƟJA (4)

where
• TA is the ambient temperature
• PD is the total power dissipation internal to the amplifier
• RƟJA is the junction-to-ambient thermal resistance
The total power dissipation PD = PDQ + PDL
where
• PDQ = (VS+ ‐ VS-) x IQ, is the power dissipation due to the amplifier quiescent current
• PDL(max) = VS 2 / (4 × RL), is the internal power dissipation due to the output load current
As a worst-case example, compute the maximum TJ using an OPA2863-DGK (VSSOP package) configured as
a unity gain buffer, operating on ±6-V supplies at an ambient temperature of 25°C and driving a grounded 500-Ω
load.

PD = 12 V × 2 mA + 62 / (4 × 500 Ω) = 42 mW (5)

Maximum TJ = 25°C + (0.042 W × 180.3°C/W) = 33°C, which is much less than the maximum allowed junction
temperature of 150°C.
9.4.2 Layout Example
VS+
Representati ve schematic of a
single channel
C BYP

+ RS

C BYP
VS-

RG RF

Ground and power plane exist on inner

layers.

CBYP Ground and power plane removed

Place series output resistors close RS from inner layers. Ground fill on outer
to output pin to minimi ze 1 8 layers also removed
parasitic capacitance
RF
RS Place bypass capacitors
2 7 close t o power pins
RG
RF
Place gain and feedback resistors close
3 6 to pins to mi nimize stray capacit ance
RG
Place bypass capacitors
close t o power pins 4 5
Remove GND and Power plane under
CBYP output and i nv erting pins to minimize
stray PCB capacitance

Figure 9-7. Layout Recommendation for Dual-Channel DGK Package

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10 Device and Documentation Support

10.1 Documentation Support
10.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, OPA2863ADGK Evaluation Module user's guide
• Texas Instruments, Single-Supply Op Amp Design Techniques application report
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
MSP430™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 20-Jan-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA2863DR ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O2863D Samples

OPA2863IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG | SN Level-2-260C-1 YEAR -40 to 125 2FJ4 Samples

OPA2863RUNR ACTIVE QFN RUN 10 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 O263 Samples

OPA4863PWR ACTIVE TSSOP PW 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OPA4863 Samples

OPA863DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 2QS5 Samples

OPA863SIDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 O863 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Jan-2024

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA2863 :

• Automotive : OPA2863-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Oct-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2863DR SOIC D 8 3000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2863IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2863IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2863RUNR QFN RUN 10 3000 180.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
OPA4863PWR TSSOP PW 14 3000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
OPA863DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA863SIDBVR SOT-23 DBV 6 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Oct-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2863DR SOIC D 8 3000 356.0 356.0 35.0
OPA2863IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
OPA2863IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
OPA2863RUNR QFN RUN 10 3000 213.0 191.0 35.0
OPA4863PWR TSSOP PW 14 3000 356.0 356.0 35.0
OPA863DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA863SIDBVR SOT-23 DBV 6 3000 190.0 190.0 30.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
1.45 MAX

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

ALTERNATIVE PACKAGE SINGULATION VIEW

4214840/E 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/E 02/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/E 02/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

ALTERNATIVE PACKAGE SINGULATION VIEW

4214839/J 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/J 02/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/J 02/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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 GENERIC PACKAGE VIEW
RUN 10 WQFN - 0.8 mm max height
2 X 2, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4228249/A

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 PACKAGE OUTLINE
RUN0010B SCALE 5.000
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2.1
B A
1.9

2.1
PIN 1 INDEX AREA
1.9

0.8
0.7 C

SEATING PLANE
0.05 0.08 C
0.00

SYMM
(0.2) TYP
5
4
6

SYMM
2X 1.5

6X 0.5
9
1 0.3
10X
10 0.2
PIN 1 ID 0.1 C A B
0.6
10X 0.05
0.4

4226925/A 08/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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 EXAMPLE BOARD LAYOUT
RUN0010B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

SYMM

10X (0.7) SEE SOLDER MASK

10 DETAIL

10X (0.25) 1 9

SYMM
6X (0.5) (1.7)

(R0.05) TYP
4 6

(1.7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X

0.07 MIN
0.07 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK

EXPOSED METAL
SOLDER MASK EXPOSED SOLDER MASK
OPENING METAL OPENING

NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4226925/A 08/2021
NOTES: (continued)

3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).

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 EXAMPLE STENCIL DESIGN
RUN0010B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

10X (0.7)
10

10X (0.25) 1 9

SYMM
6X (0.5) (1.7)

(R0.05) TYP
4 6

5
SYMM

(1.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 20X

4226925/A 08/2021

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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