Verilog code for a comparator - FPGA4student.com https://www.fpga4student.com/2017/02/verilog-code-fo...

Home FPGA Projects Verilog Projects VHDL Projects FPGA Tutorial Verilog vs VHDL Search
About

Verilog code for a comparator

In this project, a simple 2-bit comparator is designed and implemented in Verilog HDL. Truth table, Join 18,000+ Followers
K-Map and minimized equations for the comparator are presented. The Verilog code of the
comparator is simulated by ModelSim and the simulation waveform is presented.

Popular FPGA projects

Verilog code for D Flip Flop

D Flip-Flop is a
fundamental component in
digital logic circuits. Verilog
code for D Flip Flop is
presented in this project. There are t...

Verilog code for Arithmetic

Logic Unit (ALU)
Last time , an Arithmetic
Logic Unit ( ALU ) is
designed and implemented
in VHDL . Full VHDL code for the ALU
was presented. Today, f...

The specification of the 2-bit comparator is as follows: Image processing on

FPGA using Verilog HDL
• Input: 2-bit A and B for comparison This FPGA project is
aimed to show in details
• Output: how to process an image
using Verilog from reading an input
◦ A_greater_B: high if A > B else low bitmap image (.bmp) in Verilog...
◦ A_equal_B: high if A = B else low
[FPGA Tutorial] Seven-
◦ A_less_B: high if A<B else low Segment LED Display on
Basys 3 FPGA
The truth table for the comparator: This FPGA tutorial will
guide you how to control
the 4-digit seven-segment display on
Basys 3 FPGA Board. A display
A1 A0 B1 B0 A_greater_ A_equal_B A_less_B controller will be ...
B
0 0 0 0 0 1 0 Verilog code for counter
with testbench
0 0 0 1 0 0 1
In this project, Verilog code
0 0 1 0 0 0 1 for counters with testbench
0 0 1 1 0 0 1 will be presented including
0 1 0 0 1 0 0 up counter, down counter, up-down
counter, and r...
0 1 0 1 0 1 0
0 1 1 0 0 0 1 VHDL code for Seven-
0 1 1 1 0 0 1 Segment Display on Basys
3 FPGA
1 0 0 0 1 0 0
Last time , I wrote a full
1 0 0 1 1 0 0 FPGA tutorial on how to
1 0 1 0 0 1 0 control the 4-digit 7-segment display on
1 0 1 1 0 0 1 Basys 3 FPGA. A full Verilog code for
displayi...
1 1 0 0 1 0 0
1 1 0 1 1 0 0 Verilog code for 16-bit
1 1 1 0 1 0 0 single cycle MIPS
1 1 1 1 0 1 0 processor
In this project, a 16-bit
single-cycle MIPS
K-Map tables and the corresponding equations for the comparator: processor is implemented in Verilog
HDL. MIPS is an RISC processor ,
which is widely used by ...
A1A0
A_greater 00 01 11 10
_B
B1B0 0 1 1 1
00
01 0 0 1 1
11 0 0 0 0
10 0 0 1 0

A_greater_B = B0 B1 A0 + B1 A1 + A1 A0 B0
= A0 B0 (B1 + A1) + + B1 A1

A1A0
00
A_equal 01 11 10
_B
B1B0 1 0 0 0
00
01 0 1 0 0

1 of 4 08/11/22, 15:40
Verilog code for a comparator - FPGA4student.com https://www.fpga4student.com/2017/02/verilog-code-fo...

11 0 0 1 0
10 0 0 0 1

A_equal_B = (B1 A1+A1 B1) (B0 A0+A0 B0)

A1A0
00
A_less_ 01 11 10
B
B1B0 0 0 0 0
00
01 1 0 0 0
11 1 1 0 1
10 1 1 0 0

A_less_B = A0 A1 B0 + A1 B1 + B1 B0 A0
After obtaining the minimized equations of the outputs of the comparator, it is easy to write Verilog
code for the comparator.
Below is the Verilog code for the comparator:

// FPGA projects using Verilog/ VHDL

// fpga4student.com : FPGA projects, Verilog projects, VHDL projects
// Verilog code for 2-bit comparator
module comparator(input [1:0] A,B, output A_less_B, A_equal_B, A_greater_B);
wire tmp1,tmp2,tmp3,tmp4,tmp5, tmp6, tmp7, tmp8;
// A = B output
xnor u1(tmp1,A[1],B[1]);
xnor u2(tmp2,A[0],B[0]);
and u3(A_equal_B,tmp1,tmp2);
// A less than B output
assign tmp3 = (~A[0])& (~A[1])& B[0];
assign tmp4 = (~A[1])& B[1];
assign tmp5 = (~A[0])& B[1]& B[0];
assign A_less_B = tmp3 | tmp4 | tmp5;
// A greater than B output
assign tmp6 = (~B[0])& (~B[1])& A[0];
assign tmp7 = (~B[1])& A[1];
assign tmp8 = (~B[0])& A[1]& A[0];
assign A_greater_B = tmp6 | tmp7 | tmp8;
endmodule
`timescale 10 ps/ 10 ps
// FPGA projects using Verilog/ VHDL
// fpga4student.com
// Verilog testbench code for 2-bit comparator
module tb_comparator;
reg [1:0] A, B;
wire A_less_B, A_equal_B, A_greater_B;
integer i;
// device under test
comparator dut(A,B,A_less_B, A_equal_B, A_greater_B);
initial begin
for (i=0;i<4;i=i+1)
begin
A = i;
B = i + 1;
#20;
end
for (i=0;i<4;i=i+1)
begin
A = i;
B = i;
#20;
end
for (i=0;i<4;i=i+1)
begin
A = i+1;
B = i;
#20;
end
end
endmodule
Finally, simulate the Verilog code and testbench in ModelSim and verify the operation of the
comparator through simulation waveform.

By observing the waveform, Verilog code for the comparator are working correctly.

Recommended Verilog projects:

2 of 4 08/11/22, 15:40