USN BUE303
Third Semester B.E./B.Tech. Degree Examination, Dec.2023/Jan.2024
Analog and Digital Electronics
Time: 3 hrs. Max. Marks: 100
Note: 1. Answer any FIVE full questions, choosing ONE full question from each module.
2. M : Marks , L: Bloom’s level , C: Course outcomes.
Module – 1 M L C
Q.1 a. Explain the Operation of Base bias circuit with relevant expression. 6 L1 CO1
b. Design a base-bias circuit with 12 V supply, IC = 2 mA, VCE = 9 V and 8 L3 CO4
β = 70 also find IB, RB and RC.
c. Explain the operation of BJT as a switch. 6 L2 CO1
OR
Q.2 a. Compare basic biasing circuits. 6 L2 CO4
b. A voltage divider bias circuit has R1 = 33 KΩ, R2 = 10 KΩ, RC = 2.2 KΩ, 8 L3 CO1
RE = 1 KΩ, VCC = 20 V, hFE = 100. Calculate VB, VE, IE, IC, VC and VCE,
assume VBE = 0.7 V.
c. What is stability factor? Explain the stability factors for basic biasing 6 L2 CO1
circuits.
Module – 2
Q.3 a. Explain the operation of phase shift oscillator. 6 L2 CO4
b. Design an RC phase shift oscillator to obtain an output signal frequency of 6 L3 CO4
1 kHz (Assume C = 0.1 μF)
c. Explain Colpitts oscillator with circuit diagram. 8 L2 CO4
OR
Q.4 a. With the help of neat diagram, explain the working of Wein bridge 6 L2 CO4
oscillator.
b. With neat circuit diagram, explain the operation of 555 pulse generator. 8 L2 CO4
c. Calculate frequency of oscillation and feedback fraction for Hartley 6 L3 CO4
oscillator. Given L1 = 1000 μH, L2 = 100 μH and C = 20 pF.
Module – 3
Q.5 a. Express the following functions into Canonical form, 6 L2 CO1
(i) f1 ab ac bc
(ii) f 2 a b(b c)
b. Obtain minimal expression using K-map for the following function : 8 L2 CO1
F(a , b, c, d ) m (0,1,4,6,7,9,15) d (3,5,11,13)
c. Design a logic circuit that has 4 inputs, the output will be high, when the 6 L3 CO1
majority of the inputs are high. Use K-map to simplify.
OR
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BUE303
Q.6 a. Simplify the Boolean function using Q-M minimization technique 10 L2 CO1
V f (a , b, c, d ) m( 2,3,4,5,13,15) d (8,9,10,11)
b. Reduce the following function using K-map method : 6 L2 CO1
f (a , b, c, d) M (0,2,3,8,9,12,13,15)
c. Explain combinational logic model. 4 L1 CO1
Module – 4
Q.7 a. Explain the carry look ahead adder with the relevant expressions and logic 8 L2 CO3
diagram.
b. Implement the following expression using 3 : 8 decoder with active high 6 L2 CO3
outputs :
(i) f1 ( x 2 , x1, x 0 ) m(1,5,7)
(ii) f 2 ( x 2 , x1 , x 0 ) M(2,3,4,6)
c. Design and implement half adder using logic gates. 6 L2 CO3
OR
Q.8 a. Design a two bit binary comparator and implement with suitable gates. 10 L3 CO2
b. Implement f(a, b, c, d) = M(0,3,5,8,9,10,12,14) using 8 : 1 MUX 10 L3 CO2
Module – 5
Q.9 a. Explain the working of Master-Slave JK-FF with logic diagram. 10 L2 CO2
b. Obtain the characteristic equation of JK and D-Flip Flop. 10 L2 CO2
OR
Q.10 a. Design synchronous mod-6 counter using clocked JK flip-flops for the 10 L3 CO5
sequence 0→2→3→6→5→1
b. Explain 4-bit universal shift register operation with suitable diagram. 10 L2 CO5
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