SPMC01A

SP
Microcontroller

SEP. 21, 2001

Version 1.4

SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO.
is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
 SPMC01A

Table of Contents
PAGE

1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3

2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3

3. FEATURES.................................................................................................................................................................................................. 3

4. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 4

4.1. PIN ASSIGNMENT .................................................................................................................................................................................. 4
5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 5
5.1. CPU ..................................................................................................................................................................................................... 5
5.2. MEMORY ............................................................................................................................................................................................... 5
5.3. OSCILLATOR .......................................................................................................................................................................................... 6
5.4. MASK OPTIONS...................................................................................................................................................................................... 6
5.5. FUNCTION CONTROL REGISTER.............................................................................................................................................................. 7
5.6. I/O AND CONTROL REGISTER - SEE APPENDIX A, B, C, D, F (I/O DIAGRAM) .......................................................................................... 8
5.7. RESET - SEE APPENDIX E (RESET BLOCK DIAGRAM) ........................................................................................................................... 10
5.8. INTERRUPT - SEE APPENDIX A, B, F, G (INTERRUPT DIAGRAM) ............................................................................................................11
5.9. WAIT / STOP MODE .............................................................................................................................................................................. 14

6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 15

6.1. ABSOLUTE MAXIMUM RATING ............................................................................................................................................................... 15
6.2. DC CHARACTERISTICS (VCC = 5.0V, TA = 25°C) ................................................................................................................................ 15
6.3. THE RELATIONSHIP BTWEEN THE ROSC AND THE FOSC............................................................................................................................. 16
7. APPENDIXS .............................................................................................................................................................................................. 17
7.1. APPENDIX A: PA5 - 0 & PB0 I/O DIAGRAM ........................................................................................................................................... 17
7.2. APPENDIX B: PA6, PA7 I/O DIAGRAM .................................................................................................................................................. 18
7.3. APPENDIX C: PB1 I/O DIAGRAM .......................................................................................................................................................... 19
7.4. APPENDIX D: PB4 & RESET I/O DIAGRAM ............................................................................................................................................ 20
7.5. APPENDIX E: RESET BLOCK DIAGRAM .................................................................................................................................................. 21
7.6. APPENDIX F: PB5 & IRQ I/O DIAGRAM ................................................................................................................................................ 22
7.7. APPENDIX G: INTERRUPT SOURCE DIAGRAM ........................................................................................................................................ 23
7.8. APPENDIX H: TIMER BLOCK DIAGRAM ................................................................................................................................................... 24

8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 25

8.1. PAD ASSIGNMENT ............................................................................................................................................................................... 25
8.2. ORDERING INFORMATION ..................................................................................................................................................................... 25
8.3. PAD LOCATIONS .................................................................................................................................................................................. 26
8.4. PACKAGE INFORMATION ....................................................................................................................................................................... 26
9. DISCLAIMER............................................................................................................................................................................................. 27

10. REVISION HISTORY ................................................................................................................................................................................. 28

© Sunplus Technology Co., Ltd. 2 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

MICROCONTROLLER

1. GENERAL DESCRIPTION 3. FEATURES

SUNPLUS SPMC01A contains a SUNPLUS 8 bit Micro-Controller ! Built-in 8-bit SUNPLUS CPU core and up to 6.0MHz clock
Units (MCU), 12 programmable general I/Os, 2.5K bytes ROM, 64 operation
bytes RAM and an 8-bit Timer. The advanced sub-micron CMOS ! 64 Bytes SRAM
process technology ensures SPMC01A‘s high performance, high ! 2.5K Bytes ROM for users' program
reliability and sophisticated functionalities. In addition, SPMC01A ! On-chip RC oscillator (only one external resistor needed) or
also provides high sink current with slow output transition port pins, crystal input or external clock input
multi external interrupt pins, Low Voltage Reset (LVR) function, ! Total 10 programmable I/Os
and multi oscillator options. SPMC01A offers one of the best ! Up to 6 external interrupt pins
cost/performance ratios in the industry. ! 1 I/O can be with RESET input selected by Mask Option
! 3 I/Os with Slow output transition Function
! One 8-bit timer with Real Time Interrupt
2. BLOCK DIAGRAM ! One Watchdog timer
! Power-saving STOP & WAIT modes
XO/R OSC. 2.5K bytes ROM 64 bytes RAM ! Illegal address reset
XI CKT $600~$FFF $C0 ~ $FF

! Low voltage reset circuit

VDD
! Operating Voltage Range: 2.4V - 5.5V
8 - bit CPU
VSS
! Provides Chip Form, Package in PDIP or SOIC
DATA BUS

TIMER 1 Interrupt Generator

& RTI &
& Watch_Dog timer RESET generator

PA3 - 0 I/O PORT PA6 - 4

ADDRESS BUS

/1
& /5 I/O PORT
PA7 External Interrupt PB0,PB1

I/O PORT I/O PORT

RESET(PB4) & /1 /1 & IRQ(PB5)
External RESET Pin External IRQ Pin

© Sunplus Technology Co., Ltd. 3 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

4. SIGNAL DESCRIPTIONS
Mnemonic PIN No. Type Description
VDD 15 I Power
VSS 14 I Ground
XO/R 1 I Crystal in or resistor
XI 2 O Crystal out or Ext. Clock in
RESET/PB4 3 I/O External reset or PB4 (I/O)
IRQ/PB5 13 I/O Interrupt in or PB5 (I/O)
PA3 - 0 12 - 9 I/O Port A
PA7 - 4 7-4
PB0 8 I/O Port B
PB1 16

4.1. PIN Assignment

XO/R 1 16 PB1
XI 2 15 VDD
RESET/PB4 3 14 VSS
PA7 4 13 IRQ/PB5
PA6 5 12 PA0
PA5 6 11 PA1
PA4 7 10 PA2
PB0 8 9 PA3

16 PIN DIP PACKAGE

© Sunplus Technology Co., Ltd. 4 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

5. FUNCTIONAL DESCRIPTIONS
5.1. CPU 5.2. Memory
The microprocessor of SPMC01A is a SUNPLUS high 5.2.1. Memory map
performance processor equipped with Accumulator, Program $0000
Counter, X Register, Stack Pointer and Processor Status Register
I/O Registers
(The same as 6502 instruction‘s structure). SPMC01A is a fully
static CMOS design. The oscillation frequency could be varied $000A
$000B
up to 6.0MHz depends on the application needs. The SPMC01A
development system includes a SUNPLUS ICE, Evaluation Chip Not used
and Engineering Development Board. $00BF
$00C0
User SRAM
5.1.1. Processor status register
64 bytes
Bit 7 6 5 4 3 2 1 0
$00FF
Flag N V - B - I Z C $0400
N: Negative, V: Overflow, B: Brk command, I: IRQ disable, Z: Zero, C: Carry Reserved for test

0.5K bytes ROM

5.1.2. Block diagram of SUNPLUS CPU $05FF
$0600
REGISTER SECTION CONTROL SECTION Program ROM
RESET IRQ NMI

INTERRUPT
LOGIC
2.5K bytes
$0FFF
A0 INDEX RDY
A1 REGISTER
A2 X PD
A3
5.2.2. RAM
ABL

A4
A5 STACK POINT
REGISTER
A6
Total of sixty-four bytes of RAM (including the stack) is available
S
A7
INSTRUCTION
DECODE
ALU
from $00C0 to $00FF. The stack begins at address $00FF and
ADDRESS
BUS proceeds down to $00C0.
ACCUMULATOR
A
TIMING
CONTROL

A8
PCL
5.2.3. ROM
PCH
A9
PROCESSOR CLOCK
A10
A11 INPUT DATA
STATUS
REGISTER
GENERATOR
Total of 3072 bytes of on-chip ROM including 2560 bytes of user
ABH

P
CLK 0 IN
A12 LATCH
A13 IDLI
R/W
ROM located from $0600 through $0FFF and 512 bytes of internal
A14
A15 DATA BUS
BUFFER
INSTRUCTION
REGISTER test ROM located from $0400 through $05FF. Users‘ program
D0
LEGEND
D1
D2
DATA
can only be allocated $0600 through $0FFF (2.5K).
= 8BIT LINE = 1 BIT LINE D3
D4 BUS
D5
D6
D7

5.2.4. NMI, RESET, IRQ vectors

The address of NMI (not provided in this chip), RESET and IRQ
are located from $0FFA to $0FFF. The interrupt vectors should
be specified in the program as follows:

ORG $0FFA ;define SPMC01A chip

;interrupt vector.
DW NMI_ROUTINE
DW RESET
DW INT_ROUTINE

© Sunplus Technology Co., Ltd. 5 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

When using Evaluation board with EPROM (for 27C256), the

SPMC01A SPMC01A SPMC01A
address of $7FFA must be defined as follows:
XI XO/R XI XO/R XI XO/R

VDD
ORG $7FFA ;interrupt vector for
Rosc UNCONNECTED
;EPROM with 20 pf 20 pf
External Clock
DW NMI_ROUTINE ;Evaluation Board.
(a) Crystal or (c) External
DW RESET Ceramic Resonator (b) RC Oscillator Clock Source
Connections Connections Connection
DW INT_ROUTINE

When using Evaluation board with Sunplus ICE, users fill the ORG 5.4. Mask Options
address of $0FFFA as follows:
The SPMC01A has the following mask options:
1). Oscillator Select: Crystal / Resonator or External Resistor or
ORG $0FFFA ;interrupt vector for
External Clock input.
;SUNPLUS ICE.
2). PA5 - 0, PB0 Pull-down and PB1 Pull-up resistor: always
DW NMI_ROUTINE
disable or controllable by user‘s program.
DW RESET
3). PA3 - 0 external Interrupt capability: Enable or Disable.
DW INT_ROUTINE
4). External Interrupt Trigger (PA3 - 0 and IRQ): Edge Trigger or
Edge-Level Trigger.
5.3. Oscillator 5). RESET / PB4 pin: I/O or I/O with RESET input function.
The SPMC01A supports AT-cut parallel resonant oscillated Crystal 6). Timer clock source: fCPU/4 or fCPU/1.
/Resonator or RC oscillator or external clock sources by mask 7). Watch-Dog Timer Reset: Enable or Disable.
option (select one from those three types). The design of 8). Low Voltage Reset: Reset on Vcc while lower than 2.2V
application circuit should follow the vendors‘ specifications or voltage or No detection.
recommendations. The diagrams listed below are typical
X’TAL/ROSC circuits for most applications:

© Sunplus Technology Co., Ltd. 6 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

5.5. Function Control Register

All function registers will set to ‘0’ when a reset occurred except the RT1 and RT0 will set to ‘1’ when a reset occurred.
Addr Register R/W 7 6 5 4 3 2 1 0 Enable
$0000 R PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PORT A DATA
PA W (0) (0) (0) (0) (0) (0) (0) (0)
$0001 R PB5 PB4 X(0) PB1 PB0
PORT B DATA
PB W (0) (0) PB2 (0) (0)
$0002 PORT A DATA R (0) (0) (0) (0) (0) (0) (0) (0) 0 = IN
DPA DIRECTION W DPA7 DPA6 DPA5 DPA4 DPA3 DPA2 DPA1 DPA0 1 = OUT
$0003 PORT B DATA R (0) (0) (0) (0) (0) (0) 0 = IN
DPB DIRECTION W SLE DPB5 DPB4 DPB2 DPB1 DPB0 1 = OUT
$0004 TIMER CONTROL R TOF(0) RTIF(0) TOFE RTIE 0(0) 0(0) RT1 RT0
TCS & STATUS W (0) (0) TOFR RTIFR (1) (1) 1 = SET
$0005 TIMER COUNTER R TMR7(0) TMR6(0) TMR5(0) TMR4(0) TMR3(0) TMR2(0) TMR1(0) TMR0(0)
TCR REGISTER W
$0006 IRQ CONTROL & R (0) (0) IRQF(0) IRQF1(0) IRQE1 IRQE
IRQS STATUS W IRQR1 IRQR (0) (0) 1 = SET
$0007 WATCH DOG R
WDT TIMER STATUS W WDT(0) 1 = CLR
$0008 R
STOP & WAIT
SNW W STOP(0) WAIT(0) 1 = SET
$0009 PORTA PULLUP / R (0) (0) (0) (0) (0) (0)
RPA DOWN REGISTER. W RPA5 RPA4 RPA3 RPA2 RPA1 RPA0 0 = EN
$000A PORTB PULLUP / R (0) (0) (0)
RPB DOWN REGISTER. W RPB4 RPB1 RPB0 0 = EN
The value of bracket is power-on default value.
The gray block Is reserved.

© Sunplus Technology Co., Ltd. 7 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

5.6. I/O and Control Register

- see Appendix A, B, C, D, F (I/O Diagram)
Total of 12 I/Os (grouped into two I/O ports, PA and PB) are normal I/Os and pull-up always. PB1 is normal I/O with
provided. The descriptions are as follows: programmable pull-up.
1). The PortA (PA7 - 0) and PortB (PB1 - 0) are normal I/O ports. 2). The other 2 I/Os can be used as RESET or PB4 by MASK
PA5 - 0 and PB0 have programmable pull-down. PA7 - 6 are Option and IRQ or PB5 by programming control.

5.6.1. Port A (PA7 - 0) description: (see Appendix A, B)

Addr Register 7 6 5 4 3 2 1 0
$0000 PORT A DATA DATA DATA DATA DATA DATA DATA DATA DATA
0 In In In In In In In In
$0002 DIRECTION
1 Out Out Out Out Out Out Out Out
0 Always Always Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down Pull-Down
$0009 Pull-Up/Down
1 Pull-Up Pull-Up Disable Disable Disable Disable Disable Disable
Up/Down resistor 5KΩ 5KΩ 100KΩ 100KΩ 100KΩ 100KΩ 100KΩ 100KΩ
Source/sink current -/8mA -/8mA -8/8mA -8/8mA -8/8mA -8/8mA -8/8mA -8/8mA
Special Function Ext. INT - - - Ext. INT Ext. INT Ext. INT Ext. INT

5.6.2. Port A data registrar ($0000 PA) 5.6.4. Port A pull-down control register ($0009 RPA)
PortA‘s output data will be determined by $0000 (PA Data Register) PA5-0 Pull-down resistors can always be disabled or controlled by
when PortA programmed as output. Any read of the PortA Data user's program through mask option, but PA6 and PA7 are pull-up
Register will return the logical state of the I/O pin when PortA is always. The register, RPA, is used to enable or disable the
programmed as input. The PA Data Register is set to ‘0’ when a pull-up/down resistors on PA5-0, when the resistors are existing
RESET occurred. selected by mask option. When RPA = ’0’, it will enable pull-down
resistor of corresponding pins (PA5 - 0) at Input mode. When
5.6.3. Port A data direction register ($0002 DPA) RPA = ’1’, it will disable pull-down resistor of corresponding pins

The Port A can be programmed as input or output by $0002 DPA (PA5 - 0) at Input mode. No pull-down resistor is available during

Register. When DPA = ’1’, the corresponding pin programmed as output mode. The RPA will be set to ‘0’ (enabling mode) by

output. When DPA = ’0’, the corresponding pin programmed as RESET.

input. The DPA is set to ‘0’ (input) when a RESET occurred.

Note: SPMC01A: PA [0..5] can be pull-down or disable.
" In SPMC05A, both pull-up and pull-down are available. However,
when using SPMC05A to simulate SPMC01A and disable Rp,
SUNPLUS recommends to disable Rp by setting $0009 RPA = 1 in
SPMC05A.

5.6.5. Port B (PB0, PB1, RESET/PB4, IRQ/PB5): (see Appendix A, C, D, F)

Addr Register 7 6 5 4 3 2 1 0

$0001 PORT B DATA IRQ/DATA RESET/DATA X DATA DATA

0 In In X In In
$0003 DIRECTION SLE*
1 Out Out Aux Out Out
0 Pull-Up Pull-Up Pull-Down
$000A Pull-Up/Down
1 Disable Disable Disable
Up/Down resistor 100KΩ 100KΩ 100KΩ
Source/sink current -/8mA -8/8mA -/25mA -/25mA -8/8mA
Special Function IRQ RESET - -
Note*: This bit is defined as SLE bit. Please refer to SLOW TRANSITION ENABLE for more detail.

© Sunplus Technology Co., Ltd. 8 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

5.6.6. Port B data register ($0001 PB) 5.6.10. IRQ / PB5: (see Appendix F)
PortB‘s output data will be determined by $0001 PB Data Register The IRQ/PB5 pin can be selected as I/O or I/O with IRQ by
when PortB is programmed as output. Any read of the PortB program.
Data Register will return to logical state of I/O pin when PortB is 1). When IRQ function is selected, the IRQ pin is the main
programmed as input. Data register will be set to ‘0’ when external source of an interrupt with active-low polarity. This
RESET occurred. pin is connected to a Schmitt trigger input. It is an open-drain
mode and therefore, it needs to be pulled-up externally.
5.6.7. Port B data direction register ($0003 DPB) 2). When I/O function is selected, PB5 pin is normal I/O with

PortB can be programmed as input or output by $0003 DPB open-drain always.

Register. When DPB = ’1’, the corresponding pin(s) is (are)

programmed as output. When DPB = ’0’, the corresponding pin(s) 5.6.11. High sink current port: (see Appendix C)
is (are) programmed as input. The DPB will be set to ‘0’ (input The PB1 output current can sink 25mA or 50mA determined by the
mode) when a RESET occurred. The direction of PB1 and PB2 programming of DPB B1, B2, and PB B1, B2. To configure I/O
must be identical. mode on PB1 properly, the direction of DPB1 and DPB2 must be
identical. Output sinks current as following (DPB B1 = 1 and DPB
5.6.8. Port B pull-up/down control register ($000A RPB) B2 = 1):

PB0 Pull-down with PB1 Pull-up resistors can be disabled or

controlled by user‘s program through mask option. PB4 Pull-up 5.6.11.1. The sink current is 25mA when PB B1 = 0
resistor can be disabled or controlled by user‘s program. The and PB B2 = 1.
register, RPB, is used to enable or disable the pull-up/down Example: PB0 set as input. PB1, PB4 as output.

resistors on PB0, PB1 and PB4. When RPB = ’0’, it will enable
pull-down resistor of PB0 or pull-up of PB1, PB4 at Input mode. LDA #%XXX1X110 ;X don‘t care

When RPB = ’1’, it will disable the corresponding pull-down STA DPB ;set PB4, PB1 as output, PB0

resistors of PB0 or pull-up of PB1, PB4 at Input mode. No ;as input

pull-down resistor is available during output mode. The RPB will LDA #%XXX1XX00

be set to ‘0’ (enabling mode) by RESET. STA RPB ;set PB0 pull-down, PB1
;pull-up, PB4 no pull-up.
Note: Pull-up or down varied on different bodies LDA #%XXX1X10X
SPMC01A: PB0: Pull-down or disable, PB1: pull-up or disable STA PB ;PB4 is “high”, PB1 is “low”
SPMC05A: PB0: Pull-down or up, PB1: No option (always pull-up)
;& sink current is 25mA.
LDA PB ;from PB0 read out side
In SPMC05A, both pull-up and pull-down are available. However,
;data.
when using SPMC05A to simulate SPMC01A and disable Rp,
AND #%00000001 ;only used PB0
SUNPLUS recommends to disable Rp by setting $000A RPB = 1
in SPMC05A.
5.6.11.2. The sink current is 50mA when PB B1 = 0
5.6.9. RESET / PB4: (see Appendix D) and PB B2 = 0.
Example: PB0 set as input. PB1, PB4 as output.
The RESET/PB4 pin can be selected as I/O or I/O with RESET by
Mask option. When RESET is selected, RESET pin is the only
LDA #%XXX1X110 ;X don‘t care
external source of reset. This pin is connected to a Schmitt
STA DPB ;set PB4, PB1 as output, PB0
trigger input gate, pull-up 100KΩ (by setting $000A b4 = 0) & low
;as input
active. PB4 pin is a normal I/O with programmable pull-up
LDA #%XXX1XX00
100KΩ when I/O function is selected.
STA RPB ;set PB0 pull-down, PB1
;pull-up, PB4 no pull-up.
LDA #%XXX1X00X
STA PB ;PB4 is “high”, PB1 is “low”
;& sink current is 50mA.

© Sunplus Technology Co., Ltd. 9 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

5.6.11.3. PB1 is used as input when DPB B1 = 0 and

DPB B2 = 0.
Example: PB0, PB1, and PB4 set as input. Loop1: LDA TEMP
EOR #C2h ;cross-change B6, B7 & B1
LDA #%XXX0X000 ;X don‘t care STA TEMP
STA DPB ;set PB4, PB1, and PB0 as STA PA ;PA6, PA7 output pulse.
;input STA PB ;PB1 output pulse
LDA #%XXX1XX00 LDX #00h ;delay
STA RPB ;set PB0 pull-down, PB1 Loop2: DEX
;pull-up, PB4 no pull-up. BNE Loop2
LDA PB ;from PB4, PB1, and PB0 read JMP Loop1 ;repeat output of PA6, PA7,
;out side data. ;PB1.
AND #%00010011 ;use PB4, PB1, and PB0
No enable slow transition enable slow transtiion with capacitor
5.6.12. External interrupt input ports: PB1 PA6 PB1 PA6
50pf 500pf

(see Appendix A, B, F, G) PA7 PA7

500pf

The PA3 - 0, PA7, and PB5 can be used as I/O or I/O with
interrupt function. For interrupt function, PA3 - 0 interrupt is CPUCLK

enabled or disabled by mask option and controlled by IRQE PA6,PA7,PB1 Falling & Rising
edge slow transition
($0006). PA7 is enabled or disabled by IRQE1 ($0006). PB5 is
no slow transtion slow transtion
enabled or disabled by IRQE ($0006). For more details on
interrupt statements, please see INTERRUPT section.
5.7. RESET - see Appendix E (Reset Block Diagram)
5.6.13. Slow transition enable (SLE)- $0003 bit 7 5.7.1. External reset (RESET pin) (see Appendix D, E)
(see Appendix C)
The RESET/PB4 pin can be select to PB4 I/O or I/O with RESET
PA6, PA7 and PB1 pins have Slow Transition signal output function by Mask option. When RESET is selected, the RESET
function (SLE). If this function is enabled ($0003 bit7 = 1), the pin is the only external reset source with active-low polarity. This
transition time of outputs is 250ns ± 20% with 50pf(PB), 500pf(PA)
pin is connected to a Schmidt trigger input. It has pull-up resistor
loaded at 2.0MHz. When SLE ($0003 bit7) = 0, slow transition by programmed control. It is recommended to set RPB b4 as ‘0’
output is disabled. Note that the SLE register of SPMC01A is in to enable pull-up resistor when RESET function is applied, such
$03 PORTB DATA DIRECTION. However, the SLE register of does not need an external resistor.
SPMC02A and SPMC05A is in $09 PORTA PULL-UP/DOWN
REGISTER. If SPMC05A is used to simulate SPMC01A, the SLE 5.7.2. Power on reset (see Appendix E)
should be modified for the difference before code releasing for
This reset is an internal reset. The Power-on-Reset will generate
SPMC01A.
the reset signal that will reset the CPU until oscillator stabilized.
To confirm the Power on Reset is generated properly, the system
Example: PA6, PA7 & PB1 set as output and have slow transition
power should be held at a zero potential with respect to ground.
function.
Improper initial setting of the power might cause the system can
not work properly. The CPU will become active after 4096 clock
LDA #%11XXXXXX ;X: user-define
cycles.
STA DPA ;DPA $0002 port A direction,
;set PA6, 7 as output
5.7.3. Watch dog timer reset ($0007 bit0 WDT)
LDA #%1XXXX11X ;DPB $0003 port B direction,
(see Appendix E, H)
;set PB1 as output
STA DPB ;and set SLE as “1” for The Watch-Dog Timer can be disabled or enabled through mask

;enable slow transition. option. The internal reset of Watch-Dog will be generated by a

LDA #FFh time-out of the Watch-Dog Timer automatically when Watch-Dog is

STA TEMP ;TEMP a register of $C0h~Ffh enabled. It is implemented on this device by using the output of

© Sunplus Technology Co., Ltd. 10 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

the RTI circuit and further dividing it by eight (RT1, RT0 timing Preventing a WDT time-out reset is done by writing a ‘1’ to WDT
times 8). This time out generates reset if the WDT register is not ($0007 b0) within a specific time. The min. WDT reset times
clear. An internal reset is generated and reset vector is fetched. listed in (RT1, RT0) & WDT Interrupt Frequency Table.

Addr Register R/W 7 6 5 4 3 2 1 0 Enable

$0007 WATCH DOG R
WDT TIMER STATUS W WDT(0) 1 = CLR

Example: Clear Watch-Dog Timer 5.7.5. Low voltage reset (LVR) (see Appendix E)
MainPGMLoop: The internal LVR reset generated when VDD falls below the
JSR Clear_WDT specified LVR trigger voltage value (2.2 volt.) at least one CPU
.... ;Long program will over clock cycle.
;Watch-Dog Timer
JSR Clear_WDT ;so need call clear WDT 5.8. Interrupt - see Appendix A, B, F, G
;subroutine again. (Interrupt Diagram)
....
5.8.1. Software interrupt (BRK)
JMP MainPGMLoop
The BRK is an executable instruction interrupt since it executed
Clear_WDT:
regardless of the state of the I-bit in the processor status register
LDA #01h
flag (inside CPU). When BRK occurred, jump to IRQ_routine.
STA WDT ;WDT ($0007), clear
As with any instruction, interrupts pending during the previous
;$0007 B0 WDT register.
instruction is served.
RTS

5.8.2. External interrupt

5.7.4. Illegal address reset (IAR) (see Appendix E)
The External interrupt sources include IRQ pin, PA3 - 0 and PA7.
The internal reset of IAR generated when an instruction opcode
The IRQ pins provide an asynchronous interrupt to the CPU by
fetch occurs from an address not implemented in the RAM
program control. The PA3-0 can be mask option as an external
($00C0-$00FF) nor ROM ($0400-$0FFF). The IAR will generate
interrupt. PA7 can be programmed as an external interrupt, not
the reset signal that will reset the CPU and other peripherals.
by mask option. The PA7 and IRQ pin are designed with Schmitt
Trigger input and low active, but PA3 - 0 are high active.

Addr Register R/W 7 6 5 4 3 2 1 0 Enable

$0006 IRQ CONTROL & R 0(0) 0(0) 0 0 IRQF(0) IRQF1(0) IRQE1 IRQE
IRQS STATUS W IRQR1 IRQR (0) (0) 1 = SET

5.8.3. IRQ, PA3 - 0 interrupt (see Appendix A, F, G)

The IRQ/PB5 pin can be selected to I/O or I/O with IRQ by 1). Falling edge on the IRQ pin.
program. When IRQ function is selected, the IRQ pin is the main 2). Rising edge on any of PA3 - 0 pin. (If PA3 - 0 is mask option
external source of an interrupt with active-low polarity. This pin is enabled.)
connected to a Schmitt trigger input. Since it is an open-drain
mode, it needs to be pulled-up externally. When PB5 I/O function If mask option is set to “Edge-Level Trigger” mode, the following
is selected, PB5 is normal I/O with open-drain always. When conditions will cause IRQ interrupt:
IRQE1 is disabled, the interrupt flag of IRQ, IRQF, will be cleared
during creating interrupt. However, if IRQE1 is enabled, the 1). Falling edge and Low level trigger on the IRQ pin.
IRQF will not be cleared by interrupt. This interrupt source can be 2). Rising edge and High level on any one of PA3 - 0 pin. (If PA3 -
either " Edge-Trigger" or "Level-Trigger". It is selected by mask 0 is mask option enabled.)
option. If mask option is set to “Edge-Trigger” mode, the following
conditions will cause IRQ interrupt:

© Sunplus Technology Co., Ltd. 11 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

When IRQ pin or PA3 - 0 pins generate an interrupt (it sets IRQF IRQ_END:
($0006 bit3) = 1), the IRQE (if set $0006 bit0 = 1, enable the STA IRQS
interrupt function of IRQ) controls whether the interrupt request RTI
being sent to CPU. The IRQR ($0006 bit6) is the IRQ pin and
Note*: The IRQ pin is not register-mapped; so, it could not acknowledge
PA3 - 0 pins interrupt acknowledge. When IRQR = 1, it will clear
from register. It needs software check only.
the interrupt flag, IRQF.

5.8.5. Timer interrupt (TIMER) (see Appendix H)

5.8.4. PA7 interrupt (see Appendix B, G)
The timer‘s interrupt is generated by the multi-function timer when
The PA7 interrupt is falling-edge trigger. It is controlled by IRQE1
either a timer overflow or a real-time interrupt has occurred. The
($0006 bit 1). When PA7 interrupt occurred, the interrupt flag of
timer-interrupt flags (TOF, RTIF), enabling bits (TOFE, RTIE) and
PA7, IRQF1 ($0006 bit2), will be set. The IRQR1 ($0006 bit7) is
timer-interrupt-acknowledge bits (TOFR, RTIFR) are all for the
the PA7 pin interrupt acknowledge. When IRQR1 = ’1’, it will
timer interrupt in the Timer Control & Status Register (TCS)
clear the interrupt flag IRQF1 ($0006 bit2 = 0).
located at $0004. The I-bit in the Processor Status Flag (inside of
CPU) must be cleared to ‘0’ to ensure the interrupt is enabled.
Example: Use IRQ pin, PA3 - 0, PA7 as interrupt.
For more details on settings of the Timer Control & Status
Registrar (TCS), please see the MULTI-FUNCTION TIMER
LDA #%11000011 ;enable IRQ, PA3 - 0,
section.
;PA7 and clear interrupt
;Flag
5.8.6. Multi-function timer- See Appendix H
STA IRQS ;IRQS = $0006
(Timer Block Diagram)
.... ;Other working
The timer is a 15-bit multi-function ripple Up-Counter. The
IRQVacter:
feature functions include Timer Overflow, Real Time Interrupt (RTI),
LDA IRQS ;Interrupt subroutine.
Power on Reset, and Watch-Dog-Timer Reset (WDT). When the
AND #%00000100 ;check interrupt of PA7
Timer Counter Register (TCR $0005) overflows, the Timer
BNE PA7_IRQ
Overflow Flag (TOF) will be set and TOF = 1 will occur an interrupt
PA03_IRQ:
request to CPU if Timer Overflow Enable is set (TOFE = 1). As
LDA IRQS
long as TOFR = ’1’, the TOF flag bit is always cleared. The Real
AND #%00001000 ;check interrupt of
Time Interrupt Flag (RTIF) will be set when 1 of 4 selections (RT1,
;PA3 - 0
RT0) is active. RTIF = 1 will generate an interrupt request to
BEQ IRQ_END ;no PA3 - 0 & PA7
CPU if Real Time Interrupt Enable set (RTIE = 1). Whenever
;external interrupt
RTIFR = 1, the RTIF flag bit will be cleared. When a RESET is
.... ;PA3 - 0 interrupt
occurred, RT1 and RT0 of TCS are set as ‘1’ and rest of the bits
;work something.
on TCS are set as ‘0’.
LDA #%01000011 ;set PA3 - 0, PA7 &
;clear PA3 - 0 IRQ
5.8.7. Timer register
;Flag. But
JMP IRQ_END ;don't clear PA7 IRQ Flag The 15-Stage timers contain two registers: Timer Counter & Timer

;for next IRQ of PA7. Control/Status Register.

PA7_IRQ:
.... ;PA7 interrupts 5.8.7.1. Timer counter register (TCR) - $0005
;work something. The timer counter register is a read-only register that contains the
LDA #%10000011 ;set PA3 - 0, PA7 & current value of the 8-bit at the beginning of the timer chain. The
;clear PA7 IRQ Flag, value of each bit of the TCR is shown in following table. The
;but do not clear PA3 register is cleared by reset.
;- 0 IRQ Flag for next
;IRQ.

© Sunplus Technology Co., Ltd. 12 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

Addr Register R/W 7 6 5 4 3 2 1 0 Enable

$0005 TIMER COUNTER R TMR7(0) TMR6(0) TMR5(0) TMR4(0) TMR3(0) TMR2(0) TMR1(0) TMR0(0)
TCR REGISTER W
Timer Counter Register (TCR)

5.8.7.2. Timer control/status register (TCS)- $0004

The TCS contains the timer interrupt flag (TOF, RTIF), the timer Bit 2 and bit 3 are write-only bits that will read as logical zeros.
interrupt enable (TOFE, RTIE), timer interrupt acknowledge The following table shows the value of each bit in the TCS, which
(TOFR, RTIFR) and real timer interrupt rate select bits (RT1, RT0). is set to 0. RT1 and RT0 are set to 1 by reset initially.

Addr Register R/W 7 6 5 4 3 2 1 0 Enable

$0004 TIMER CONTROL R TOF(0) RTIF(0) TOFE RTIE 0(0) 0(0) RT1 RT0
TCS & STATUS W (0) (0) TOFR RTIFR (1) (1) 1 = SET
Timer Control/Status Register (TCS)

5.8.8. TOF - Timer overflow flag 5.8.11. RTIE - Real time interrupt enable
(The TOF is a read-only flag bit.) The RTIE is an enable bit that allows generation of a timer
1 = Set when the 8-bit ripple counter rolls over from $FF change to interrupt by the RTIF bit.
$00. A timer interrupt request will generate if TOFE also set. 1 = When set, the timer interrupt generated when the RTIF flag bit
0 = Reset by writing a logical one to the TOF acknowledgment bit, set.
TOFR. 0 = When cleared, there is no timer interrupt being generated
even though RTIF flag is set.
5.8.9. RTIF - Real time interrupt Flag
(The RTIF is a read-only flag bit.) 5.8.12. TOFR - Timer overflow acknowledge
1 = Set when the output of the chosen Real Time Interrupt stage The TOFR is an acknowledgment bit that resets TOF flag.
goes active. A timer interrupt request will generate if RTIE is Reading the TOFR will always return a logical zero.
set. 1 = Clears the TOF flag bit.
0 = Reset by writing a logical one to the RTIF acknowledges bit, 0 = Does not clear the TOF flag bit.
RTIFR.
5.8.13. RT1:RT0 - Real time interrupt rate select
5.8.10. TOFE - Timer overflow enable The RT0 & RT1 control bits select one of four taps for the Real
The TOFE is an enable bit that allows generation of timer interrupt Time Interrupt circuit. The following table shows the available
upon overflow of the Timer Counter Register. interrupt rates for two frequency values of timer 1 clock selected
1 = When set, the timers interrupt generated when the TOF flag bit by mask option.
set.
0 = When cleared, there is no timer interrupt being generated for
TOF1 flag.

Example: CPU Clock fCPU = 1.0MHz (Oscillation Frequency = 2MHz) with two options for Timer 1 clock

RTI RATES MIN. WDT RESET (=RTI/8)

RT1:RT0 Divider option fCPU/4 option fCPU/1 Divider option fCPU/4 option fCPU/1

00 2048 8.192ms 2.048ms 16384 65.536ms 16.384ms

01 4096 16.384ms 4.096ms 32768 131ms 32.768ms
10 8192 32.768ms 8.192ms 65536 262ms 66ms
11 16384 65.536ms 16.384ms 131072 524ms 131ms
(RT1, RT0) & WDT Interrupt Frequency Table at fCPU = 1.0MHz.

© Sunplus Technology Co., Ltd. 13 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

Example: Enable Timer Counter & RTI (RT1 = 1,RT0 = 0), use
2.0MHz Rosc.

LDA #%00111110 ;TCS $0004 set TOFE, TO_IRQ:

;RTIE, RT1, RT0 = 10, .... ;Working for used
STA TCS ;& clear interrupt Flag ;Timer Overflow (TO)
.... ;Other instruction for LDA #%00111010 ;set RTI, TO enable
;initialized or work ;again, only clear
CLI ;software enable interrupt ;TOF
IRQ_Vacter: IRQ_END:
LDA TCS ;Interrupt subroutine. STA TCS
AND #%10000000 ;check Timer Overflow RTI
;interrupt
BNE TO_IRQ 5.9. Wait / Stop Mode
RTI_IRQ: The WAIT mode function will set CPU clock disabled and Timer
LDA TCS counter enabled if WAIT $0008 bit0 = 1. The TOF, RTI, or
AND #%01000000 ;check Real Time external interrupt will make CPU being recovered normally from
;Interrupt wait mode interrupt point next address. The STOP mode
BEQ IRQ_END function will set CPU and Timer counter disabled if STOP $0008
.... ;Working for used RTI bit4 = 1 and only the external interrupt will make CPU and Timer
counter being recovered normally from Stop mod interrupt point
LDA #%00110110 ;set RTI, TO enable next address.
;again, only clear
;RTIF
JMP IRQ_END

Addr Register R/W 7 6 5 4 3 2 1 0 Enable

$0008 R
STOP & WAIT
SNW W STOP(0) WAIT(0) 1 = SET

Example:
.... ;Normal working. Stop_Set:
Wait_Set: LDA #%00010000 ;set Stop mode
LDA #%00000001 ;STPWAT $0008, set ;enable.
;Wait modes enable. STA STPWAT ;enter the STOP mode.
STA STPWAT ;enter the WAIT mode. NOP ;*
NOP ;* NOP ;
NOP ; .... ;Normal working.
.... ;Normal working. JMP MainPGMLoop
JMP MainPGMLoop

Note*: To add two more NOPs to ensure proper wake up is preferred.

© Sunplus Technology Co., Ltd. 14 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Rating

Power Supply Voltage VCC = +2.4V to + 5.5V

Input Voltage VIN = - 0.3V to VCC+0.3V
Output Voltage VOUT = 0V to VCC
CPU clock From 200KHz to 6.0MHz
Operating Ambient Temperature TOPR = - 0°C to +70°C
Storage Temperature TSTR = -20°C to +125°C
Note: Stresses beyond those given in the Absolute Maximum Ratings table may cause operational errors or damage to the device. For normal operation
conditions see AC/DC Electrical Characteristics.

6.2. DC Characteristics (VCC = 5.0V, TA = 25°C)

Characteristic Condition Symbol Min. Typ. Max. Unit

Output high voltage
IOH = -8mA VOH 2.4 - - V
PA5 - 0*, PB0*
Output low voltage
IOL = 8mA VOL - - 0.4 V
PA7 - 0, PB0
Output low voltage
IOL = 25mA VOL - - 0.5 V
PB1
Input high voltage
VIH 3.5 - - V
PA5 - 0, PB1 - 0
Input low voltage
VIL - - 1.4 V
PA5 - 0, PB1 - 0
Positive Going input threshold voltage
PA6, PA7, IRQ/PB4, VIH - 2.0 - V
RESET/PB5
Negative-going input threshold voltage
PA6, PA7, IRQ/PB4, VIL - 0.8 - V
RESET/PB5
I/O port Hi-Z leakage
Pull-Down/up inactive IIZ - - 10 µA
PA5 - 0, PB1 - 0
Pull-down resistance
VIN = 5.0V RPUDWN - 100 - KΩ
PA5 - 0, PB0
Pull-up resistance Pull-up always
RPULLUP - 5.0 - KΩ
PA6, PA7 VIN = 0V
Pull-up resistance PB1 VIN = 0V RPULLUP - 100 - KΩ
Power consumption ICC - 2.0 - mA
Stand by current ISTB - 5.0 - µA
LVR trigger voltage VLVR - 2.2 - V

© Sunplus Technology Co., Ltd. 15 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

6.3. The Relationship btween the ROSC and the FOSC

6.3.1. VDD = 3.0V, TA = 25℃ 6.3.3. Frequency vs. temperature

Frequency normalized to 25℃

6.0
1.04
5.0
Rosc=82Kohms
FCPU ( MHz )

FCPU/FCPU(25℃)
4.0
1.02
3.0 VDD=4.5V

2.0
1.00
1.0 VDD=3.0V

0.0 0.98
0 200 400 600 800
Rosc ( Kohms ) 0.96
0 10 20 30 40 50 60 70
Temperature (℃)
6.3.2. VDD = 5.0V, TA = 25℃

6.0 6.3.4. Frequency vs. VDD

5.0
6.0
FCPU ( MHz )

4.0
5.0 Rosc = 27 Kohms
3.0
4.0
FCPU (MHz)

2.0
1.0 3.0
0.0
2.0
0 200 400 600 800 Rosc = 82 Kohms
1.0
Rosc ( Kohms )
0.0
2 3 4 5
V DD (Volts)

© Sunplus Technology Co., Ltd. 16 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SEP. 21, 2001
Version: 1.4
SPMC01A

P.S. :
PA == PORT A DATA ($0000)
0 = in / 1 = Out DPA == PORT A DIRECTION CONTROL ($0002)
RPA == PORT A PULL-UP / PULL-DOWN CONTROL ($0009)
DPA ($0002)
RST == CHIP INTERNAL RESET SIGNAL
DPB ($0003) Data Direction
Register Bit
0 is OPEN
PA WRITE 1 is SHORT
($0000)
PB WRITE Data I/O
($0001) OUTPUT
Register Bit Pin
0 is OPEN
-8mA Drive & 8mA sink

17
1 1 is SHORT Capability
PA READ
($0000)
PB READ
($0001) 0 100K
0 = enable / 1 = disable
RPA ($0009) 0 is SHORT
7.1. Appendix A: PA5 - 0 & PB0 I/O Diagram

RPB ($000A) Pull-(Up/Down)

1 is OPEN
Register Bit
RST
PA0 ~ PA3 only :
to IRQ interrupt system
Mask option
(software enable or P.S. :

© Sunplus Technology Co., Ltd.

always disable when as input) PB == PORT B DATA ($0001)
DPB == PORT B DIRECTION CONTROL ($0003)

Proprietary & Confidential

RPB == PORT B PULL-UP / PULL-DOWN CONTROL ($000A)
RST == CHIP INTERNAL RESET SIGNAL
7. APPENDIXS PA5 - 0 & PB0 I/O DIAGRAM
 SEP. 21, 2001
Version: 1.4
SPMC01A

0 = in / 1 = Out
DPA WRITE
($0002) Data Direction PWR
Register Bit
5K
0 is OPEN (always enable)
1 is SHORT
PA WRITE
($0000) Data OPEN-DRAIN I/O
Register Bit OUTPUT Pin
8mA Sink Capability
(Open - Drained type )

18
Slow enable
($0009 RPA bit7 = 1)
1 0 is OPEN
1 is SHORT
PA READ
($0000)
0 ( Vih = 2.0V , Vil = 0.8V )
RPA WRITE
7.2. Appendix B: PA6, PA7 I/O Diagram

($0009) Pull-Up
Register Bit PA7 only :
to IRQ interrupt system
RST P.S. :
PA == PORT A DATA ($0000)

© Sunplus Technology Co., Ltd.

DPA== PORT A DIRECTION CONTROL ($0002)
RPA == PORT A PULL-UP / PULL-DOWN CONTROL ($0009)

Proprietary & Confidential

PA7 - 6 I/O DIAGRAM RST == CHIP INTERNAL RESET SIGNAL
 SEP. 21, 2001
Version: 1.4
SPMC01A

PWR
0 = in / 1 = Out
DPB WRITE
Data Direction
($0003)
(DPB1, DPB2)
0 is SHORT
Register Bit 1 is OPEN
0 is OPEN 100K
PB WRITE 1 is SHORT
($0001) Data
(PB1, PB2) OPEN-DRAIN I/O
Register Bit OUTPUT Pin
25mA Sink Capability
(Open - drained type )
Slow enable
($0009 RPA bit7 = 1)

19
1 0 is OPEN
PB READ 1 is SHORT
($0001)
0
0 = enable / 1 = disable
RPB WRITE
($000A) Pull-Up
RST
Register Bit CPUCLK
7.3. Appendix C: PB1 I/O Diagram

Mask option
(software enable when as input PB1 slow change at raising
P.S. : & falling edge
or always disable)
PB == PORT B DATA ($0001)

© Sunplus Technology Co., Ltd.

no slow transtion slow transtion
DPB == PORT B DIRECTION CONTROL ($0003)
RPB == PORT B PULL-UP / PULL-DOWN CONTROL ($000A)

Proprietary & Confidential

RST == CHIP INTERNAL RESET SIGNAL
PB1 I/O DIAGRAM
 SEP. 21, 2001
Version: 1.4
SPMC01A

0 = in / 1 = Out
DPB WRITE PWR
($0003-b4) Data Direction
Register Bit
0 is SHORT
1 is OPEN
100K
0 is OPEN
PB WRITE 1 is SHORT
($0001-b4) Data RESET In
OUTPUT or
Register Bit I/O Pin
1 -8mA Drive &

20
0 is OPEN
PB READ 1 is SHORT 8mA sink Capability
($0001-b4)
0
0 = enable / 1 = disable
RPB WRITE
($000A-b4) Pull-Up
7.4. Appendix D: PB4 & Reset I/O Diagram

Register Bit
To MRESET
RST (RESET BLOCK DIAGRAM)
P.S. :

© Sunplus Technology Co., Ltd.

Mask Option
PB == PORT B DATA ($0001)
(RESET Input Function Enable or Disable)
DPB == PORT B DIRECTION CONTROL ($0003)

Proprietary & Confidential

RPB == PORT B PULL-UP / PULL-DOWN CONTROL ($000A)
RST == CHIP INTERNAL RESET SIGNAL RESET (PB4)
 SEP. 21, 2001
Version: 1.4
SPMC01A

Mask Option
(WDT Input Function Enable or Disable)
Clock
ADDress WatchDog Timer Reset
DATA (WDT)
ADDress Illegal Address
(ILADR)
VDD Power-On Reset

21
(POR)
RST
(to CPU & Peripherals)
VDD Low Voltage Reset
(LVR)
7.5. Appendix E: Reset Block Diagram

Mask Option
(LVR Function Enable or Disable)
MRESET

© Sunplus Technology Co., Ltd.

Proprietary & Confidential
RESET BLOCK DIAGRAM
 SEP. 21, 2001
Version: 1.4
SPMC01A

0 = in / 1 = Out
DPB WRITE
($0003-b5) Data Direction
Register Bit
0 is OPEN
1 is SHORT
PB WRITE
($0001-b5) Data IRQ In
OPEN-DRAIN
or
Register Bit OUTPUT
I/O Pin
8mA sink Capability
1 0 is OPEN (Open - drained type)

22
1 is SHORT
PB READ
($0001-b5)
0
RST
To MIRQ
(INTERRUPT SOURCE DIAGRAM)
7.6. Appendix F: PB5 & IRQ I/O Diagram

P.S. :
PB == PORT B DATA ($0001)
DPB == PORT B DIRECTION CONTROL ($0003)

© Sunplus Technology Co., Ltd.

RPB == PORT B PULL-UP / PULL-DOWN CONTROL ($000A)
RST == CHIP INTERNAL RESET SIGNAL

Proprietary & Confidential

IRQ (PB5)
 SEP. 21, 2001
Version: 1.4
SPMC01A

MIRQ
PWR
PA0
PA ($0000 - b0)
PA1
PA ($0000 - b1)
PA2 Q
PA ($0000 - b2) D
DFRI
PA3
PA ($0000 - b3)
0 is OPEN CK QN
( Mask Option ) 1 is SHORT RN
(PORT Ext. Int. )
RST D
(internal RESET signal) IRQR IRQF
IRQS ($0006 - b6) C IRQS ($0006 - b3)
IRQE1B B
(~IRQE1)
( IRQ Fetch Vector ) A QN
(Edge / Edge - Level)
( Mask Option) (IRQ Level)

23
0 is OPEN
IRQS ($0006 - b0)
IRQE 1 is SHORT
IRQE1 IRQEX
IRQS ($0006 - b1) (TO IRQ in CPU)
0 is OPEN
1 is SHORT
PWR IRQI (from Timer Block)
7.7. Appendix G: Interrupt Source Diagram

IRQF1
D Q IRQS ($0006 - b2)
DFRI
PA7 CK QN
PA ($0000 - b7) RN
(internal RESET signal) RST
IRQS ($0006 - b7) IRQR1

© Sunplus Technology Co., Ltd.

Proprietary & Confidential
INTERRUPT SOURCE DIAGRAM
 SEP. 21, 2001
Version: 1.4
SPMC01A

Mask Option
(fCPU divided dy 4 or No divided)
$0005 (TCR)
Timer Counter Rigister
fCPU
fTM1
TM1R7 TM1R6 TM1R5 TM1R4 TM1R3 TM1R2 TM1R1 TM1R0 fosc External
Internal
4 2 Timer Clock
fCPU
22
fCPU Timer Clock (Rosc / Crystal)
fTM1
28
Counter
fTM1 fTM1 fTM1 fTM1 fTM1 fTM1
214 213 212 211 210 29
1 = Clear
OverFlow Watch Dog
to Power On Reset (POR) Clear
Detect

24
Circuit RTI Select Circuit
Watch Dog
8
Timer
$0004 (TCS)
Timer Control & Status Rigister
to RESET BLOCK
TOF RTIF TOFE RTIE TOFR RTIFR RT1 RT0
7.8. Appendix H: Timer Block Diagram

PWR
0 is OPEN
1 is SHORT
IRQT

© Sunplus Technology Co., Ltd.

D Q
PWR DFF
0 is OPEN

Proprietary & Confidential

CK QN
D Q 1 is SHORT CLR
DFF IRQI
IRQV1 (to Interrupt Block)
CK QN
CLR
TIMER 1 BLOCK DIAGRAM
 SPMC01A

8. PACKAGE/PAD LOCATIONS
8.1. PAD Assignment

XO/R

VDD
PB1
XI
3 1 16 15

14 VSS
RESET/PB4 3 Y
13 IRQ/PB5
PA7 4
X
(0,0) 12 PA0
PA6 5
11 PA1

6 7 8 9 10
PA5

PA4

PB0

PA3

PA2

Chip Size: 1520µm x 1610µm

The IC substrate should be connected to VSS

Note1: Chip size included scribe line.

Note2: 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible.

8.2. Ordering Information

Product Number Package Type

SPMC01A-nnnnV-C Chip form

SPMC01A-nnnnV-P Package form - PDIP 16
Note1: Code number (nnnnV) is assigned for customer.
Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z).

© Sunplus Technology Co., Ltd. 25 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

8.3. PAD Locations

PAD No. PAD Name X Y

1 XO 51 609
2 XI -166 610
3 RESET / PB4 -574 191
4 PA7 -574 -26
5 PA6 -574 -375
6 PA5 -342 -610
7 PA4 -126 -610
8 PB0 91 -610
9 PA3 307 -610
10 PA2 523 -610
11 PA1 590 -288
12 PA0 590 -72
13 IRQ / PB5 590 186
14 VSS 590 365
15 VDD 539 609
16 PB1 283 610

8.4. Package Information

8.4.1. PDIP 16

E1

D1 A2 c

L1
D1 Body Length
E1 Body Width
e b A2 Body Thickness
L1 Lead Length
Body Size Lead Size b Lead Width
D1 E1 A2 L1 b c e c Lead Thickness
750 250 130 115 18 10 100 e Lead Pitch
All units are in mil. 1mil = 25.4µm PDIP-16-300

© Sunplus Technology Co., Ltd. 26 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

9. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or
regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and
prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this
publication are current before placing orders. Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are
specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits
illustrated in this document are for reference purposes only.

© Sunplus Technology Co., Ltd. 27 SEP. 21, 2001

Proprietary & Confidential Version: 1.4
 SPMC01A

10. REVISION HISTORY

Date Revision # Description Page

NOV. 04, 1997 0.1 Original

SEP. 17, 1997 0.2 1. Modify “BLOCK DIAGRAM”

2. Renew to a new document format

JAN. 09, 1998 0.3 1. Add Operation Voltage Range: 2.4V - 6.0V in “FEATURES” and “DC CHARACTERISTICS”
2. Chang font: “Arial"
3. Add "EMULATION BOARD" and "PIGGY BACK BOARD" User Guide

MAR. 02, 1998 1.0 Delete “PRELIMINARY”

JUN. 04, 1998 1.1 1. Add “FREQUENCY vs. VDD, TEMPERATURE”

2. Revise the pin naming in “BLOCK DIAGRAM”, ”PIN ASSIGMENT”, ”BONDING
DIAGRAM”, ”BONDING CORRDINATE”: OSC2 -> XO, OSC1 -> XI

DEC. 13, 1999 1.2 1. Add PIN No. in “PIN ASSIGNMENT”

2. Add “DISCLAIMER”
3. Renew to a new document format

NOV. 07, 2000 1.3 1. Wording improvement

2. To revise the CPU low bound clock range from 1KHz to 200KHz
3. To correct the I/O block diagrams on Appendix C: PB1 I/O Diagram, Appendix F: PB5 & IRQ
I/O Diagram, and Appendix G: Interrupt Source Diagram
4. To remove Appendix D: I-V Curve of PB1, and Appendix L: Piggyback Board
5. Add “Note: The 0.1µF capacitor between VDD and VSS…” 23
6. Add “REVISION HISTORY” 26
7. Renew to a new document format

SEP. 21, 2001 1.4 1. Modify storage temperature = -20℃ to 125℃ 16

2. Correct Timer 1 Block Diagram in the “7.8 Appendix H: Timer Block Diagram “ 24
3. Add “8.2 Ordering Information” 25
4. Correct chip size 25
5. Add “8.4 Package Information” 26
6. Add Note1 in the “8.1 PAD Assignment”
7. Renew to a new document format

© Sunplus Technology Co., Ltd. 28 SEP. 21, 2001

Proprietary & Confidential Version: 1.4