Digital System Design
CPE – 344
Lab 3
Name Rohaid Ahmed Mirza
Registration Number FA19-BCE-006
Class BCE – 7A
Instructor’s Name Sir Bilal Qasim
Pre lab:
Main Code:
module ripple16bit(
output [15:0] s,
output c,
input [15:0] a,
input [15:0] b,
input cin
);
wire c1,c2,c3;
ripplecarry r1(s[3:0],c1,a[3:0],b[3:0],cin);
ripplecarry r2(s[7:4],c2,a[7:4],b[7:4],c1);
ripplecarry r3(s[11:8],c3,a[11:8],b[11:8],c2);
ripplecarry r4(s[15:12],c,a[15:12],b[15:12],c3);
endmodule
module ripplecarry(sum,cout,a,b,cin);
output [3:0] sum;
output cout;
input [3:0] a,b;
input cin;
wire c1,c2,c3;
fulladder FA0(sum[0],c1,a[0],b[0],cin);
fulladder FA1(sum[1],c2,a[1],b[1],c1);
fulladder FA2(sum[2],c3,a[2],b[2],c2);
fulladder FA3(sum[3],cout,a[3],b[3],c3);
endmodule
module fulladder(sum,cout,a,b,cin);
output sum,cout;
input a,b,cin;
wire y0,y1,y2;
xor (y0,a,b);
xor (sum,y0,cin);
and (y2,a,b);
and (y1,y0,cin);
or (cout,y1,y2);
endmodule
Testbench:
module test16;
// Inputs
reg [15:0] a;
reg [15:0] b;
reg cin;
// Outputs
wire [15:0] s;
wire c;
// Instantiate the Unit Under Test (UUT)
ripple16bit uut (
.s(s),
.c(c),
.a(a),
.b(b),
.cin(cin)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
#50;
a = 8; b = 7;
#50; $finish;
end
endmodule
In lab 1:
Main Code:
module CLA_4bit(
output [3:0] s,
output cout,
input [3:0] a,
input [3:0] b,
input cin
);
wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4;
assign p0=(a[0]^b[0]),
p1=(a[1]^b[1]),
p2=(a[2]^b[2]),
p3=(a[3]^b[3]);
assign g0=(a[0]&b[0]),
g1=(a[1]&b[1]),
g2=(a[2]&b[2]),
g3=(a[3]&b[3]);
assign c0=cin;
assign c1 = g0 | (p0&c0);
assign c2 = g1 | (p1&c1);
assign c3 = g2 | (p2&c2);
assign c4 = g3 | (p3&c3);
assign s[0]=p0^c0,
s[1]=p1^c1,
s[2]=p2^c2,
s[3]=p3^c3;
assign cout=c4;
endmodule
Testbench:
module test4bit;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire [3:0] s;
wire cout;
// Instantiate the Unit Under Test (UUT)
CLA_4bit uut (
.s(s),
.cout(cout),
.a(a),
.b(b),
.cin(cin)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#50;
a = 8; b = 7;
#50; $finish;
// Add stimulus here
end
endmodule
Post lab:
Main Code:
module cla16bit(
output [15:0] s,
output c,
input [15:0] a,b,
input cin
);
wire c1,c2,c3;
CLA_4bit cla1(s[3:0],c1,a[3:0],b[3:0],cin);
CLA_4bit cla2(s[7:4],c2,a[7:4],b[7:4],c1);
CLA_4bit cla3(s[11:8],c3,a[11:8],b[11:8],c2);
CLA_4bit cla4(s[15:12],c,a[15:12],b[15:12],c3);
endmodule
module CLA_4bit(
output [3:0] s,
output cout,
input [3:0] a,
input [3:0] b,
input cin
);
wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4;
assign p0=(a[0]^b[0]),
p1=(a[1]^b[1]),
p2=(a[2]^b[2]),
p3=(a[3]^b[3]);
assign g0=(a[0]&b[0]),
g1=(a[1]&b[1]),
g2=(a[2]&b[2]),
g3=(a[3]&b[3]);
assign c0=cin;
assign c1 = g0 | (p0&c0);
assign c2 = g1 | (p1&c1);
assign c3 = g2 | (p2&c2);
assign c4 = g3 | (p3&c3);
assign s[0]=p0^c0,
s[1]=p1^c1,
s[2]=p2^c2,
s[3]=p3^c3;
assign cout=c4;
endmodule
Testbench:
module test;
// Inputs
reg [15:0] a;
reg [15:0] b;
reg cin;
// Outputs
wire [15:0] s;
wire c;
// Instantiate the Unit Under Test (UUT)
cla16bit uut (
.s(s),
.c(c),
.a(a),
.b(b),
.cin(cin)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 10; b = 20;
#100;
a = 4900; b = 702;
#100; $finish;
// Add stimulus here
end
endmodule
Conclusion:
In this lab, we implemented 4-bit carry look ahead adder. We also designed 16-bit CLA from
4 4-bit CLAs Verilog programming. We verified our modules with simulations.
