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Static Timing Analysis

Static timing analysis checks the timing of a circuit without input vectors by analyzing the timing paths between registers. It is faster than dynamic timing analysis and checks all paths. Static timing analysis verifies that a circuit meets timing requirements like setup and hold times given a clock period. It takes as inputs the design, timing library, constraints, and parasitic data and outputs timing reports. Timing paths have a startpoint, combinational logic, and endpoint, and static timing analysis checks that data arrival times meet required times defined by constraints.

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Tarikul Islam
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489 views3 pages

Static Timing Analysis

Static timing analysis checks the timing of a circuit without input vectors by analyzing the timing paths between registers. It is faster than dynamic timing analysis and checks all paths. Static timing analysis verifies that a circuit meets timing requirements like setup and hold times given a clock period. It takes as inputs the design, timing library, constraints, and parasitic data and outputs timing reports. Timing paths have a startpoint, combinational logic, and endpoint, and static timing analysis checks that data arrival times meet required times defined by constraints.

Uploaded by

Tarikul Islam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Static Timing Analysis

 There are two types of timing analysis:


o Static Timing Analysis: Checks static delay requirements of the circuit without
any input/output vectors. Doesn’t check for logical correctness of the design
o Dynamic Timing Analysis: Verify functionality of the design by applying input
vectors and checking for the correct output vectors

 Difference between Static and Dynamic timing analysis:


o Compared to dynamic simulation, static timing analysis is much faster because it
is not necessary to simulate the logical operation of the circuit. STA is also more
thorough because it checks all timing paths

 Purpose of Static timing analysis:


o STA analyzes the timing of a circuit to verify the circuit works at the specified
frequency
 Inputs of STA
o Design Data (DB / Def file/Netlist)
o Timing Lib
o Timing Constraints (SDC)
o Parasitic Reports/Files
 Outputs of STA
o Timing Reports
 Timing Paths
o Each timing path consists of the following elements:
 Startpoint: The start of a timing path where data is launched by a clock
edge or where the data must be available at a specific time. Every
startpoint must be either an input port or a register clock pin.
 Combinational logic network: Elements that have no memory or internal
state. Combinational logic can contain AND, OR, XOR, and inverter
elements, but cannot contain flip-flops, latches, registers, or RAM.
 Endpoint: The end of a timing path where data is captured by a clock
edge or where the data must be available at a specific time. Every
endpoint must be either a register data input pin or an output port
 Types of Timing paths:

 Setup Time: Setup time is the amount of time required for the input to a Flip-Flop to be
stable before a clock edge.
o To meet setup time constraint, Required Time ⋝ Arrival Time
 Required Time = Clock Period - Setup Time (of the capturing flip-flop)
 Arrival Time = CK→Q Delay (of Launching flip-flop) + Comb. Delay
 Clock Period - Setup Time ⋝ CK→Q Delay (of Launching flip-flop) + Comb.
Delay
 Setup Time ≤ Clock Period - CK→Q Delay - Comb. Delay

 Hold Time: Hold time is the minimum time duration that the input data required to be stable
AFTER the active clock edge so that the input data can be reliably saved into the flip-flop.
o To meet hold time constraints, Arrival Time ⋝ Required Time
 Required Time = Hold Time 
Arrival Time = CK→Q Delay (of Launching flip-flop) + Comb. Delay
CK→ Q Delay (of Launching flip-flop) + Comb. Delay ⋝ Hold Time
Hold Time ≤ CK→Q Delay + Comb. Delay
 Important Notes:
o Maximun Clock Frequency Calculation
o Methods to fix Setup and Hold Violations
o False path: A path that is never sensitized due to the logic configuration, expected
data sequence, or operating mode.
o Multicycle path: A path designed to take more than one clock cycle from launch to
capture.
o Half-cycle path: A half cycle timing path is one in which launch and capture happen
on different clock edges. A half cycle path can be in terms of both setup and hold.

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