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Static CMOS
● Pull-Up Network (PUN) and Pull-Down
Network (PDN)
o PUN and PDN are complementary
o PUN: PMOS devices only
COMPLEX STATIC CMOS o PDN: NMOS devices only
GATES ● PUN and PDN are dual networks
o Dual networks: parallel connection in one =
series connection in the other, vice versa
● Only one network is on at a time
● If CMOS gate implements logic function F:
o PUN implements function F
o PDN implements function G=F’
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Example Example 1
Find out the minimum transistor implementation of the following function
NAND Gate NOR Gate
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Example 2 Analysis of CMOS Gates
Find out the minimum transistor implementation of the following function ● Transistors in parallel → resistances
in parallel
o Effective resistance = R/2
o Effective width = 2W
● Transistors in series → resistances
in series
o Effective resistance=2R
o Effective length = 2L (equivalent to
W/2)
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Example: Transistor Sizing Start from longest path
• Smaller widths.
• Larger output cap.
● Draw circuit, size transistors for equal rise/fall times. Assume 2:1
mobility ratio and equal threshold.
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Equivalent Inverter Static Properties of Complementary CMOS Gates
● CMOS gates: many paths to Vdd and Gnd ● Full rail-to-rail swing with VOH = VDD and VOL = GND
o Multiple values for VM, VIL, VIH, etc
● Symmetrical VTC
o Different delays for each input combination
● Equivalent inverter ● Propagation delay function of load capacitance and resistance of
transistors
o Represent each gate as an inverter with appropriate device width
o Include only transistors which are on or switching ● No static power dissipation, since the circuits are designed such that
o Calculate VM, delays, etc using inverter equations the pull-down and pullup networks are mutually exclusive
● Direct path (short circuit) current during switching
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Propagation Delay of Complementary CMOS
Gates
● Three possible input combinations switch the ● For a 2 input NAND gate,
output of the gate from high-to-low: o If both inputs are driven low, the two PMOS devices are on. The delay in this case
o (a) A = B = 0 ->1, is 0.69(Rp /2) CL , since the two resistors are in parallel.
o When only one PMOS device turns on, delay is given by 0.69(Rp )CL – Worst case
o (b) A = 0 -> 1, B = 1
o For the pull-down path, the output is discharged only if both A and B are switched
o (c) A = 1, B = 0 -> 1, high, and the delay is given by 0.69(2RN ) CL to a first order.
● Adding devices in series slows down the circuit, and devices must be made
wider to avoid a performance penalty.
● When sizing the transistors in a gate with multiple fan-in’s, we should pick the
combination of inputs that triggers the worst-case conditions.
● For example, for a NAND gate to have the same pull-down delay (tphl ) as a
minimum-sized inverter, the NMOS devices in the NAND stack must be made
twice as wide so that the equivalent resistance the NAND pull-down is the
same as the inverter. The PMOS devices can remain unchanged.
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● The delay dependence on input patterns ● The delay dependence on input patterns
Similiarly, worst case tphL occurs for A = B = 0 -> 1
best case tphL occurs for A= 0 -> 1, B = 1
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NOR Gate Propagation delay of complex gates
● In more complex logic gates that have large fan-in, the internal node
capacitances can become significant
● In the case of a NOR gate,
o The NMOS devices (M1 and M2 ) can have the same device widths as
the NMOS device in the inverter.
o The PMOS devices must be made two times larger compared to the
PMOS in the inverter.
● Since PMOS devices have a lower mobility relative to NMOS devices,
stacking devices in series must be avoided as much as possible. A
NAND implementation is preferred over a NOR implementation for tpHL = 0.69(R1C1 + (R1 + R2) C2 + (R1 + R2+ R3) C3 + (R1 + R2+ R3 + R4) CL)
implementing generic logic. M1 appears in all the terms, which makes this device important when
attempting to minimize delay.
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Reduction of delays for Large Fan-in Reduction of delays for Large Fan-in (Cont..)
● Transistor sizing
o Increasing size decreases the second-order factor in the tp expression. ● Logic Restructuring
o However, if load is dominated by intrinsic capacitance (self-loading), o Partitioning large fan-in gates into small fan-in gates
propagation delay is not improved.
● increasing the transistor size, results in larger parasitic capacitors, which affect
the propagation delay of the gate and also present a larger load to the
preceding gate.
● Progressive transistor sizing
o The important resistance is reduced while reducing capacitance.
M1 > M2 > M3 > …. > MN
Distributed RC-line
Can Reduce Delay by more than 30%!
It is not simple in a real layout
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Optimizing performance in
● Buffering: Isolate Fan-in from Fan-out Combinational Networks - Logical Effort
● Systematic method for optimizing CMOS circuits for speed
o Balances gate delays and logic depth
o Enables systematic method of finding minimum sizes to achieve delay
specification
o Keeps high fan-in resistance isolated from large capacitive load CL o Implicitly assumes switch RC model for propagation delay.
● Use another circuit style - To reduce the number of transistors ● Ability of a logic gate to deliver output current compared to an inverter
o Ratioed with same PU and PD resistances.
o Pass-transistor logic etc…
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8-input AND Review: Inverter Delay Model
● Inverter Delay Expression:
with tp0 represents the intrinsic delay of an inverter, and f the ratio between the
external load and the input capacitance of the gate. f is often called the electrical
effort .
Which implementation is best?
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Logical Effort
Logical Effort (Cont..)
● For the complex gates, the basic delay equation of the inverter can be
modified as
● The factor g is called the logical effort,
o For a given load, complex gates have to work harder than an inverter to
produce a similar response.
● p represents the ratio of the intrinsic (or unloaded) delays of the o The logical effort of a logic gate tells how much worse it is at producing
complex gate and the simple inverter. output current than an inverter, given that each of its inputs may contain
o The more involved structure of the multiple-input gate, combined with its only the same input capacitance as the inverter.
series devices, increases its intrinsic delay. ● Reduced output current means slower operation, and thus the logical effort
o p is a function of gate topology as well as layout style. number for a logic gate tells how much more slowly it will drive a load than
would an inverter.
Gate p o Logical effort is how much more input capacitance a gate presents to
Inverter 1 Estimates of intrinsic delay factors of various deliver the same output current as an inverter.
logic types, and a fixed PMOS/NMOS ratio
o Logical effort is a useful parameter, because it depends only on circuit
NAND n
topology
NOR n
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Logical Effort (Cont..) General Signal Path with N Stages
● The total delay of a path through a combinational logic block can be
expressed as
● To determine the minimum delay of the path, N – 1 partial derivatives
are found out and set them to zero,
f1 g 1 = f2 g 2 = … = fN g N
i.e.., each stage should bear the same ‘gate effort’:
● The path effective fanout/electrical effort, F = CL /Cg1
● Path logical effort: G = g1g2…gN
Logic efforts of common logic gates, assuming a PMOS/NMOS ratio of 2.
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● Branching effort, ● The path electrical effort can be written as
● The total path effort
● Con-path is the load capacitance of the gate along the path we are
analyzing and Coff-path is the capacitance of the connections that lead
off the path.
● The gate effort that minimizes the path delay is found to equal
● The path Branching effort,
B = b1b2b3……bN ● The minimum delay through the path is
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8-input AND
● Case a: 2*(3.33F)1/2 + 9pinv
● Case b: 2*(3.33F)1/2 + 6pinv
● Case c: 4*(2.96F)1/4 + 7pinv
o pinv – Parasitic delay of the inverter
o Case b is always better than Case a
o When F = 1, Case b will be the best
o For higher values of F, Case c will be the best
Which implementation is best?
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Example
Consider the network given below. The output of the network is loaded
with a capacitance which is 5 times larger than the input capacitance of
the first gate, which is a minimum-sized inverter.
Effective fanout, F = 5
First find out the input capacitances of each stage
5 𝑐
∗ 1 = 1.93 ⇒ 𝑐 = 2.6 ∗ 5/3 = 1.93 ⇒ 𝑏 = 2.24
𝑐 𝑏
𝑏
∗ 5/3 = 1.93 ⇒ 𝑎 = 1.93
𝑎
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● Select gate sizes x and y for least delay from A to B ● Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27
● Electrical Effort F = 45/8
● Branching Effort B = 3 * 2 = 6
● Path Effort H = GBF = 125
● Best Stage Effort = H1/3 = 5
● Parasitic Delay P = 2 + 3 + 2 = 7
● Delay D = 3*5 + 7 = 22
● y = 45 * (5/3) / 5 = 15
● x = (15*2) * (5/3) / 5 = 10
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● For the circuit given below ● G = 5/3 * 1 * 1 * 5/3 * 2,
o What is the path effort from In to Out?
● F = 200/5 = 40,
o What electrical effort/stage minimizes the delay of this chain of gates?
o Size the gates to minimize the delay from In to Out ● B=2*1*1*2*1=4
● ● H = 8000/9 => h = (8000/9)1/5 = 3.89
● (200/d) * 2 = 3.89 => d = 102.83
● (d/c) * (5/3) = 3.89 => c = 44.1
● (2c/b) * (1) = 3.89 => b = 22.69
● (b/a) * (1) = 3.89 => a = 5.84
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Power Consumption in CMOS Logic Gates
● The power dissipation is a strong function of ● The transition activity is a strong function of the logic function being
o Transistor sizing (which affects physical capacitance), implemented.
o Input and output rise/fall times (which affects the short-circuit power) α0->1 = p0 (1 - p0)
o Device thresholds and temperature (which affect leakage power) ● Assuming that the inputs are independent and uniformly distributed,
o Switching activity any N -input static gate has a transition probability
● The dynamic power dissipation is given
Pd = CLVDD2α0->1f
● Making a gate more complex mostly affects the switching activity α0->1, ● N0 is the number of zero entries and N1 is the number of one entries
which has two components: in the output column of the truth table of the function
o a static component that is only a function of the topology of the logic
network, and
o a dynamic one that results from the timing behavior of the circuit—the
latter factor is also called glitching.
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Design Techniques to Reduce Switching Activity
(Cont..)
● Using a uniform input distribution to compute activity is not a good Logic Restructuring
one, since the propagation through logic gates can significantly modify
the signal statistics.
● The switching activity of a logic gate is a strong function of the input
signal statistics.
● For a 2-input static NOR gate, and let pa and pb be the probabilities
that the inputs A and B are one . Also assume that the inputs are not
correlated. The probability that the output node equals one is given by
● Therefore, the probability of a transition from 0 to 1 is
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Design Techniques to Reduce Switching Activity Design Techniques to Reduce Switching Activity
(Cont..) (Cont..)
● The chain implementation will have an overall lower switching activity
than the tree implementation for random inputs.
● However, the timing behavior and glitching also need to be
considered.
o In this example the tree topology will have lower (no) glitching activity
since the signal paths are balanced to all the gates
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Design Techniques to Reduce Switching Activity
(Cont..)
CMOS disadvantages
● Input ordering ● For N-input CMOS gate, 2N transistors required
o Each input connects to an NMOS and PMOS transistor
o Large input capacitance: limits fan-out
o Large fan-in gates: always have long transistor stack
● in PUN or PDN
o Limits pull-up or pull-down delay
o Requires very large transistors
● Since both circuits implement identical logic functionality, it is clear that the
activity at the output node Z is equal in both cases.
● The difference is in the activity at the intermediate node. In the first circuit, this
activity equals (1 - 0.5 x 0.2) (0.5 x 0.2) = 0.09.
● In the second case, the probability that a 0 -> 1 transition occurs equals (1 –
0.2x0.1) (0.2 x 0.1)= 0.0196. This is substantially lower.
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