L5

Module 3:

CMOS Circuit characterization and

Performance Estimation
 Outline of Module

DC transfer Characteristics of CMOS inverter

Circuit characterization and performance estimation:
Delay estimation, Logical effort and Transistor Sizing
Power Dissipation:
Static & Dynamic Power Dissipation

Acknowledgement:
Most of the slides taken from
CMOS VLSI Design by N. Weste (Lec.5, 6, 7)
Digital Integrated Circuits by Rabaey
CMOS inverter: DC transfer Characteristics,
Logic Levels and Noise Margin
 DC Response

DC Response: Vout vs. Vin for a gate

Ex: Inverter
When Vin = 0 -> Vout = VDD
When Vin = VDD -> Vout = 0
In between, Vout depends on VDD
transistor size and current Idsp
By KCL, must settle such that Vin Vout
Idsn = |Idsp| Idsn
We could solve equations
But graphical solution gives more insight
 Operating Regions
Revisit transistor operating regions

VDD Vin0 Vin5

A B

Vout Vin1 Vin4

C
Vin2 Vin3
Vin3 Vin2
D Vin4 Vin1
E
0 Vtn VDD/2 VDD+Vtp VDD
VDD Vout
Vin
DC Transfer Curve
 Beta Ratio

If p/n  1, switching point will move from VDD/2

Called skewed gate
VDD
p
10
n
Vout 2
1
0.5
p
0.1
n

0
VDD
Vin

If r > 1, the inverter is HI-skewed.

If r < 1, the inverter is LO-skewed.

If r = 1, the inverter has normal skew or is unskewed.

 Noise Margins

Noise Margin allows to determine the allowable noise voltage

on the input of a gate so that the output will not be corrupted.

Vout

Unity Gain Points

VDD
Output Characteristics Input Characteristics Slope = -1
VDD VOH
Logical High
Output Range VOH Logical High
 p/ n > 1
Input Range
NMH
VIH Vin Vout
Indeterminate
VIL Region
NML
Logical Low VOL
Logical Low VOL Input Range Vin
0
Output Range Vtn VIL VIH VDD- VDD
|Vtp|
GND
L6

Transient Response & Delay Estimation

 Transient Response

DC analysis tells us Vout if Vin is constant

Transient analysis tells us Vout(t) if Vin(t) changes

Requires solving differential equations

Input is usually considered to be a step or ramp

From 0 to VDD or vice versa

 Inverter Step Response
Ex: find step response of inverter driving load cap

Vin (t )  u(t  t0 )VDD

Vin(t)
Vout (t  t0 )  VDD Vout(t)
Cload
dVout (t ) I dsn (t )
 Idsn(t)
dt Cload
Vin(t)

Vout(t)
t
t0
 Delay Definitions

tpdr: rising propagation delay

From input to rising output crossing
VDD/2
tpdf: falling propagation delay
From input to falling output crossing
VDD/2
tpd: average propagation delay
tpd = (tpdr + tpdf)/2
tr: rise time
From output crossing 0.2 VDD to 0.8
VDD
tf: fall time
From output crossing 0.8 VDD to 0.2
VDD
 Simulated Inverter Delay

Solving differential equations by hand is too hard

SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write, may hide insight

2.0

1.5

1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5

0.0

0.0 200p 400p 600p 800p 1n

t(s)
 Delay Estimation

Need to easily estimate delay

Not as accurate as simulation
But easier to ask “What if?”

The step response usually looks like a 1st order RC response with a
decaying exponential.
Use RC delay models to estimate delay
C = total capacitance on output node
Use effective resistance R
So that tpd = RC

Characterize transistors by finding their effective R

Depends on average current as gate switches
 Effective Resistance

Shockley models have limited value

Not accurate enough for modern transistors
Too complicated for much hand analysis

Simplification: treat transistor as resistor

Replace Ids(Vds, Vgs) with effective resistance R
Ids = Vds/R
R averaged across switching of digital gate

Too inaccurate to predict current at any given time

But good enough to predict RC delay
 RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
 RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/m of gate width in 0.6 m
Gradually decline to 1 fF/m in 65 nm
Resistance
R  10 K•m in 0.6 m process
Improves with shorter channel lengths
1.25 K•m in 65 nm process
Unit transistors
May refer to minimum contacted device (4/2 )
Or maybe 1 m wide device
Doesn’t matter as long as you are consistent
 Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter

d = 6RC
 Layout Dependence of Capacitance

In a good layout, diffusion nodes are

shared wherever possible to reduce
the diffusion capacitance.

Moreover, the uncontacted diffusion

nodes between series transistors
are usually smaller than those that
must be contacted.

Such uncontacted nodes have less

capacitance, although we will
neglect the difference for hand
calculations.
 Example: 3-input NAND

Sketch a 3-input NAND with transistor widths chosen to achieve effective

rise and fall resistances equal to a unit inverter (R).
Example: 3-input
NAND
 3-input NAND Caps

Annotate the 3-input NAND gate with gate and diffusion capacitance.
 Transient Response & Delay Calculation

The effective resistance R is an

empirical parameter anyway, so it is
preferable to incorporate the factor of
ln2 to define a new effective resistance
R’ = R ln2. Now the propagation delay
is simply R’C.
 Transient Response & Delay Calculation

It can be further approximated as a first-order system with a single time constant:

For example, if R1 = R2 = R and C1 = C2 = C, then Y1 = 2.6 RC, Y2 = 0.4 RC, Y = 3 RC

L7

Elmore Delay
ON transistors look like resistors
Pull-up or pull-down network modeled as RC ladder
Elmore delay of RC ladder

R1 R2 R3 RN

C1 C2 C3 CN

tpd = R1C1 + (R1 + R2)C2

At node n1, the capacitance is C1 and the resistance to the source is R1 . At node Vout , the
capacitance is C2 and the resistance to the source is (R1 + R2).
 Example: 3-input NAND
Estimate worst-case rising and falling delay of 3-input NAND driving h
identical gates.

t pdr   9  5h  RC

tpdf = (3C)(R/3) + (3C)(R/3 + R/3) + ((9 + 5h)C)(R/3+ R/3 + R/3) = (12 + 5h)RC
 Delay Components
Delay has two parts
Parasitic delay
• 9 or 12 RC
• Independent of load
Effort delay
• 5h RC
• Proportional to load capacitance

Delay has two components: d = f + p

L8

Logical Effort
 Linear Delay
Chip designers face a bewildering array of choices
What is the best circuit topology for a function?
How many stages of logic give least delay?
How wide should the transistors be?

Logical effort is a method to make these decisions

Uses a simple model of delay
Helps make rapid comparisons between alternatives

Delay has two components: d = f + p

 Delay in a Logic Gate
d
Express delays in process-independent unit d  abs
Delay has two components: d = f + p 
f: effort delay = gh (a.k.a. stage effort) 3RC
 3 ps in 65 nm process
Again has two components 60 ps in 0.6 m process
g: logical effort (ratio of input capacitance of the gate to the input
capacitance of inverter)
Measures relative ability of gate to deliver current
g  1 for inverter
h: electrical effort = Cout / Cin
Ratio of output to input capacitance
Sometimes called fanout
p: parasitic delay
Represents delay of gate driving no load
Set by internal parasitic capacitance
 Computing Logical Effort
DEF: Logical effort is the ratio of the input capacitance of a
gate to the input capacitance of an inverter delivering the
same output current.
Measure from delay vs. fanout plots
Or estimate by counting transistor widths

2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1

Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3
Computing Logical Effort
Logical Effort
 Delay Plots

d =f+p
= gh + p

What about
NOR2?
 Parasitic Delay

Parasitic delay is the delay of the gate when it

drives zero load 3RC

In multiples of pinv (1)

 Example: Ring Oscillator

Estimate the frequency of an N-stage ring oscillator

31 stage ring oscillator in 0.6

Logical Effort: g = 1 m process has frequency
Electrical Effort: h = 1 of ~ 200 MHz
Parasitic Delay: p = 1
Stage Delay: d = 2
Frequency:fosc = 1/(2*N*d) = 1/4N
 Example: FO4 Inverter
Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort: g = 1
Electrical Effort: h = 4 The FO4 delay is about
Parasitic Delay: p = 1 300 ps in 0.6 m process
15 ps in a 65 nm process
Stage Delay: d = 5
 Multistage Logic Networks

The path logical effort G can be expressed as the products of the logical efforts of
each
stage along the path.

The path electrical effort H can be given as the ratio of the output capacitance the
path
must drive divided by the input capacitance presented by the path.

The path effort F is the product of the stage efforts of each

stage.
Can we write F = GH?
 Paths that Branch

No! Consider paths that branch:

15
G =1 90
H = 90 / 5 = 18 5
GH = 18
15
h1 = (15 +15) / 5 = 6 90
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH
 Branching Effort
Introduce branching effort
Accounts for branching between stages in path

Con path  Coff path

b
Con path

Now we compute the path effort

F = GBH
 Multistage Delays

Path Effort Delay

Path Parasitic Delay

Path Delay
 Path Delays

The product of the stage efforts is F, independent of gate sizes.

The path delay D is the sumof the delays of each stage.

The path effort delay is the sum of the stage efforts. The sum
of a set of numbers whose product is constant is minimized by
choosing all the numbers to be equal.

In other words, the path delay is minimized when each stage bears the same effort. If a path
has N stages and each bears the same effort, that effort must be
 Designing Fast Circuits
If a path has N stages and each bears the same effort, that effort must be

the minimum possible delay of an N-stage path with path effort F and path parasitic
delay P is

Starting with the load at the end of the path, work backward applying the
capacitance
transformation to determine the size of each stage.
 Example: 3-stage path
Select gate sizes x and y for least delay from A to B
Logical Effort: G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort: H = 45/8

x
Branching Effort: B = 3 * 2 = 6
y
x
45
Path Effort: F = GBH = 125
A 8
x
y B
Best Stage Effort fˆ  3 F  5 45

Parasitic Delay P = 2 + 3 + 2 = 7
Delay D = 3*5 + 7 = 22
 Example: 3-stage path
Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3
 Best Number of Stages

How many stages should a path use?

Minimizing number of stages is not always fastest
Example: drive 64-bit datapath with unit inverter

D = NF1/N + P
= N(64)1/N + N
 Method of Logical Effort

1) Compute path effort F  GBH

2) Estimate best number of stages N  log 4 F
3) Sketch path with N stages
4) Estimate least delay D  NF  P
1
N

5) Determine best stage effort

ˆf  F N1

1) Find gate sizes gi Couti

Cini 
fˆ
 Limits of Logical Effort

Need path to compute G

But don’t know number of stages without G

Simplistic delay model

Neglects input rise time effects

Interconnect
Iteration required in designs with wire

Maximum speed only

Not minimum area/power for constrained delay
Power Dissipation
 Average Power
Instantanoeous Power

Energy Consumed or supplied over time interval T

Average Power over time interval T

Power is expressed in units of Watts (W) and Energy in Joules.

(1W = 1 J/s)
 Examples

When the capacitor is charged from 0 to VC, it stores energy EC

 CMOS Inverter
Energy stored in capacitor when input switches from 1 to 0

Only half of the energy from the power supply is stored in the capacitor.

The other half is dissipated (converted to heat) in the pMOS transistor because the
transistor
has a voltage across it at the same time a current flows through it.

The power dissipated depends only on the load capacitance, not on the size of the
transistor or the speed at which the gate switches.

When the input switches from 0 back to 1, the energy stored in the capacitor is dissipated in
the nMOS transistor. No energy is drawn from the power supply during this transition.
 Switching Power

When Vin rises, the pMOS starts to turn OFF. However,

there is a small blip of current while the partially ON pMOS
fights against the nMOS. This is called short-circuit
current.

The gate switches at some average frequency fsw . Over some interval T, the load will be
charged and discharged Tfsw times.

This is called the dynamic power because it arises from the switching of the load.
Because most gates do not switch every clock cycle, it is often more convenient to
express switching frequency fsw as an activity factor times the clock frequency f.
 Sources of Power Dissipation
Power dissipation in CMOS circuits comes from two components: