Lecture:
Circuits &
Layout
Outline
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
1: Circuits & Layout CMOS VLSI Design 4th Ed. 2
CMOS Gate Design
Activity:
– Sketch a 4-input CMOS NOR gate
A
B
C
D
Y
1: Circuits & Layout CMOS VLSI Design 4th Ed. 3
CMOS Circuit Styles
Static complementary CMOS - except during switching,
output connected to either VDD or GND via a low-
resistance path
high noise margins
- full rail to rail swing
- VOH and VOL are at VDD and GND, respectively
low output impedance, high input impedance
no steady state path between VDD and GND (no static power
consumption)
delay a function of load capacitance and transistor resistance
comparable rise and fall times (under the appropriate transistor
sizing conditions)
Dynamic CMOS - relies on temporary storage of signal
values on the capacitance of high-impedance circuit
nodes
simpler, faster gates
increased sensitivity to noise
CSE477 L06 Static CMOS Logic.4 Irwin&Vijay, PSU, 2003
Complementary CMOS
Complementary CMOS logic gates
– nMOS pull-down network pMOS
– pMOS pull-up network pull-up
network
inputs
– a.k.a. static CMOS output
nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
1: Circuits & Layout CMOS VLSI Design 4th Ed. 5
Static Complementary CMOS
Pull-up network (PUN) and pull-down network (PDN)
VDD
PMOS transistors only
In1
pull-up: make a connection from VDD to F
In2 PUN
when F(In1,In2,…InN) = 1
InN
F(In1,In2,…InN)
In1
pull-down: make a connection from F to
In2 PDN
GND when F(In1,In2,…InN) = 0
InN
NMOS transistors only
PUN and PDN are dual logic networks
CSE477 L06 Static CMOS Logic.6 Irwin&Vijay, PSU, 2003
Threshold Drops
VDD VDD
PUN
VDD
0 0
CL CL
PDN VDD VDD
CL CL
VDD
CSE477 L06 Static CMOS Logic.7 Irwin&Vijay, PSU, 2003
Threshold Drops
VDD VDD
PUN
S D
VDD
D 0 VDD S 0 VDD - VTn
VGS
CL CL
PDN VDD 0 VDD |VTp|
VGS
D CL S CL
VDD
S D
CSE477 L06 Static CMOS Logic.8 Irwin&Vijay, PSU, 2003
Construction of PDN
NMOS devices in series implement a NAND function
A•B
A
NMOS devices in parallel implement a NOR function
A+B
A B
CSE477 L06 Static CMOS Logic.9 Irwin&Vijay, PSU, 2003
Dual PUN and PDN
PUN and PDN are dual networks
DeMorgan’s theorems
A+B=A•B [!(A + B) = !A • !B or !(A | B) = !A & !B]
A•B =A+B [!(A • B) = !A + !B or !(A & B) = !A | !B]
a parallel connection of transistors in the PUN corresponds to a
series connection of the PDN
Complementary gate is naturally inverting (NAND,
NOR, AOI, OAI)
Number of transistors for an N-input logic gate is 2N
CSE477 L06 Static CMOS Logic.10 Irwin&Vijay, PSU, 2003
Series and Parallel
nMOS: 1 = ON a a a a a
0 0 1 1
g1
pMOS: 0 = ON
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON
Series: both must be ON a a a a a
Parallel: either can be ON g1
g2
0
0
0
1
1
0
1
1
b b b b b
(b) ON OFF OFF OFF
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(c) OFF ON ON ON
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(d) ON ON ON OFF
1: Circuits & Layout CMOS VLSI Design 4th Ed. 11
Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS Y
A
B
Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel
1: Circuits & Layout CMOS VLSI Design 4th Ed. 12
Static CMOS Circuits
N and P channel networks implement logic functions
– Each network Connected between Output and VDD or VSS
1: Circuits & Layout CMOS VLSI Design 4th Ed. 13
CMOS NAND
A B F
0 0 1
A B
0 1 1
1 0 1
A•B
1 1 0
A
A
B
CSE477 L06 Static CMOS Logic.14 Irwin&Vijay, PSU, 2003
CMOS NOR
A B F
B
0 0 1
A 0 1 0
1 0 0
A+B
1 1 0
A B
A
B
CSE477 L06 Static CMOS Logic.15 Irwin&Vijay, PSU, 2003
Compound Gates
Compound gates can do any inverting function
Ex:
A C A C
B D B D
(a) (b)
C D
A B C D
A B
(c)
(d)
C D
A
A B
B
Y Y
C
A C
D
B D
(f)
(e)
1: Circuits & Layout CMOS VLSI Design 4th Ed. 16
Layout of Complex Gate
1: Circuits & Layout CMOS VLSI Design 4th Ed. 17
Example: O3AI
A
B
C D
Y
D
A B C
1: Circuits & Layout CMOS VLSI Design 4th Ed. 18
Practice 1
OUT = D + A • (B + C)
B
A
C
A
D
B C
1: Circuits & Layout CMOS VLSI Design 4th Ed. 19
Complex CMOS Gate
B
A
C
D
OUT = !(D + A • (B + C))
A
D
B C
CSE477 L06 Static CMOS Logic.20 Irwin&Vijay, PSU, 2003
Practice 1
OUT = D + A • (B + C) VDD VDD
C
SN1 F SN4 A
F
SN2 B
A A
D D SN3
B C B C D
(a) pull-down network (b) Deriving the pull-up network A
hierarchically by identifying
D
sub-nets
B C
(c) complete gate
1: Circuits & Layout CMOS VLSI Design 4th Ed. 21
Standard Cell Layout Methodology
Routing
channel
VDD
signals
GND
What logic function is this?
CSE477 L06 Static CMOS Logic.22 Irwin&Vijay, PSU, 2003
Practice 2
1: Circuits & Layout CMOS VLSI Design 4th Ed. 23
Duality is not Necessary
1: Circuits & Layout CMOS VLSI Design 4th Ed. 24
Signal Strength
Strength of signal
– How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
– But degraded or weak 1
pMOS pass strong 1
– But degraded or weak 0
Thus nMOS are best for pull-down network
1: Circuits & Layout CMOS VLSI Design 4th Ed. 25
Gate Layout
Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
1: Circuits & Layout CMOS VLSI Design 4th Ed. 26
Example: Inverter
1: Circuits & Layout CMOS VLSI Design 4th Ed. 27
Example: NAND3
Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
1: Circuits & Layout CMOS VLSI Design 4th Ed. 28
Stick Diagrams
Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact
GND GND
INV NAND3
1: Circuits & Layout CMOS VLSI Design 4th Ed. 29
Wiring Tracks
A wiring track is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
Transistors also consume one wiring track
1: Circuits & Layout CMOS VLSI Design 4th Ed. 30
Well spacing
Wells must surround transistors by 6 l
– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track
1: Circuits & Layout CMOS VLSI Design 4th Ed. 31
Area Estimation
Estimate area by counting wiring tracks
– Multiply by 8 to express in l
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1: Circuits & Layout CMOS VLSI Design 4th Ed. 32
Example: O3AI
Sketch a stick diagram for O3AI and estimate area
–
1: Circuits & Layout CMOS VLSI Design 4th Ed. 33
Stick Diagrams
Stick Diagrams
Objectives:
• To know what is meant by stick diagram.
• To understand the capabilities and limitations of stick
diagram.
• To learn how to draw stick diagrams for a given MOS
circuit.
Outcome:
• At the end of this module the students will be able
draw the stick diagram for simple MOS circuits.
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Stick Diagrams
N+ N+
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Stick Diagrams
VDD
VDD
X
X
x x x
x Stick
Diagram X
Gnd Gnd
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Stick Diagrams
VDD
VDD
X
X
x x x
x X
Gnd Gnd
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Stick Diagrams
VLSI design aims to translate circuit concepts
onto silicon.
stick diagrams are a means of capturing
topography and layer information using
simple diagrams.
Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
Acts as an interface between symbolic circuit
and the actual layout.
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Stick Diagrams
Does show all components/vias.
It shows relative placement of components.
Goes one step closer to the layout
Helps plan the layout and routing
A stick diagram is a cartoon of a layout.
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Stick Diagrams
Does not show
• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics..
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Stick Diagrams – Notations
Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Similarly for contacts, via, tub etc..
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Stick Diagrams
Stick Diagrams – Some rules
Rule 1.
When two or more ‘sticks’ of the same type cross
or touch each other that represents electrical
contact.
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Stick Diagrams
Stick Diagrams – Some rules
Rule 2.
When two or more ‘sticks’ of different type cross
or touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).
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Stick Diagrams
Stick Diagrams – Some rules
Rule 3.
When a poly crosses diffusion it represents a
transistor.
Note: If a contact is shown then it is not a transistor.
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Stick Diagrams – Some rules
Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie
on one side of the line and all nMOS will have
to be on the other side.
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
How to draw Stick Diagrams
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Power
A Out
Ground
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S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
VDD VDD
Inverter
NAND2
Out Out
In A B
GND GND
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Stick Diagram Drawing : CMOS
Steps
1) Implement the expression in CMOS Logic
2) Find all Euler paths that cover the graph
3) Find n and p Euler paths that have same
labeling
4) Draw Stick diagram for optimization of
diffusion areas
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Stick Diagrams
Logic Graph X PUN
A
j C
B C
X i VDD
X = C • (A + B)
C
i B j A
A B A
B PDN
C GND
PUN: Pull-up Network, PDN: Pull-down Network
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Two Versions of C • (A + B)
A C B A B C
VDD VDD
X X
GND GND
Two Strips Line of Diffusions One Strip Line of Diffusions
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Two Stick Layouts of !(C • (A + B))
crossover requiring vias
A C B A B C
VDD VDD
X X
GND GND
uninterrupted diffusion strip
CSE477 L06 Static CMOS Logic.53 Irwin&Vijay, PSU, 2003
Consistent Euler Path
An uninterrupted diffusion strip is possible only if there
exists a Euler path in the logic graph
Euler path: a path through all nodes in the graph such that
each edge is visited once and only once.
X
X i VDD
B j A
GND A B C
For a single poly strip for every input signal, the Euler
paths in the PUN and PDN must be consistent (the same)
CSE477 L06 Static CMOS Logic.54 Irwin&Vijay, PSU, 2003
OAI22 Logic Graph
X PUN
A C
B D D C
X VDD
X = ((A+B)•(C+D))
C D
B A
A B PDN
A GND
B
C
D
CSE477 L06 Static CMOS Logic.55 Irwin&Vijay, PSU, 2003
OAI22 Layout
A B D C
VDD
GND
Some functions have no consistent Euler path like
x = !(a + bc + de) (but x = !(bc + a + de) does!)
CSE477 L06 Static CMOS Logic.56 Irwin&Vijay, PSU, 2003
Example: x = AB + CD
VDD
Euler paths {A B C D }
D C
A B
X = AB + CD
C B
VDD
D A
X
GND GND
A B C D
Stick diagram for ordering { A B C D } 57
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Example: x = ab+cd
x x
b c b c
x VDD x VD D
a d a d
GND GND
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
VD D
Euler Paths x
For both PUD
and PDN GND
a b c d
(c) stick diagram for ordering {a b c d}
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Layout of Complex Gate
1: Circuits & Layout
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CMOS Gate1
OUT = (D+E).A+B C
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Minimize area-Eulers path
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Euler graph APPROACH
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Stick Diagram using Euler Graph Method
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Stick Diagram Optimum Gate Ordering ALL IN ONE
Find a Euler path in both the pull-down tree
graph and the pull-up tree graph with
identical ordering of the inputs.
Euler path: traverses each branch of the
graph exactly once!
By reordering the input gates as E-D-A-B-C,
we can obtain an optimum layout of the
given CMOS gate with single actives for both
NMOS and PMOS devices (below).
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Stick diagram
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Example: 1. Draw Logic Graph
Identify each transistor
by a unique name of its
gate signal (A, B, C, D,
E in the example of
Figure 1).
Identify each
connection to the
transistor by a unique
name (1,2,3,4 in the
example of Figure 1).
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Example: 2. Define Euler Path
Euler paths are defined
by a path the traverses
each node in the path,
such that each edge is
visited only once.
The path is defined by
the order of each
transistor name. If the
path traverses
transistor A then B then
C. Then the path name
is {A, B, C}
The Euler path of the
Pull up network must be
the same as the path of
the Pull down network.
Euler paths are not
necessarily unique.
It may be necessary to
redefine the function to
find a Euler path.
F = E + (CD) + (AB) =
(AB) +E + (CD)
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Example: 3. Connection label layout
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Example: 4. VDD, VSS and Output Labels
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Example: 5. Interconnected
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1) Z=ABCD
2) Z=A+B+C+D DRAW THE
3) Z=ABC+D STICK
DIAGRAMS
4) Z=(AB+C) D
5) Z=(A+B+C)D
6) Z=A(B+C)+DE
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