ECEN 454:
Digital Integrated Circuit
Design
Lecture 1
CMOS VLSI Design 4th Ed.
Outline
A Brief History
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
1: Circuits & Layout CMOS VLSI Design 4th Ed. 2
A Brief History
1958: First integrated circuit
– Flip-flop using two transistors
– Built by Jack Kilby at Texas
Instruments
2010 Courtesy Texas Instruments
– Intel Core i7 mprocessor
• 2.3 billion transistors
– 64 Gb Flash memory
• > 16 billion transistors
[Trinh09]
© 2009 IEEE
1: Circuits & Layout CMOS VLSI Design 4th Ed. 3
Growth Rate
53% compound annual growth rate over 50 years
– No other technology has grown so fast so long
Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society
[Moore65]
Electronics Magazine
1: Circuits & Layout CMOS VLSI Design 4th Ed. 4
Annual Sales
>1019 transistors manufactured in 2008
– 1 billion for every human on the planet
1: Circuits & Layout CMOS VLSI Design 4th Ed. 5
Invention of the Transistor
Vacuum tubes ruled in first half of 20th century
Large, expensive, power-hungry, unreliable
1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs
– See Crystal Fire
by Riordan, Hoddeson
AT&T Archives.
Reprinted with
permission.
1: Circuits & Layout CMOS VLSI Design 4th Ed. 6
Transistor Types
Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration
1: Circuits & Layout CMOS VLSI Design 4th Ed. 7
MOS Integrated Circuits
1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle
Intel
Museum.
[Vadasz69]
Reprinted
© 1969 IEEE. with
permission.
Intel 1101 256-bit SRAM Intel 4004 4-bit mProc
1980s-present: CMOS processes for low idle power
1: Circuits & Layout CMOS VLSI Design 4th Ed. 8
Moore’s Law: Then
1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
[Moore65]
VLSI: > 10k gates
Electronics Magazine
1: Circuits & Layout CMOS VLSI Design 4th Ed. 9
And Now…
1: Circuits & Layout CMOS VLSI Design 4th Ed. 10
Feature Size
Minimum feature size shrinking 30% every 2-3 years
1: Circuits & Layout CMOS VLSI Design 4th Ed. 11
Corollaries
Many other factors grow exponentially
– Ex: clock frequency, processor performance
1: Circuits & Layout CMOS VLSI Design 4th Ed. 12
CMOS Gate Design
Activity:
– Sketch a 4-input CMOS NOR gate
A
B
C
D
Y
1: Circuits & Layout CMOS VLSI Design 4th Ed. 13
Complementary CMOS
Complementary CMOS logic gates
– nMOS pull-down network pMOS
– pMOS pull-up network pull-up
network
inputs
– a.k.a. static CMOS output
nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
1: Circuits & Layout CMOS VLSI Design 4th Ed. 14
Series and Parallel
a a a a
nMOS: 1 = ON g1
a
0 0 1 1
g2
pMOS: 0 = ON b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON
Series: both must be ON a a a a a
Parallel: either can be ON g1
g2
0
0
0
1
1
0
1
1
b b b b b
(b) ON OFF OFF OFF
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(c) OFF ON ON ON
a a a a a
g1 g2 0 0 0 1 1 0 1 1
b b b b b
(d) ON ON ON OFF
1: Circuits & Layout CMOS VLSI Design 4th Ed. 15
Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS Y
A
B
Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel
1: Circuits & Layout CMOS VLSI Design 4th Ed. 16
Compound Gates
Compound gates can do any inverting function
Ex: Y A B C D (AND-AND-OR-INVERT, AOI22)
A C A C
B D B D
(a) (b)
C D
A B C D
A B
(c)
(d)
C D
A
A B
B
Y Y
C
A C
D
B D
(f)
(e)
1: Circuits & Layout CMOS VLSI Design 4th Ed. 17
Example: O3AI
Y A B C D
A
B
C D
Y
D
A B C
1: Circuits & Layout CMOS VLSI Design 4th Ed. 18
Signal Strength
Strength of signal
– How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
– But degraded or weak 1
pMOS pass strong 1
– But degraded or weak 0
Thus nMOS are best for pull-down network
1: Circuits & Layout CMOS VLSI Design 4th Ed. 19
Pass Transistors
Transistors can be used as switches
g=0 Input g = 1 Output
g
s d 0 strong 0
s d g=1 g=1
s d 1 degraded 1
g=0 Input Output
g=0
g s d 0 degraded 0
s d g=1
g=0
s d 1 strong 1
1: Circuits & Layout CMOS VLSI Design 4th Ed. 20
Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb
g g g
a b a b a b
gb gb gb
1: Circuits & Layout CMOS VLSI Design 4th Ed. 21
Tristates
Tristate buffer produces Z when not enabled
EN
EN A Y
0 0 Z A Y
0 1 Z
1 0 0
EN
1 1 1
A Y
EN
1: Circuits & Layout CMOS VLSI Design 4th Ed. 22
Nonrestoring Tristate
Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y
EN
A Y
EN
1: Circuits & Layout CMOS VLSI Design 4th Ed. 23
Tristate Inverter
Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A A
A
EN
Y Y Y
EN
EN = 0 EN = 1
Y = 'Z' Y=A
1: Circuits & Layout CMOS VLSI Design 4th Ed. 24
Multiplexers
2:1 multiplexer chooses between two inputs
S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1
1: Circuits & Layout CMOS VLSI Design 4th Ed. 25
Gate-Level Mux Design
Y SD1 SD0 (too many transistors)
How many transistors are needed? 20
D1
S Y
D0
D1 4 2
S 4 2 Y
D0 4 2
2
1: Circuits & Layout CMOS VLSI Design 4th Ed. 26
Transmission Gate Mux
Nonrestoring mux uses two transmission gates
– Only 4 transistors
S
D0
S Y
D1
1: Circuits & Layout CMOS VLSI Design 4th Ed. 27
Inverting Mux
Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
Noninverting multiplexer adds an inverter
D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
1: Circuits & Layout CMOS VLSI Design 4th Ed. 28
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates S1S0 S1S0 S1S0 S1S0
D0
S0 S1
D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1
D3
1: Circuits & Layout CMOS VLSI Design 4th Ed. 29
D Latch
When CLK = 1, latch is transparent
– D flows through to Q like a buffer
When CLK = 0, the latch is opaque
– Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
CLK CLK
D
Latch
D Q
Q
1: Circuits & Layout CMOS VLSI Design 4th Ed. 30
D Latch Design
Multiplexer chooses D or old Q
CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK
CLK
1: Circuits & Layout CMOS VLSI Design 4th Ed. 31
D Latch Operation
Q Q
D Q D Q
CLK = 1 CLK = 0
CLK
1: Circuits & Layout CMOS VLSI Design 4th Ed. 32
D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
CLK
CLK
D
Flop
D Q
Q
1: Circuits & Layout CMOS VLSI Design 4th Ed. 33
D Flip-flop Design
Built from master and slave D latches
CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch
Latch
QM
D Q
CLK CLK
1: Circuits & Layout CMOS VLSI Design 4th Ed. 34
D Flip-flop Operation
QM Q
D
CLK = 0
QM
D Q
CLK = 1
CLK
1: Circuits & Layout CMOS VLSI Design 4th Ed. 35
Race Condition
Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition
CLK1
CLK1 CLK2 CLK2
Q1
Flop
Flop
Q1 Q2
D
Q2
1: Circuits & Layout CMOS VLSI Design 4th Ed. 36
Nonoverlapping Clocks
Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
We will use them in this class for safe design
– Industry manages skew more carefully instead
2 1
QM
D Q
2 2 1 1
2 1
1
2
1: Circuits & Layout CMOS VLSI Design 4th Ed. 37
Gate Layout
Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
1: Circuits & Layout CMOS VLSI Design 4th Ed. 38
Example: Inverter
1: Circuits & Layout CMOS VLSI Design 4th Ed. 39
Example: NAND3
Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
1: Circuits & Layout CMOS VLSI Design 4th Ed. 40
Stick Diagrams
Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact
GND GND
INV NAND3
1: Circuits & Layout CMOS VLSI Design 4th Ed. 41
Wiring Tracks
A wiring track is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
Transistors also consume one wiring track
1: Circuits & Layout CMOS VLSI Design 4th Ed. 42
Well spacing
Wells must surround transistors by 6 l
– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track
1: Circuits & Layout CMOS VLSI Design 4th Ed. 43
Area Estimation
Estimate area by counting wiring tracks
– Multiply by 8 to express in l
40 l
32 l
1: Circuits & Layout CMOS VLSI Design 4th Ed. 44
Example: O3AI
Sketch a stick diagram for O3AI and estimate area
–
Y A B C D
VDD
A B C D
6 tracks =
48 l
Y
GND
5 tracks =
40 l
1: Circuits & Layout CMOS VLSI Design 4th Ed. 45
