Advance Digital Integrated Circuit Design

Circuits Design for Low Power

Hieu M. Nguyen

Digital Integrated Circuit Design©2017 PC.1

 Agenda
Overview of VLSI power

Technology, Scaling, and Power

Review of scaling

A look at the real trends and projections for the future

Active power – components, trends, managing, estimating

Static power – components, trends, managing, estimating

Summary

Digital Integrated Circuit Design©2017 PC.2

 A quick look at the power consumption of a modern Laptop
(IBM R40)

Power is all about the (digital) VLSI circuits…..and the backlight!

100%
90% Other
80%
LCD+BckLt
70%
60% Wireless
50% Mem
40% Graphics
30%
20% NB/SB; misc
10% CPU
0%
CPU FTP Tx 3D Games
Workload 17W 30W
26W

Src: Mahesri et al., U of Illinois, 2004

Digital Integrated Circuit Design©2017 PC.3

 A quick look at the power consumption of a Server

Again, it’s a VLSI problem – but this time with analog!

cpu
pwr mem

i/o

Source Bose, Hot Chips 2005,

Digital Integrated Circuit Design©2017 PC.4

 Designing within limits: power & energy

 Thermal limits (for most parts self-heating is a

substantial thermal issue)
- package cost (4-5W limit for cheap plastic package, 50-100W/sq-cm air cooled limit, 5k-7.5kW 19” rack)
- Device reliability (junction temp > 125C quickly reduces reliability)
- Performance (25C -> 105C loss of 30% of performance)

- Distribution limits
- Substantial portion of wiring resource, area for power dist.
- Higher current => lower R, greater dI/dt => more wire, decap
- Package capable of low impedance distribution

- Energy capacity limits

- AA battery ~1000mA.hr => limits power, function, or lifetime
- Energy cost
- Energy for IT equipment large fraction of total cost of ownership

Digital Integrated Circuit Design©2017 PC.5

 Agenda

Overview of VLSI power

Technology, Scaling, and Power

Review of scaling

A look at the real trends and projections for the future

Active power – components, trends, managing, estimating

Static power – components, trends, managing, estimating

Summary

Digital Integrated Circuit Design©2017 PC.6

 CMOS circuit power consumption components

P = ½ CswVdd DV f + IstVdd + IstaticVdd

 Dynamic power consumption ( ½ CswVdd DV f + IstVdd)

– Load switching (including parasitic & interconnect)
– Glitching
– Shoot through power (IstVdd)
 Static power consumption (IstaticVdd)
– Current sources – bias currents
– Current dependent logic -- NMOS, pseudo-NMOS, CML
– Junction currents
– Subthreshold MOS currents
– Gate tunneling

Digital Integrated Circuit Design©2017 PC.7

 Review of Constant Field Scaling

Parameter Value Scaled

Value

Dimensions L, W, aL,
Tox aW,
aTox

Dopant Na, Na/a,

These are
concentrations Nd Nd/a distributions…
Voltage V aV
how do the s s
scale?
Field E E
Capacitance C aC
Current I aI
Propagation t at
time (~CV/I)

Power (VI) P a2P

Scale factor a<1
Density d d/a2
Power density P/A P/A

Digital Integrated Circuit Design©2017 PC.8

 Agenda

Overview of VLSI power

Technology, Scaling, and Power

Review of scaling

A look at the real trends and projections for the future

Active power – components, trends, managing, estimating

Static power – components, trends, managing, estimating

Summary

Digital Integrated Circuit Design©2017 PC.9

 CMOS Circuit Delay and Frequency
P = ½C swVdd DV f + IstVdd + IstaticVdd

VLSI system frequency determined by:

Sum of propagation delays across gates in “critical path” --
Each gate delay, includes time to charge/discharge
load thru one or more FETs and interconnect delay
to distribute the signal to next gate input.

Td = kCV/I
= kCV/(Vdd-Vt)a

Sakuri a-power law model of delay

Digital Integrated Circuit Design©2017 PC.10

 Gate Delay Trends
P = ½C swVdd DV f + IstVdd + IstaticVdd

Consistent with
C.F. Scaling

Each technology generation,

gate delay reduced about 30% Td = kCV/I
(src: ITRS ’05) = kCV/(Vdd-Vt)a
Digital Integrated Circuit Design©2017 PC.11
 Microprocessor Frequency
P = ½ C V DV f + I Vdd + I sw dd st staticVdd

In practice the trend is:

Frequency increasing by 2X (delay decreasing by 50%),
not the 1.4X (30%) for constant field scaling for 1um to 65nm
node (src: ITRS ’01).
Why? decreasing logic/stage and increased pipeline depth.

Intel 32b (after Hrishikesh, et. al) * Below 65nm

35 node return to
90
80
30 1.4X/generation
70 25 [ITRS’05] Why?

period (ns)
Fo4/cycle

60
20 cycle in FO4
50
15 Period
40
30 10
20
5
10
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
technology

Digital Integrated Circuit Design©2017 PC.12

 Dynamic Energy
 
dVout
EVdd   iVdd (t )Vdddt  Vdd  CL dt
t 0 0
dt
Vdd iVdd
EVdd  C LVdd   2
dVout C LVdd Vout
Vout 0
  CL
dV
Ec   iCL (t )Vout dt   C L out Vout dt
t 0 0
dt
 
dVout
Vdd
1 Ec   iVd d (t )Voutdt   CL Voutdt


dt
Ec  C L 
2 t 0 0
Vout dVout C V
L dd Vdd

Vout 0
2 Ec  CL V
Vout 0
dVout  CLVdd 2 / 2
out

Energy dissipated for either output transition consumes:

½ CL Vdd2

P = ½ CswVdd DV f + IstVdd + IstaticVdd

Gate level energy consumption should improve as

a3 under constant field scaling, but….

Digital Integrated Circuit Design©2017 PC.13

 Supply Voltage Trend
P = ½ C Vdd DV f +
sw IstVdd + IstaticVdd
2.5
Vdd (Volts)
2

1.5

0.5 Slow decline

to 0.7V in 22nm
0 (some think nothing
0.25m 0.18m 0.13m 90nm 65nm 45nm
below 0.9V for HP uProcs)

With each generation, voltage has decreased 0.85x,

not 0.7x for constant field.
Thus, energy/device is decreasing by 50% rather than 65%

Digital Integrated Circuit Design©2017 PC.14

 Active Power Trend
P = ½ CswVdd DV f + IstVdd + IstaticVdd

Expected HP MP power
300

ITRS’01
250
Power (W)

200

150 ITRS’05 198 Watts forever!

100
160 140 120 100 80 60 40 20
Technology

But, number of transistors has been increasing, thus

- a net increase in energy consumption,
- with freq 2x, active power is increasing by 50%
(src: ITRS ’01-’05)

Digital Integrated Circuit Design©2017 PC.15

 Recent (180nm – 65nm) “Real Scaling”

Parameter Value Scaled Value

Dimensions L, W, 0.7 L, 0.7 W,

Tox 0.7 Tox

Dopant Na, Nd 1.4 Na, 1.4

concentrations Nd

Voltage V 0.7 V 0.9 V

Performance F 1.4 F 2.0 F
Power/device P 0.5 P 1.0 P
Power/chip P 1P 1.5 P
Power density P/A P/A 2.0 P/A

Digital Integrated Circuit Design©2017 PC.16

 Future (65nm – 22nm) “Projected Scaling”

Parameter Value Scaled Value

Dimensions L, W, 0.7 L, 0.7 W,

Tox 0.7 Tox

Dopant Na, Nd 1.4 Na, 1.4

concentrations Nd

Voltage V 0.7 V 0.9 V

Performance F 1.4 F

Power/device P 0.5 P 0.8 P

Power/chip P 1P 1.2 P
198 Watts
Power density P/A P/A 1.2 P/A forever!?
How?

Digital Integrated Circuit Design©2017 PC.17

 Active-Power Reduction Techniques
P = ½ CswVdd DV f + IstVdd + IstaticVdd
Active power can be reduced
through:
 Capacitance minimization
 Power/Performance in sizing
 Clock-gating
 Glitch suppression
 Hardware-accelerators
 System-on-a-chip integration
 Voltage minimization
 (Dynamic) voltage-scaling
 Low swing signaling
 SOC/Accelerators
 Frequency minimization
 (Dynamic) frequency-scaling
 SOC/Accelerators

Digital Integrated Circuit Design©2017 PC.18

 Capacitance minimization

P = ½ CswVdd DV f + IstVdd + IstaticVdd

Only the devices (device width) used in the design
consume active power!

 Runs counter to the complexity-for-

IPC trend
 Runs counter to the SOC trend

Digital Integrated Circuit Design©2017 PC.19

 Capacitance minimization

Example of managing design capacitance:

Device sizing for power efficiency is significantly different than sizing for
performance – eg. sizing of the gate size multiplier in an exponential-
horn of inverters for driving large loads.
100

Energy.Delay^2
Metric

10

Energy.Delay

Delay

Energy

1
0 2 4 6 8 10
Multiplier k
Digital Integrated Circuit Design©2017 PC.20
 Functional Clock Gating

P = ½ CswVdd DV f + IstVdd + IstaticVdd

 25-50% of power consumption due to driving latches
(Bose, Martinozi, Brooks 2001 50%)

 Utilization of most latches is low (~10-35%)

 Gate off unused latches and associated logic:
– Unit level clock gating – turn off clocks to FPU,
MMX, Shifter, L/S unit, … at clk buffer or splitter
– Functional clock gating – turn off clocks to individual
latch banks – forwarding latch, shift-amount register,
overflow logic & latches, …qualify (AND) clock to latch
 Asynch is the most aggressive gating – but is it efficient?

Digital Integrated Circuit Design©2017 PC.21

 Glitch suppression

P = ½ CswVdd DV f + IstVdd + IstaticVdd

 Glitches can represent a sizeable portion of active
power, (up to 30% for some circuits in some studies)
 Three basic mechanisms for avoidance:
– Use non-glitching logic, e.g. domino
– Add redundant logic to avoid glitching hazards
 Increases cap, testability problems
– Adjust delays in the design to avoid
 Shouldn’t timing tools do this already if it is possible?

Digital Integrated Circuit Design©2017 PC.22

 Voltage minimization

P = ½ CswVdd DV f + IstVdd + IstaticVdd

 Lowering voltage swing, DV, lowers power

– Low swing logic efforts have not been very
successful (unless you consider array voltage
sensing)
– Low swing busses have been quite successful
 Lowering supply, Vdd and DV, (voltage scaling) is most
promising:
– Frequency ~V, Power ~V3

Digital Integrated Circuit Design©2017 PC.23

 Voltage Scaling Reduces Active Power
 Voltage Scaling Benefits
 Can be used widely over entire chip
Avg Relative Ring Osc Delay/Power
 Complementary CMOS scales well
over a wide voltage range => Can 5 1.2
optimize power/performance
(MIPS/mW) over a wide range 4.5
4 1
 Voltage Scaling Challenges 3.5 0.8
 Custom CPUs, Analog, PLLs, and I/O 3 a-pwr delay
meas delay
drivers don’t voltage scale easily 2.5 0.6
model pwr
 Sensitivity to supply voltage 2 meas pwr
0.4
varies circuit to circuit – esp SRAM, 1.5
buffers, NAND4 1 0.2
0.5
 Thresholds tend to be too high at low
supply 0 0
0.7 0.95 1.2 1.45 1.7
Supply Voltage

After Carpenter, Microprocessor forum, ‘01

Digital Integrated Circuit Design©2017 PC.24

 Dynamic Voltage-Scaling (e.g. XScale, PPC405LP)

PowerPC 405LP measurements: 18:1 power range over 4:1 frequency range

500 Measured Freq 500

Frequency (MHz)

Measured Power
400 400

Power (mW)
300 300

200 200

100 100
After Nowka,
0 0 et.al. ISSCC, Feb ‘02
1 1.2 1.4 1.6 1.8 2
Supply Voltage (V)

Digital Integrated Circuit Design©2017 PC.25

 Frequency minimization

P = ½ CswVdd DV f + IstVdd + IstaticVdd

 Lowering frequency lowers power linearly

– DOES NOT improve energy efficiency, just slows
down energy consumption
– Important for avoiding thermal problems

Digital Integrated Circuit Design©2017 PC.26

 Voltage-Frequency-Scaling Measurements
PowerPC 405LP

Freq
Scaling

Plus DVS

Src: After Nowka,

Freq scale ¼ freq, ¼ pwr; DVS ¼ freq, 1/10 pwr et.al. JSSC, Nov ‘02

Digital Integrated Circuit Design©2017 PC.27

 Shoot-through minimization

Ist
in out
P = ½ CswVdd DV f + IstVdd + IstaticVdd

 For most designs, shoot-thru represents 8-15% of

active power.
in
 Avoidance and minimization:
– Lower supply voltage
out – Domino?
– Avoid slow input slews
Both Pfet & – Careful of level-shifters in multiple voltage domain
Nfet conducting
designs

Digital Integrated Circuit Design©2017 PC.28

 Estimating Active Power Consumption

P = ½ CswVdd DV f + IstVdd + IstaticVdd

 The problem is how to estimate capacitance switched

 Switch factor SF: ½ Csw i= S iSF Cnode
i
– Low level circuit analysis – spice analysis
– Higher level: spreadsheet/back-of-the-envelope/power
tools for estimation
 Aggregate or node-by-node estimation of switch factors –
1.0 ungated clocks, 0.5 signals which switch every cycle,
0.1-0.2 for processor logic
 These can be more accurately derived by tools which look at
pattern dependence and timing
 Node Capacitance – sum of all cap: output driver
parasitic, interconnect, load gate cap

Digital Integrated Circuit Design©2017 PC.29

 Agenda
Overview of VLSI power

Technology, Scaling, and Power

Review of scaling

A look at the real trends and projections for the future

Active power – components, trends, managing, estimating

Static power – components, trends, managing, estimating

Summary

Digital Integrated Circuit Design©2017 PC.30

 Static Power

P = CswVdd DV f + IstVdd + IstaticVdd

 Static energy consumption (IstaticVdd)

– Current sources – even uA bias currents can add
up.
– NMOS, pseudo-NMOS – not commonly used
– CMOS CML logic – significant power for specialized
use.
– Junction currents
– Subthreshold MOS currents
– Gate tunneling

Digital Integrated Circuit Design©2017 PC.31

 Subthreshold Leakage

P = KVe(Vgs-Vt)q/nkT (1 – e -Vds q/kT)

 Supplies have been held artificially high (for freq)
– Threshold has not dropped as fast as it should (because of
variability and high supply voltages)
– We’d like to maintain Ion:Ioff = ~1000uA/u : 10nA/u
– Relatively poor performance => Low Vt options
 70-180mV lower Vt, 10-100x higher leakage, 5-15% faster
 Subthreshold lkg especially increasing in short
channel devices (DIBL) & at high T – 100-1000nA/u
 Subthreshold slope 85-110 mV/decade
 Cooling changes the slope….but can it be energy
efficient?
Digital Integrated Circuit Design©2017 PC.32
 Passive Power Continues to Explode
Leakage is the price we pay for the increasing device performance

1000

100

Power Density (W/cm2)

Active
Fit of published active Power
10
and subthreshold CMOS
Passive Power
device leakage 1
densities
0.1

0.01 Gate Leakage

1994 2005
0.001
1 0.1 0.01
Gate Length (microns)

Src: Nowak, et al

Digital Integrated Circuit Design©2017 PC.33

 Gate Leakage
 Gate tunneling becoming dominant leakage mechanism in very thin gate
oxides

 Current exponential in oxide thickness

 Current exponential in voltage across oxide

 Reduction techniques:
– Lower the field (voltage or oxide thickness)

– New gate ox material

Metal gate electrode

Poly-Si

High-k material

SiON Oxide interlayer

30A

Digital Integrated Circuit Design©2017 PC.34

 Future Leakage, Standby Power Trends
Standby Power/Gate
150

Power (nW)
100

50

0
160 140 120 100 80 60 40 20
Technology

Src: ITRS ‘01

And, recall number of transistors/die

has been increasing 2X/2yrs
(Active power/gate should be 0.5x/gen,
has been 1X/gen)

For the foreseeable future, leakage is a major power issue

Digital Integrated Circuit Design©2017 PC.35

 Standby-Power Reduction Techniques

Standby power can be reduced through:

 Capacitance minimization
 Voltage-scaling
 Power gating
 Vdd/Vt selection

Digital Integrated Circuit Design©2017 PC.36

 Capacitance minimization

Only the devices (device width) used in the design leak!

 Runs counter to the complexity-for-

IPC trend
 Runs counter to the SOC trend
 Transistors are not free -- Even
though they are not switched they
still leak

Digital Integrated Circuit Design©2017 PC.37

 Voltage Scaling Standby Reduction

Decreasing the supply voltage significantly improves standby power

2
Logic leakage w/VCO inactive
Standby Power (mW)

1.5

0.5

0
0.8 1 1.2 1.4 1.6 1.8 2
Logic Voltage(V)
Subthreshold dominated technology
After Nowka, et.al. ISSCC ‘02

Digital Integrated Circuit Design©2017 PC.38

 Supply/Power Gating

 Especially for energy constrained (e.g. battery powered

systems). Two levels of gating:
– “Standby, freeze, sleep, deep-sleep, doze, nap,
hibernate”: lower or turn off power supply to system
to avoid power consumption when inactive
 Control difficulties, hidden-state, entry/exit, “instant-
on” or user-visible.
– Unit level power gating – turn off inactive units while
system is active
 Eg. MTCMOS
 Distribution, entry/exit control & glitching, state-loss…

Digital Integrated Circuit Design©2017 PC.39

 MTCMOS

 Use header and/or footer switches to disconnect supplies when

inactive.
 For performance, low-Vt for logic devices.
 10-100x leakage improvement, ~5% perf overhead
 Loss of state when disconnected from supplies
 Large number of variants in the literature

B
B Standby
A headers/
Xb A footers
A B Xb
A B

Digital Integrated Circuit Design©2017 PC.40

 Vt / Tox selection

X Xb X Xb
Low Hi
threshold/ threshold/
Thin oxide Thicker
oxide
 Low Vt devices on critical paths, rest high Vt
 70-180mV higher Vt, 10-100x lower leakage, 5-20% slower
 Small fraction of devices low-Vt (1-5%)
 Thick oxide reduces gate leakage by orders of magnitude

Digital Integrated Circuit Design©2017 PC.41

 Device Stacking

Xb
X Xb X
Stacked
devices

 Decreases subthreshold leakage

 Improvement beyond use of long channel device
 2-5x improvement in subthreshold leakage
 15-35% performance penalty

Digital Integrated Circuit Design©2017 PC.42

 Vt or/and Vdd selection

 Design tradeoff:
– Performance => High supply, low threshold
– Active Power => Low supply, low threshold
– Standby => Low supply, high threshold
 Static
– Stack effect – minimizing subthreshold thru
single fet paths
– Multiple thresholds: High Vt and Low Vt
transistors
– Multiple supplies: high and low Vdd

Digital Integrated Circuit Design©2017 PC.43

 Vt or/and Vdd selection (cont’d)

 Design tradeoff:
– Performance => High supply, low threshold
– Active Power => Low supply, low threshold
– Standby => Low supply, high threshold
 Static
– Stack effect – minimizing subthreshold thru single fet
paths
– Multiple thresholds: High Vt and Low Vt Transistors
– Multiple supplies: high and low Vdd
– Problem: optimum (Vdd,Vt) changes over time, across
dice
 Dynamic (Vdd,Vt) selection
– DVS for supply voltage
– Dynamic threshold control thru:
 Active well
 Substrate biasing
 SOI back gate, DTMOS, dual-gate technologies

Digital Integrated Circuit Design©2017 PC.44

 Hitachi-SH4 leakage reduction

Triple Well Process

Reverse Bias Active Well –
can achieve >100x leakage reduction

3.3V
GP
GN
Vbp 1.8V

VDD 1.8V

Switch Switch
Cell 1.8V Cell
Logic
GND 0V

Vbn 0V

-1.5V

Digital Integrated Circuit Design©2017 PC.45

 Nwell/Virtual Gnd Leakage Reduction
Similar technique for Nwell/Psub technology
– Intel approach
VB +

VDD+VB

Vbp VDD

uP Core
VDD VDD
Leakpfet
VB
Leaknfet
VSS 0V

GND 0V

Digital Integrated Circuit Design©2017 PC.46

 Estimating Leakage Power Consumption

P = ½ CswVdd DV f + IstVdd + IstaticVdd

 The problem is how to estimate the leakage current

 Estimating leakage currents
– Low level circuit analysis – spice analysis
– Higher level: spreadsheet/back-of-the-envelope/power
tools for estimation
 Subthreshold: Estimates based on the fraction of the device
width leaking. Usually evaluated for some non-nominal point
in the process and higher temperature. Aggregate or node-
by-node estimation of derating factors – fraction of devices
with field across the SD device ~1/3 for logic.
 Gate leakage: Estimates based on the fraction of the device
area leaking. Aggregate or node-by-node estimation of
derating factors – fraction of devices with field across the
gate of the device.

Digital Integrated Circuit Design©2017 PC.47

 Agenda
Overview of VLSI power

Technology, Scaling, and Power

Review of scaling

A look at the real trends and projections for the future

Active power – components, trends, managing, estimating

Static power – components, trends, managing, estimating

Summary

Digital Integrated Circuit Design©2017 PC.48

 Low Power Circuits Summary

Technology, Scaling, and Power

Technology scaling hasn’t solved the power/energy problems.

So what to do? We’ve shown that,

Do less and/or do in parallel at low V. For the circuit designer this

implies:
– supporting low V,

– supporting power-down modes,

– choosing the right mix of Vt,

– sizing devices appropriately

– choosing right Vdd, (adaptation!)

Digital Integrated Circuit Design©2017 PC.49

 References

 Power Metrics
– T. Sakurai and A. Newton, “Alpha-power law MOSFET model and its
applications to CMOS inverter delay and other formulas”, IEEE Journal
of Solid State Circuits, v. 25.2, pp. 584-594, Apr. 1990.
– R. Gonzalez, B. Gordon, M. Horowitz, “Supply and threshold voltage
scaling for low power CMOS” IEEE Journal of Solid State Circuits, v. 32,
no. 8, pp. 1210-1216, August 2000.
– Zyuban and Strenski, “Unified Methodology for Resolving Power-
Performance Tradeoffs at the Microarchitectural and Circuit
Levels”,ISPLED Aug.2002
– Brodersen, Horowitz, Markovic, Nikolic, Stojanovic “Methods for True
Power Minimization”, ICCAD Nov. 2002
– Stojanovic, Markovic, Nikolic, Horowitz, Brodersen, “Energy-Delay
Tradoffs in Combinational Logic using Gate Sizing and Supply Voltage
Optimization”, ESSCIRC, Sep. 2002

Digital Integrated Circuit Design©2017 PC.50

 References
 Power/Low Power

– SIA, International Technology Roadmap for Semiconductors, 2001,2003, 2005 available

online.
– V. Agarwal, M.S. Hrishikesh, S.W. Keckler, and D. Burger. "Clock Rate Versus IPC: The End
of the Road for Conventional Microarchitectures," 27th International Symposium on
Computer Architecture (ISCA), June, 2000.
– Allan, et. al., “2001 Tech. Roadmap for Semiconductors”,IEEE Computer Jan. 2002
– Chandrakasan, Broderson, (ed) Low Power CMOS Design IEEE Press, 1998.
– Oklobdzija (ed) The Computer Engineering Handbook CRC Press, 2002
– Kuo, Lou Low voltage CMOS VLSI Circuits, Wiley, 1999.
– Bellaouar, Elmasry, Low Power Digital VLSI Design, Circuits and Systems, Kluwer, 1995.
– Chandrakasan, Broderson, Low Power Digital CMOS Design Kluwer, 1995.
– A. Correale, “Overview of the power minimization techniques employed in the IBM PowerPC
4xx embedded controllers” IEEE Symposium on Low Power Electronics Digest of Technical
Papers, pp. 75-80, 1995.
– K. Nowka, G. Carpenter, E. MacDonald, H. Ngo, B. Brock, K. Ishii, T. Nguyen, J. Burns, “A
0.9V to 1.95V dynamic voltage scalable and frequency scalable 32-bit PowerPC processor “,
Proceedings of the IEEE International Solid State Circuits Conference, Feb. 2002.
– K. Nowka, G. Carpenter, E. MacDonald, H. Ngo, B. Brock, K. Ishii, T. Nguyen, J. Burns, “A
32-bit PowerPC System-on-a-Chip with support for dynamic voltage scaling and dynamic
frequency scaling”, IEEE Journal of Solid State Circuits, November, 2002.

Digital Integrated Circuit Design©2017 PC.51

 References

 Low Voltage / Voltage Scaling

– E. Vittoz, “Low-power design: ways to approach the limits” IEEE International Solid State
Circuits Conference Digest of Technical Papers, pp. 14-18, 1994.
– M. Horowitz, T. Indermaur, R. Gonzalez, “Low-power digital design” IEEE Symposium on
Low Power Electronics Digest of Technical Papers, pp. 8-11, 1994.
– R. Gonzalez, B. Gordon, M. Horowitz, “Supply and threshold voltage scaling for low power
CMOS” IEEE Journal of Solid State Circuits, v. 32, no. 8, pp. 1210-1216, August 2000.
– T. Burd and R. Brodersen, “Energy efficient CMOS microprocessor design ” Proceedings of
the Twenty-Eighth Hawaii International Conference on System Sciences, v. 1, pp. 288-297,
466, 1995.
– K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T.
Maeda, T. Kuroda, “A 300 MIPS/W RISC core processor with variable supply-voltage
scheme in variable threshold-voltage CMOS” Proceedings of the IEEE Conference on
Custom Integrated Circuits Conference, pp. 587 –590, 1997
– T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K.
Matsuda, T. Maeda, T. Sakurai, T. Furuyama, “Variable supply-voltage scheme for low-
power high-speed CMOS digital design” IEEE Journal of Solid State Circuits, v. 33, no. 3, pp.
454-462, March 1998.
– T. Burd, T. Pering, A. Stratakos, R. Brodersen, “A dynamic voltage scaled microprocessor
system ” IEEE International Solid State Circuits Conference Digest of Technical Papers, pp.
294-295, 466, 2000.

Digital Integrated Circuit Design©2017 PC.52

 References

 Technology and Circuit Techniques

– E. Nowak, et al., “Scaling beyond the 65 nm node with FinFET-DGCMOS” Proceedings of

the IEEE Custom Integrated Circuits Conference, Sept. 21-24, 2003, pp.339 – 342
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