VLSI Design

Power

Frank Sill Torres

Department of Electronic Engineering, Federal University of Minas Gerais,
Av. Antônio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil

franksill@ufmg.br
http://www.cpdee.ufmg.br/~frank/
 Trend: Performance

1000000
100000 Pentium® 4 proc
10000 1 TIPS
1000
MIPS 100
386 Pentium® proc
10
8086
1
0.1
8080
0.01
1970 1980 1990 2000 2010 2020

Source: Moore, ISSCC 2003

Copyright Sill Torres, 2012 2

 Trends – Power Dissipation

SoC Consumer Portable Power Trend [Source: ITRS, 2010 Update]

Copyright Sill Torres, 2012

Problems in Power Dissipation
Power Dissipation in a Notebook
Energy Dissipation in mobile devices
 Current Progresses

Batter.
20 kg

◼ Factor 4 in the last 10 years ➔ still much too less

Copyright Sill Torres, 2012 7

Why Power Matters
⚫ More transistors are packed into the chip.
⚫ Packaging costs
⚫ Power supply rail design
⚫ Chip and system cooling costs
⚫ Noise immunity and system reliability
⚫ Battery life (in portable systems)
⚫ Environmental concerns
Office equipment accounted for 5% of total US
commercial energy usage in 1993
Energy Star compliant systems
Why Worry about Power
Energy Dissipation on a chip
High temperatures cause chips to fail
Meaning of Low-Power Design
⚫ Design practices that reduce power
consumption at least by one order of magnitude;
in practice 50% reduction is often acceptable.
⚫ General considerations in low-power design
Algorithms and architectures
High-level and software techniques
Gate and circuit-level methods
Power estimation techniques
Test power
Energy and Power Metrics
⚫ Energy
 Measure in Joules or kWh
 No activity is possible without energy
 Measures the ability of a system to do work or produce change
 Energy efficiency in Joules - rate at which power is consumed
over time
⚫ Power
 Measured in Watts or kW
 Amount of energy used per unit time
 Average power – average energy used/unit time
 Instantaneous power – energy consumed if time unit goes to
zero
Energy and Power Metrics

lower energy number means less power to perform a

computation at the same frequency
Where Does Power Go in CMOS?

⚫Dynamic Power Consumption

Charging and discharging of capacitors
⚫Short Circuit Currents
Short circuit path between power supply rails
during switching
⚫Leakage
Leaking diodes and transistors
CMOS Energy & Power Equations

E = CL VDD2 P0→1 + tsc VDD Ipeak P0/1→1/0 + VDD Ileak

f = P * fclock

P = CL VDD2 f 0→1 + tscVDD Ipeak f + VDD Ileak

Dynamic Short-circuit Leakage

power power power

CSE477 L12&13 Low Power.16 Irwin&Vijay, PSU, 2003

Power Dissipation in CMOS Logic (0.25µ)
Ptotal (0→1) = CL VDD2 + tscVDD Ipeak + VDDIleakage
VDD VDD

CL

Energy is proportional to capacitive load!

%75 %20 %5
Power versus Energy
Power versus Energy
CMOS Dynamic Power
CMOS Dynamic Power
 NOR static transition probability
= 3/4 x 1/4 = 3/16

CSE477 L12&13 Low Power.22 Irwin&Vijay, PSU, 2003

 NOR Gate Transition Probabilities
❑ Switching activity is a strong function of the input signal
statistics
PA and PB are the probabilities that inputs A and B are one

0
A B
CL PA
1 0 1
PB

P0→1 = P0 x P1 = (1-(1-PA)(1-PB)) (1-PA)(1-PB)

CSE477 L12&13 Low Power.23 Irwin&Vijay, PSU, 2003

 Transition Probabilities for Some Basic Gates

P0→1 = Pout=0 x Pout=1

NOR (1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB)
OR (1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB))
NAND PAPB x (1 - PAPB)
AND (1 - PAPB) x PAPB
XOR (1 - (PA + PB- 2PAPB)) x (PA + PB- 2PAPB)
X
0.5 A
Z
0.5 B

For X: P0→1 = P0 x P1 = (1-PA) PA

= 0.5 x 0.5 = 0.25
For Z: P0→1 = P0 x P1 = (1-PXPB) PXPB
= (1 – (0.5 x 0.5)) x (0.5 x 0.5) = 3/16
CSE477 L12&13 Low Power.24 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.25 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.26 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.27 Irwin&Vijay, PSU, 2003
Low Power Techniques
Dynamic Power Reduction

⚫Reduce power per transition

Reduced voltage operation – voltage scaling
Capacitance minimization – device sizing
⚫Reduce number of transitions
Glitch elimination
Dynamic Power as a Function of Device Size
❑ Device sizing affects dynamic energy consumption
gain is largest for networks with large overall effective fan-outs (F
= CL/Cg,1)
❑ The optimal gate sizing factor 1.5
(f) for dynamic energy is
smaller than the one for F=1

normalized energy
performance, especially for F=2
1
large F’s
e.g., for F=20, F=5
fopt(energy) = 3.53 while
fopt(performance) = 4.47 0.5
F=10
❑ If energy is a concern avoid F=20
oversizing beyond the
0
optimal 1 2 3 4 5 6 7
f

From Nikolic, UCB

CSE477 L12&13 Low Power.31 Irwin&Vijay, PSU, 2003
 Logic Restructuring
❑ Logic restructuring: changing the topology of a logic
network to reduce transitions
AND: P0→1 = P0 x P1 = (1 - PAPB) x PAPB
3/16
0.5 A Y
0.5 (1-0.25)*0.25 = 3/16
A W 7/64 0.5 B 15/256
B X F
15/256 0.5
0.5 C C
0.5 D F
0.5 0.5 D Z
3/16

Chain implementation has a lower overall switching activity

than the tree implementation for random inputs
Ignores glitching effects

CSE477 L12&13 Low Power.32 Irwin&Vijay, PSU, 2003

 Input Ordering

(1-0.5x0.2)x(0.5x0.2)=0.09 (1-0.2x0.1)x(0.2x0.1)=0.0196
0.5 0.2
A B X
X
B C
F 0.1 A F
0.2 C
0.1 0.5

Which is better wrt transition probabilities?

Beneficial to postpone the introduction of signals with a

high transition rate (signals with signal probability
close to 0.5)

CSE477 L12&13 Low Power.33 Irwin&Vijay, PSU, 2003

 Glitching in Static CMOS Networks
❑ Gates have a nonzero propagation delay resulting in
spurious transitions or glitches (dynamic hazards)
glitch: node exhibits multiple transitions in a single cycle before
settling to the correct logic value

CSE477 L12&13 Low Power.34 Irwin&Vijay, PSU, 2003

 Balanced Delay Paths to Reduce Glitching
❑ Glitching is due to a mismatch in the path lengths in
the logic network; if all input signals of a gate change
simultaneously, no glitching occurs

0 0
0 F1 1 0 F1 1
0 F2 2
F3
0 F3 0
0 F2 1

So equalize the lengths of timing paths through logic

CSE477 L12&13 Low Power.35 Irwin&Vijay, PSU, 2003

 Power and Energy Design Space

Constant Variable
Throughput/Latency Throughput/Latency
Energy Design Time Non-active Modules Run Time
Logic design
DFS, DVS
Active Reduced Vdd
Clock Gating (Dynamic Freq,
(Dynamic) TSizing Voltage
Scaling)
Multi-Vdd
Sleep Transistors
Multi-VT
Leakage Multi-Vdd
Stack effect Variable VT
(Standby) Variable VT
Pin ordering
Input control

CSE477 L12&13 Low Power.36 Irwin&Vijay, PSU, 2003

 Dynamic Power as a Function of VDD
❑ Decreasing the VDD 5.5
decreases dynamic 5
4.5
energy consumption 4
(quadratically) 3.5
3

❑ But, increases gate 2.5

2
delay (decreases 1.5
performance) 1
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

VDD (V)
❑ Determine the critical path(s) at design time and use high
VDD for the transistors on those paths for speed. Use a
lower VDD on the other gates, especially those that drive
large capacitances (as this yields the largest energy
benefits).

CSE477 L12&13 Low Power.37 Irwin&Vijay, PSU, 2003

CSE477 L12&13 Low Power.38 Irwin&Vijay, PSU, 2003
 Multiple VDD Considerations
❑ Main ideas:
Use of different supply voltages within the same design
High VDD for critical parts (high performance needed)
Low VDD for non-critical parts (only low performance demands)

❑ At design phase:
Determine critical path(s) (see upper next slide)
High VDD for gates on those paths
Lower VDD on the other gates (in non-critical paths)
For low VDD: prefer gates that drive large capacitances (yields the
largest energy benefits)

❑ Usually two different VDD (but more are possible)

CSE477 L12&13 Low Power.39 Irwin&Vijay, PSU, 2003

CSE477 L12&13 Low Power.40 Irwin&Vijay, PSU, 2003
 Dual-Supply Inside a Logic Block
❑ Minimum energy consumption is achieved if all logic
paths are critical (have the same delay)
❑ Clustered voltage-scaling
Each path starts with VDDH and switches to VDDL (gray logic
gates) when delay slack is available
Level conversion is done in the flipflops at the end of the paths

Connected with VDDL

Connected with VDDH

CSE477 L12&13 Low Power.41 Irwin&Vijay, PSU, 2003

CSE477 L12&13 Low Power.42 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.43 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.44 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.45 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.46 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.47 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.48 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.49 Irwin&Vijay, PSU, 2003
 Sleep Transistors: Realization

Ring style sleep transistor implementation

Global VDD
VDD

VVDD1 VVDD2
domain domain

◼ Sleep transistors are placed around each VVDD island

Source: Kaijian Shi, Synopsys

50
CSE477 L12&13 Low Power.50 Irwin&Vijay, PSU, 2003
 Sleep Transistors: Realization cont’d

Grid style sleep transistor implementation

Global VDD
VDD
VVDD1 VVDD2

VVDD1 VVDD2

VVDD1 VVDD2

◼ VDD network cross chip; VVDD networks in each gating domain

◼ Sleep transistors are placed in grid connecting VDD and VVDDs
Source: Kaijian Shi, Synopsys

51
CSE477 L12&13 Low Power.51 Irwin&Vijay, PSU, 2003
 Sleep Transistors: Problems

VDD VDD

CMOS CMOS VDD - Vx

Gatter / Block Gatter / Block

high-Vth R I
SLEEP sleep transistor Vx = RI

Current I is not a
❑ Sleep transistor can be modeled as resistor R
leakage current!
❑ In active mode (cell is working) I is a discharging
➔ Current I through sleep transistor current of load
➔ Voltage Vx drop over resistor capacitances
➔ Output voltage reduced to VDD-Vx
Reduced Delay (of following blocks)
52
CSE477 L12&13 Low Power.52 Irwin&Vijay, PSU, 2003
CSE477 L12&13 Low Power.53 Irwin&Vijay, PSU, 2003
CMOS Energy & Power Equations

E = CL VDD2 P0→1 + tsc VDD Ipeak P0/1→1/0 + VDD Ileak

f = P * fclock

P = CL VDD2 f 0→1 + tscVDD Ipeak f + VDD Ileak

Dynamic Short-circuit Leakage

power power power

CSE477 L12&13 Low Power.54 Irwin&Vijay, PSU, 2003

Impact of CL on short circuit current
Ipeak versus CL
Psc as a function of rise/fall times
Summary: Short-Circuit Power
⚫ Short-circuit power is consumed by each transition
(increases with input transition time).
⚫ Reduction requires that gate output transition should not
be faster than the input transition (faster gates can
consume more short-circuit power).
⚫ Increasing the output load capacitance reduces short-
circuit power.
⚫ Scaling down of supply voltage with respect to threshold
voltages reduces short-circuit power.
Static (Leakage) Power

⚫Dynamic
Signal transitions
⚫Logic activity
⚫Glitches
Short-circuit
⚫Static
Leakage
Leakage Power
Leakage Power
Leakage Power as a function of VT
TSMC process leakages and VT
Ileakages versus temperatures
Leakage Current Components

⚫Subthreshold conduction, Isub

⚫Reverse bias pn junction conduction, ID
⚫Gate induced drain leakage, IGIDL due to
tunneling at the gate-drain overlap
⚫Drain source punchthrough, IPT due to
short channel and high drain-source
voltage
⚫Gate tunneling, IG through thin oxide
 Reducing Leakage Power
❑ Leakage power as a fraction of the total power
increases as clock frequency drops. Turning
supply off in unused parts can save power.
❑ For a gate it is a small fraction of the total power;
it can be significant for very large circuits.
❑ Scaling down features requires lowering the
threshold voltage, which increases leakage
power; roughly doubles with each shrinking.
❑ Multiple-threshold devices are used to reduce
leakage power.

CSE477 L12&13 Low Power.67 Irwin&Vijay, PSU, 2003