Chapter 3

UNIT-3

 Sources of Power Dissipation

 Static Power Dissipation
 Dynamic Power Dissipation
 Short-circuit Power Dissipation
 Short-circuit power dissipation occurs when both the nMOS and pMOS
networks are ON.
 This can arise due to slow rise and fall times of the inputs

Short-circuit Power Dissipation During Input

Transition
β β V 3
Psc =V dd I mean= (V dd −2 V t )3 τf = V dd3 (1−2 t ) τf
12 12 V dd
 Switching Power Dissipation
 As the input and output values keep on changing, capacitive loads at different
circuit points are charged and discharged, leading to power dissipation.
 This is known as switching power dissipation

μ ε ox W 3
Pshortcircuit =t sc ×V dd × I peak × f clock = ×(V dd −V th ) ×t sc × f clock
12 LD

 Glitching Power Dissipation

 Due to a finite delay of the logic gates, there are spurious transitions at
different nodes in the circuit.
 Apart from the abnormal behavior of the circuits, these transitions also result
in power dissipation known as glitching power dissipation.
 Leakage Power Dissipation

 I1 is the reverse-bias p–n junction diode leakage current;

 I2 is the reverse-biased p–n junction current due to tunneling of
electrons from the valence bond of the p region to the conduction bond
of the n region;
 I3 is the subthreshold leakage current between the source and the drain
when the gate voltage is less than the threshold voltage Vt;
 I4 is the oxide-tunneling current due to a reduction in the oxide
thickness;
 I5 is gate current due to hot-carrier injection of elections;
 I6 is the GIDL current due to a high field effect in the drain junction;
 I7 is the channel punch-through current due to the close proximity of
the drain and the source in short-channel devices.

 Static power dissipation occurs due to various leakage mechanisms.

 Reverse-bias p–n junction diode leakage current
 Reverse-biased p–n junction current due to the tunneling of elections
from the valence bond of the p region to the conduction bond of the n
region, known as band-to-band-tunneling current
 Subthreshold leakage current between source and drain when the gate
voltage is less than the threshold voltage Vt. Various mechanisms
which affect the subthreshold leakage current are:
 1. Drain-induced barrier lowering (DIBL)
2. Body effect
3. Narrow-width effect
4. Effect of channel length and Vth roll-off
5. Effect of temperature
 Oxide-tunneling current due to a reduction in the oxide thickness
 Gate current due to a hot-carrier injection of elections
 Gate-induced drain-leakage (GIDL) current due to high field effect in
the drain junction
 Channel punch-through current due to close proximity of the drain and
the source in short-channel devices

 Supply Voltage Scaling for Low Power

 Static Voltage Scaling (SVS) In this case, fixed supply voltages are applied to
one
 or more subsystems or blocks.
 Multilevel Voltage Scaling (MVS) This is an extension of the SVS, where two
or few fixed discrete voltages are applied to different blocks or subsystems.
 Dynamic Voltage and Frequency Scaling (DVFS) This is an extension of the
MVS, where a large number of discrete voltages are applied in response to the
changing workload conditions of the subsystems.
 Adaptive Voltage Scaling (AVS) This is an extension of the DVFS, where a
closeloop control system continuously monitors the workload and adjusts the
supply voltage.

 Device Features Size Scaling

o S-Scaling Factor
 Constant-Field Scaling
Constant-field scaling of the device dimensions, voltages, and doping densities
Quantity Before Scaling After Scaling
Channel length L L’=L/S
Channel width W W’=W/S
Gate oxide thickness tox tox’= tox/S
Junction depth xj xj’= xj/S
Power supply voltage Vdd Vdd’= Vdd/S
Threshold voltage VT0 VT0’= VT0/S
Doping Densities NA NA’= NA /S
ND ND’= ND /S
Effects of constant-field scaling on the key device parameters
Quality Before Scaling After Scaling
Gate Capacitance Cg Cg’= Cg/S
Drain Current ID ID’= ID/S
Power Dissipation P P’=P/S2
Power Density P/Area P’/Area’
Delay td td’= td/S
Energy E=P. td E’=(1/S3).E

 Constant-Voltage Scaling

Constant-voltage scaling of the device dimensions, voltages, and doping densities

 Quantity Before Scaling After Scaling
Channel length L L’=L/S
Channel width W W’=W/S
Gate oxide thickness tox tox’= tox/S
Junction depth xj xj’= xj/S
Power supply voltage Vdd Vdd’= Vdd
Threshold voltage Vto Vto’= Vto
Doping Densities NA NA’= NA .S2
ND ND’= ND .S2
Effects of constant-voltage scaling on the key device parameters
Quality Before Scaling After Scaling
Gate Capacitance Cg Cg’= Cg/S
Drain Current ID ID’= ID/S
Power Dissipation P P’=P.S
Power Density P/Area P’/Area’ =S3P/Area
Delay td td’= td/S2

 Short-Channel Effects
Short-channel effects arise when channel length is of the same order of
magnitude as depletion region thickness of the source and drain
junctions or when the length is approximately equal to the source and
drain junction depths.

 Architecture-level Approaches
o Architectural-level refers to register-transfer-level (RTL), where a circuit is
represented in terms of building blocks such as adders, multipliers, read-only
memories (ROMs), register files, etc..
o High-level synthesis technique transforms a behavioral-level specification to
an RTL-level realization.
o It is envisaged that low-power synthesis technique on the architectural level
can have a greater impact than that of gate-level approaches.
o Possible architectural approaches are: parallelism, pipelining, and power
management.
 Parallelism for Low Power
Impact of parallelism on area, power, and throughput
Parameter Without Vdd Scaling With Vdd Scaling
Area 2.2X 2.2X
Power 2.2X 0.227X
Throughput 2X 1X

P par ≈ 0.277 P ref

 Multi-Core for Low Power
Power in multi-core architecture
Number of Clock in MHz Core Supply Total Power
Cores Voltage
1 200 5 15.0
2 100 3.6 8.94
4 50 2.7 5.20
 8 25 2.1 4.5

 Pipelining for Low Power

Impact of pipelining on area, power, and throughput

Parameter Without Vdd Scaling With Vdd Scaling

Area 1.15X 1.15X
Power 2.0X 0.28X
Throughput 2X 1X
P pipe ≈ 0.28 Pref

 Combining Parallelism with Pipelining

P parpipe ≈ 0.1125 Pref
Impact of parallelism and pipelining on area, power, and throughput
Parameter Without Vdd Scaling With Vdd Scaling
Area 2.5X 2.5X
Power 5.0X 0.1125X
Throughput 4X 1X

 Voltage Scaling Using High-Level Transformations

 For automated synthesis of digital systems, high-level transformations such as
dead code elimination, common sub-expression elimination, constant folding,
in-line expansion and loop unrolling are typically used to optimize the design
parameters such as the area and throughput.
 These high-level transformations can also be used to reduce the power
consumption either by reducing the supply voltage or the switched
capacitance.

 Multilevel Voltage Scaling

 A number of studies have shown that the use of multiple supply voltages results in
the reduction of dynamic power from less than 10 % to about 50 %, with an
average of about 40 %.
 It is possible to use more than two, say three or four, supply voltages.
 However, the benefit of using multiple Vdd saturates quickly.
 Extending the approach to more than two supply voltages yields only a small
incremental benefit.
 The major gain is obtained by moving from a single Vdd to a dual Vdd.
 It has been found that in a dual-Vdd/single-Vt system, the optimal lower Vdd is
about 60–70 % of the original Vdd.
 The optimal supply voltage depends on the threshold voltage Vt of the MOS
transistors as well.
 Challenges
 Voltage Scaling Interfaces
 Converter Placement
 Floor Planning, Routing, and Placement
 Static Timing Analysis
 Power-Up and Power-Down Sequencing
 Clock Distribution
 Low-Voltage Swing
 Dynamic Voltage and Frequency Scaling
 DVFS has emerged as a very effective technique to reduce CPU energy.
 The technique is based on the observation that for most of the real-life
applications, the workload of a processor varies significantly with time and the
workload is bursty in nature for most of the applications.
 The energy drawn for the power supply, which is the integration of power over
time, can be significantly reduced.
 This is particularly important for battery-powered portable systems.

 Adaptive Voltage Scaling

A better alternative that can overcome this limitation is the adaptive voltage
scaling (AVS) where a close-loop feedback system is implemented between
the voltage scaling power supply and delay-sensing performance monitor at
execution time.