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1) Devices and Modeling Part1

This document provides an overview of the ENCS333 Digital Integrated Circuits course taught by Dr. Khader Mohammad. It includes the course schedule, topics to be covered, assessment details, required readings, and office hours. The course will cover topics such as semiconductor materials, CMOS transistor devices, logic design, sequential logic gates, layout, modeling, and SPICE simulation. Students will be assessed through short exams, a midterm exam, projects, assignments, and a final exam.

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yousef Anini
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128 views31 pages

1) Devices and Modeling Part1

This document provides an overview of the ENCS333 Digital Integrated Circuits course taught by Dr. Khader Mohammad. It includes the course schedule, topics to be covered, assessment details, required readings, and office hours. The course will cover topics such as semiconductor materials, CMOS transistor devices, logic design, sequential logic gates, layout, modeling, and SPICE simulation. Students will be assessed through short exams, a midterm exam, projects, assignments, and a final exam.

Uploaded by

yousef Anini
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DEPARTMENT OF COMPUTER SYSTEM

ENGINEERING
Digital Integrated Circuits - ENCS333

Dr. Khader Mohammad


Lecture #1
Introduction
Integrated-Circuit Devices and Modeling
Schedule and Office Hours
Day 8 ½ 9 ½ 10 ½ 11 ½ 12 ½ 13 ½ 14 ½ 15 ½ 16 ½

Saturday
Sunday
Monday O. H. O. H. ENCS313/Masri303
Tuesday ENCS333/Masri108 O. H. ENCS333/Masri108 O. H.
Wednesday O. H. ENCS313/Masri303
Thursday ENCS333/Masri108 O. H. ENCS333/Masri108
Friday

2
Digital Integrated Circuits
Course topics and Schedule

Subject

1 Introduction to Digital Integrated Circuits Design


2 Semiconductor material: pn-junction, NMOS, PMOS
3 CMOS Transistor Devices and Logic Design
4 The CMOS inverter
5 Combinational logic structures
6 Sequential logic gates; Latches and Flip-Flops
7 Layout of an Inverter and basic gates
8 Parasitic Capacitance Estimation
9 Device modeling parameterization from I-V curves.
Short Test
10 Arithmetic building blocks
11 Interconnect: R, L and C - Wire modeling
12 Timing
Power dissipation;
13 SPICE Simulation Techniques ( Project )
14 Memories and array structures
Midterm
15 Clock Distribution
16 Supply and Threshold Voltage Scaling
17 Reliability and IC qualification process
18 Advanced Voltage Scaling Techniques
19 Power Reduction Through Switching Activity Reduction
20 CAD tools and algorithms 3
21 Final & Project discussion
Grading

Assessment Policy
Assessment Type Expected Due Date Weight
Short Exam/QZes TBD 15%
Midterm Exam TBD 30%
Projects/Assignments TBD 20%

Final Exam TBD 35%

1. Handouts /lectures notes


Required Reading 2. Rabaey, Jan, Anantha Chandrakasan, and Bora Nikolic. Digital
Integrated Circuits: A Design Perspective. 2nd ed. Upper Saddle
River, NJ: Prentice Hall, 2002. ISBN: 0130909963.
3. Analysis and design of Digital Integrated Circuits: David Hodges
et. al.
4. Principles of CMOS VLSI Design by: N. Weste and K. Eshraghian

4
Design Abstraction Levels
SYSTEM/ARCHITECTURE

MODULE
+

GATE

TRANSISTOR
Vin Vout

DEVICE
G
S D
n+ n+

6
Intel 8486
Technology Evolution: Intel CPU Chips

Intel 4004 (‘71)


Intel 8080 Intel 8085

Lec 1 8
Intel 8286 Intel 8486
Courtesy Intel
80x86 Evolution
Base SoC Handheld Tablet

Micro Server

SOCChassis Digital Home Embedded


Technology Scaling: Moore’s
Law

10
Courtesy Intel
An estimate of the maximum number of transistors per chip over time.
Scaling
• Technology shrinks by 0.7/generation
• With every generation can integrate 2x more
• functions per chip; chip cost does not increase significantly
• Cost of a function decreases by 2x
• How to design chips with more and more functions?
• Design engineering population does not double every two
years…
• Need to understand different levels of abstraction

12
13
ISSCC2016-01_Visuals.pdf
14
15
3D Gate

16
CMOS

17
The MOS transistor
p-ch
• Symbols:
n-ch

4T (Bulk to VCC/VSS) 3T

• Physical structure:
Gate Gate
Source Drain Source Drain

n+ n+ p+ p+
channel channel
p-well n-well

p-substrate p-substrate
n-ch MOS p-ch MOS
The MOS transistor -
the different modes of operation
Vgs > Vt ; Vds=0V

Gate
Source Drain 0V

n+ n+

p-sub

n-type channel depletion layer


Substrate

n-ch MOS
Process technology

20
Capacitance of the MOS Transistor

Cp Cgd Cdb
diodes
Ca
Overlap cap

Parameters:
Diffusions area (diodes)
Diffusions perimeter (diodes)
Gate W (overlap cap)
Gate W*L (gate cap) Cgb Cgs Csb
Doping profiles
Note: all capacitors have voltage
dependence (not simple caps)
P1262 Line Capacitance Calculation
W S W

Cll td3 CA2 Cll Cs

Cf Cf
CA1 td CA1

Pizza model Sandwich model

Ctotal = Ca1 + Ca2 + 2*Cll + 2*Cf + 2*Cs


Layout
• Transistor defined as poly over diffusion
PMOS NMOS

nwell N diffusion
P diffusion

poly

poly
Nwell tap substrate tap S D
G
Layout vs. Schematic

24
Microwind
Sequential elements
d o
d o d o

clk clk
clk

Master Slave

Latch is open

Latch is closed

clk

o
Timing

A 20 A
B 30
20ps
G
30
O G
30
C 30 H 30ps
D 20 O

• Dynamic Timing B must be set high


• C and D must be set low
• Setup/hold time
Power of a Std. Cell
• Dynamic Power
• Internal Dynamic Power
• output Internal Power (q pin)
• Measure the power dissipated in the cell including
the power dissipated in the output parasitic pin Vcc
capacitance (but not the external load) &
correspondingly set the output capacitance
attribute for the output pin to 0 in the synopsys Ivcc
library.
• Internal Power (output pin)  in te
xt
out
[min{abs(Iavg_vcc – Ivcc_leakage), abs(Iavg_vss –
vss_leakage)}] * Vcc * Tmeas_per.

/* *** power tables are in energy units of 'pJ' *** */


Cparasitic Cload
Example (not real data)
cell (“mycellname") {
pin ("o") {
Ivss
direction : output ;
internal_power() { Vss Vss Vss_ext
related_pin : "ck d si tcka tckb" ;
rise_power (internalPowerTable_5X5_lv0sc00x0) {
index_1 ("0.0033500, 0.0167500, 0.0335000, 0.0670000, 0.2144000") ;
index_2 ("16.0200000, 36.0000000, 96.0000000, 240.0000000,
600.0000000") ;
values (\
"0.0078159, 0.0078639, 0.0082802, 0.0097401, 0.0134899",\
"0.0079230, 0.0079441, 0.0082848, 0.0095784, 0.0130071",\
"0.0079615, 0.0079867, 0.0083186, 0.0095566, 0.0128498",\
"0.0079833, 0.0080138, 0.0083476, 0.0095619, 0.0127515",\
"0.0079913, 0.0080275, 0.0083725, 0.0095782, 0.0126891"\
28
Power delivery design methodology (cont.)

 C4 bump pattern:
296u: provide an 86um trace width bussing on surface layer

270u
provide a 76um trace width
bussing on 2F layer

Surface 1FC 1BC 2B Base


2F

 75% via connection to die


bumps from 2F.
 25% via connection to die
bumps from 1FC or PTH.
 ~ 3 via connection to 2 PTHs
P1262
Challenges

 Ultra-high speed • Time-to-Market


design
• Millions of Gates
 Interconnect
• High-Level Abstraction
 Noise, Crosstalk
 Reliability,
• Reuse & IP: Portability
Manufacturability • Predictability
 Power Dissipation • etc.
 Clock distribution.

30
Challenges
Frequency/speed Moore’s Law - Logic Density/Area

Power

31
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