STA - Static Timing Analysis

STA Lecturer: Gil Rahav Semester B , EE Dept. BGU. Freescale Semiconductors Israel

Static Verification Flow

RTL Domain

Functional Simulation
Synthesis

Testbench

Equivalence Checking

Static Timing Analysis

Scan Place Clock Tree Route

Sign Off

Gate-level Domain

Equivalence Checking

What is Static Verification?

Static verification:
Verifies timing and functionality
STA and equivalence checking

Is exhaustive Uses formal, mathematical techniques instead of vectors Does not use dynamic logic simulation

Static Timing Analysis Flow

Read required files Every Corner and Mode Validate inputs Ready to perform STA on a gate-level synchronous design using SDF

Fix data

yes

Errors/ Warnings? no

Analyze Reports PrimeTime

Next step in design flow

Required Input Files

Delay Calculator

SDF SDF

Synthesis Synthesis technology technology library library

Design Design constraints in Tcl constraints in Tcl

Gate-level Gate-level netlist netlist

Timing Timing model model library library

Read required files

yes Fix data

Errors/ Warnings? no

continue...

Components of a Master Run Script

Each corner and mode Read Constrain

Validate Inputs Generate Reports

Quit

Read and Constrain

# Comment scripts # Comment scripts # Include all libraries - technology and IP model libraries # Include all libraries - technology and IP model libraries set link_path * my_tech_lib.db memory_lib.db set link_path * my_tech_lib.db memory_lib.db # Read all gate-level design files # Read all gate-level design files read_verilog my_full_chip.v read_verilog my_full_chip.v # Read libraries and link the design # Read libraries and link the design link_design MY_FULL_CHIP link_design MY_FULL_CHIP

Read Constrain

# Set up bc_wc analysis with 2 SDF. Wait for checks later # Set up bc_wc analysis with 2 SDF. Wait for checks later read_sdf analysis_type bc_wc max_type sdf_max min_type sdf_min read_sdf analysis_type bc_wc max_type sdf_max min_type sdf_min # Apply chip-level constraints for pre or post layout analysis # Apply chip-level constraints for pre or post layout analysis source MY_FULL_CHIP_CONST.tcl source MY_FULL_CHIP_CONST.tcl

Recall: Components of a Master Run Script

Each corner and mode Read Constrain

Validate Inputs Generate Reports

Quit

Validate Complete and Correct Constraints

report_design

Analysis Type

report_clock

Clocks

report_annotated_delay report_annotated_check

Complete SDF

check_timing

Complete Constraints

Three Types of Analysis

single

Read one SDF delay for setup OR hold analysis

bc_wc

Read two SDF delays for setup and hold analysis

on_chip_variation

Min and Max SDF represent a small variation across a die

Ready to Analyze STA Reports

Each corner and mode Read Constrain

Validate Inputs Generate Reports

Quit

Report All Violations

report_constraint all_violators
max_delay/setup ('Clk1' group) max_delay/setup ('Clk1' group) Endpoint Slack Endpoint Slack --------------------------------------------------------------------------------------------------------------------------------BB -0.50 (VIOLATED) -0.50 (VIOLATED) min_delay/hold ('Clk1' group) min_delay/hold ('Clk1' group) Endpoint Slack Endpoint Slack --------------------------------------------------------------------------------------------------------------------------------FF1/D0 -0.67 (VIOLATED) FF1/D0 -0.67 (VIOLATED) sequential_clock_pulse_width sequential_clock_pulse_width Required Actual Required Actual Pin pulse width pulse width Slack Pin pulse width pulse width Slack --------------------------------------------------------------------------------------------------------------------------------FF2/clk (high) 0.90 0.85 -0.05 (VIOLATED) FF2/clk (high) 0.90 0.85 -0.05 (VIOLATED)

The Number of Violations

report_analysis_coverage

Type of Check Total Met Violated Untested Type of Check Total Met Violated Untested ------------------------------------------------------------------------------------------------------------------------------------------------setup 6724 2366 (( 35%) 00 (( 0%) 4358 (( 65%) setup 6724 2366 35%) 0%) 4358 65%) hold 6732 2366 (( 35%) 00 (( 0%) 4366 (( 65%) hold 6732 2366 35%) 0%) 4366 65%) recovery 362 302 (( 83%) 00 (( 0%) 60 (( 17%) recovery 362 302 83%) 0%) 60 17%) removal 354 302 (( 85%) 00 (( 0%) 52 (( 15%) removal 354 302 85%) 0%) 52 15%) min_pulse_width 4672 4310 (( 92%) 00 (( 0%) 362 (( 8%) min_pulse_width 4672 4310 92%) 0%) 362 8%) clock_gating_setup 65 65 (100%) 00 (( 0%) 00 (( 0%) clock_gating_setup 65 65 (100%) 0%) 0%) clock_gating_hold 65 65 (100%) 00 (( 0%) 00 (( 0%) clock_gating_hold 65 65 (100%) 0%) 0%) out_setup 138 138 (100%) 00 (( 0%) 00 (( 0%) out_setup 138 138 (100%) 0%) 0%) out_hold 138 74 (( 54%) 64 (( 46%) 00 (( 0%) out_hold 138 74 54%) 64 46%) 0%) ------------------------------------------------------------------------------------------------------------------------------------------------------------All Checks 19250 9988 (( 52%) 64 (( 0%) 9198 (( 48%) All Checks 19250 9988 52%) 64 0%) 9198 48%)

More Details: Path Timing Reports

pt_shell> report_timing Default: Returns the worst path for max analysis for: Each clock Recovery checks Clock gating checks Customize with MANY different switches: Setup versus hold reports Increase the significant digits Focus on specific paths Increase the # of generated reports Include net fanout Expand the calculated clock network delay

Clock Network Reports

report_clock_timing type skew

For each clock, report REAL skew

FF3
D

FF1
D

Max Dela ys

22 ns

FF4
U4

0.

FF2
U2 D U5

U3

7 .7

ns s

0.21ns

CLK

U6

0.

n 82

Bottleneck Analysis
Identify cells involved in multiple violations. Use the results to determine cells to buffer or upsize. report_bottleneck report_bottleneck
This cell is involved in 100 violations!

U2/U104

Specify Timing Assertions (1)

Example:
Set up the basic timing assertions for the design. Start with the clock information.
pt_shell> pt_shell> pt_shell> pt_shell> pt_shell> pt_shell> create_clock -name CLK -period 30 [get_port CLOCK] set_clock_uncertainty 0.5 [all_clocks] set_clock_latency -min 3.5 [get_clocks CLK] set_clock_latency -max 5.5 [get_clocks CLK] set_clock_transition -min 0.25 [get_clocks CLK] set_clock_transition -max 0.3 [get_clocks CLK]

For post layout clock tree: set_propagated_clock <clock_object_list> or set timing_all_clocks_propagated true

Specify Timing Assertions (2)

Reference clock waveform Reference clock waveform with uncertainty Reference clock waveform with latency Reference clock waveform with transition Reference clock waveform with uncertainty, latency, and transition

15

30

15

30

5.5

20.5

35.5

15

30

5.5

20.5

35.5

Advanced Timing Analysis

Analysis Modes Data to Data Checks Case Analysis Multiple Clocks per Register Minimum Pulse Width Checks Derived Clocks Clock Gating Checks Netlist Editing Report_clock_timing Clock Reconvergence Pessimism Worst-Arrival Slew Propagation Debugging Delay Calculation

Back-Annotation - Parasitics
Reduced and Distributed Parasitic Files
Reduced format annotates an RC pi model, and computes the effective capacitance.
r ive Dr
C1

s oad L
R C2

Pi model

Effective Capacitance

Distributed format enables PrimeTime to annotate each physical segment of the routed netlist (most accurate form of RC backannotation)
U2 U1
R1 C1 C2 R2 C3 R3 C4

U3

...

PrimeTime Timing Models Support

PrimeTime offers the following timing models to address STA needs for IP, large hierarchical designs, and custom design:

Quick Timing Model (QTM) Extracted Timing Model (ETM) Interface Logic Model (ILM) Stamp Model

Timing Model Usage Scenario in PrimeTime

Usage Scenario
Top-Down Design IP Reuse Interface to non-STA and 3rd party tools Synthesis Tasks Chip-Level STA Memory and Datapath

Appropriate Model
Quick Timing Models ETMs ETMs ILMs / ETMs ILMs Stamp Models

Quick Timing Models (QTMs)

Provide means to quickly and easily create a timing model of an unfinished block for performing timing analysis Should later be replaced with gate-level netlists or equivalent models Created with PrimeTime commands - no compiling needed! Can contain: Port specs for the block Setup and hold constraints for inputs Clock-to-output delays Input-to-output delays Benefits accurate specs generated with a lot less effort apply chip level timing constraints and time the whole design discover violators up front

Quick Timing Models - What are they?

IVA FD1

OPERATION[1:0]

9
NR3

Q CP

ND3

OUTPUT_VALUE[1:12]

IVA

Constraint (setup) FD1 ND3

CLOCK

Delay IVA
2

Q CP

6
NR3

OVERFLOW

VALUE[1:12]

QTM is a set of interactive PrimeTime commands - not a language Like all PrimeTime commands, QTM can be saved in a script QTM model can be saved in db or Stamp format

Extracted Timing Models (ETM)

Enable IP Reuse and interchange of timing models between EDA tools Compact black-box timing models

contain timing arcs between external pins Internal pins only for generated/internal clocks models written out in Stamp, .lib ,or db formats context independent Exceptions and latches supported Provide huge performance improvements

ETM Design
A X A B B CLK Y CLK Y X

Interface Logic Models (ILM)

Enable Hierarchical STA Reduce memory and CPU usage for chip-level analysis Offer big netlist reduction if block IOs are registered Back-annotation and constraint files for interface logic are written out along with netlist Benefits: High accuracy because interface logic is not abstracted Fast model generation time Context independent Can change load, drive, operating conditions, parasitics, SDF, constraints without re-generating the model

Design
A X A

ILM
X

B CLK

B CLK

Interface Logic Models (ILM)

ILMs can be used in SDF and parasitics based flows
pt_shell> write_ilm_[sdf/parasitics] <output_file>

Support for Hierarchical SI analysis

pt_shell> create_ilm include {xtalk_pins}

Support for Model Validation

pt_shell> compare_interface_timing <ref_file> <cmp_file> -slack 0.2 -include slack

Stamp Modeling
Generally created for transistor-level designs, where there is no gate-level netlist. Stamp timing models are usually created by core or technology vendors, as a compiled db. Capabilities include the ability to model: pin-to-pin timing arcs setup and hold data pin capacitance and drive mode information tri-state outputs internally generated clocks Stamp models co-exist with the Library Compiler .lib models

Chip-Level Verification using Models

Top-Level
Block1 (ILM) Block3 (ETM)

Block2 (top netlist) Block4 (ILM) Block5 (ETM)

Using ILMs and ETMs to address capacity and timing issues in multimillion gate design

Does Your Design Meet Timing?

pt_shell> report_analysis_coverage
Type of Check Total Met Violated Untested Type of Check Total Met Violated Untested ------------------------------------------------------------------------------------------------------------------------------------------------------------setup 6724 5366 (( 80%) 00 (( 0%) 1358 (( 20%) setup 6724 5366 80%) 0%) 1358 20%) hold 6732 5366 (( 80%) 00 (( 0%) 1366 (( 20%) hold 6732 5366 80%) 0%) 1366 20%) recovery 362 302 (( 83%) 00 (( 0%) 60 (( 17%) recovery 362 302 83%) 0%) 60 17%) removal 354 302 (( 85%) 00 (( 0%) 52 (( 15%) removal 354 302 85%) 0%) 52 15%) min_pulse_width 4672 4310 (( 92%) 00 (( 0%) 362 (( 8%) min_pulse_width 4672 4310 92%) 0%) 362 8%) clock_gating_setup 65 65 (100%) 00 (( 0%) 00 (( 0%) clock_gating_setup 65 65 (100%) 0%) 0%) clock_gating_hold 65 65 (100%) 00 (( 0%) 00 (( 0%) clock_gating_hold 65 65 (100%) 0%) 0%) out_setup 138 138 (100%) 00 (( 0%) 00 (( 0%) out_setup 138 138 (100%) 0%) 0%) out_hold 138 74 (( 54%) 64 (( 46%) 00 (( 0%) out_hold 138 74 54%) 64 46%) 0%) ------------------------------------------------------------------------------------------------------------------------------------------------------------All Checks 19250 15988 (( 84%) 64 (( 0%) 3198 (( 16%) All Checks 19250 15988 84%) 64 0%) 3198 16%)

Are You Finished?

When PrimeTime was run it revealed 64 violations in the design.

What else is there?

Are the violations real? Can you explain warnings in the log files? What are your suggestions for resolution? You have a special situation what are the issues?

Timing Verification of Synchronous Designs

All registers must reliably capture data at the desired clock edges.

FF1

FF2

F1
clk

F1
clk

Clk
0 2 4

Static Timing Verification of FF2: Setup

FF1

FF2 U2 U3

F1
0ns 4ns

CLK

F1
CLK

Clk

FF1/clk FF2/D

1.1ns

5.1ns

Where does this 1.1ns shift come from? Why is the shift different here?

Setup

FF2/clk
1ns 5ns

PrimeTime Terminology
FF1

Data Arrival
FF2 U2 U3

F1
CLK

F1
CLK

Clk

Data Required
Data Arrival Time FF1/clk FF2/D
Setup
1.1ns 5.1ns

Slack is the difference between data arrival and data required. Data Required Time

FF2/clk
1ns 5ns

Four Sections in a Timing Report

report_timing
Header
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk) Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk) Path Group: Clk Path Type: max Point Incr Path ----------------------------------------------------------clock Clk (rise edge) 0.00 0.00 clock network delay (propagated) 1.10 * 1.10 FF1/CLK (fdef1a15) 0.00 1.10 r FF1/Q (fdef1a15) 0.50 * 1.60 r U2/Y (buf1a27) 0.11 * 1.71 r U3/Y (buf1a27) 0.11 * 1.82 r FF2/D (fdef1a15) 0.05 * 1.87 r data arrival time 1.87 clock Clk (rise edge) 4.00 4.00 clock network delay (propagated) 1.00 * 5.00 FF2/CLK (fdef1a15) 5.00 r library setup time -0.21 * 4.79 data required time 4.79 -----------------------------------------------------------data required time 4.79 data arrival time -1.87 -----------------------------------------------------------slack (MET) 2.92

Data arrival

Data required

Slack

The Header

Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)

Header

Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk) Path Group: Clk Path Type: max

Capture clock Report is for setup

FF1

FF2 U2 U3

F1
CLK

F1
CLK

Clk

Data Arrival Section

Point Incr Path ----------------------------------------------------------clock Clk (rise edge) 0.00 0.00 clock network delay (propagated) 1.10 * 1.10 FF1/CLK (fdef1a15) 0.00 1.10 r FF1/Q (fdef1a15) 0.50 * 1.60 r U2/Y (buf1a27) 0.11 * 1.71 r Library reference U3/Y (buf1a27) 0.11 * 1.82 r names FF2/D (fdef1a15) 0.05 * 1.87 r data arrival time 1.87

Calculated latency

SDF

Data arrival

.11ns .50ns 1.1ns .11ns .05ns

F1
0 2 4

CLK
FF1

U2 r

U3 r

F1
CLK
FF2

Clk

Data Required Section

Point Incr Path ----------------------------------------------------------clock Clk (rise edge) 0.00 0.00 clock network delay (propagated) 1.10 * 1.10 FF1/CLK (fdef1a15) 0.00 1.10 r FF1/Q (fdef1a15) 0.50 * 1.60 r U2/Y (buf1a27) 0.11 * 1.71 r U3/Y (buf1a27) 0.11 * 1.82 r FF2/D (fdef1a15) 0.05 * 1.87 r data arrival time 1.87 clock Clk (rise edge) clock network delay (propagated) FF2/CLK (fdef1a15) SDF library setup time data required time 4.00 1.00 * -0.21 * 4.00 5.00 5.00 r 4.79 4.79

Data required

FF1

FF2 U2 U3 r

F1
0 2 4

0.21ns

1.0ns

CLK

F1
CLK

Clk

Summary - Slack
report_timing
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk) Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk) Path Group: Clk Path Type: max Point Incr Path ----------------------------------------------------------clock Clk (rise edge) 0.00 0.00 clock network delay (propagated) 1.10 * 1.10 FF1/CLK (fdef1a15) 0.00 1.10 r FF1/Q (fdef1a15) 0.50 * 1.60 r U2/Y (buf1a27) 0.11 * 1.71 r U3/Y (buf1a27) 0.11 * 1.82 r FF2/D (fdef1a15) 0.05 * 1.87 r data arrival time 1.87 clock Clk (rise edge) 4.00 4.00 clock network delay (propagated) 1.00 * 5.00 FF2/CLK (fdef1a15) 5.00 r library setup time -0.21 * 4.79 data required time 4.79 -----------------------------------------------------------data required time 4.79 data arrival time -1.87 -----------------------------------------------------------slack (MET) 2.92

Slack

Static Timing Verification of FF2: Hold

FF1 FF2 U2 U3

F1
0ns 4ns

CLK

F1
CLK

Clk

FF1/clk FF2/D

1.1ns

5.1ns

STABLE Hold

FF2/clk
1ns 5ns

Which clock edge causes the data to change?

Which Edges are Used in a Timing Report?

FF1 FF2 U2 U3

F1
0ns 4ns

CLK

F1
CLK

Clk

FF1/clk FF2/D

1.1ns

5.1ns

Hold

Setup

FF2/clk
1ns 5ns

PrimeTime Terminology
FF1

Data Arrival
FF2 U2 U3

F1
0ns 4ns

CLK

F1
CLK

Clk

Data Required
Data Arrival

FF1/clk FF2/D Data Required FF2/clk

1.1ns

5.1ns

Slack is the difference between data arrival and required.

Hold

1ns

5ns

Example Hold Timing Report

Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk) Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk) Path Group: Clk Path Type: min Point Incr Path ---------------------------------------------------------clock Clk (rise edge) 0.00 0.00 clock network delay (propagated) 1.10 * 1.10 FF1/CLK (fdef1a15) 0.00 1.10 r FF1/Q (fdef1a15) 0.40 * 1.50 f U2/Y (buf1a27) 0.05 * 1.55 f U3/Y (buf1a27) 0.05 * 1.60 f FF2/D (fdef1a15) 0.01 * 1.61 f data arrival time 1.61 clock Clk (rise edge) 0.00 0.00 clock network delay (propagated) 1.00 * 1.00 FF2/CLK (fdef1a15) 1.00 r library hold time 0.10 * 1.10 data required time 1.10 ---------------------------------------------------------data required time 1.10 data arrival time -1.61 ---------------------------------------------------------slack (MET) 0.51

Negedge Triggered Registers: Setup Time

FF1

FF2

F1
0 2 4

clk

F1
clk

Clk

FF1/clk
2.9ns

FF2/D
Setup

FF2/clk
1ns 5ns

What About Hold Time?

FF1

Q
0 2 4

FF2

F1
clk

F1
clk

Clk

FF1/clk FF2/D

2.9ns

6.9ns

STABLE Hold

FF2/clk
1ns 5ns

Which Edges are Used in a Timing Report?

FF1 FF2

F1
clk

F1
clk

Clk

FF1/clk FF2/D

2.9ns

Hold

Setup

FF2/clk
1ns 5ns

Timing Report for Hold

Startpoint: FF1 (falling edge-triggered flip-flop clocked by Clk) Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk) Path Group: Clk Path Type: min Point Incr Path ---------------------------------------------------------clock Clk (fall edge) 2.00 2.00 clock network delay (propagated) 0.90 * 2.90 FF1/CLK (fdmf1a15) 0.00 2.90 f FF1/Q (fdef1a15) 0.40 * 3.30 f U2/Y (buf1a27) 0.05 * 3.35 f U3/Y (buf1a27) 0.05 * 3.40 f FF2/D (fdef1a15) 0.01 * 3.41 f data arrival time 3.41 clock Clk (rise edge) 0.00 0.00 clock network delay (propagated) 1.00 * 1.00 FF2/CLK (fdef1a15) 1.00 r library hold time 0.10 * 1.10 data required time 1.10 ---------------------------------------------------------data required time 1.10 data arrival time -3.41 ---------------------------------------------------------slack (MET) 2.31

Setup Definition - Summary

Data must become valid and stable at least one setup time before being captured by flip-flop.
EQN 1 Slacksetup = Data Required Time Data Arrival Time 0 EQN 2 Slacksetup = (Tcapture t setup ) (Tlaunch + t prop ) 0
Clk Spec Library Clk Spec Cell + Net

FF1/CLK FF2/CLK FF2/D

VALID Data Arrival Time Data Required Time Slack VALID

Hold Definition - Summary

Data remains stable for a minimum time as required by capture flip-flop. (Hold Check)
EQN 1 Slackhold = Data Arrival Time Data Required Time EQN 2 Slackhold = ( Tlaunch + t prop ) - ( Tcapture + t hold )
Clk Spec Cell + Net Clk Spec

Library

FF1/CLK FF2/CLK FF2/D

VALID Data Arrival Time Data Required Time Slack VALID

Timing Models
Timing models are cells with many timing arcs:
Flip-flop with setup and hold timing checks Delay cell included along the data arrival time

FF1

A Delay = 1.0ns B Setup or Hold

C
D

FF2

F1
clk

F1
clk

Clk

clk

RAM

Example Timing Report

Point Incr Path ---------------------------------------------------------------------------clock SYS_CLK (rise edge) 0.000 0.000 clock network delay (propagated) 2.713 * 2.713 I_ORCA_TOP/I_PCI_WRITE_FIFO/count_int_reg[0]1/CP (sdcrq1) 0.000 2.713 r I_ORCA_TOP/I_PCI_WRITE_FIFO/count_int_reg[0]1/Q (sdcrq1) 0.678 * 3.390 r I_ORCA_TOP/I_PCI_WRITE_FIFO/PCI_WFIFO_RAM/A1[0] (ram32x32) 0.008 * 3.398 r data arrival time 3.398 clock SYS_CLK (rise edge) 0.000 0.000 clock network delay (propagated) 2.711 * 2.711 I_ORCA_TOP/I_PCI_WRITE_FIFO/PCI_WFIFO_RAM/CE1 (ram32x32) 2.711 r library hold time 0.282 * 2.992 data required time 2.992 ----------------------------------------------------------------------------data required time 2.992 data arrival time -3.398 ---------------------------------------------------------------------------slack (MET) 0.406

Asynchronous Clear/Reset Pins

Data Arrival
ClrN
ClrN F1 clk FF5 ClrN F1 clk FF6 ClrN

F1
clk FF2

Clk

Data Required
Min Data Arrival Clk FF2/ClrN Min Data Required
Recovery

Max Data Arrival

0ns

4ns

Max Data Required

Removal

FF2/clk

1ns

5ns

Timing Report Recovery

Startpoint: I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg (rising edge-triggered flip-flop clocked by SYS_2x_CLK) Endpoint: I_ORCA_TOP/I_RISC_CORE/I_ALU/Neg_Flag_reg (recovery check against rising-edge clock SYS_2x_CLK) Path Group: **async_default** Path Type: max Point Incr Path ----------------------------------------------------------------------------clock SYS_2x_CLK (rise edge) 0.000 0.000 clock network delay (propagated) 2.846 * 2.846 I_ORCA_TOP/I_RESET_BLOCK/sys_2x_rst_n_buf_reg/CP (sdcrq1) 0.000 2.846 r . . . I_ORCA_TOP/I_RISC_CORE/I_ALU/Neg_Flag_reg/CDN (sdcrb1) 0.073 * 3.974 r data arrival time 3.974 clock SYS_2x_CLK (rise edge) 4.000 4.000 clock network delay (propagated) 2.833 * 6.833 I_ORCA_TOP/I_RISC_CORE/I_ALU/Neg_Flag_reg/CP (sdcrb1) 6.833 r library recovery time 0.128 * 6.962 data required time 6.962 -----------------------------------------------------------------------------data required time 6.962 data arrival time -3.974 ------------------------------------------------------------------------------slack (MET) 2.988

Estimating Rnet and Cnet Pre-layout

Extraction data of already routed designs are used to build a lookup table called the wire load model WLM is based on the statistical estimates of R and C based on Net Fanout
Net Fanout 1 2 3 4 Resistance K 0.00498 0.01295 0.02092 0.02888 Capacitance pF 0.00312 0.00812 0.01312
From Library
0.00498 K

Cpin
0.00312 pF

0.01811

Wire Load Model (RC)

Estimated RCs are represented as wire load model Estimated RCs are represented as wire load model

Cell Delay Calculation

Cell delays are calculated from a Non Linear Delay Model (NLDM) table in the technology library Tables are indexed by input transition and total output load for each gate
Cell Delay = f (Input Transition Time, Output Load)
Output Load (pF)
0.5 ns Input Trans (ns)
0.005 pF 0.045 pF

.005 0.0 0.5 1.0 .1 .15 .25

.05 .15 . 23 .4

.10 .2 .3 .55

.15 .25 .38 .75

Cell Delay = .23 ns From Library From Wire Load Model

Cell Delay (ns)

Net Delay Calculation

Net delay is the time-of-flight due to the nets RC Nets RC is obtained from wire load model for pre-layout design
Net delay
Cpin

Rnet

Cnet

Net Delay = f (Rnet, Cnet + Cpin) Post-layout Rs and Cs are extracted as a parasitics file. Post-layout Rs and Cs are extracted as a parasitics file.

Output Transition Calculation

There is another NLDM table in the library to calculate output transition Output transition of a cell becomes the input transition of the next cell down the chain
Output Transition = f (Input Transition Time, Output Load)
Output Load (pF)
0.5 ns Output Trans = 0.30 ns Input Trans (ns)

.005
0.005 pF

. 05 0.20 0.30 0.40

.10 0.37 0.49 0.62

.15 0.60 0.80 1.00

0.00 0.50 1.00

0.10 0.18 0.25

0.045 pF

From Library From Wire Load Model

Output Transition (ns)

What About Pre and Post Layout STA?

Post layout, an STA tool calculates clock network effects Propagated Clocks
FF1 FF2

SDF contains estimated or actual delays

F1
clk

F1
clk

Clk

Clock Network

a t im s s u e ffect o t, y rk e u ayo netwo l Pre

k c lo c te

Ideal Clocks

Pre or Post Layout Timing Report

Point Incr Path ---------------------------------------------------------clock Clk (rise edge) 0.00 0.00 clock network delay (propagated) 1.10 * 1.10 FF1/CLK (fdef1a15) 0.00 1.10 r FF1/Q (fdef1a15) 0.40 * 1.50 f U2/Y (buf1a27) 0.05 * 1.55 f U3/Y (buf1a27) 0.05 * 1.60 f FF2/D (fdef1a15) 0.01 * 1.61 f data arrival time 1.61 clock Clk (rise edge) 0.00 0.00 clock network delay (propagated) 1.00 * 1.00 FF2/CLK (fdef1a15) 1.00 r library hold time -0.10 * 1.10 data required time 1.10 ---------------------------------------------------------data required time 1.10 data arrival time -1.61 ---------------------------------------------------------slack (MET) 0.51

What About Negedge Triggered Registers?

FF1

FF2

F1
clk

F1
clk

Clk

Clk FF2.D

0ns

2ns

4ns

FF2.clk

Hold
1ns

Setup
5ns

What About Multi-Frequency Clocks?

FF1 FF2

F1
clk

Q D

F1
clk

Clk1 Clk2

Create both clocks

0ns Clk1 4ns 8ns

Base Period is from 0ns to 12ns

12ns

Hold
Clk2 0ns 3ns 6ns

Setup

9ns

12ns

What About Interface Paths: Input Ports?

You specify the arrival times at the input ports of the design. Input External Delay
Q

FF1

Data Arrival
FF2

F1
clk

U2

D
U3

F1
clk

Clk
0 2 4

Data Required

What About Interface Paths: Output Ports?

You specify the path required time at the output ports of the design.

Data Arrival
FF1

Output External Delay

M
FF2

F1
Clk
0 2 4

U2

D
U3

clk

F1
clk

Interface Paths in a Timing Report: Output

Point Incr Path ---------------------------------------------------------clock Clk (rise edge) 0.00 0.00 clock network delay (propagated) 1.10 * 1.10 FF1/CLK (fdef1a15) 0.00 1.10 r FF1/Q (fdef1a15) 0.50 * 1.60 r U2/Y (buf1a27) 0.11 * 1.71 r U3/Y (buf1a27) 0.11 * 1.82 r M (out) 0.05 * 1.87 r data arrival time 1.87 clock Clk (rise edge) 4.00 4.00 clock network delay (propagated) 0.00 * 4.00 output external delay -0.21 * 3.79 data required time 3.79 ---------------------------------------------------------data required time 3.79 data arrival time -1.87 ---------------------------------------------------------slack (MET) 1.92

Other Timing Checks Verified by STA

recovery removal setup hold out_setup MY_DESIGN out_hold

Clk3

Clk4

nochange
Clk1 ClkEn Clk2 Timing Model U1

clk_gating_setup clock_gating_hold

max_skew min_period min_pulse_width

Timing checks: specified by the user Timing checks: specified by the vendor

Introduction to Digital VLSI Design VLSI

STA part 2

What

Fast and Exhaustive

Independent of functionality or stimulus

Spice accurate

Implement and Verify

When
Process DFM Arch

IR Drop

RTL

Timing SI/EM Synth

Xtrn

Place

Route

Clocks

Components
Timing Specs

Drives Design Processes

Inputs to other Design Analysis

Delay Calculation Constraint Checking

Delay Calculation Timing Arcs

Input Falling Output Rising Combinational Element

Input Rising Output Falling

datain Sequential Element clock

dataout Setup Rising/Setup Falling Sequential Rising Sequential Falling

Delay Calculation NLDM Library

NLDM

Delay Output Load

Input transition

Delay Calculation NLDM Library (contd.)

NLDM Libraries

Delay Calculation ECSM Library

Current Source Model: Voltage Controlled - Current Source

Delay Calculation Interconnect

IEEE Standard format SPEF Distributed RC

Delay Calculation Analysis Corners

Gate or Transistor
P Process (Slow, Typical, Fast) V Supply Voltage T Temperature

Interconnect
P Process (Wide, Narrow, Tall, Short, K) T - Temperature

Delay Calculation Thresholds

Threshold Points Transition Time

Propagation Delay

Delay Calculation
Path Delay Calculations

Worst arrival time of signal at input pin of capture flop = ? Best arrival time of signal at input pin of capture flop = ?

Constraint Checking Introduction

Sequential Operation of a single Cycle path

Timing Paths

Sequential Delay

Combinational Delay

What this mark is for?

Constraint Checking Constraint Types

Conditions that need to be met
Clocks Max allowed transition time Max allowed load or capacitance Max allowed Delay

Boundary Settings
Input transition time Output loading Logic settings

Exceptions to the single cycle rule

False paths Multicycle paths

Clocks

Ex-I
Synchronous Designs

Ex-II

Ex-III

Ex-IV

Default single cycle of operation Launch Edge and Capture Edge Properties Period Waveform Rise/Fall Transition Time Skew or Uncertainty Generated Clocks Derived from a master Synchronous by definition Definite edge relationship

d1

d2

d1 != d2

Virtual Clocks
Virtual Clocks do not have any physical existence Virtual Clocks are used as a reference to module for input and output delays Virtual Clocks are local to module design
10 nS

Properties
Period Waveform

Input Arrival Time

Output Required Time

Global Constraints
Specifying min-max Cap Range This specification ensures that circuits used in design work within library characterization limits Specifying max Transition This specification ensures that transition thus propagated doesnt give rise to a bad propagation delays Specifying driver-load on ports This specification ensures that standard load value is modeled at ports Specifying Input and Output Delays at Ports

Check Types
Setup Hold Recovery Removal Clock Gating Min Pulse Width Data-to-Data

Timing Checks Setup Time and Hold Time

Remember: Setup and Hold Times are Interdependent

Setup Time and Hold Time are Properties of the Sequential Element Circuit These need to be honoured to guarantee expected operation of the design

Timing Checks Setup Check

Data Launched by Launch Edge of FF1 Captured by Intended Capture Edge of FF2 Data launched by launch edge of FF1 should arrive at the data input of FF2 latest by Capture Edge Time Setup Time of FF2

Timing Checks Hold Check

Data launched by Launch Edge of FF1 should not be captured by an edge preceding the intended Capture Edge of FF2, OR Data launched by edge following Launch Edge of FF1 should not be captured by the intended Capture Edge of FF2 Data should reach the data input of FF2 no earlier than the hold time of FF2

Timing Checks Recovery and Removal

Timing Checks Min Pulse Width

Timing Checks Glitch Detection

Timing Checks Clock Gating Checks

Timing Checks Data-to-Data Checks

Why Data to Data Checks are required
Constraints on asynchronous or self-timed circuit interfaces Constraints on signals with unusual clock waveforms that cannot be easily specified with the create_clock command Constraints on skew between bus lines Recovery and removal constraints between asynchronous preset and clear input pins Constraints on handshaking interface logic
D1 D2
Setup Hold

Constrained Pin Related Pin

D1 D2

Timing Exceptions
False Paths
Timing Paths that are invalid
Paths between asynchronous clocks Paths that are static for a particular timing mode

Multicycle Paths
Non-default cycle operation

Logic Setting
Pins or nets that are tied to 1/0 for a particular timing mode

Disable Timing
Timing Arcs that are disabled

Advanced Topics
Timing Models
Extracted Timing Models Interface Logic Models Quick Timing Models

Statistical Timing Analysis

Problem
Given corner data below, which combinations are expected to lead to worst and best gate delays?
Process Slow Typical Fast Voltage 0.9V 1.0V 1.1V Temperature -20C 27C 105C

Introduction to Digital VLSI Design VLSI

STA part 3

Overview
In this era of high performance electronics, timing continues to be a top priority and designers are spending increased effort addressing IC performance.

Two Methods are employed for Timing Analysis:

Dynamic Timing Analysis Static Timing Analysis

Dynamic Timing Analysis

Traditionally, a dynamic simulator has been used to verify the functionality and timing of an entire design or blocks within the design. Dynamic timing simulation requires vectors, a logic simulator and timing information. With this methodology, input vectors are used to exercise functional paths based on dynamic timing behaviors for the chip or block. Dynamic simulation is becoming more problematic because of the difficulty in creating comprehensive vectors with high levels of coverage. Time-to-market pressure, chip complexity, limitations in the speed and capacity of traditional simulators are all motivating factors for migration towards static timing techniques.

Static Timing Analysis (STA)

STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design. First, a design is analyzed, then all possible paths are timed and checked against the requirements. Since STA is not based on functional vectors, it is typically very fast and can accommodate very large designs (multimillion gate designs). STA is exhaustive in that every path in the design is checked for timing violations. STA does not verify the functionality of a design. Also, certain design styles are not well suited for static approach. For instance, dynamic simulation may be required for asynchronous parts of a design and certainly for any mixed-signal portions.

Static Timing Analysis (STA)

STA consists of three major steps:
Break down the design into timing paths (R-R, PI-R,PI-PO & R-PO). Delay of each path is calculated All path delays are checked against timing constraints to see if it is met.

STA advantage
Speed (orders of magnitude faster than dynamic simulation) Capacity to handling full chip Exhaustive timing coverage Vectors are not required

STA disadvantage
It is pessimistic (too conservative) Reports false paths

Flow Inputs:
Gate-level Verilog. Constraints (SDC) Extracted nets (SPEF) Libraries (liberty format - .lib)

Timing Closure
Timing Closure is the ability to detect and fix timing problems in the design flow as early as possible. This is done by checking the correctness of intermediate results through Static Timing Analysis (STA) and also by dynamic timing simulation with SDF back annotation. In case of failure - which means that the timing goals have not been achieved - modification of timing constraints must be done through well defined loops, re-synthesis and in worst case re-design.

Cell Timing Characterization

Delay tables Generated using a detailed transistor-level circuit simulator SPICE (differential-equations solver) Simulate the circuit of the cell for a number of different input slews and load capacitances Propagation time (50% Vdd at input to 50% at output) Output slew (10% Vdd at output to 90% Vdd at output)

NLDM
Cell Delay (Non-linear) = f (CL, Sin) and Sout = f (CL, Sin)

Interpolate between table entries Interpolation error is usually below 10% of SPICE

Delay Calculation

Timing Path Definition

STA tool does not report delays by net or by cell. Instead it reports by timing paths with constraint. Valid timing paths: Primary input to Register Register to register Register to primary output Input to output Valid start of a timing path Clock pins of FF Primary inputs Valid end of a timing path Data pins of FF Primary output ports Control pin of gated clock

Path Delays
When delay paths are added, the following factors affect the delays:
Slew propagation Ideally, the slew propagation should be timing path specific. However, the STA does not do this. It uses either worst_slew or worst_arrival.
worst_slew refers to using the slowest transition for signals arriving at a multi-input cell output (fastest transition for min delay mode). This is CTE default pessimistic behavior . worst_arrival refers to using the input signal that arrives the latest (using the earliest for min delay mode).

Analysis Modes
Semiconductor device parameters can vary with conditions such as fabrication process, operating temperature, and power supply voltage. The STA tool supports three analysis modes:
Single operating condition single set of delay parameters is used for the whole circuit, based on one set of process, temperature, and voltage conditions. Min-Max (BC-WC) operating condition simultaneously checks the circuit for the two extreme operating conditions, minimum and maximum. For setup checks, it uses maximum delays for all paths. For hold checks, it uses minimum delays. On-chip-variation mode - conservative analysis that allows both minimum and maximum delays to apply to different paths at the same time. For a setup check, it uses maximum delays for the launch clock path and data path, and minimum delays for the capture clock path. For a hold check, it uses minimum delays for the launch clock path and data path, and maximum delays for the capture clock path.

Single Operating Condition

Single set of delay parameters for the whole circuit, based on one set of process, temperature, and voltage conditions.
Hold Setup

setAnalysisMode single setAnalysisMode -hold setOpCond BEST -library fast.lib

setAnalysisMode single setAnalysisMode -setup setOpCond WORST -library slow.lib

Best case/Worst case Analysis

Simultaneous checks of extreme operating conditions, minimum and maximum. For setup checks, it uses maximum delays for all paths. For hold checks, it uses minimum delays for all paths.

setAnalysisMode bcWc setAnalysisMode setup setOpCond min Best minLibrary fast.lib max Worst maxLibrary slow.lib

On-Chip Variation Analysis

Conservative analysis that allows both minimum and maximum delays to apply to different paths at the same time. For a setup check, it uses maximum delays for the launch clock path and data path, and minimum delays for the capture clock path. For a hold check, it uses minimum delays for the launch clock path and data path, and maximum delays for the capture clock path.

setAnalysisMode onChipVariation

Derating
Minimum and Maximum delays can be adjust by specified factors to model the effects of operating conditions. This adjustment of calculated delays is called derating. Derating affects the delay and slack values reported by report_timing. setTimingDerate max early 0.8 late 1.0 setTimingDerate min early 1.0 late 1.1

Clock Reconvergence Pessimism Removal (CRPR)

When launching and capturing clock share common path, the common path min delay and max delay will add additional pessimism to both setup and hold analysis. CRPR can be used to remove this pessimism.

setAnalysisMode crpr onChipVariation set_global timing_remove_clock_reconvergence_pessimism true

Timing exceptions
Timing exception includes the following:
False Path- Use the set_false_path command to specify a logic path that exists in the design but should not be analyzed. Setting a false path removes the timing constraints on the path. Multiple Cycle Path - Use the set_multicycle_path command to specify the number of clock cycles required to propagate data from the start to the end of the path. Min/Max Delay - Use the set_max_delay and set_min_delay commands t override the default setup and hold constraints with specific maximum and minimum time values.

Setup/Hold Analysis (in the absence of timing exceptions)

Setup check - verifies that the data launched from FF1 at time=0 arrives at the D input of FF2 in time for the capture edge at time=10. If the data takes too long to arrive, it is reported as a setup violation. Hold check - verifies that the data launched from FF1 at time 0 does not get propagated so soon that it gets captured at FF2 at the clock edge at time 0. If the data arrives too soon, it is reported as a hold violation.

Multiple Cycle Setup

If data is launched every 3 cycles, then setup is checked against the third rising edge (9.75) and hold is checked against next rising edge (which is CLKg1 at 6.50). STA tool verifies that the data launched by the setup launch edge is not captured by the previous capture edge. So the default hold check for multi-cycle setup is capture edge minus one.

Multiple Cycle Hold

The number after the -hold option specifies the number of cycles to move the hold check backward from the default position implied by the setup check. A positive number moves the check backward by the specified number of cycles. Specifying zero does not change the hold check time.

Recovery/Removal check
Timing checks which are related to asynchronous input pin of a flip flop. Although a flip-flop is asynchronously set or clear , the negation from its reset state is synchronous . A recovery timing check specifies a minimum amount of time allowed between the release of a asynchronous signal from the active state to the next active clock edge . A removal timing check specifies the minimum amount of time between an active edge and the release of an asynchronous control signal.

Case Analysis
Case analysis allows timing analysis to be performed using logic constants or logic transitions (rising or falling) on ports or pins, to limit the signal propagated through the design. Case analysis is a path-pruning mechanism and is most commonly used for timing the device in a given operational configuration or functional mode. For example, case analysis can be used to compare normal circuit operation against scan or BIST operation.

Timing Models
Timing extraction plays an important role in hierarchical top-down flow and bottom-up IP authoring flow by reducing the complexity of timing verification and by providing a level of abstraction which hides the implementation details of IP blocks. Three most desired features in timing extraction are accuracy, efficiency, and usability. The model must preserve the timing behavior of the original circuit and produce accurate results. Three types of models can be generated: Quick Timing Model (QTM) Extracted Timing Model (ETM) Interface Logic Model (ILM)

QTM
A temporary model used early in the design cycle for a block that has no netlist available. QTM creation is faster than writing ad-hoc model . The model contains both min and max time arc for setup and hold checks. Check consistency between blocks constraints and updates boundary constraints (after each iteration of synthesis) The netlist used for QTM generation can be easily generated (low effort RTL mapping) since existence or absence of timing arc is independent from the logic/physical design. Inputs Constraints (SDC) Configuration file Header file The QTM model is generated using Black Box commands. Using this command set allows to define timing arcs and electrical data (i.e. output driver, input load,)

ILM
ILMs embody a structural approach to model generation, where the original gate-level netlist is replaced by another gate-level netlist that contains only the interface logic of the original netlist. Interface logic contains all circuitry leading from I/O ports to edgetriggered registers called interface registers. The clock tree leading to interface registers is preserved in an ILM. Logic that is only contained in register-to-register paths on a block is notin an ILM.

ETM
Extracted timing models differ from ILMs in that the interface logic for a block is replaced by context-independent timing relationships between pins on a library cell. The extracted library cell contains timing arcs between external pins. Internal pins are introduced only when there are clocks defined on internal pins of the design

Analysis Modes

Analysis Modes