Data Sheet

ADL8106
GaAs, pHEMT, Low Noise Amplifier, 18 GHz to 54 GHz

FEATURES FUNCTIONAL BLOCK DIAGRAM

► Integrated power supply capacitors and bias inductors
► Integrated ac-coupling capacitors
► Gain: 21.5 dB typical at 30 GHz to 44 GHz
► Input return loss: 12.5 dB typical at 30 GHz to 44 GHz
► Output return loss: 19 dB typical at 30 GHz to 44 GHz
► OP1dB: 14.5 dB typical at 30 GHz to 44 GHz
► PSAT: 19 dBm typical at 30 GHz to 44 GHz
► OIP3: 21.5 dBm typical at 30 GHz to 44 GHz
► Noise figure: 3.5 dB typical at 30 GHz to 44 GHz
► 3 V typical supply voltage at 120 mA
► 50 Ω matched input and output
► 24-terminal, 5.00 mm × 5.00 mm, chip array small outline no lead
cavity [LGA_CAV]
Figure 1. Functional Block Diagram
APPLICATIONS
► Test instrumentation
► Military and space
GENERAL DESCRIPTION
The ADL8106 is a gallium arsenide (GaAs), pseudomorphic high
electron mobility transfer (pHEMT), monolithic microwave integrat-
ed circuit (MMIC), wideband low noise amplifier that operates from
18 GHz to 54 GHz. All the typically required external passive
components for operation (ac coupling capacitors and power supply
decoupling capacitors) are integrated, which facilitates a small and
compact printed circuit board (PCB) footprint.
The ADL8106 provides a gain of 21.5 dB, an output power for 1 dB
compression (OP1dB) of 14.5 dBm, and a typical output third-order
intercept (OIP3) of 21.5 dBm at 30 GHz to 44 GHz. The ADL8106
requires 120 mA from a 3 V supply voltage (VDDx). The ADL8106
is housed in a 5.00 mm × 5.00 mm, 24-terminal chip array small
outline no lead cavity (LGA_CAV) package.

Rev. 0
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Data Sheet ADL8106
TABLE OF CONTENTS

Features................................................................ 1 Electrostatic Discharge (ESD) Ratings...............6

Applications........................................................... 1 ESD Caution.......................................................6
General Description...............................................1 Pin Configuration and Function Descriptions........ 7
Functional Block Diagram......................................1 Interface Schematics..........................................7
Electrical Specifications.........................................3 Typical Performance Characteristics..................... 8
18 GHz to 20 GHz Frequency Range................ 3 Lower Voltage Higher Current Operation......... 15
20 GHz to 30 GHz Frequency Range................ 3 Theory of Operation.............................................22
30 GHz to 44 GHz Frequency Range................ 4 Applications Information...................................... 23
44 GHz to 50 GHz Frequency Range................ 4 Biasing the ADL8106 with the HMC920........... 23
50 GHz to 54 GHz Frequency Range................ 5 Outline Dimensions............................................. 26
Absolute Maximum Ratings...................................6 Ordering Guide.................................................26
Thermal Resistance........................................... 6 Evaluation Boards............................................ 26

REVISION HISTORY

8/2022—Revision 0: Initial Version

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Data Sheet ADL8106
ELECTRICAL SPECIFICATIONS

18 GHz TO 20 GHz FREQUENCY RANGE

TCASE = 25°C, VDD1 drain bias voltage (VDD1) = VDD2 drain bias voltage (VDD2) = 3 V, and quiescent drain current (IDQ) = 120 mA, unless
otherwise stated. Adjust the negative gate bias voltage (VGG1) between −2 V to 0 V to achieve an IDQ = 120 mA typical.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 18 20 GHz
GAIN 18.5 dB
Gain Variation over Temperature 0.028 dB/°C
RETURN LOSS
Input 16 dB
Output 16.5 dB
OUTPUT
OP1dB 11.5 dBm
Saturated Power (PSAT) 14.5 dBm
OIP3 17.5 dBm Output power (POUT) per tone = 0 dBm with 1 MHz tone spacing
Second-Order Intercept (OIP2) 15 dBm POUT per tone = 0 dBm with 1 MHz tone spacing
NOISE FIGURE 4 dB
SUPPLY
IDQ 120 mA Adjust VGG1 to achieve IDQ = 120 mA typical
VDD 2 3 3.5 V

20 GHz TO 30 GHz FREQUENCY RANGE

TCASE = 25°C, VDD1 = VDD2 = 3 V, and IDQ = 120 mA, unless otherwise stated. Adjust the VGG1 between −2 V to 0 V to achieve an IDQ = 120 mA
typical.

Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 20 30 GHz
GAIN 17.5 20 dB
Gain Variation over Temperature 0.028 dB/°C
RETURN LOSS
Input 13 dB
Output 15.5 dB
OUTPUT
OP1dB 12 14 dBm
PSAT 17 dBm
OIP3 21 dBm POUT per tone = 0 dBm with 1 MHz tone spacing
OIP2 24 dBm POUT per tone = 0 dBm with 1 MHz tone spacing
NOISE FIGURE 3.0 dB
SUPPLY
IDQ 120 mA Adjust VGG1 to achieve IDQ = 120 mA typical
VDD 2 3 3.5 V

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Data Sheet ADL8106
ELECTRICAL SPECIFICATIONS

30 GHz TO 44 GHz FREQUENCY RANGE

TCASE = 25°C, VDD1 = VDD2 = 3 V, and IDQ = 120 mA, unless otherwise stated. Adjust VGG1 between −2 V to 0 V to achieve an IDQ = 120 mA
typical.

Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 30 44 GHz
GAIN 19 21.5 dB
Gain Variation over Temperature 0.028 dB/°C
RETURN LOSS
Input 12.5 dB
Output 19 dB
OUTPUT
OP1dB 12 14.5 dBm
PSAT 19 dBm
OIP3 21.5 dBm POUT per tone = 0 dBm with 1 MHz tone spacing
NOISE FIGURE 3.5 dB
SUPPLY
IDQ 120 mA Adjust VGG1 to achieve IDQ = 120 mA typical
VDD 2 3 3.5 V

44 GHz TO 50 GHz FREQUENCY RANGE

TCASE = 25°C, VDD1 = VDD2 = 3 V, and IDQ = 120 mA, unless otherwise stated. Adjust VGG1 between −2 V to 0 V to achieve an IDQ = 120 mA
typical.

Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 44 50 GHz
GAIN 22 dB
Gain Variation over Temperature 0.031 dB/°C
RETURN LOSS
Input 15 dB
Output 18 dB
OUTPUT
OP1dB 16.5 dBm
PSAT 20.5 dBm
OIP3 22 dBm POUT per tone = 0 dBm with 1 MHz tone spacing
NOISE FIGURE 4 dB
SUPPLY
IDQ 120 mA Adjust VGG1 to achieve IDQ = 120 mA typical
VDD 2 3 3.5 V

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Data Sheet ADL8106
ELECTRICAL SPECIFICATIONS

50 GHz TO 54 GHz FREQUENCY RANGE

TCASE = 25°C, VDD1 = VDD2 = 3 V, and IDQ = 120 mA, unless otherwise stated. Adjust VGG1 between −2 V to 0 V to achieve an IDQ = 120 mA
typical.

Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 50 54 GHz
GAIN 20.5 dB
Gain Variation over Temperature 0.031 dB/°C
RETURN LOSS
Input 15 dB
Output 14.5 dB
OUTPUT
OP1dB 19 dBm
PSAT 20 dBm
OIP3 23 dBm POUT per tone = 0 dBm with 1 MHz tone spacing
NOISE FIGURE 4 dB
SUPPLY
IDQ 120 mA Adjust VGG1 to achieve IDQ = 120 mA typical
VDD 2 3 3.5 V

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Data Sheet ADL8106
ABSOLUTE MAXIMUM RATINGS

Table 6. ELECTROSTATIC DISCHARGE (ESD) RATINGS

Parameter Rating
The following ESD information is provided for handling of EDS-sen-
Drain Bias Voltage (VDD1 and VDD2) 4V sitive devices in an ESD protected area only.
Negative Gate Bias Voltage (VGG1) −2.1 V to 0 V
RF Input Power (RFIN) 17 dBm Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Continuous Power Dissipation (PDISS), TCASE = 85°C 1.49 W
(Derate 16.6 mW/°C Above 85°C) ESD Ratings for ADL8106
Temperature Table 8. ADL8106, 24-Terminal LGA_CAV
Storage Range −65°C to +150°C ESD Model Withstand Threshold (V) Class
Operating Range −40°C to +85°C HBM ±300 1A
Quiescent Channel (TCASE = 85°C, VDDx = 3 V, IDQ = 106.7°C
120 mA, Input Power (PIN) = Off) ESD CAUTION
Maximum Channel 175°C
ESD (electrostatic discharge) sensitive device. Charged devi-
Stresses at or above those listed under Absolute Maximum Ratings ces and circuit boards can discharge without detection. Although
may cause permanent damage to the product. This is a stress this product features patented or proprietary protection circuitry,
rating only; functional operation of the product at these or any other damage may occur on devices subjected to high energy ESD.
conditions above those indicated in the operational section of this Therefore, proper ESD precautions should be taken to avoid
specification is not implied. Operation beyond the maximum operat- performance degradation or loss of functionality.
ing conditions for extended periods may affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to system design and oper-
ating environment. Careful attention to the PCB thermal design is
required.
θJC is the channel-to-case thermal resistance (channel to exposed
metal ground pad on the underside of the device).

Table 7. Thermal Resistance

Package Type θJC1 Unit
CE-24-2 60.3 °C/W
1 Thermal resistance (θJC) was determined by simulation under the following
conditions: the heat transfer is due solely to thermal conduction from the
channel through the ground paddle to the PCB, and the ground paddle is held
constant at the operating temperature of 85°C.

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Data Sheet ADL8106
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Description
1, 2, 3, 5, 6, 7, 9, GND Ground. Connect to a ground plane that has low electrical and thermal impedance. See Figure 3 for the interface schematic.
11, 12, 13, 14,
15, 17, 18, 19,
21, 22, 23, 24
4 RFIN RF Input. The RFIN pin has a dc path to ground followed by an ac coupling capacitor in the RF signal path. If the dc bias level of the input
signal is not equal to 0 V, externally ac-couple the RFIN pin. See Figure 4 for the interface schematic.
8 VGG1 Negative Gate Bias Control. The gate voltage can be applied to VGG1. Adjust the negative voltage on the VGG1 pin to set the IDQ to the
desired level. See Figure 5 for the interface schematic.
10, 20 VDD1, VDD2 Drain Bias Pads with Integrated RF Chokes. Connect a common dc bias to the VDDx pads to provide drain current. See Figure 6 for the
interface schematic.
16 RFOUT RF Output. The RFOUT pin has a resistive path to ground and an ac coupling capacitor in the RF signal path. If the dc bias level of the
next stage is not equal to 0 V, externally ac-couple the RFOUT pin. See Figure 6 for the interface schematic.

INTERFACE SCHEMATICS

Figure 3. GND Interface Schematic

Figure 4. RFIN Interface Schematic

Figure 5. VGG1 Interface Schematic

Figure 6. VDD1, VDD2, and RFOUT Interface Schematic

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. Gain and Return Loss vs. Frequency, VDD = 3 V, IDQ = 120 mA Figure 10. Gain vs. Frequency for Various Temperatures,
VDD = 3 V, IDQ = 120 mA

Figure 8. Gain vs. Frequency for Various VDD Values, IDQ = 120 mA
Figure 11. Gain vs. Frequency for Various IDQ Values, VDD = 3 V

Figure 9. Input Return Loss vs. Frequency for Various Temperatures,

VDD = 3 V, IDQ = 120 mA Figure 12. Input Return Loss vs. Frequency for Various VDD Values,
IDQ = 120 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 13. Input Return Loss vs. Frequency for Various IDQ Values, VDD = 3 V Figure 16. Output Return Loss vs. Frequency for Various Temperatures,
VDD = 3 V, IDQ = 120 mA

Figure 14. Output Return Loss vs. Frequency for Various VDD Values,
IDQ = 120 mA Figure 17. Output Return Loss vs. Frequency for Various IDQ Values,
VDD = 3 V

Figure 15. Reverse Isolation vs. Frequency for Various Temperatures,

VDD = 3 V, IDQ = 120 mA Figure 18. Noise Figure vs. Frequency for Various Temperatures,
VDD = 3 V, IDQ = 120 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 19. Noise Figure vs. Frequency for Various VDD Values, IDQ = 120 mA Figure 22. Noise Figure vs. Frequency for Various IDQ Values, VDD = 3 V

Figure 20. OP1dB vs. Frequency for Various Temperatures, Figure 23. PSAT vs. Frequency for Various Temperatures,
VDD = 3 V, IDQ = 120 mA VDD = 3 V, IDQ = 120 mA

Figure 21. OP1dB vs. Frequency for Various VDD Values, IDQ = 120 mA Figure 24. PSAT vs. Frequency for Various VDD Values, IDQ = 120 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 25. OP1dB vs. Frequency for Various IDQ Values, VDD = 3 V Figure 28. PSAT vs. Frequency for Various IDQ Values, VDD = 3 V

Figure 26. POUT, Gain, Power Added Efficiency (PAE), and Drain Current (IDD) Figure 29. POUT, Gain, PAE, and IDD vs. PIN, 36 GHz, VDD = 3 V, IDQ = 120 mA
vs. PIN, 20 GHz, VDD = 3 V, IDQ = 120 mA

Figure 30. POUT, Gain, PAE, and IDD vs. PIN, 48 GHz, VDD = 3 V, IDQ = 120 mA
Figure 27. POUT, Gain, PAE, and IDD vs. PIN, 28 GHz, VDD = 3 V, IDQ = 120 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 31. POUT, Gain, PAE, and IDD vs. PIN, 54 GHz, VDD = 3 V, IDQ = 120 mA
Figure 34. PDISS vs. PIN for Various Frequencies at TCASE = 85°C, VDD = 3 V,
IDQ = 120 mA

Figure 32. OIP3 vs. Frequency for Various Temperatures,

POUT per Tone = 0 dBm, VDD = 3 V, IDQ = 120 mA
Figure 35. OIP3 vs. Frequency for VDD Values, POUT per Tone = 0 dBm,
IDQ = 120 mA

Figure 33. OIP3 vs. Frequency for Various IDQ Values, POUT per Tone = 0 dBm,
VDD = 3 V
Figure 36. Third-Order Intermodulation Distortion (IM3) vs. POUT per Tone for
Various Frequencies, VDD = 2 V, IDQ = 120 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 37. IM3 vs. POUT per Tone for Various Frequencies, VDD = 2.5 V, Figure 40. OIP2 vs. Frequency for Various Temperature,
IDQ = 120 mA POUT per Tone = 0 dBm, VDD = 3 V, IDQ = 120 mA

Figure 38. IM3 vs. POUT per Tone for Various Frequencies, VDD = 3 V, Figure 41. OIP2 vs. Frequency for Various VDD Values,
IDQ = 120 mA POUT per Tone = 0 dBm, IDQ = 120 mA

Figure 39. IM3 vs. POUT per Tone for Various Frequencies, VDD = 3.5 V, Figure 42. OIP2 vs. Frequency for Various IDQ Values, POUT per Tone = 0 dBm,
IDQ = 120 mA VDD = 3 V

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 43. IDD vs. PIN at Various Temperatures, 36 GHz, Figure 46. IDD vs. PIN at Various Frequencies, VDD = 3 V, IDQ = 120 mA
VDD = 3 V, IDQ = 120 mA

Figure 44. IDQ vs. Gate Voltage for Various Temperature, VDD = 3 V

Figure 45. VGG1 Current (IGG1) vs. PIN at Various Temperatures, 36 GHz, VDD
= 3 V, IDQ = 120 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

LOWER VOLTAGE HIGHER CURRENT OPERATION

Figure 47. Gain and Return Loss vs. Frequency, VDD = 2.5 V, IDQ = 160 mA Figure 50. Gain vs. Frequency for Various Temperatures,
VDD = 2.5 V, IDQ = 160 mA

Figure 48. Gain vs. Frequency for Various VDD Values, IDQ = 160 mA
Figure 51. Gain vs. Frequency for Various IDQ Values, VDD = 2.5 V

Figure 49. Input Return Loss vs. Frequency for Various Temperatures,
VDD = 2.5 V, IDQ = 160 mA Figure 52. Input Return Loss vs. Frequency for Various VDD Values,
IDQ = 160 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 53. Input Return Loss vs. Frequency for Various IDQ Values, Figure 56. Output Return Loss vs. Frequency for Various Temperatures,
VDD = 2.5 V VDD = 2.5 V, IDQ = 160 mA

Figure 54. Output Return Loss vs. Frequency for Various VDD Values, Figure 57. Output Return Loss vs. Frequency for Various IDQ Values,
IDQ = 160 mA VDD = 2.5 V

Figure 55. Reverse Isolation vs. Frequency for Various Temperatures, Figure 58. Noise Figure vs. Frequency for Various Temperatures, VDD = 2.5 V,
VDD = 2.5 V, IDQ = 160 mA IDQ = 160 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 59. Noise Figure vs. Frequency for Various VDD Values, IDQ = 160 mA Figure 62. Noise Figure vs. Frequency for Various IDQ Values, VDD = 2.5 V

Figure 60. OP1dB vs. Frequency for Various Temperatures, Figure 63. PSAT vs. Frequency for Various Temperatures,
VDD = 2.5 V, IDQ = 160 mA VDD = 2.5 V, IDQ = 160 mA

Figure 61. OP1dB vs. Frequency for Various VDD Values, IDQ = 160 mA Figure 64. PSAT vs. Frequency for Various VDD Values, IDQ = 160 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 65. OP1dB vs. Frequency for Various IDQ Values, VDD = 2.5 V Figure 68. PSAT vs. Frequency for Various IDQ Values, VDD = 2.5 V

Figure 66. POUT, Gain, PAE, and IDD vs. PIN, 20 GHz, VDD = 2.5 V, IDQ = 160 mA Figure 69. POUT, Gain, PAE, and IDD vs. PIN, 36 GHz, VDD = 2.5 V, IDQ = 160 mA

Figure 67. POUT, Gain, PAE, and IDD vs. PIN, 28 GHz, VDD = 2.5 V, IDQ = 160 mA Figure 70. POUT, Gain, PAE, and IDD vs. PIN, 48 GHz, VDD = 2.5 V, IDQ = 160 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 71. POUT, Gain, PAE, and IDD vs. PIN, 54 GHz, VDD = 2.5 V, IDQ = 160 mA Figure 74. PDISS vs. PIN for Various Frequencies at TCASE = 85°C, VDD = 2.5 V,
IDQ = 160 mA

Figure 72. OIP3 vs. Frequency for Various Temperatures,

POUT per Tone = 0 dBm, VDD = 2.5 V, IDQ = 160 mA Figure 75. OIP3 vs. Frequency for Various VDD Values,
POUT per Tone = 0 dBm, IDQ = 160 mA

Figure 73. OIP3 vs. Frequency for Various IDQ Values, POUT per Tone = 0 dBm,
VDD = 2.5 V Figure 76. IM3 vs. POUT per Tone for Various Frequencies,
VDD = 2 V, IDQ = 160 mA

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 77. IM3 vs. POUT per Tone for Various Frequencies, Figure 80. OIP2 vs. Frequency for Various Temperatures,
VDD = 2.5 V, IDQ = 160 mA POUT per Tone = 0 dBm, VDD = 2.5 V, IDQ = 160 mA

Figure 78. IM3 vs. POUT per Tone for Various Frequencies, Figure 81. OIP2 vs. Frequency for Various VDD Values,
VDD = 3 V, IDQ = 160 mA POUT per Tone = 0 dBm, IDQ = 160 mA

Figure 79. IM3 vs. POUT per Tone for Various Frequencies, Figure 82. OIP2 vs. Frequency for Various IDQ Values, POUT per Tone = 0 dBm,
VDD = 3.5 V, IDQ = 160 mA VDD = 2.5 V

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Data Sheet ADL8106
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 83. IDD vs. PIN at Various Temperatures, 36 GHz, Figure 86. IDD vs. PIN at Various Frequencies, VDD = 2.5 V, IDQ = 160 mA
VDD = 2.5 V, IDQ = 160 mA

Figure 84. IDQ vs. Gate Voltage for Various Temperature, VDD = 2.5 V

Figure 85. IGG1 vs. PIN at Various Temperatures, 36 GHz,

VDD = 2.5 V, IDQ = 160 mA

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Data Sheet ADL8106
THEORY OF OPERATION

The ADL8106 is a wideband GaAs, pHEMT, low noise amplifier with

integrated decoupling components. Figure 87 shows a simplified
block diagram. The drain current is set by the negative voltage
applied to the VGG1 pin. The drain bias voltage is applied through
the VDD1 and VDD2 pins with the current split evenly between
the two pins. Bias inductors and 0.1 μF and 100 μF decoupling
capacitors are integrated.
The RFIN and RFOUT pins are ac-coupled and matched to 50 Ω.
However, if these pins are connecting to devices with bias levels
that are not equal to 0 V, externally ac-couple the RFIN and RFOUT
pins.

Figure 87. Simplified Block Diagram

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Data Sheet ADL8106
APPLICATIONS INFORMATION

Figure 88 shows the basic connections for operating the ADL8106, relationship. Additionally, the HMC920 properly sequences gate
and the configuration used to characterize and qualify the device. and drain voltages to ensure safe on and off operation and offers
The RFIN and RFOUT pins are internally ac-coupled. However, if circuit self protection in the event of a short circuit. The active
the dc bias level of the input signal is not equal to 0 V, externally bias controller contains an internal charge pump that generates the
ac-couple the RFIN pin. Likewise, if the RFOUT pin is driving an negative voltage needed to drive the VGG1 pin on the ADL8106.
input with a bias level other than 0 V, externally ac-couple this pin. Alternatively, an external negative voltage can be provided.
Because VDD1, VDD2 and VGG1 are internally decoupled, no For more information regarding the use of the HMC920, refer to the
external decoupling components are required on these pins. HMC920 data sheet and the AN-1363 Application Note.
VGG1 sets the drain current of the amplifier (VGG1 ~ −0.65 V for
Application Circuit Setup
an IDQ of 120 mA). VDD1 and VDD2 provide the drain current (3 V
nominal) with equal currents on each pin. Figure 89 shows the application circuit for bias control of the
To avoid damaging the device, set VGG1 before VDD1 and VDD2 ADL8106 using the HMC920. The HMC920 drain current is meas-
are applied. Set VGG1 to −2 V before turning on VDD1 and ured and the VGATE output voltage adjusts until the set point drain
VDD2. VGG1 can then be adjusted upwards until the desired IDQ current is achieved. The various external component values around
is achieved. Then, apply the RF input signal. If the desired gate the HMC920 are calculated as follows.
voltage is known, VGG1 can be set to that voltage value directly The target drain current must first be determined and set. This
without taking it to the pinch off voltage (−2 V). current must be set based on the maximum drain current that is
To turn off the device, turn off the RF input signal, turn off VDD1 expected to be required during operation, including when the device
and VDD2 and then turn off VGG1. is generating the maximum expected output power. This current
is set by the resistor connected between the ISENSE pin on the
See the ADL8106-EVALZ user guide for information on using the HMC920 (Pin 25) and ground using the following equation:
evaluation board.
IDRAIN (A) = 166/RSENSE + 0.0135
To ensure adequate headroom, the supply voltage for the HMC920
must be set higher than the target drain voltage to the ADL8106 (3
V). Accordingly, the supply voltage to HMC920 is set to 5 V.
The voltage on the LDOCC pin (Pin 29) on the HMC920 drives the
VDRAIN pins which in turn drive the VDDx pins of the ADL8106.
Because the LDOCC output is connected to the VDRAIN output
through an internal metal-oxide semiconductor field effect transistor
(MOSFET) switch with an on resistance of 0.5 Ω, the LDOCC
voltage must be set slightly higher than the target drain voltage to
the ADL8106. To determine the required LDOCC voltage, use the
following equation:
VLDOCC = VDRAIN + IDRAIN × 0.5
Figure 88. Basic Connections Therefore, VLDOCC = 3 V + (0.14 × 0.5) = 3.07 V.
To set VLDOCC to 3.07 V, use the following equation with R5 set to
BIASING THE ADL8106 WITH THE HMC920 10 kΩ:
The HMC920 is designed to provide active bias control for depletion R8 = (R5/2) × (VLDOCC − 2)
mode amplifiers, such as the ADL8106. The HMC920 measures
and regulates drain current to compensate for temperature changes Therefore, R8 = (10000/2) × (3.07 – 2) = 5.350 kΩ (choose 5.36 kΩ
and part to part variations in the drain current to gate voltage standard value).

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Data Sheet ADL8106
APPLICATIONS INFORMATION

Figure 89. Active Bias Control of the ADL8106 Using the HMC920

HMC920 Bias Sequence Note that Figure 90 indicates a current consumption of 175 mA,
which includes the complete current consumption of the circuit, that
When the ADL8106 bias control circuit (HMC920) is set up, the bias is, 140 mA drain current for the ADL8106 and an additional 35 mA
can be toggled on and off by applying 3.5 V (high) or 0 V (low) to of IDQ in the HMC920. Also, the PAE for constant drain current bias
the EN pin. If EN is left floating, the pin floats high. When EN is in Figure 93 assumes a supply voltage of 5 V (the supply voltage to
set to 3.5 V, the gate voltage (VGATE) initially drops to −2 V and the the HMC920) and a constant current of 175 mA.
drain voltage (VDRAIN) rises to +3 V. Then, VGATE and the VGG1
voltage (VGG1) increase until the drain current (IDRAIN) reaches its
target value. The closed control loop then regulates IDRAIN to its
target value. When the EN pin goes low, VGATE and VGG1 drop back
to −2 V, and VDRAIN drops to 0 V.

Constant Drain Current Biasing vs. Constant

Gate Voltage Biasing
In comparison to a constant gate voltage bias, where the current
increases dynamically when RF power is applied, constant drain
current bias results in constant power consumption.
The performance of the constant drain current circuit is summarized
in Figure 90 to Figure 95. These figures include comparisons with
constant gate voltage bias.
Figure 90. IDD vs. PIN, VDD = 3 V, Frequency = 36 GHz, Constant Drain Current
The OP1dB and PSAT performance for the constant drain current
Bias (140 mA + 35 mA) and Constant Gate Voltage Bias (IDQ = 120 mA)
bias can be varied by varying the drain current setpoint. By increas-
ing the bias current, OP1dB and PSAT improve as shown in Figure
92 and Figure 95. The trade-off with constant drain current is that
the drain current is present for all RF input and output power levels.

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Data Sheet ADL8106
APPLICATIONS INFORMATION

Figure 91. OP1dB vs. Frequency for Various Temperatures, Data Measured Figure 94. PSAT vs. Frequency for Various Temperatures, Data Measured with
with Constant Drain Current of 140 mA IDD = 140 mA

Figure 92. OP1dB vs. Frequency for Various Constant Drain Currents Figure 95. PSAT vs. Frequency for Various Constant Drain Currents

Figure 93. PAE vs. PIN, VDD = 3 V, Frequency = 36 GHz, Constant Drain
Current Bias (140 mA + 35 mA) and Constant Gate Voltage Bias (IDQ= 120
mA)

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Data Sheet ADL8106
OUTLINE DIMENSIONS

Figure 96. 24-Terminal Chip Array Small Outline No Lead [LGA_CAV]

5.00 mm × 5.00 mm Body and 1.60 mm Package Height
(CE-24-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Packing Quantity Package Option
ADL8106ACEZ −40°C to +85°C 24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV] Reel, 1 CE-24-2
ADL8106ACEZ-R7 −40°C to +85°C 24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV] Reel, 100 CE-24-2
1 Z = RoHS Compliant Part.

EVALUATION BOARDS

Model1 Description
ADL8106-EVALZ Evaluation Board

1 Z = RoHS Compliant Part.

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registered trademarks are the property of their respective owners.
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Mouser Electronics

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ADL8106-EVALZ ADL8106ACEZ ADL8106ACEZ-R7