a LC2MOS

Quad 14-Bit DAC

AD7836
FEATURES GENERAL DESCRIPTION
Four 14-Bit DACs in One Package The AD7836 contains four 14-bit DACs on one monolithic
Voltage Outputs chip. It has output voltages with a full-scale range of ± 10 V
Separate Offset Adjust for Each Output from reference voltages of ± 5 V.
Reference Range of
5 V The AD7836 accepts 14-bit parallel loaded data from the exter-
Maximum Output Voltage Range of
10 V nal bus into one of the input latches under the control of the
Clear Function to User-Defined Code WR, CS and DAC channel address pins, A0–A2.
44-Pin MQFP Package
The DAC outputs are updated individually, on reception of new
APPLICATIONS data. In addition, the SEL input can be used to apply the user
Process Control programmed value in DAC Register E to all DACs, thus setting
Automatic Test Equipment all DAC output voltages to the same level. The contents of the
General Purpose Instrumentation DAC data registers are not affected by the SEL input.
Each DAC output is buffered with a gain of two amplifier into
which an external DAC offset voltage can be inserted via the
DUTGNDx pins.
The AD7836 is available in a 44-lead MQFP package.

FUNCTIONAL BLOCK DIAGRAM

VCC VSS VDD VREF(+)A VREF(–)A VREF(+)B VREF(–)B

X1 X1
AD7836
14 DATA 14
REG
A 14 MUX DAC A
VOUTA

DB13 X1 X1 R
14 14
INPUT R
BUFFER DATA DUTGND A
REG
DB0 MUX DAC B
B
VOUTB
WR
R
CS
R
DATA DUTGND B
REG
C MUX DAC B
A0 VOUTC
ADDRESS R
A1
DECODE
A2 X1 X1 R
DATA DUTGND C
REG
D MUX DAC D
VOUTD
R
DATA
X1 X1 R
REG
E DUTGND D

DGND AGND SEL VREF(+)D VREF(–)D VREF(+)C VREF(–)C CLR

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
 (VCC = +5 V
5%; VDD = +15 V
5%; VSS = –15 V
5%; AGND = DGND = DUTGND
AD7836–SPECIFICATIONS = 0 V; RL = 5 k and CL = 50 pF to GND, TA1 = TMIN to TMAX, unless otherwise noted)
Parameter A Units Test Conditions/Comments
ACCURACY
Resolution 14 Bits
Relative Accuracy ±2 LSB max
Differential Nonlinearity ± 0.9 LSB max Guaranteed Monotonic Over Temperature
Full-Scale Error ±8 LSB max VREF(+) = +5 V, VREF(–) = –5 V. Typically within ± 1 LSB
Zero-Scale Error ±8 LSB max VREF(+) = +5 V, VREF(–) = –5 V. Typically within ± 1 LSB
Gain Error ±2 mV typ VREF(+) = +5 V, VREF(–) = –5 V
Gain Temperature Coefficient2 20 ppm FSR/°C typ
40 ppm FSR/°C max
DC Crosstalk2 50 µV max See Terminology. R L = 5 kΩ
REFERENCE INPUTS
DC Input Resistance 100 MΩ typ
Input Current ±1 µA max Per Input. Typically ± 20 nA
VREF(+) Range 0/+5 V min/max
VREF(–) Range –5/0 V min/max
[VREF(+) – VREF(–)] 2/10 V min/max For Specified Performance. Can Go as Low as 0 V,
but Performance Not Guaranteed
OUTPUT CHARACTERISTICS
Output Voltage Swing ± 10 V min 2 × (VREF(–)+[VREF(+)-VREF(–)]•D) – VDUTDGN
Short Circuit Current 25 mA max
Resistive Load 5 kΩ min To 0 V
Capacitive Load 50 pF max To 0 V
DIGITAL INPUTS
VINH, Input High Voltage 2.4 V min
VINL, Input Low Voltage 0.8 V max
IINH, Input Current ± 10 µA max Total for All Pins
CIN, Input Capacitance 10 pF max
POWER REQUIREMENTS
VCC 5.0 V nom ± 5% for Specified Performance
VDD 15.0 V nom ± 5% for Specified Performance
VSS –15.0 V nom ± 5% for Specified Performance
Power Supply Sensitivity
∆Full Scale/∆VDD 110 dB typ
∆Full Scale/∆VSS 100 dB typ
ICC 0.5 mA max VINH = VCC, VINL = DGND. Dynamic Current
8 mA max VINH = 2.4 V min, VINL = 0.8 V max
IDD 14 mA max Outputs Unloaded. Typically 7 mA
ISS 14 mA max Outputs Unloaded. Typically 7 mA

(These characteristics are included for Design Guidance and are not
AC PERFORMANCE CHARACTERISTICS subject to production testing.)
Parameter A Units Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 16 µs typ Full-Scale Change to ± 1/2 LSB. DAC Latch Contents Alternately
Loaded with All 0s and All 1s
Digital-to-Analog Glitch Impulse 150 nV-s typ Measured with VREF(+) = +5 V, VREF(–) = –5 V. DAC Latch
Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent
on Load Conditions
DC Output Impedance 0.3 Ω max See Terminology
Channel-to-Channel Isolation 115 dB typ See Terminology
DAC-to-DAC Crosstalk 10 nV-s typ See Terminology
Digital Crosstalk 10 nV-s typ Feedthrough to DAC Output Under Test Due to Change in Digital
Input Code to Another Converter
Digital Feedthrough 0.2 nV-s typ Effect of Input Bus Activity on DAC Output Under Test
Output Noise Spectral Density
@ 1 kHz 40 nV/√Hz typ All 1s Loaded to DAC. V REF(+) = VREF(–) = 0 V
NOTES
1
Temperature range for A Version: –40°C to +85°C
2
Guaranteed by design.
Specifications subject to change without notice.

–2– REV. A
 AD7836
TIMING SPECIFICATIONS1 (VCC = +5 V
5%; VDD = +15 V
5%; VSS = –15 V
5%; AGND = DGND = 0 V)
Parameter Limit at TMIN, TMAX Units Description
t1 15 ns min A0, A1, A2 to WR Setup Time
t2 0 ns min A0, A1, A2 to WR Hold Time
t3 0 ns min CS to WR Setup Time
t4 0 ns min WR to CS Hold Time
t5 44 ns min WR Pulsewidth
t6 15 ns min Data Setup Time
t7 4.5 ns min Data Hold Time
t8 44 ns min WR Pulse Interval
t9 16 µs typ Settling Time
t10 300 ns max CLR Pulse Activation Time
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.

t1 t2

A0, A1, A2

t3 t4

CS

t8

WR t5
t7
t6

DATA

t9

VOUT

t 10
CLR

VOUT

Figure 1. Timing Diagram

REV. A –3–
AD7836
ABSOLUTE MAXIMUM RATINGS 1 MQFP Package, Power Dissipation . . . . . . . . . . . . . . 480 mW
(TA = +25°C unless otherwise noted) θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W
VCC to DGND . . . . . . . . . . . . . . .–0.3 V, +7 V or VDD + 0.3 V Lead Temperature, Soldering
(Whichever Is Lower) Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V NOTES
1
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +0.3 V Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
Digital Inputs to DGND . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V operation of the device at these or any other conditions above those indicated in
VREF(+) to VREF(–) . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V the operational section of this specification is not implied. Exposure to absolute
VREF(+) to AGND . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V maximum rating conditions for extended periods may affect device reliability.
2
VREF(–) to AGND . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V Transient currents of up to 100 mA will not cause SCR latch-up.
DUTGND to AGND . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
VOUT (A–D) to AGND . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

ORDERING GUIDE

Linearity
Temperature Error DNL Package
Model Range (LSBs) (LSBs) Option*
AD7836AS –40°C to +85°C ±2 ± 0.9 S-44
*S = Plastic Quad Flatpack (MQFP).

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD7836 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. A
 AD7836
PIN DESCRIPTION
Pin Mnemonic Description
VCC Logic Power Supply; +5 V ± 5%.
VSS Negative Analog Power Supply; –15 V ± 5%.
VDD Positive Analog Power Supply; +15 V ± 5%.
DGND Digital Ground.
AGND Analog Ground.
VREF(+)A, VREF(–)A Reference Inputs for DAC A. These reference voltages are referred to AGND.
VREF(+)B, VREF(–)B Reference Inputs for DAC B. These reference voltages are referred to AGND.
VREF(+)C, VREF(–)C Reference Inputs for DAC C. These reference voltages are referred to AGND.
VREF(+)D, VREF(–)D Reference Inputs for DAC D. These reference voltages are referred to AGND.
VOUTA . . . VOUTD DAC Outputs.
CS Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
DB0 . . . DB13 Parallel Data Inputs. The AD7836 can accept a straight 14-bit parallel word on DB0 to DB13 where
DB13 is the MSB and DB0 is the LSB.
A0, A1, A2 Address inputs. A0, A1 and A2 are decoded to select one of the five input latches for a data transfer.
CLR Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog outputs are
switched to the externally set potential on the DUTGND pin. The contents of data registers A to E are
not affected when the CLR pin is taken low. When CLR is brought back high, the DAC outputs revert
back to their original outputs as determined by the data in their data registers.
WR Level-Triggered Write Input (active low), when active and used in conjunction with CS to write data to
the AD7836 input buffer. Data is latched into the selected data register on the rising edge of WR.
DUTGND A Device Sense Ground for DAC A. Vout A is referenced to the voltage applied to this pin.
DUTGND B Device Sense Ground for DAC B. Vout B is referenced to the voltage applied to this pin.
DUTGND C Device Sense Ground for DAC C. Vout C is referenced to the voltage applied to this pin.
DUTGND D Device Sense Ground for DAC D. Vout D is referenced to the voltage applied to this pin.
SEL Select pin, active high level triggered input. When the SEL input is high, the user programmed value in
DATAREG E will be loaded into all DAC registers and the DAC outputs updated accordingly. The con-
tents of the other DATA REGs (A–D) will not be affected by the SEL pin.

PIN CONFIGURATION
DUTGND C

DUTGND D
VREF(+)D
VREF(–)D
VOUTD

DB13
DB12
DB11
DB10
DB9
DB8

33 32 31 30 29 28 27 26 25 24 23

VOUTC 34 22 DB7

VREF(–)C 35 21 DB6

VREF(+)C 36 20 DB5

AGND 37 19 DB4

NC 38 AD7836 18 DB3

VDD 39 TOP VIEW 17 DB2

(Not to Scale)
NC 40 16 DB1

VSS 41 15 DB0

VREF(+)A 42 14 DGND

VREF(–)A 43 PIN 1 13 VCC

IDENTIFIER
VOUTA 44 12 CLR

1 2 3 4 5 6 7 8 9 10 11
CS
VREF(+)B
VREF(–)B
VOUTB
DUTGND B
A2
A1
A0
SEL

WR
DUTGND A

NC = NO CONNECT

REV. A –5–
AD7836
TERMINOLOGY Full-Scale Error
Relative Accuracy This is the error in DAC output voltage when all 1s are loaded
Relative accuracy or endpoint linearity is a measure of the max- into the DAC latch. Ideally the output voltage, with all 1s
imum deviation from a straight line passing through the endpoints loaded into the DAC latch, should be 2 VREF(+) – 1 LSB. Full-
of the DAC transfer function. It is measured after adjusting for scale error does not include zero-scale error.
zero error and full-scale error and is normally expressed in Least Zero-Scale Error
Significant Bits or as a percentage of full-scale reading. Zero-scale error is the error in the DAC output voltage when all
Differential Nonlinearity 0s are loaded into the DAC latch. Ideally the output voltage,
Differential nonlinearity is the difference between the measured with all 0s in the DAC latch should be equal to 2 VREF(–). Zero-
change and the ideal 1 LSB change between any two adjacent scale error is mainly due to offsets in the output amplifier.
codes. A specified differential nonlinearity of 1 LSB maximum Gain Error
ensures monotonicity. Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error).
DC Crosstalk GENERAL DESCRIPTION
Although the common input reference voltage signals are inter- DAC Architecture—General
nally buffered, small IR drops in the individual DAC reference Each channel consists of a segmented 14-bit R-2R voltage-mode
inputs across the die can mean that an update to one channel DAC. The full-scale output voltage range is equal to twice the
can produce a dc output change in one or other of the channel reference span of VREF(+) – VREF(–). The DAC coding is
outputs. straight binary; all 0s produces an output of 2 VREF(–); all 1s
The four DAC outputs are buffered by op amps that share com- produces an output of 2 VREF(+) – 1 LSB.
mon VDD and VSS power supplies. If the dc load current changes The analog output voltage of each DAC channel reflects the
in one channel (due to an update), this can result in a further dc contents of its own DAC latch. Data is transferred from the ex-
change in one or other channel outputs. This effect is most ob- ternal bus to the input register of each DAC latch on a per
vious at high load currents and reduces as the load currents are channel basis. The AD7836 has a feature whereby using the A2
reduced. With high impedance loads the effect is virtually pin, data can be transferred from the input data bus to all four
unmeasurable. input registers simultaneously.
Output Voltage Settling Time Bringing the CLR line low switches all the signal outputs,
This is the amount of time it takes for the output to settle to a VOUTA to VOUTD, to the voltage level on the DUTGND pin.
specified level for a full-scale input change. When CLR signal is brought back high the output voltages from
Digital-to-Analog Glitch Impulse the DACs will reflect the data stored in the relevant DAC
This is the amount of charge injected into the analog output when registers.
the inputs change state. It is specified as the area of the glitch in Data Loading to the AD7836
nV-secs. It is measured with VREF(+) = +5 V and VREF(–) = –5 V Data is loaded into the AD7836 in straight parallel 14-bit wide
and the digital inputs toggled between 1FFFHEX and 8000H. words.
Channel-to-Channel Isolation The DAC output voltages, VOUTA–VOUTD are updated to
Channel-to-channel isolation refers to the proportion of input reflect new data in the DAC input registers.
signal from one DACs reference input that appears at the output
The actual DAC input register that is being written to is deter-
of the other DAC. It is expressed in dBs.
mined by the logic levels present on the devices address lines, as
DAC-to-DAC Crosstalk shown in Table I.
DAC-to-DAC crosstalk is defined as the glitch impulse that ap-
pears at the output of one converter due to both the digital Table I. Address Line Truth Table
change and subsequent analog O/P change at another converter.
It is specified in nV-s. A2 A1 A0 DAC Selected
Digital Crosstalk 0 0 0 DATA REG A (DAC A)
The glitch impulse transferred to the output of one converter 0 0 1 DATA REG B (DAC B)
due to a change in digital input code to the other converter is 0 1 0 DATA REG C (DAC C)
defined as the digital crosstalk and is specified in nV-s. 0 1 1 DATA REG D (DAC D)
Digital Feedthrough 1 0 0 DATA REG E
When the device is not selected, high frequency logic activity on 1 1 1 DATA REG A–D
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. This noise is digital feedthrough.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.

–6– REV. A
 Typical Performance Characteristics–AD7836
1.0 0.9 2
VDD = 15V
0.8
0.6 VSS = –15V
0.6 VREF(+) = +5V
0.4 1 VREF(–) = –5V

DNL ERROR – LSBs

0.4
INL ERROR – LSBs

INL ERROR – LSB

0.2
0.2
0.0 0.0 0

–0.2 –0.2

–0.4 –0.4
–1
–0.6 –0.6
–0.8
–1.0 –0.9 –2
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 –40 –20 0 20 40 60 80 90
INPUT CODE/1000 INPUT CODE/1000 TEMPERATURE – °C

Figure 2. Typical INL Plot Figure 3. Typical DNL Plot Figure 4. Typical INL Error vs.
Temperature

1.0 2 6
VDD = 15V DIGITAL INPUTS @ THRESHOLDS
VDD = 15V
VSS = –15V VSS = –15V 5
VREF(+) = +5V VREF(+) = +5V
0.5 VREF(–) = –5V 1 VREF(–) = –5V 4 VCC = 5V
DNL ERROR – LSB

ERROR – LSB

VDD = 15V
FULL-SCALE ERROR

ICC – mA
3 VSS = –15V
0 0
2

OFFSET ERROR 1
–0.5 –1 DIGITAL INPUTS @ SUPPLIES
0

–1.0 –2 –1
–40 –20 0 20 40 60 80 90 –40 –20 0 20 40 60 80 90 –40 –20 0 20 40 60 80 90
TEMPERATURE – °C TEMPERATURE – °C TEMPERATURE – °C

Figure 5. Typical DNL Error vs. Figure 6. Offset and Full-Scale Error Figure 7. ICC vs. Temperature
Temperature vs. Temperature

0.7 8
10.2
VERT = 100mV/DIV
0.6
HORIZ = 1s/DIV
0.5 10.0 7

0.4
IDD/ISS – mA

VDD = 15V
9.8 VSS = –15V
VOUT – V

0.3
6 VREF(+) = +5V
0.2 VREF(–) = –5V
9.6
0.1
5
0
9.4
–0.1
4
–0.2 9.2 –40 –20 0 20 40 60 80 90
11 12 13 14
TEMPERATURE – °C
SETTLING TIME – s
Figure 10. IDD/ISS vs. Temperature
Figure 8. Typical Digital/Analog Figure 9. Settling Time (+)
Glitch Impulse

REV. A –7–
AD7836
Unipolar Configuration When bipolar-zero and full-scale adjustment are not needed,
Figure 11 shows the AD7836 in the unipolar binary circuit con- R2 and R3 can be omitted. Pin 12 on the AD588 should be
figuration. The VREF(+) input of the DAC is driven by the connected to Pin 11 and Pin 5 should be left floating.
AD586, a +5 V reference. VREF(–) is tied to ground. Table II
gives the code table for unipolar operation of the AD7836. +15V +5V

Other suitable references include the REF02, a precision 5 V

R1
reference, and the REF195, a low dropout, micropower preci- 39k
sion +5 V reference. 4 6
7 VDD VCC
2
C1 VOUT VOUT
+15V +5V 3
1F 9 VREF(+) (–10V TO +10V)
1
AD588 AD7836*
R2 5 14 DUTGND
2 VDD VCC 100k 10 15
6 VOUT VREF(–) AGND
VREF(+) VOUT 11 16
8 (0 TO +10V) VSS DGND
AD586 AD7836*
5 R1
10k DUTGND R3 12 8 13
C1 SIGNAL
1nF 4 100k
AGND GND
–15V
VREF(–) DGND
VSS *ADDITIONAL PINS OMITTED FOR CLARITY
SIGNAL
GND
SIGNAL Figure 12. Bipolar ± 5 V Operation
GND
–15V
*ADDITIONAL PINS OMITTED FOR CLARITY Table III. Code Table for Bipolar Operation
Figure 11. Unipolar +5 V Operation Binary Number in DAC Latch Analog Output
Offset and gain may be adjusted in Figure 2 as follows: To ad- MSB LSB (VOUT)
just offset, disconnect the VREF(–) input from 0 V, load the DAC
with all 0s and adjust the VREF(–) voltage until VOUT = 0 V. For 11 1111 1111 1111 2[VREF(–) + VREF (16383/16384)] V
gain adjustment, the AD7836 should be loaded with all 1s and 10 0000 0000 0001 2[VREF(–) + VREF (8193/16384)] V
R1 adjusted until VOUT = 10 V(16383/16384) = 9.999389. 10 0000 0000 0000 2[VREF(–) + VREF (8192/16384)] V
01 1111 1111 1111 2[VREF(–) + VREF (8191/16384)] V
Many circuits will not require these offset and gain adjustments. In 00 0000 0000 0001 2[VREF(–) + VREF (1/16384)] V
these circuits R1 can be omitted. Pin 5 of the AD586 may be left 00 0000 0000 0000 2[VREF(–)] V
open circuit and Pin 2 (VREF(–)) of the AD7836 tied to 0 V.
NOTE
VREF = (VREF(+) – VREF(–)).
Table II. Code Table for Unipolar Operation For VREF(+) = +5 V, and V REF(–) = –5 V, V REF =10 V, 1 LSB = 2 VREF V/2 14
= 20 V/16384 = 1220 µV.
Binary Number in DAC Latch Analog Output
MSB LSB (VOUT) CONTROLLED POWER-ON OF THE OUTPUT STAGE
11 1111 1111 1111 2 VREF (16383/16384) V A block diagram of the output stage of the AD7836 is shown in
10 0000 0000 0000 2 VREF (8192/16384) V Figure 13. It is capable of driving a load of 5 kΩ in parallel
01 1111 1111 1111 2 VREF (8191/16384) V with 50 pF. G1 to G6 are transmission gates that are used to
00 0000 0000 0001 2 VREF (1/16384) V control the power on voltage present at VOUT. On power up G1
00 0000 0000 0000 0V and G2 are also used in conjunction with the CLR input to set
VOUT to the user defined voltage present at the DUTGND pin.
NOTE
When CLR is taken back high the DAC outputs reflect the data
VREF = VREF(+); VREF(–) = 0 V for unipolar operation.
For VREF(+) = +5 V, 1 LSB = +10 V/2 14 = +10 V/16384 = 610 µV. in the DAC registers.
Bipolar Configuration G1
Figure 12 shows the AD7836 set up for ± 10 V operation. The DAC G6
AD588 provides precision ± 5 V tracking outputs that are fed to VOUT
the VREF(+) and VREF(–) inputs of the AD7836. The code table G3
for bipolar operation of the AD7836 is shown in Table III.
G2 G4
In Figure 12, full-scale and bipolar zero adjustments are pro- R = 13.5k
vided by varying the gain and balance on the AD588. R2 varies
the gain on the AD588 while R3 adjusts the offset of both the R G5
6k
+5 V and –5 V outputs together with respect to ground.
For bipolar-zero adjustment, the DAC is loaded with DUTGND

1000 . . . 0000 and R3 is adjusted until VOUT = 0 V. Full scale Figure 13. Block Diagram of AD7836 Output Stage
is adjusted by loading the DAC with all 1s and adjusting R2 un-
til VOUT = 10(8191/8192) V = 9.998779 V.

–8– REV. A
 AD7836
Power-On with CLR Low G1
G6
The output stage of the AD7836 has been designed to allow DAC
VOUT
output stability during power-on. If CLR is kept low during
G3
power-on, then just after power is applied to the AD7836, the
situation is as depicted in Figure 14. G1, G4 and G6 are open
G2 G4
while G2, G3 and G5 are closed. R

G1 R G5
6k
DAC G6
VOUT
DUTGND
G3

Figure 16. Output Stage After CLR Is Taken High

G2 G4
R Power-On with CLR High
If CLR is high on the application of power to the device, the
R G5
6k output stages of the AD7836 are configured as in Figure 17
while VDD/VSS are less than ± 10 V. G1 is closed and G2 is open
DUTGND thereby connecting the output of the DAC to the input of its
output amplifier. G3 and G5 are closed while G4 and G6 are
Figure 14. Output Stage with VDD < 10 V
open thus connecting the output amplifier as a unity gain
VOUT is kept within a few hundred millivolts of DUTGND via buffer. VOUT is connected to DUTGND via G5 through a 6 kΩ
G5 and a 6kΩ resistor. This thin-film resistor is connected in resistor until VDD and VSS reach approximately ± 10 V.
parallel with the gain resistors of the output amplifier. The out-
put amplifier is connected as a unity gain buffer via G3, and the G1
G6
DUTGND voltage is applied to the buffer input via G2. The DAC
VOUT
amplifier’s output is thus at the same voltage as the DUTGND
G3
pin. The output stage remains configured as in Figure 14 until
the voltage at VDD and VSS reaches approximately ± 10 V. By
G2 G4
now the output amplifier has enough headroom to handle sig- R
nals at its input and has also had time to settle. The internal
power-on circuitry opens G3 and G5 and closes G4 and G6. This R G5
6k
situation is shown in Figure 15. Now the output amplifier is
configured in its noise gain configuration via G4 and G6. The DUTGND
DUTGND voltage is still connected to the noninverting input
via G2 and this voltage appears at VOUT. Figure 17. Output Stage Powering Up with CLR High
While VDD/VSS < ± 10 V
G1 When the supplies reach ± 10 V, the internal power on circuitry
DAC G6
VOUT
opens G3 and G5 and closes G4 and G6 configuring the output
stage as shown in Figure 18.
G3

G1
G2 G4 G6
R DAC
VOUT

R G5 G3
6k

G2 G4
DUTGND R

Figure 15. Output Stage with VDD > 10 V and CLR Low R G5
6k
VOUT has been disconnected from the DUTGND pin by the
opening of G5 but will track the voltage present at DUTGND DUTGND
via the configuration shown in Figure 15.
Figure 18. Output Stage Powering Up with CLR High
When CLR is taken back high, the output stage is configured as
When VDD/VSS > ± 10 V
shown in Figure 16. The internal control logic closes G1 and
opens G2. The output amplifier is connected in a noninverting
gain of two configuration. The voltage that appears on the Vout
pins is determined by the data present in the DAC registers. To
set all output voltages to the same known state, a write to
DATA REG E with the SEL pin high allows all DAC registers
to be updated with the same data.

REV. A –9–
AD7836
DUTGND Voltage Range APPLICATIONS
During power-on, the VOUT pins of the AD7836 are connected Power Supply Bypassing and Grounding
to the relevant DUTGND pins via G6 and the 6 kΩ thin-film In any circuit where accuracy is important, careful consider-
resistor. The DUTGND potential must obey the max ratings at ation of the power supply and ground return layout helps to
all times. Thus, the voltage at DUTGND must always be ensure the rated performance. The printed circuit board on
within the range VSS – 0.3 V, VDD + 0.3 V. However, in order which the AD7836 is mounted should be designed such that
that the voltages at the VOUT pins of the AD7836 stay within the analog and digital sections are separated and confined to
± 2 V of the relevant DUTGND potential during power-on, the certain areas of the board. This facilitates the use of ground
voltage applied to DUTGND should also be kept within the planes that can be separated easily. A minimum etch tech-
range AGND – 2 V, AGND + 2 V. nique is generally best for ground planes as it gives the best
Once the AD7836 has powered on and the on-chip amplifiers shielding. Digital and analog ground planes should only be
have settled, any voltage that is now applied to the DUTGND joined at one place. If the AD7836 is the only device requiring
pin is subtracted from the DAC output which has been gained an AGND to DGND connection, then the ground planes
up by a factor of two. Thus, for specified operation, the maxi- should be connected at the AGND and DGND pins of the
mum voltage that can be applied to the DUTGND pin increases AD7836. If the AD7836 is in a system where multiple devices
to the maximum allowable 2 × VREF(+) voltage, and the mini- require an AGND to DGND connection, the connection
mum voltage that can be applied to DUTGND is the minimum should still be made at one point only, a star ground point
2 × VREF(–) voltage. After the AD7836 has fully powered on, which should be established as close as possible to the
the outputs can track any DUTGND voltage within this AD7836.
minimum/maximum range. Digital lines running under the device should be avoided as
MICROPROCESSOR INTERFACING these will couple noise onto the die. The analog ground plane
Interfacing the AD7836—16-Bit Interface should be allowed to run under the AD7836 to avoid noise
The AD7836 can be interfaced to a variety of 16-bit micro- coupling. The power supply lines of the AD7836 should use
controllers or DSP processors. Figure 19 shows the AD7836 as large a trace as possible to provide low impedance paths and
interfaced to a generic 16-bit microcontroller/DSP processor. reduce the effects of glitches on the power supply line. Fast
The lower address lines from the processor are connected to switching signals like clocks should be shielded with digital
A0, A1 and A2 on the AD7836 as shown. The upper address ground to avoid radiating noise to other parts of the board and
lines are decoded to provide a chip select signal for the should never be run near the analog inputs.
AD7836. They are also decoded (in conjunction with the lower Avoid crossover of digital and analog signals. Traces on oppo-
address lines if need be) to provide a SEL signal. The fast inter- site sides of the board should run at right angles to each other.
face timing of the AD7836 allows direct interface to a wide vari- This reduces the effects of feedthrough through the board. A
ety of microcontrollers and DSPs as shown in Figure 19. microstrip technique is by far the best but not always possible
with a double sided board. In this technique, the component
CONTROLLER/ side of the board is dedicated to ground plane while signal
DSP AD7836* traces are placed on the solder side.
PROCESSOR*

D13 D13
The AD7836 should have ample supply bypassing located as
DATA • • close to the package as possible, ideally right up against the
• •
BUS • •
D0 D0 device. Figure 20 shows the recommended capacitor values of
10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF
UPPER BITS OF
ADDRESS BUS ADDRESS CS capacitors are the tantalum bead type. The 0.1 µF capacitor
DECODE
should have low Effective Series Resistance (ESR) and Effec-
A2 A2
tive Series Inductance (ESI), such as the common ceramic
A1 A1 types, which provide a low impedance path to ground at high
A0 A0 frequencies to handle transient currents due to internal logic
R/W WR
switching.
*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 19. AD7836 Parallel Interface VCC VDD

0.1F 10F 10F 0.1F
AD7836

VSS
10F 0.1F

Figure 20. Recommended Decoupling Scheme

for AD7836

–10– REV. A
 AD7836
Automated Test Equipment Programmable Reference Generation for the AD7836 in an
The AD7836 is particularly suited for use in an automated test ATE Application
environment. Figure 21 shows the AD7836 providing the nec- The AD7836 is particularly suited for use in an automated test
essary voltages for the pin driver and the window comparator in environment. The reference input for the AD7836 quad 14-bit
a typical ATE pin electronics configuration. AD588s are used DAC requires two references for each DAC. Programmable
to provide reference voltages for the AD7836. In the configu- references may be a requirement in some ATE applications as
ration shown, the AD588s are configured so that the voltage at the offset and gain errors at the output of each DAC can be ad-
Pin 1 is 5 V greater than the voltage at Pin 9 and the voltage at justed by varying the voltages on the reference pins of the DAC.
Pin 15 is 5 V less than the voltage at Pin 9. To trim offset errors, the DAC is loaded with the digital code
000 . . . 000 and the voltage on the VREF(–) pin is adjusted until
+15V –15V VOFFSET the desired negative output voltage is obtained. To trim out
2 16 gain errors, first the offset error is trimmed. Then the DAC is
4 3 +15V loaded with the code 111 . . . 111 and the voltage on the
6 1
8
VREF(+)A/B
VOUTA
VREF(+) pin is adjusted until the desired full scale voltage
15
13 AD588
14
VREF(–)A/B PIN minus one LSB is obtained.
DRIVER
7
1F 9 VOUTB It is not uncommon in ATE design, to have other circuitry at
DUTGND A/B
0.1F –15V
the output of the AD7836 that can have offset and gain errors
10 11 12 AD7836* of up to say ± 300 mV. These offset and gain errors can be eas-
DUTGND C/D
ily removed by adjusting the reference voltages of the AD7836.
+15V –15V VOUT
DEVICE
GND The AD7836 uses nominal reference values of ± 5 V to achieve
4
2 16
VOUTC an output span of ± 10 V. Since the AD7836 has a gain of two
3
6 1 DEVICE
from the reference inputs to the DAC output, adjusting the ref-
8
15
VREF(+)C/D
VOUTD GND erence voltages by ± 150 mV will adjust the DAC offset and
13
AD588 14
VREF(–)C/D gain by ± 300 mV.
10
11
AGND There are a number of suitable 8- and 10-bit DACs available
12
that would be suitable to drive the reference inputs of the
7 8 WINDOW AD7836, such as the AD7804 which is a quad 10-bit digital-to-
1F DEVICE COMPARATOR
GND TO TESTER analog converter with serial load capabilities. The voltage out-
*ADDITIONAL PINS OMITTED FOR CLARITY put from this DAC is in the form of VBIAS ± VSWING and rail to
rail operation is achievable. The voltage reference for this DAC
Figure 21. ATE Application
can be internally generated or provided externally. This DAC
One of the AD588s is used as a reference for DACs 1 and 2. also contains an 8-bit SUB DAC which can be used to shift the
These DACs are used to provide high and low levels for the pin complete transfer function of each DAC around the VBIAS
driver. The pin driver may have an associated offset. This can point. This can be used as a fine trim on the output voltage. In
be nulled by applying an offset voltage to Pin 9 of the AD588. this Application two AD7804s are required to provide program-
First, the code 1000 . . . 0000 is loaded into the DACA latch mable reference capability for all four DACs. One AD7804 is
and the pin driver output is set to the DACA output. The used to drive the VREF(+) pins and the second package used to
VOFFSET voltage is adjusted until 0 V appears between the pin drive the VREF(–) pins.
driver output and DUT GND. This causes both VREF(+) and
Another suitable DAC for providing programmable reference
VREF(–) to be offset with respect to AGND by an amount equal
capability is the AD8803. This is an octal 8-bit trimDAC® and
to VOFFSET. However, the output of the pin driver will vary
provides independent control of both the top and bottom ends
from –10 V to +10 V with respect to DUT GND as the DAC
of the trimDAC. This is helpful in maximizing the resolution of
input code varies from 000 . . . 000 to 111 . . . 111. The
devices with a limited allowable voltage control range.
VOFFSET voltage is also applied to the DUTGND pins. When a
clear is performed on the AD7836, the output of the pin driver The AD8803 has an output voltage range of GND to VDD (0 V to
will be 0 V with respect to Device GND. +5 V). To trim the VREF(+) input, the appropriate trim range
on the AD8803 DAC can be set using the VREFL and VREFH
The other AD588 is used to provide a reference voltage for
pins allowing 8 bits of resolution between the two points. This
DACs C and D. These provide the reference voltages for the
will allow the VREF(+) pin to be adjusted to remove gain errors.
window comparator shown in the diagram. Note that Pin 9 of
this AD588 is connected to Device GND. This causes To trim the VREF(–) voltage, some method of providing a trim
VREF(+)C & D and VREF(–)C & D to be referenced to Device voltage in the required negative voltage range is required. Nei-
GND. As DAC 3 and DAC 4 input codes vary from ther the AD7804 or the AD8803 can provide this range in nor-
000 . . . 000 to 111 . . . 111, VOUT3 and VOUT4 vary from –10 V mal operation as their output range is 0 V to +5 V. There are
to +10 V with respect to Device GND. Device GND is also two methods of producing this negative voltage. One method is
connected to DUTGND. When the AD7836 is cleared, to provide a positive output voltage and then to level shift that
VOUTC and VOUTD are cleared to 0 V with respect to DEVICE analog voltage to the required negative range. Alternatively
GND.
TrimDAC is a registered trademark of Analog Devices, Inc.

REV. A –11–
AD7836
these DACs can be operated with supplies of 0 V and a –5 V, the digital signals driving the DACs need to be level shifted
with the VDD pin connected to 0 V and the GND pin connected from the 0 V to +5 V range to the –5 V to 0 V range. Figure 22
to –5 V. Now these can be used to provide the negative refer- shows a typical application circuit to provide programmable ref-
ence voltages for the VREF(–) inputs on the AD7836. However, erence capabilities for the AD7836.

C2163a–0–9/99
ADDR BUS

+5V

ADDR
DECODER 8/10-BIT VDD
FSIN/CS DAC
A0,A1,A2
DIN 0V to 5V
SDATA VREF(+)A
SCLK VOUTA VOUT
SCLK
GND

LOGIC LEVEL AD7836*

CONTROLLER SHIFT

8/10-BIT VDD
FSIN/CS DAC

DIN 0V to -5V
VREF(–) A
SCLK

GND

–5V

DATA BUS DATA BUS

AGND
*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 22. Programmable Reference Generation for the AD7836

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

44-Lead MQFP (S-44)

0.548 (13.925)
0.546 (13.875)
0.096 (2.44)
MAX 0.398 (10.11)
0.390 (9.91)
0.037 (0.94)
0.025 (0.64) 8
0.8 33 23
34 22
SEATING
PLANE

PRINTED IN U.S.A.
TOP VIEW
(PINS DOWN)

44 12

0.040 (1.02) 1 11
0.040 (1.02) 0.032 (0.81)
0.032 (0.81)
0.033 (0.84) 0.016 (0.41)
0.083 (2.11) 0.029 (0.74) 0.012 (0.30)
0.077 (1.96)

–12– REV. A