Fully Accurate 16-Bit VOUT nanoDAC™

SPI Interface 2.7 V to 5.5 V, in an SOT-23

AD5062
FEATURES FUNCTIONAL BLOCK DIAGRAM
VREF VDD
Single 16-bit DAC, 1 LSB INL
Power-on reset to midscale or zero-scale
POWER-ON AD5062
Guaranteed monotonic by design RESET
BUF

3 power-down functions
Low power serial interface with Schmitt-triggered inputs REF(+)
DAC
VOUT
Tiny 8-lead SOT-23 package, low power REGISTER DAC

Fast settling time of 4 μs typically

2.7 V to 5.5 V power supply
AGND
Low glitch on power-up INPUT
POWER-DOWN
CONTROL RESISTOR
Unbuffered voltage capable of driving 60 kΩ load LOGIC
CONTROL LOGIC
NETWORK
SYNC interrupt facility

04766-001
APPLICATIONS
Process control SYNC SCLK DIN DACGND

Data acquisition systems Figure 1.

Portable battery-powered instruments
Digital gain and offset adjustment Table 1. Related Devices
Programmable voltage and current sources Part No. Description
Programmable attenuators AD5061 2.7 V to 5.5 V, 16-bit nanoDAC D/A,
4 LSBs INL, SOT-23.
AD5063 2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, MSOP.
AD5040/AD5060 2.7 V to 5.5 V, 14-/16-bit nanoDAC D/A,
1 LSB INL, SOT-23.

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The AD5062, a member of ADI’s nanoDAC family, is a low 1. Available in a tiny 8-lead SOT-23 package.
power, single 16-bit unbuffered voltage-out DAC that operates 2. 16-bit accurate, 1 LSB INL.
from a single 2.7 V to 5.5 V supply. The part offers a relative 3. Low glitch on power-up.
accuracy specification of ±1 LSB, and operation is guaranteed
4. High speed serial interface with clock speeds up to 30 MHz.
monotonic with a ±1 LSB DNL specification. The part uses a
5. Three power-down modes available to the user.
versatile 3-wire serial interface that operates at clock rates up
to 30 MHz, and is compatible with standard SPI®, QSPI™, 6. Reset to known output voltage (zero-scale or mid-scale).
MICROWIRE™, and DSP interface standards. The reference for
the AD5062 is supplied from an external VREF pin. A reference
buffer is also provided on-chip. The part incorporates a power-
on reset circuit that ensures the DAC output powers up to zero
scale or mid-scale and remains there until a valid write takes
place to the device. The part contains a power-down feature
that reduces the current consumption of the device to typically
300 nA at 5 V and provides software-selectable output loads
while in power-down mode. The part is put into power-down
mode over the serial interface. Total unadjusted error for the
part is <0.8 mV.
This part exhibits very low glitch on power-up.

Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.
AD5062

TABLE OF CONTENTS
Features .............................................................................................. 1 Reference Buffer ......................................................................... 14
Applications ....................................................................................... 1 Serial Interface ............................................................................ 14
Functional Block Diagram .............................................................. 1 Input Shift Register .................................................................... 14
General Description ......................................................................... 1 SYNC Interrupt .......................................................................... 14
Product Highlights ........................................................................... 1 Power-On to Midscale or Zero Scale ....................................... 15
Revision History ............................................................................... 2 Software Reset ............................................................................. 15
Specifications..................................................................................... 3 Power-Down Modes .................................................................. 15
Timing Characteristics..................................................................... 5 Microprocessor Interfacing ....................................................... 15
Absolute Maximum Ratings............................................................ 6 Applications..................................................................................... 17
ESD Caution .................................................................................. 6 Choosing a Reference for the AD5062 .................................... 17
Pin Configuration and Function Descriptions ............................. 7 Bipolar Operation Using the AD5062 ..................................... 17
Typical Performance Characteristics ............................................. 8 Using AD5062 with a Galvanically Isolated Interface Chip . 18
Terminology .................................................................................... 13 Power Supply Bypassing and Grounding ................................ 18
Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 19
DAC Architecture ....................................................................... 14 Ordering Guide .......................................................................... 19

REVISION HISTORY
5/09—Rev. 0 to Rev. A
Changes to Figure 43 ...................................................................... 17

7/05—Revision 0: Initial Version

Rev. A | Page 2 of 20
 AD5062

SPECIFICATIONS
VDD = 5.5 V, VREF = 4.096 V, RL = Unloaded, CL = 22 pF to GND; TMIN to TMAX, unless otherwise noted.

Table 2.
A,B Grade 1
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 16 Bits
Relative Accuracy (INL) 2 ±0.5 ±1 LSB −40°C to +85°C, B grade
±0.5 ±2 −40°C to +85°C, A grade
Total Unadjusted Error (TUE) ±500 ±800 μV −40°C to +85°C, B grade
±500 ±800 −40°C to +85°C, A grade
Differential Nonlinearity (DNL) ±0.5 ±1 LSB Guaranteed monotonic
−40°C to +85°C, B grade
±0.5 ±1 Guaranteed monotonic
−40°C to +85°C, A grade
Gain Error ±0.01 ±0.02 % of FSR TA = −40°C to +85°C B grade
±0.01 ±0.02 TA = −40°C to +85°C A grade
Gain Error Temperature Coefficient 1 ppm of FSR/°C
Offset Error ±0.025 ±0. 05 mV TA = −40°C to + 85°C, B grade
±0.025 ±0. 05 TA = −40°C to + 85°C, A grade
Offset Error Temperature Coefficient 0.5 μV/°C
Full-Scale Error ±500 ±800 μV All 1s loaded to DAC register, B grade
TA = −40°C to +85°C
±500 ±800 All 1s loaded to DAC register, A grade
TA = −40°C to +85°C
OUTPUT CHARACTERISTICS 3
Output Voltage Range 0 VREF V Unipolar operation
Output Voltage Settling Time 4 μs ¼ scale to ¾ scale code transition to
±1LSB.
Output Noise Spectral Density 24 nV/√Hz DAC code = midscale, 1 kHz
Output Voltage Noise 6 μV p-p DAC code = midscale, 0.1 to 10 Hz
bandwidth
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry
Digital Feedthrough 0.1 nV-s
DC Output Impedance (Normal) 8 kΩ Output impedance tolerance ±20%
DC Output Impedance (Power-Down)
(Output Connected to 1 kΩ Network) 1 kΩ Output impedance tolerance ±20%
(Output Connected to 100 kΩ Network) 100 kΩ Output impedance tolerance ±20%
REFERENCE INPUT/ OUTPUT
VREF Input Range2 2 VDD − 50 mV
Input Current (Power-Down) ±0.1 μA Zero-scale loaded
Input Current (Normal) ±0. 5 μA
DC Input Impedance 1 MΩ Bipolar/unipolar operation
LOGIC INPUTS
Input Current 4 ±1 ±2 μA
VIL, Input Low Voltage 0.8 V VDD = 4.5 V to 5.5 V
0.8 VDD = 2.7 V to 3.6 V
VIH, Input High Voltage 2.0 V VDD = 2.7 V to 5.5 V
1.8 VDD = 2.7 V to 3.6 V
Pin Capacitance 4 pF

Rev. A | Page 3 of 20
AD5062
A,B Grade 1
Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS
VDD 2.7 5.5 V All digital inputs at 0 V or VDD
IDD (Normal Mode) DAC active and excluding load current
VDD = 2.7 V to 5.5 V 0.65 0.7 mA VIN = VDD and VIL = GND, VDD = 5.5 V,
VREF = 4.096 V, code = midscale
IDD (All Power-Down Modes)
VDD = 2.5 V to 5.5 V 1 μA VIH = VDD and VIL = GND VDD = 5.5 V,
VREF = 4.096 V, code = midscale
Power Supply Rejection Ratio (PSRR) 0.5 LSB ∆VDD ± 10%, VDD = 5 V, unloaded
1
Temperature range for the B grade: −40°C to +85°C, typical at 25°C; temperature range for the Y grade: −40°C to +125°C.
2
Refer to Figure 27, Figure 28, Figure 29, Figure 30, and Figure 31 for device performance under lower supply and reference voltage conditions.
3
Guaranteed by design and characterization, not production tested.
4
Total current flowing into all pins.

Rev. A | Page 4 of 20
 AD5062

TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.
Parameter Limit 1 Unit Test Conditions/Comments
t1 2 33 ns min SCLK cycle time
t2 5 ns min SCLK high time
t3 3 ns min SCLK low time
t4 10 ns min SYNC to SCLK falling edge setup time
t5 3 ns min Data setup time
t6 2 ns min Data hold time
t7 0 ns min SCLK falling edge to SYNC rising edge
t8 12 ns min Minimum SYNC high time
t9 9 ns min SYNC rising edge to next SCLK fall ignore
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 30 MHz.

t4 t2 t1 t9

SCLK
t8 t3 t7
SYNC

t6
t5

04766-002
DIN D23 D22 D2 D1 D0 D23 D22

Figure 2. Timing Diagram

Rev. A | Page 5 of 20
AD5062

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings
Table 4. may cause permanent damage to the device. This is a stress
Parameter Rating rating only and functional operation of the device at these or
VDD to GND −0.3 V to +7.0 V any other conditions above those indicated in the operational
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute
VOUT to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect
VREF to GND −0.3 V to VDD + 0.3 V device reliability.
Operating Temperature Range
This device is a high performance integrated circuit with an
Industrial (B grade) −40°C to +85°C
ESD rating of <2 kV, and is ESD-sensitive. Proper precautions
Storage Temperature Range −65°C to +150°C
should be taken for handling and assembly.
Maximum Junction Temperature 150°C
SOT-23 Package
Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance 206°C/W
θJc Thermal Impedance 44°C/W
Reflow Soldering (Pb-free)
Peak Temperature 260°C
Time-at-Peak Temperature 10 sec to 40 sec
ESD 1 kV

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 20
 AD5062

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DIN 1 8 SCLK
AD5062
VDD 2 TOP VIEW 7 SYNC
(Not to Scale)
VREF 3 6 DACGND

04766-003
VOUT 4 5 AGND

Figure 3.

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
2 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND.
3 VREF Reference Voltage Input.
4 VOUT Analog Output Voltage from DAC.
5 AGND Ground Reference Point for Analog Circuitry.
6 DACGND Ground Input to the DAC.
7 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
8 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.

Rev. A | Page 7 of 20
AD5062

TYPICAL PERFORMANCE CHARACTERISTICS

1.6 1.2
TA = 25°C VDD = 5.5V, VREF = 4.096V
1.4 1.0
VDD = 5V, VREF = 4.096V VDD = 2.7V, VREF = 2.0V
1.2 MAX INL @ VDD = 5.5V
0.8
1.0
0.8 0.6
0.6 0.4
INL ERROR (LSB)

INL ERROR (LSB)

0.4 MAX INL @ VDD = 2.7V
0.2
0.2
0 0 MIN INL @ VDD = 5.5V
–0.2 –0.2
–0.4
–0.4
–0.6
–0.8 –0.6
MIN INL @ VDD = 2.7V
–1.0 –0.8
–1.2
04766-004

04766-007
–1.0
–1.4
–1.6 –1.2
0 10000 20000 30000 40000 50000 60000 –40 –20 0 20 40 60 80 100
DAC CODE TEMPERATURE (°C)

Figure 4. Typical INL Plot Figure 7. INL vs. Temperature

0.15 1.2
TA = 25°C
VDD = 5.5V, VREF = 4.096V
0.12 VDD = 5V, VREF = 4.096V 1.0 VDD = 2.7V, VREF = 2.0V
0.8
0.09
0.6
0.06
0.4 MAX DNL @ VDD = 5.5V
TUE ERROR (mV)

DNL ERROR (LSB)

0.03
0.2
0 0
MAX DNL @ VDD = 2.7V
–0.03 –0.2
MIN DNL @ VDD = 2.7V
–0.4
–0.06
–0.6
–0.09
–0.8 MIN DNL @ VDD = 5.5V
04766-005

–0.12

04766-008
–1.0
–0.15 –1.2
0 10000 20000 30000 40000 50000 60000 –40 –20 0 20 40 60 80 100
DAC CODE TEMPERATURE (°C)

Figure 5. Typical TUE Plot Figure 8. DNL vs. Temperature

1.5 1.2
TA = 25°C
1.3 V = 5V, V VDD = 5.5V, VREF = 4.096V
DD REF = 4.096V 1.0 VDD = 2.7V, VREF = 2.0V
1.1
0.8
0.9
0.7 0.6
0.5 0.4 MAX TUE @ VDD = 5.5V
DNL ERROR (LSB)

TUE ERROR (mV)

0.3 MAX TUE @ VDD = 2.7V

0.2
0.1
0
–0.1
–0.3 –0.2
–0.5 –0.4
–0.7 MIN TUE @ VDD = 5.5V
–0.6
–0.9 MIN TUE @ VDD = 2.7V
–0.8
–1.1
04766-006

04766-009

–1.3 –1.0
–1.5 –1.2
0 10000 20000 30000 40000 50000 60000 –40 –20 0 20 40 60 80 100
DAC CODE TEMPERATURE (°C)

Figure 6. Typical DNL Plot Figure 9. TUE vs. Temperature

Rev. A | Page 8 of 20
 AD5062
1.6 0.040
TA = 25°C V = 5.5V, V = 4.096V
1.4 0.035 VDD = 2.7V, VREF = 2.0V
DD REF
1.2 0.030
1.0 0.025
MAX INL ERROR @ VDD = 5.5V
0.8 0.020
0.6 0.015
INL ERROR (LSB)

0.4 0.010

OFFSET (mV)
0.2 0.005 MAX OFFSET @ VDD = 5.5V
0 0
–0.2 –0.005
–0.4 –0.010 MAX OFFSET @ VDD = 2.7V
MIN INL ERROR @ VDD = 5.5V
–0.6 –0.015
–0.8 –0.020
–1.0 –0.025
–1.2 –0.030

04766-010

04766-013
–1.4 –0.035
–1.6 –0.040
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –40 –20 0 20 40 60 80 100
REFERENCE VOLTAGE (V) TEMPERATURE (°C)

Figure 10. INL vs. Reference Input Voltage Figure 13. Offset vs. Temperature

0.8 1.0
TA = 25°C TA = 25°C
0.7
0.6 0.9 CODE = MID-SCALE
0.5
0.8
0.4 VDD = 5.5V, VREF = 4.096V

SUPPLY CURRENT (mA)

0.3 0.7
DNL ERROR (LSB)

MAX DNL ERROR @ VDD = 5.5V

0.2
0.6
0.1
VDD = 5.0V, VREF = 4.096V
0 0.5
–0.1
–0.2 0.4
VDD = 3.0V, VREF = 2.5V
–0.3
0.3
–0.4 MIN DNL ERROR @ VDD = 5.5V
–0.5 0.2
–0.6
04766-011

04766-014
0.1
–0.7
–0.8 0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –40 –20 0 20 40 60 80 100
REFERENCE VOLTAGE (V) TEMPERATURE (°C)

Figure 11. DNL vs. Reference Input Voltage Figure 14. Supply Current vs. Temperature

1.0
1.0
TA = 25°C TA = 25°C
0.8
0.9 CODE = MID-SCALE
0.6
0.8
0.4
0.7
TUE ERROR (mV)

VDD = 5.5V, VREF = 4.096V

0.2
MAX TUE ERROR @ VDD = 5.5V 0.6
IDD (mA)

0
0.5
MIN TUE ERROR @ VDD = 5.5V VDD = 3.0V, VREF = 2.5V
–0.2
0.4
–0.4
0.3
–0.6 0.2
04766-012

–0.8
04766-015

0.1
–1.0
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0 10000 20000 30000 40000 50000 60000 70000
REFERENCE VOLTAGE (V)
DAC CODE

Figure 12. TUE vs. Reference Input Voltage Figure 15. Supply Current vs. Digital Input Code

Rev. A | Page 9 of 20
AD5062
1.0
VREF = 2.5V
TA = 25°C CH3 = SCLK
0.9
CODE = MID-SCALE
0.8
SUPPLY CURRENT (mA)

0.7

0.6

0.5

0.4 CH2 = VOUT

0.3

0.2
CH1 = TRIGGER

04766-019
04766-016
0.1

0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 CH1 2V/DIV CH2 2V/DIV CH3 2V TIME BASE = 5.00μs
SUPPLY VOLTAGE (V)

Figure 16. Supply Current vs. Supply Voltage Figure 19. Exiting Power-Down @ VDD=3.0 V

24TH CLOCK FALLING VDD = 3V

DAC= FULL SCALE
VREF = 2.7V
TA = 25°C

CH1 = SCLK

CH2 = VOUT

04766-020
04766-017

Y AXIS = 2μV/DIV
X AXIS = 4s/DIV

CH2 50mV/DIV CH1 2V/DIV TIME BASE 400ns/DIV

Figure 17. Digital-to-Analog Glitch Impulse; See Figure 21 Figure 20. 0.1 Hz to 10 Hz Noise Plot

300 VDD = 5V
VDD = 5V VREF = 4.096
TA = 25°C TA = 25°C
VREF = 4.096V 10ns/SAMPLE
NOISE SPECTRAL DENSITY (nv/ Hz)

250
AMPLITUDE (200μV/DIV)

200

150

FULL SCALE
100 MIDSCALE

50 ZERO SCALE
04766-021
04766-018

0 0 50 100 150 200 250 300 350 400 450 500

100 1000 10000 100000 1000000 SAMPLES
FREQUENCY (Hz)

Figure 21. Glitch Energy

Figure 18. Output Noise Spectral Density

Rev. A | Page 10 of 20
 AD5062
0.010
VDD = 5.5V VREF = 4.096V
0.008 VDD = 2.7V VREF = 2.0V

0.006

0.004 CH1 = VDD

GAIN ERROR (%fsr)

0.002

0
GAIN ERROR @ VDD = 5.5V
–0.002

–0.004 CH2 = VOUT

–0.006
VDD = 5V VREF = 4.096VDD
GAIN ERROR @ VDD = 2.7V

04766-025
RAMP RATE = 200μs

04766-010
–0.008
TA = 25°C
–0.010
–40 –20 0 20 40 60 80 100 120 140 CH1 2V/DIV CH2 1V/DIV TIME BASE = 100μs
TEMPERATURE (°C)

Figure 22. Gain Error vs. Temperature Figure 25. Hardware Power-Down Glitch

16
CH1 = SCLK
14

12 CH2 = SYNC

10
FREQUENCY

6
CH3 = VOUT
4

VDD = 5V VREF = 4.096VDD

04766-026
2 TA = 25°C
04766-081

CH4 = TRIGGER

0 CH1 2V/DIV CH2 2V/DIV CH3 20mV/DIV CH4 2V/DIV

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 MORE TIME BASE 1μs/DIV
BIN

Figure 26. Exiting Software Power-Down Glitch

Figure 23. IDD Histogram @ VDD = 3 V

1.2
16 TA = 25°C
1.0 VDD = 5.5V

14 0.8
MAX INL @ VDD = 5.5V
0.6
12
0.4
INL ERROR (LSB)

10 0.2
FREQUENCY

0
8
–0.2

6 –0.4
MIN INL @ VDD = 5.5V
–0.6
4
–0.8
04766-083

2 –1.0
04766-082

–1.2
0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
0.60 0.61 0.62 0.63 0.64 0.65 MORE REFERENCE VOLTAGE (V)
BIN
Figure 27. INL vs. VREF @ VDD = 5.5 V
Figure 24. IDD Histogram @ VDD = 5 V

Rev. A | Page 11 of 20
AD5062
1.2 1.2
TA = 25°C TA = 25°C
1.0 VDD = 5.0V 1.0 VDD = 2.7V
0.8 0.8
MAX INL @ VDD = 5.0V
0.6 0.6
MAX INL @ VDD = 2.7V
0.4 0.4
INL ERROR (LSB)

INL ERROR (LSB)

0.2 0.2

0 0

–0.2 –0.2
–0.4 –0.4
MIN INL @ VDD = 2.7V
–0.6 MIN INL @ VDD = 5.0V –0.6

–0.8 –0.8

04766-084

04766-087
–1.0 –1.0

–1.2 –1.2
1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6
REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V)

Figure 28. INL vs. VREF @ VDD = 5.0 V Figure 31. INL vs. VREF @VDD = 2.7 V

1.2 0.10
TA = 25°C VDD = 5.5V, VREF = 4.096V
1.0 VDD = 4.5V 0.08 VDD = 2.7V, VREF = 2.0V
0.8
MAX INL @ VDD = 4.5V 0.06
0.6 MAX GAIN ERROR @ VDD = 5.5V
0.04
GAIN ERROR (%FSR)
0.4 MAX GAIN ERROR @ VDD = 2.7V
INL ERROR (LSB)

0.2 0.02

0 0

–0.2 –0.02
–0.4 MIN GAIN ERROR @ VDD = 2.7V
–0.04
–0.6 MIN INL @ VDD = 4.5V MIN GAIN ERROR @ VDD = 5.5V
–0.06
–0.8
04766-085

04766-080
–1.0 –0.08

–1.2 –0.10
1.5 2.0 2.5 3.0 3.5 4.0 4.5 –40 –20 0 20 40 60 80 100
REFERENCE VOLTAGE (V) TEMPERATURE (°C)

Figure 29. INL vs. VREF @ VDD = 4.5 V Figure 32. Gain Error vs. Temperature

1.2
TA = 25°C
1.0 VDD = 3.0V
0.8

0.6
MAX INL @ VDD = 3.0V
0.4
INL ERROR (LSB)

0.2

–0.2

–0.4
MIN INL @ VDD = 3.0V
–0.6
–0.8
04766-086

–1.0

–1.2
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
REFERENCE VOLTAGE (V)

Figure 30. INL vs. VREF @ VDD = 3.5 V

Rev. A | Page 12 of 20
 AD5062

TERMINOLOGY
Relative Accuracy Total Unadjusted Error (TUE)
For the DAC, relative accuracy or integral nonlinearity (INL) Total unadjusted error is a measure of the output error taking
is a measure of the maximum deviation, in LSBs, from a straight all the various errors into account. A typical TUE vs. code plot
line passing through the endpoints of the DAC transfer function. is shown in Figure 5.
A typical INL vs. code plot is shown in Figure 4. Zero-Code Error Drift
Differential Nonlinearity (DNL) This is a measure of the change in zero-code error with a
Differential nonlinearity is the difference between the measured change in temperature. It is expressed in μV/°C.
change and the ideal 1 LSB change between any two adjacent Gain Error Drift
codes. A specified differential nonlinearity of ±1 LSB maximum This is a measure of the change in gain error with changes in
ensures monotonicity. This DAC is guaranteed monotonic by temperature. It is expressed in (ppm of full-scale range)/°C.
design. A typical DNL vs. code plot is shown in Figure 7. Digital-to-Analog Glitch Impulse
Zero-Code Error Digital-to-analog glitch impulse is the impulse injected into the
Zero-code error is a measure of the output error when zero analog output when the input code in the DAC register changes
code (0x0000) is loaded to the DAC register. Ideally, the output state. It is normally specified as the area of the glitch in nV-s
should be 0 V. The zero-code error is always positive in the and is measured when the digital input code is changed by
AD5062 because the output of the DAC cannot go below 0 V. 1 LSB at the major carry transition; see Figure 17 and Figure 21.
This is due to the offset errors in the DAC. Zero-code error is The expanded view in Figure 17 shows the glitch generated
expressed in mV. following completion of the calibration routine; Figure 21
Full-Scale Error zooms in on this glitch.
Full-scale error is a measure of the output error when full-scale Digital Feedthrough
code (0xFFFF) is loaded to the DAC register. Ideally, the output Digital feedthrough is a measure of the impulse injected into
should be VDD − 1 LSB. Full-scale error is expressed in percent the analog output of the DAC from the digital inputs of the
of full-scale range. DAC, but is measured when the DAC output is not updated. It
Gain Error is specified in nV-s and measured with a full-scale code change
This is a measure of the span error of the DAC. It is the devia- on the data bus; that is, from all 0s to all 1s, and vice versa.
tion in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.

Rev. A | Page 13 of 20
AD5062

THEORY OF OPERATION
The AD5062 is a single 16-bit, serial input, voltage output DAC. The write sequence begins by bringing the SYNC line low. Data
It operates from supply voltages of 2.7 V to 5.5 V. Data is from the DIN line is clocked into the 24-bit shift register on the
written to the AD5062 in a 24-bit word format, via a 3-wire falling edge of SCLK. The serial clock frequency can be as high
serial interface. as 30 MHz, making these parts compatible with high speed
The AD5062 incorporates a power-on reset circuit that ensures DSPs. On the 24th falling clock edge, the last data bit is clocked
the DAC output powers up to zero-scale or midscale. The in and the programmed function is executed (that is, a change
device also has a software power-down mode pin that reduces in the DAC register contents and/or a change in the mode of
the typical current consumption to less than 1 μA. operation).

DAC ARCHITECTURE At this stage, the SYNC line may be kept low or be brought
high. In either case, it must be brought high for a minimum of
The DAC architecture of the AD5062 consists of two matched
33 ns before the next write sequence so that a falling edge of
DAC sections. A simplified circuit diagram is shown in
SYNC can initiate the next write sequence. Because the SYNC
Figure 33. The four MSBs of the 16-bit data-word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects buffer draws more current when VIN = 1.8 V than it does when
VIN = 0.8 V, SYNC should be idled low between write sequences
one of 15 matched resistors to either DACGND or VREF buffer
output. The remaining 12 bits of the data-word drive switches for even lower power operation of the part. As previously indi-
S0 to S11 of a 12-bit voltage mode R-2R ladder network. cated, however, it must be brought high again just before the
next write sequence.
VOUT

2R 2R 2R 2R 2R 2R 2R INPUT SHIFT REGISTER

S0 S1 S11 E1 E2 E15 The input shift register is 24 bits wide; see Figure 34. PD1 and
VREF PD0 are control bits that control which mode of operation the
part is in (normal mode or any one of three power-down
047766-027

12-BIT R-2R LADDER FOUR MSBs DECODED INTO

modes). There is a more complete description of the various
15 EQUAL SEGMENTS modes in the Power-Down Modes section. The next 16 bits are
Figure 33. DAC Ladder Structure the data bits. These are transferred to the DAC register on the
24th falling edge of SCLK.
REFERENCE BUFFER
The AD5062 operates with an external reference. The reference SYNC INTERRUPT
input (VREF) has an input range of 2 V to VDD − 50 mV. This In a normal write sequence, the SYNC line is kept low for at
input voltage is then used to provide a buffered reference for the least 24 falling edges of SCLK and the DAC is updated on the
DAC core. 24th falling edge. However, if SYNC is brought high before the
SERIAL INTERFACE 24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
The AD5062 has a 3-wire serial interface (SYNC, SCLK, and
invalid. Neither an update of the DAC register contents nor a
DIN), which is compatible with SPI, QSPI, and MICROWIRE
change in the operating mode occurs; see Figure 37.
interface standards, as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
DB15 (MSB) DB0 (LSB)

0 0 0 0 0 0 PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

0 0 NORMAL OPERATION
0 1 3-STATE
04766-028

1 0 100kΩ TO GND POWER-DOWN MODES

1 1 1kΩ TO GND

Figure 34. Input Register Contents

Rev. A | Page 14 of 20
 AD5062
POWER-ON TO MIDSCALE OR ZERO SCALE
AD5062 VOUT
The AD5062 contains a power-on reset circuit that controls the DAC
output voltage during power-up. The DAC register is filled with
the midscale code and the output voltage is midscale or the
DAC register is filled with the zero-scale code and the output POWER-DOWN
CIRCUITRY RESISTOR
voltage is zero-scale. It remains there until a valid write NETWORK

04766-029
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC Figure 35. Output Stage During Power-Down
while it is in the process of powering up.
The bias generator, the DAC core, and other associated linear
SOFTWARE RESET circuitry are all shut down when the power-down mode is
The device can be put into software reset by setting all bits in activated. However, the contents of the DAC register are unaf-
the DAC register to 1; this includes writing 1s to Bit D23 to fected when in power-down. The time to exit power-down is
Bit D16, which is not the normal mode of operation. Note that typically 2.5 μs for VDD = 5 V, and 5 μs for VDD = 3 V; see Figure 19.
the SYNCinterrupt command cannot be performed if a soft-
ware reset command is started.
MICROPROCESSOR INTERFACING
AD5062 to ADSP-2101/ADSP-2103 Interface
POWER-DOWN MODES
Figure 36 shows a serial interface between the AD5062 and the
The AD5062 contains four separate modes of operation. These
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
modes are software-programmable by setting two bits (DB17
be set up to operate in the SPORT transmit alternate framing
and DB16) in the control register. Table 6 shows how the state
mode. The ADSP-2101/ADSP-2103 SPORT is programmed
of the bits corresponds to the mode of operation of the device.
through the SPORT control register and should be configured
Table 6. Modes of Operation for the AD5062 as follows: internal clock operation, active low framing, 16-bit
DB17 DB16 Operating Mode word length. Transmission is initiated by writing a word to the
0 0 Normal operation
Tx register after the SPORT has been enabled.
Power-down mode: ADSP-2101/ AD5062
0 1 3-state ADSP-21031
1 0 100 kΩ to GND
TFS SYNC
1 1 1 kΩ to GND
DT DIN
When both bits are set to 0, the part works normally with its

04766-030
SCLK SCLK
normal power consumption. However, for the three power-
down modes, the supply current falls to less than 1 μA at 5.5 V. 1ADDITIONAL PINS OMITTED FOR CLARITY

Not only does the supply current fall, but the output stage is Figure 36. AD5062 to ADSP-2101/ADSP-2103 Interface
also internally switched from the output of the DAC to a
resistor network of known values. This has the advantage that
the output impedance of the part is known while the part is in
power-down mode. There are three different options. The
output is connected internally to GND through a 1 kΩ resistor
or a 100 kΩ resistor, or it is left open-circuited (3-state). The
output stage is illustrated in Figure 35.

SCLK

SYNC
04766-031

DIN DB23 DB0 DB23 DB0

INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES

SYNC HIGH BEFORE 24TH FALLING EDGE ON THE 24TH FALLING EDGE

Figure 37. SYNC Interrupt Facility

Rev. A | Page 15 of 20
AD5062
AD5062 to 68HC11/68L11 Interface AD5062 to 80C51/80L51 Interface
Figure 38 shows a serial interface between the AD5062 and the Figure 40 shows a serial interface between the AD5062 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 80C51/80L51 microcontroller. The setup for the interface is:
drives the SCLK pin of the AD5062, while the MOSI output TxD of the 80C51/80L51 drives SCLK of the AD5062 while
drives the serial data line of the DAC. The SYNC signal is RxD drives the serial data line of the part. The SYNC signal is
derived from a port line (PC7). The setup conditions for correct again derived from a bit-programmable pin on the port. In this
operation of this interface require that the 68HC11/68L11 be case, Port Line P3.3 is used. When data is to be transmitted to
configured so that its CPOL bit is 0 and its CPHA bit is 1. When the AD5062, P3.3 is taken low. The 80C51/80L51 transmits data
data is being transmitted to the DAC, the SYNC line is taken only in 8-bit bytes; thus only eight falling clock edges occur in
low (PC7). When the 68HC11/68L11 is configured where its the transmit cycle. To load data to the DAC, P3.3 is left low after
CPOL bit is 0 and its CPHA bit is 1, data appearing on the the first eight bits are transmitted, and a second write cycle is
MOSI output is valid on the falling edge of SCK. Serial data initiated to transmit the second byte of data. P3.3 is taken high
from the 68HC11/68L11 is transmitted in 8-bit bytes with only following the completion of this cycle. The 80C51/80L51
eight falling clock edges occurring in the transmit cycle. Data is outputs the serial data in a format that has the LSB first. The
transmitted MSB first. In order to load data to the AD5062, AD5062 requires its data with the MSB as the first bit received;
PC7 is left low after the first eight bits are transferred, and a the 80C51/80L51 transmit routine should take this into account.
second serial write operation is performed to the DAC, and PC7
80C51/80L511 AD50621
is taken high at the end of this procedure.
68HC11/
AD50621 P3.3 SYNC
68L111
TxD SCLK

04766-034
PC7 SYNC RxD DIN

SCK SCLK
1ADDITIONAL PINS OMITTED FOR CLARITY
04766-032

MOSI DIN

Figure 40. AD5062 to 80C51/80L51 Interface

1ADDITIONAL PINS OMITTED FOR CLARITY
AD5062 to MICROWIRE Interface
Figure 38. AD5062 to 68HC11/68L11 Interface
Figure 41 shows an interface between the AD5062 and any
AD5062 to Blackfin® ADSP-BF53x Interface MICROWIRE-compatible device. Serial data is shifted out on
Figure 39 shows a serial interface between the AD5062 and the the falling edge of the serial clock and is clocked into the
Blackfin ADSP-53x microprocessor. The ADSP-BF53x proces- AD5062 on the rising edge of the SK.
sor family incorporates two dual-channel synchronous serial
MICROWIRE1 AD50621
ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5062,
the setup for the interface is: DT0PRI drives the SDIN pin of CS SYNC

the AD5062, while TSCLK0 drives the SCLK of the part; the SK SCLK

04766-035
SYNC is driven from TFS0. SO DIN

ADSP-BF53x1 AD50621 1ADDITIONAL PINS OMITTED FOR CLARITY

Figure 41. AD5062 to MICROWIRE Interface

DT0PRI DIN
TSCLK0 SCLK
04766-033

TFS0 SYNC

1ADDITIONAL PINS OMITTED FOR CLARITY

Figure 39. AD5062 to Blackfin ADSP-BF53x Interface

Rev. A | Page 16 of 20
 AD5062

APPLICATIONS
CHOOSING A REFERENCE FOR THE AD5062 In high accuracy applications, which have a relatively low noise
To achieve the optimum performance from the AD5062, budget, reference output voltage noise needs to be considered. It
thought should be given to the choice of a precision voltage is important to choose a reference with as low an output noise
reference. The AD5062 has just one reference input, VREF. The voltage as practical for the system noise resolution required.
voltage on the reference input is used to supply the positive Precision voltage references, such as the ADR435, produce low
input to the DAC. Therefore, any error in the reference is output noise in the 0.1 Hz to 10 Hz region. Table 7 shows
reflected in the DAC. examples of recommended precision references for use as
supply to the AD5062.
There are four possible sources of error when choosing a
voltage reference for high accuracy applications: initial Table 7. Precision References Part List for the AD5062
accuracy, ppm drift, long-term drift, and output voltage noise. Initial Temperature
Initial accuracy on the output voltage of the DAC will lead to a Part Accuracy Drift 0.1 Hz to 10 Hz
full-scale error in the DAC. To minimize these errors, a refer- No. (mV max) (ppm/°C max) Noise (μV p-p typ)
ence with high initial accuracy is preferred. Also, choosing a ADR435 ±2 3 (SO-8) 8
reference with an output trim adjustment, such as the ADR43x ADR425 ±2 3 (SO-8) 3.4
family, allows a system designer to trim out system errors by ADR02 ±3 3 (SO-8) 10
setting a reference voltage to a voltage other than the nominal. ADR02 ±3 3 (SC70) 10
The trim adjustment can also be used at the operating ADR395 ±5 9 (TSOT-23) 8
temperature to trim out any error.
Because the supply current required by the AD5062 is
BIPOLAR OPERATION USING THE AD5062
extremely low, the parts are ideal for low supply applications. The AD5062 has been designed for single-supply operation, but
The ADR395 voltage reference is recommended. This requires a bipolar output range is also possible using the circuit in
less than 100 μA of quiescent current and can, therefore, drive Figure 43. The circuit shown yields an output voltage range of
multiple DACs in one system, if required. It also provides very ±5 V. Rail-to-rail operation at the amplifier output is achievable
good noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range. using an AD820/AD8032 or an OP196/OP295.
7V The output voltage for any input code can be calculated as
5V follows:
ADR395
⎡ D ⎞ ⎛ R1 + R 2 ⎞ ⎛ R 2 ⎞⎤
VO = ⎢VDD × ⎛⎜ ⎟×⎜ ⎟ − VDD × ⎜ ⎟
⎣ ⎝ 65536 ⎠ ⎝ R1 ⎠ ⎝ R1 ⎠⎥⎦
3-WIRE SYNC VOUT = 0V TO 5V
SERIAL SCLK AD5062 where D represents the input code in decimal (0–65536).
INTERFACE DIN
04766-036

With VREF = 5 V, R1 = R2 = 10 kΩ:

10 × D ⎞
Figure 42. ADR395 as Reference to AD5062 VO = ⎛⎜ ⎟ − 5V
⎝ 65536 ⎠
Long-term drift is a measure of how much the reference drifts
over time. A reference with a tight long-term drift specification This is an output voltage range of ±5 V with 0x0000
ensures that the overall solution remains relatively stable during corresponding to a −5 V output and 0xFFFF corresponding to a
its entire lifetime. The temperature coefficient of a reference’s +5 V output.
output voltage affects INL, DNL, and TUE. A reference with a R2 = 10kΩ

tight temperature coefficient specification should be chosen to +5V

+5V R1 = 10kΩ
reduce temperature dependence of the DAC output voltage on –
ambient conditions. AD820/
OP295 ±5V
+
VOUT –5V
VREF
10µF 0.1µF AD5062

3-WIRE
04766-037

SERIAL
INTERFACE
Figure 43. Bipolar Operation with the AD5062

Rev. A | Page 17 of 20
AD5062
USING AD5062 WITH A GALVANICALLY ISOLATED POWER SUPPLY BYPASSING AND GROUNDING
INTERFACE CHIP When accuracy is important in a circuit, it is helpful to carefully
In process control applications in industrial environments, it is consider the power supply and ground return layout on the
often necessary to use a galvanically isolated interface to protect board. The printed circuit board containing the AD5062 should
and isolate the controlling circuitry from any hazardous have separate analog and digital sections, each having its own
common-mode voltages that may occur in the area where the area of the board. If the AD5062 is in a system where other
DAC is functioning. iCoupler® provides isolation in excess of devices require an AGND-to-DGND connection, the
2.5 kV. Because the AD5062 uses a 3-wire serial logic interface, connection should be made at one point only. This ground
the ADuM130x family provides an ideal digital solution for the point should be as close as possible to the AD5062.
DAC interface. The power supply to the AD5062 should be bypassed with
The ADuM130x isolators provide three independent isolation 10 μF and 0.1 μF capacitors. The capacitors should be physically
channels in a variety of channel configurations and data rates. as close as possible to the device, with the 0.1 μF capacitor
They operate across the full range from 2.7 V to 5.5 V, providing ideally right up against the device. The 10 μF capacitors are the
compatibility with lower voltage systems as well as enabling a tantalum bead type. It is important that the 0.1 μF capacitor has
voltage translation functionality across the isolation barrier. low effective series resistance (ESR) and effective series
Figure 44 shows a typical galvanically isolated configuration inductance (ESI), as do common ceramic types of capacitors.
using the AD5062. The power supply to the part also needs to This 0.1 μF capacitor provides a low impedance path to ground
be isolated; this is accomplished by using a transformer. On the for high frequencies caused by transient currents due to internal
DAC side of the transformer, a 5 V regulator provides the 5 V logic switching.
supply required for the AD5062. The power supply line itself should have as large a trace as
5V
possible to provide a low impedance path and reduce glitch
REGULATOR effects on the supply line. Clocks and other fast switching
POWER 10μF 0.1μF
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
VDD
ensure that they run at right angles to each other to reduce
SCLK V1A V0A SCLK
feedthrough effects through the board. The best board layout
ADuM1300 AD5062 technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
SDI V1B V0B SYNC VOUT signal traces are placed on the solder side. However, this is not
always possible with a two-layer board.

DATA V1C V0C DIN

04766-038

GND

Figure 44. AD5062 with a Galvanically Isolated Interface

Rev. A | Page 18 of 20
 AD5062

OUTLINE DIMENSIONS
3.00
2.90
2.80

8 7 6 5 3.00
1.70
1.60 2.80
1.50 2.60
1 2 3 4

PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX 0.22 MAX
0.95 MIN 0.08 MIN
0.60
0.15 MAX 8° 0.45
0.05 MIN SEATING 4° 0.60
0.38 MAX PLANE 0.30
BSC
0.22 MIN 0°

121608-A
COMPLIANT TO JEDEC STANDARDS MO-178-BA

Figure 45. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)
Dimensions shown in millimeters

ORDERING GUIDE
Temperature Package Package
Model Range INL Description Description Options Branding
AD5062BRJZ-1REEL7 1 −40°C to +85°C 1 LSB 2.7 V to 5.5 V, Reset to 0 V 8 Lead SOT-23 RJ-8 D46
AD5062BRJZ-1500RL71 −40°C to +85°C 1 LSB 2.7 V to 5.5 V, Reset to 0 V 8 Lead SOT-23 RJ-8 D46
AD5062BRJZ-2REEL71 −40°C to +85°C 1 LSB 2.7 V to 5.5 V, Reset to Midscale 8 Lead SOT-23 RJ-8 D47
AD5062BRJZ-2500RL71 −40°C to +85°C 1 LSB 2.7 V to 5.5 V, Reset to Midscale 8 Lead SOT-23 RJ-8 D47
AD5062ARJZ-1500RL71 −40°C to +85°C 2 LSB 2.7 V to 5.5 V, Reset to 0 V 8 Lead SOT-23 RJ-8 D48
AD5062ARJZ-1REEL71 −40°C to +85°C 2 LSB 2.7 V to 5.5 V, Reset to 0 V 8 Lead SOT-23 RJ-8 D48
EVAL AD5062EB Evaluation Board
1
Z = RoHS Compliant Part.

Rev. A | Page 19 of 20
AD5062

NOTES

©2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04766-0-5/09(A)

Rev. A | Page 20 of 20