19-2956; Rev 1; 10/09

KIT
ATION
EVALU BLE
AVA ILA

Multichannel, 16-Bit, 200ksps Analog-to-Digital

Converters
General Description Features

MAX1167/MAX1168
The MAX1167/MAX1168 low-power, multichannel, 16- ♦ 16-Bit Resolution, No Missing Codes
bit analog-to-digital converters (ADCs) feature a suc-
cessive-approximation ADC, integrated +4.096V ♦ +5V Single-Supply Operation
reference, a reference buffer, an internal oscillator, ♦ Adjustable Logic Level (+2.7V to +5.25V)
automatic power-down, and a high-speed SPI™/
QSPI™/MICROWIRE™-compatible interface. The ♦ Input Voltage Range: 0 to VREF
MAX1167/MAX1168 operate with a single +5V analog ♦ Internal (+4.096V) or External (+3.8V to AVDD)
supply and feature a separate digital supply, allowing
Reference
direct interfacing with +2.7V to +5.5V digital logic.
♦ Internal Track/Hold, 4MHz Input Bandwidth
The MAX1167/MAX1168 consume only 3.6mA (AVDD =
DVDD = +5V) at 200ksps when using an external reference. ♦ Internal or External Clock
AutoShutdown™ reduces the supply current to 185µA at
10ksps and to less than 10µA at reduced sampling rates. ♦ SPI/QSPI/MICROWIRE-Compatible Serial
Interface, MAX1168 Performs DSP-Initiated
The MAX1167 includes a 4-channel input multiplexer, and
Conversions
the MAX1168 accepts up to eight analog inputs.
In addition, digital signal processor (DSP)-initiated con- ♦ 8-Bit-Wide or 16-Bit-Wide Data-Transfer Mode
versions are simplified with the DSP frame-sync input and (MAX1168 Only)
output featured in the MAX1168. The MAX1168 includes
♦ 4-Channel (MAX1167) or 8-Channel (MAX1168)
a data-bit transfer input to select between 8-bit-wide or
16-bit-wide data-transfer modes. Both devices feature a Input Mux
scan mode that converts each channel sequentially or Scan Mode Sequentially Converts Multiple
one channel continuously. Channels or One Channel Continuously
Excellent dynamic performance and low power, com- ♦ Low Power
bined with ease of use and an integrated reference, make 3.6mA at 200ksps
the MAX1167/MAX1168 ideal for control and data-acqui- 1.85mA at 100ksps
sition operations or for other applications with demanding 185µA at 10ksps
power consumption and space requirements. The 0.6µA in Full Power-Down Mode
MAX1167 is available in a 16-pin QSOP package and the
MAX1168 is available in a 24-pin QSOP package. Both ♦ Small Package Size
devices are guaranteed over the commercial (0°C to 16-Pin QSOP (MAX1167)
+70°C) and extended (-40°C to +85°C) temperature 24-Pin QSOP (MAX1168)
ranges. Use the MAX1168 evaluation kit to evaluate the
MAX1168.
Ordering Information
Applications
PIN- INL
Motor Control PART TEMP RANGE
PACKAGE (LSB)
Industrial Process Control MAX1167BCEE 0°C to +70°C 16 QSOP ±3
Industrial I/O Modules MAX1167BEEE -40°C to +85°C 16 QSOP ±3
Data-Acquisition Systems MAX1168BCEG 0°C to +70°C 24 QSOP ±3
Thermocouple Measurements MAX1168BEEG -40°C to +85°C 24 QSOP ±3

Accelerometer Measurements

Pin Configurations appear at end of data sheet.

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
ABSOLUTE MAXIMUM RATINGS
MAX1167/MAX1168

AVDD to AGND .........................................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C)

DVDD to DGND.........................................................-0.3V to +6V 16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
DGND to AGND.....................................................-0.3V to +0.3V 24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
AIN_, REF, REFCAP to AGND..................-0.3V to (AVDD + 0.3V) Operating Temperature Ranges
SCLK, CS, DSEL, DSPR, DIN to DGND ...................-0.3V to +6V MAX116_ _ CE_ ..................................................0°C to +70°C
DOUT, DSPX, EOC to DGND...................-0.3V to (DVDD + 0.3V) MAX116_ _ EE_ ...............................................-40°C to +85°C
Maximum Current into Any Pin............................................50mA Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 1)
Resolution 16 Bits
Relative Accuracy (Note 2) INL MAX116_B ±1.8 ±3 LSB
MAX116_B 16-bit
Differential Nonlinearity DNL +0.7 +1.75 LSB
(16 bit, no missing codes over temperature) NMC
RMS External reference 0.7
Transition Noise LSBRMS
noise Internal reference 0.8
Offset Error ±0.1 ±10 mV
Gain Error (Note 3) ±0.01 ±0.2 %FSR
Offset Drift 1 ppm/°C
Gain Drift (Note 3) ±1.2 ppm/°C
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-P) (Note 1)
Signal-to-Noise Plus Distortion SINAD 85 88.5 dB
Signal-to-Noise Ratio SNR 86 88.5 dB
Total Harmonic Distortion THD -100 -88 dB
Spurious-Free Dynamic Range SFDR 88 101 dB
Full-Power Bandwidth -3dB point 4 MHz
Full-Linear Bandwidth SINAD > 85dB 10 kHz
Channel-to-Channel Isolation (Note 4) 96 dB
CONVERSION RATE
Internal clock, no data transfer,
5.52 7.07
Conversion Time tCONV single conversion (Note 5) μs
External clock 3.75
Acquisition Time tACQ (Note 6) 729 ns
External clock, data transfer and conversion 0.1 4.8
Serial Clock Frequency f SCLK MHz
External clock, data transfer only 9

2 _______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
ELECTRICAL CHARACTERISTICS (continued)

MAX1167/MAX1168
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Internal Clock Frequency f INTCLK Internal clock 3.2 4.0 MHz
Aperture Delay tAD 15 ns
Aperture Jitter tAJ <50 ps
8-bit-wide data-transfer mode 4.17 200.00
16-bit-wide data-transfer mode 3.125 150.00
Internal clock, single conversion, 8-bit-wide
89
data-transfer mode
Internal clock, single conversion, 16-bit-
Sample Rate (Note 7) fS 68 ksps
wide data-transfer mode
Internal clock, scan mode, 8-bit-wide data-
103
transfer mode (four conversions)
External clock, scan mode, 16-bit-wide
82
data-transfer mode (four conversions)
Duty Cycle 45 55 %
ANALOG INPUT (AIN_)
Input Range VAIN _ 0 VREF V
Input Capacitance CAIN _ 45 pF
EXTERNAL REFERENCE
AVDD
Input Voltage Range VREF (Note 8) 3.8 V
- 0.2
VAIN _ = 0 34
Input Current IREF SCLK idle 0.1 μA
CS = DVDD, SCLK idle 0.1
INTERNAL REFERENCE
Reference Voltage VREFIN 4.042 4.096 4.136 V
Reference Short-Circuit Current IREFSC 13 mA
Reference Temperature
±25 ppm/°C
Coefficient
Reference Wake-Up Time tRWAKE VREF = 0 5 ms
DIGITAL INPUTS (SCLK, CS, DSEL, DSPR, DIN) (DVDD = +2.7V to +5.25V)
0.7

Input High Voltage VIH V
DVDD
0.3

Input Low Voltage VIL V
DVDD
Input Leakage Current I IN Digital inputs = 0 to DVDD ±0.1 ±1 μA
Input Hysteresis VHYST 0.2 V
Input Capacitance CIN 15 pF

_______________________________________________________________________________________ 3
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
ELECTRICAL CHARACTERISTICS (continued)
MAX1167/MAX1168

(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF
= +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUT (DOUT, DSPX, EOC) (DVDD = +2.7V to +5.25V)
DVDD -
Output High Voltage VOH I SOURCE = 0.5mA V
0.4
I SINK = 10mA, DVDD = +4.75V to +5.25V 0.8
Output Low Voltage VOL V
I SINK = 1.6mA, DVDD = +2.7V to +5.25V 0.4
Three-State Output Leakage
IL CS = DVDD ±0.1 ±10 μA
Current
Three-State Output Capacitance C OUT CS = DVDD 15 pF
POWER SUPPLIES
Analog Supply AVDD 4.75 5.25 V
Digital Supply DVDD 2.70 5.25 V
External reference 2.7 3.3
200ksps
Internal reference 3.6 4.2
External reference 1.4
100ksps
Internal reference 2.7
Analog Supply Current (Note 9) IAVDD mA
External reference 0.14
10ksps
Internal reference 1.8
External reference 0.014
1ksps
Internal reference 1.7
200ksps 0.87 1.3
DOUT = 100ksps 0.45
Digital Supply Current IDVDD mA
all zeros 10ksps 0.045
1ksps 0.005
Internal reference and
CS = DVDD, reference buffer on 0.66
IAVDD + SCLK = 0, between conversions
Power-Down Supply Current mA
IDVDD DIN = 0, Internal reference on,
DSPR = DVDD reference buffer off 0.20
between conversions
IAVDD + CS = DVDD, SCLK = 0, DIN = 0,
Shutdown Supply Current 0.6 10 μA
IDVDD DSPR = DVDD, full power-down
AVDD = DVDD = 4.75V to 5.25V, full-scale
Power-Supply Rejection Ratio PSRR 63 dB
input (Note 10)

4 _______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)

MAX1167/MAX1168
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external
VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time tACQ External clock (Note 6) 729 ns
SCLK to DOUT Valid tDO CDOUT = 30pF 50 ns
CS Fall to DOUT Enable tDV CDOUT = 30pF 80 ns
CS Rise to DOUT Disable tTR CDOUT = 30pF 80 ns
CS Pulse Width tCSW 100 ns
SCLK rise
CS to SCLK Setup tCSS 100 ns
SCLK fall (DSP)
SCLK rise
CS to SCLK Hold tCSH 0 ns
SCLK fall (DSP)
Conversion 93
SCLK High Pulse Width tCH Duty cycle 45% to 55% ns
Data transfer 50
Conversion 93
SCLK Low Pulse Width tCL Duty cycle 45% to 55% ns
Data transfer 50
SCLK Period tCP 209 ns
SCLK rise
DIN to SCLK Setup tDS 50 ns
SCLK fall (DSP)
SCLK rise
DIN to SCLK Hold tDH 0 ns
SCLK fall (DSP)
CS Falling to DSPR Rising tDF 100 ns
DSPR to SCLK Falling Setup tFSS 100 ns
DSPR to SCLK Falling Hold tFSH 0 ns

_______________________________________________________________________________________ 5
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)
MAX1167/MAX1168

(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion
(200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time tACQ External clock (Note 6) 729 ns
SCLK to DOUT Valid tDO CDOUT = 30pF 100 ns
CS Fall to DOUT Enable tDV CDOUT = 30pF 100 ns
CS Rise to DOUT Disable tTR CDOUT = 30pF 80 ns
CS Pulse Width tCSW 100 ns
SCLK rise
CS to SCLK Setup tCSS 100 ns
SCLK fall (DSP)
SCLK rise
CS to SCLK Hold tCSH 0 ns
SCLK fall (DSP)
Conversion 93
SCLK High Pulse Width tCH Duty cycle 45% to 55% ns
Data transfer 93
Conversion 93
SCLK Low Pulse Width tCL Duty cycle 45% to 55% ns
Data transfer 93
SCLK Period tCP 209 ns
SCLK rise
DIN to SCLK Setup tDS 100 ns
SCLK fall (DSP)
SCLK rise
DIN to SCLK Hold tDH 0 ns
SCLK fall (DSP)
CS Falling to DSPR Rising tDF 100 ns
DSPR to SCLK Falling Setup tFSS 100 ns
DSPR to SCLK Falling Hold tFSH 0 ns
Note 1: AVDD = DVDD = +5.0V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset and reference errors nulled.
Note 4: DC voltage applied to on channel, and a full-scale 1kHz sine wave applied to off channels.
Note 5: Conversion time is measured from the rising edge of the 8th external SCLK pulse to EOC transition minus tACQ in 8-bit
data-transfer mode.
Note 6: See Figures 10 and 17.
Note 7: fSCLK = 4.8MHz, fINTCLK = 4.0MHz. Sample rate is calculated with the formula fs = n1 (n2 / fSCLK + n3 / fINTCLK)-1 where:
n1 = number of scans, n2 = number of SCLK cycles, and n3 = number of internal clock cycles (see Figures 11–14).
Note 8: Guaranteed by design; not production tested.
Note 9: Internal reference and buffer are left on between conversions.
Note 10: Defined as the change in the positive full scale caused by a ±5% variation in the nominal supply voltage.

6 _______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Typical Operating Characteristics

MAX1167/MAX1168
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CDOUT = 30pF, external VREF = +4.096V, TA = +25°C, unless otherwise noted.)

INL vs. CODE DNL vs. CODE FFT AT fAIN = 1kHz

1.5 1.5 20

MAX1167/68 toc03
MAX1167/68 toc01

MAX1167/68 toc02
0
1.0 1.0
-20

0.5 0.5 -40

AMPLITUDE (dB)
DNL (LSB)
INL (LSB)

-60
0 0
-80
-0.5 -0.5 -100

-120
-1.0 -1.0
-140

-1.5 -1.5 -160

0 16384 32768 49152 65536 0 16384 32768 49152 65536 0 20 40 60 80 100
CODE CODE FREQUENCY (kHz)

SINAD vs. FREQUENCY SFDR vs. FREQUENCY THD vs. FREQUENCY

100 120 0
MAX1167/68 toc04

MAX1167/68 toc05

MAX1167/68 toc06
fSAMPLE = 200kbps
90
100 -20
80
70
80 -40
SINAD (dB)

60
SFDR (dB)

THD (dB)

50 60 -60
40
40 -80
30
20
20 -100
10
fSAMPLE = 200kbps fSAMPLE = 200ksps
0 0 -120
0.1 1 10 100 0.1 1 10 100 0.1 1 10 100
FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz)

ANALOG SUPPLY CURRENT ANALOG SUPPLY CURRENT

SUPPLY CURRENT vs. CONVERSION RATE vs. ANALOG SUPPLY VOLTAGE vs. ANALOG SUPPLY VOLTAGE
(EXTERNAL CLOCK) (INTERNAL REFERENCE) (EXTERNAL REFERENCE)
3.0 2.95 2.00
MAX1167/68 toc07

MAX1167/68 toc08

MAX1167/68 toc09

DVDD = AVDD = +5V DVDD = +5V TA = +85°C

DOUT = ALL ZEROS DVDD = +5V
2.5 fS = 200ksps TA = +70°C
EXTERNAL CLOCK fS = 200ksps
2.90 TA = +85°C 1.95 TA = +70°C
SPI MODE
SUPPLY CURRENT (mA)

2.0
IAVDD (mA)

IAVDD (mA)

1.5 2.85 1.90

1.0
2.80 1.85
TA = +25°C TA = +25°C
0.5
IAVDD, INT REF
2.75 TA = 0°C 1.80 TA = 0°C
0 IAVDD, EXT REF
IDVDD TA = -40°C TA = -40°C
-0.5 2.70 1.75
0 20 40 60 80 100 120 140 160 180 200 4.75 4.85 4.95 5.05 5.15 5.25 4.75 4.85 4.95 5.05 5.15 5.25
CONVERSION RATE (ksps) AVDD (V) AVDD (V)

_______________________________________________________________________________________ 7
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Typical Operating Characteristics (continued)
MAX1167/MAX1168

(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CDOUT = 30pF, external VREF = +4.096V, TA = +25°C, unless otherwise noted.)

POWER-DOWN SUPPLY CURRENT POWER-DOWN SUPPLY CURRENT

DIGITAL SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE vs. DVDD SUPPLY VOLTAGE
vs. DIGITAL SUPPLY VOLTAGE (INTERNAL REFERENCE) (INTERNAL REFERENCE)
MAX1167/68 toc11 MAX1167/68 toc12
2.6
MAX1167/68 toc10
0.58 1.04 0.7 1.03
AVDD = +5V DVDD = +5V DVDD = +5V
AV
2.2 VIL = 0 0.57 1.03 0.6
VIH = DVDD 1.02
fS = 200ksps
1.8 DOUT = 1010...1010 0.56 IAVDD 1.02 0.5

IAVDD (mA)
IDVDD (μA)

IAVDD (mA)
IDVDD (μA)
IDVDD (mA)

DOUT = 0000...0000
1.4 0.55 1.01 0.4 1.01
IAVDD
IDVDD
1.0 0.54 1.00 0.3
IDVDD 1.00
0.6 0.53 0.99 0.2

0.2 0.52 0.98 0.1 0.99

2.70 3.21 3.72 4.23 4.74 5.25 4.75 4.85 4.95 5.05 5.15 5.25 2.70 3.21 3.72 4.23 4.74 5.25
DVDD (V) AVDD (V) DVDD (V)

SHUTDOWN SUPPLY CURRENT SHUTDOWN SUPPLY CURRENT

vs. AVDD SUPPLY VOLTAGE vs. DVDD SUPPLY VOLTAGE
(EXTERNAL REFERENCE) (EXTERNAL REFERENCE)
MAX1167/68 toc13 MAX1167/68 toc14
0.58 0.54 0.7 0.43

DVDD = +5V DVDD = +5V

AV
0.57 0.50 0.6 0.42
IAVDD
0.56 0.46 0.5 0.41
IDVDD (μA)

IDVDD (μA)
IAVDD (nA)

IAVDD (nA)
0.55 IDVDD 0.42 0.4 0.40
IAVDD
0.54 0.38 0.3 0.39

0.53 0.34 0.2 IDVDD 0.38

0.52 0.30 0.1 0.37

4.75 4.85 4.95 5.05 5.15 5.25 2.70 3.21 3.72 4.23 4.74 5.25
AVDD (V) DVDD (V)

POWER-DOWN SUPPLY CURRENT SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE (INTERNAL REFERENCE) vs. TEMPERATURE (EXTERNAL REFERENCE)
MAX1167/68 toc15 MAX1167/68 toc16
0.58 1.04 0.58 0.45
DVDD = AVDD = +5V DVDD = AVDD = +5V
0.57 1.03 0.57
IAVDD 0.43
IAVDD
0.56 1.02 0.56
IAVDD (mA)
IDVDD (μA)

IDVDD (μA)

0.41
IAVDD (nA)

0.55 1.01 0.55

IDVDD IDVDD
0.39
0.54 1.00 0.54

0.37
0.53 0.99 0.53

0.52 0.98 0.52 0.35

-40 -15 10 35 60 85 -40 -15 10 35 60 85
TEMPERATURE (°C) TEMPERATURE (°C)
8 _______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Typical Operating Characteristics (continued)

MAX1167/MAX1168
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CDOUT = 30pF, external VREF = +4.096V, TA = +25°C, unless otherwise noted.)

OFFSET ERROR vs. SUPPLY VOLTAGE GAIN ERROR vs. SUPPLY VOLTAGE OFFSET ERROR vs. TEMPERATURE
200 0.05 200

MAX1167/68 toc18
MAX1167/68 toc17

MAX1167/68 toc19
VREF = +4.096V VREF = +4.096V VREF = +4.096V
0.04 150
100

0.03 100
GAIN ERROR (%FSR)
OFFSET ERROR (μV)

OFFSET ERROR (μV)

0
0.02 50
-100
0.01 0
-200
0 -50

-300 -0.01 -100

-400 -0.02 -150

4.75 4.85 4.95 5.05 5.15 5.25 4.75 4.85 4.95 5.05 5.15 5.25 -40 -15 10 35 60 85
AVDD (V) AVDD (V) TEMPERATURE (°C)

CHANNEL-TO-CHANNEL ISOLATION INTERNAL +4.096V REFERENCE VOLTAGE

GAIN ERROR vs. TEMPERATURE vs. FREQUENCY vs. ANALOG SUPPLY VOLTAGE
0 0 MAX1167/68 toc21 4.104
MAX1167/68 toc20

MAX1167/68 toc22
VREF = +4.096V
DVDD = +5V TA = +85°C
-20
-0.001
4.100
GAIN ERROR (%FSR)

-40
ISOLATION (dB)

-0.002 TA = +70°C
VREF (V)

-60 4.096
-0.003 TA = +25°C
-80
4.092
-0.004 TA = -40°C TA = 0°C
-100

-0.005 -120 4.088

-40 -15 10 35 60 85 0 20 40 60 80 100 4.75 4.85 4.95 5.05 5.15 5.25
TEMPERATURE (°C) FREQUENCY (kHz) AVDD (V)

EXTERNAL REFERENCE INPUT CURRENT INTERNAL REFERENCE VOLTAGE INTERNAL CLOCK CONVERSION TIME
vs. EXTERNAL REFERENCE VOLTAGE vs. REF LOAD (8th RISING SCLK TO FALLING EOC)
160 4.5 70
MAX1167/68 toc24

MAX1167/68 toc25
MAX1167/68 toc23

VAIN = 0 4.0 8-BIT DATA-TRANSFER MODE 60

140 60
fSCLK = 4.8MHz 16-BIT DATA-TRANSFER MODE
AVDD = DVDD = +5V 3.5 53
120
50 fSCLK = 4.8MHz 46
3.0 44
100 39
tCONV(ms)

38
VREF (V)
IREF (μA)

199ksps, EXTERNAL CLOCK 2.5 40

80 31 33
2.0 30 28
60 24 22
87.19ksps, INTERNAL CLOCK 1.5
fSCLK = 0 20 17 17
40 1.0 INTERNAL REFERENCE MODE
LOAD APPLIED TO REF 10 12
20 0.5 10 6
CREF = 1μF
0 0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 2 4 6 8 10 12 14 1 2 3 4 5 6 7 8
VREF (V) IREF (mA) NUMBER OF SCAN-MODE CONVERSIONS

_______________________________________________________________________________________ 9
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Pin Description
MAX1167/MAX1168

PIN
NAME FUNCTION
MAX1167 MAX1168
Serial Data Output. Data changes state on SCLK’s falling edge in SPI/QSPI/MICROWIRE
1 3 DOUT mode and on SCLK’s rising edge in DSP mode (MAX1168 only). DOUT is high impedance
when CS is high.

Serial Clock Input. SCLK drives the conversion process in external clock mode and clocks
2 4 SCLK
data out.

Serial Data Input. Use DIN to communicate with the command/configuration/control

3 5 DIN register. In SPI/QSPI/MICROWIRE mode, the rising edge of SCLK clocks in data at DIN. In
DSP mode, the falling edge of SCLK clocks in data at DIN.

End-of-Conversion Output. In internal clock mode, a logic low at EOC signals the end of a
4 6 EOC
conversion with the result available at DOUT. In external clock mode, EOC remains high.
5 7 AIN0 Analog Input 0

6 8 AIN1 Analog Input 1

7 9 AIN2 Analog Input 2

8 10 AIN3 Analog Input 3

Reference Voltage Input/Output. VREF sets the analog voltage range. Bypass to AGND
9 15 REF
with a 10µF capacitor. Bypass with a 1µF (min) capacitor when using internal reference.
Reference Bypass Capacitor Connection. Bypass to AGND with a 0.1µF capacitor when
10 16 REFCAP
using internal reference. Internal reference and buffer shut down in external reference mode.
11 17 AGND Analog Ground. Connect to pin 18 (MAX1168) or pin 12 (MAX1167).

12 18 AGND Primary Analog Ground (Star Ground). Power return for AVDD.

13 19 AVDD Analog Supply Voltage. Bypass to AGND with a 0.1µF capacitor.

Active-Low Chip-Select Input. Forcing CS high places the MAX1167/MAX1168 in shutdown

with a typical supply current of 0.6µA. In SPI/QSPI/MICROWIRE mode, a high-to-low
14 20 CS transition on CS activates normal operating mode. In DSP mode, after the initial CS
transition from high to low, CS can remain low for the entire conversion process (see the
Operating Modes section).

15 21 DGND Digital Ground

16 22 DVDD Digital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.

DSP Frame-Sync Receive Input. A frame-sync pulse received at DSPR initiates a
— 1 DSPR
conversion. Connect to logic high when using SPI/QSPI/MICROWIRE mode.

Data-Bit Transfer-Select Input. Logic low on DSEL places the device in 8-bit-wide data-
— 2 DSEL transfer mode. Logic high places the device in 16-bit-wide data-transfer mode. Do not
leave DSEL unconnected.

— 11 AIN4 Analog Input 4

— 12 AIN5 Analog Input 5

10 ______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Pin Description (continued)

MAX1167/MAX1168
PIN
NAME FUNCTION
MAX1167 MAX1168
— 13 AIN6 Analog Input 6

— 14 AIN7 Analog Input 7

DSP Frame-Sync Transmit Output. A frame-sync pulse at DSPX notifies the DSP that the
— 23 DSPX
MSB data is available at DOUT. Leave DSPX unconnected when not in DSP mode.
— 24 N.C. No Connection. Not internally connected.

DVDD DVDD

1mA 1mA

DOUT DOUT DOUT DOUT

1mA CLOAD = 30pF CLOAD = 30pF 1mA CLOAD = 30pF CLOAD = 30pF

DGND DGND DGND DGND

a) VOL TO VOH b) HIGH-Z TO VOL AND VOH TO VOL a) VOH TO HIGH-Z b) VOL TO HIGH-Z

Figure 1. Load Circuits for DOUT Enable Time and SCLK-to- Figure 2. Load Circuits for DOUT Disable Time
DOUT Delay Time

Detailed Description In SPI/QSPI/MICROWIRE mode, a falling edge on CS

wakes the analog circuitry and allows SCLK to clock in
The MAX1167/MAX1168 low-power, multichannel, 16-bit
data. Acquisition and conversion are initiated by SCLK.
ADCs feature a successive-approximation ADC, auto-
The conversion result is available at DOUT in unipolar
matic power-down, integrated +4.096V reference, and a
serial format. DOUT is held low until data becomes
high-speed SPI/QSPI/MICROWIRE-compatible interface.
available (MSB first) on the 8th falling edge of SCLK
A DSPR input and DSPX output allow the MAX1168 to
when in 8-bit transfer mode, and on the 16th falling
communicate with digital signal processors (DSPs) with
edge when in 16-bit transfer mode (see the Operating
no external glue logic. The MAX1167/MAX1168 operate
Modes section). Figure 8 shows the detailed SPI/QSPI/
with a single +5V analog supply and feature a separate
MICROWIRE serial-interface timing diagram.
digital supply, allowing direct interfacing with +2.7V to
+5.5V digital logic. In external clock mode, the MAX1168 also interfaces
with DSPs. In DSP mode, a frame-sync pulse from the
Figures 3 and 4 show the functional diagrams of the
DSP initiates a conversion that is driven by SCLK. The
MAX1167/MAX1168, and Figures 5 and 6 show the
MAX1168 formats a frame-sync pulse to notify the DSP
MAX1167/MAX1168 in a typical operating circuit. The
that the conversion results are available at DOUT in
serial interface simplifies communication with micro-
MSB-first, unipolar, serial-data format. Figure 16 shows
processors (µPs).
the detailed DSP serial-interface timing diagram (see the
In external reference mode, the MAX1167/MAX1168 Operating Modes section).
have two power modes: normal mode and shutdown
mode. Driving CS high places the MAX1167/MAX1168 in Analog Input
shutdown mode, reducing the supply current to 0.6µA Figure 7 illustrates the input-sampling architecture of
(typ). Pull CS low to place the MAX1167/MAX1168 in the ADC. The voltage applied at REF or the internal
normal operating mode. The internal reference mode +4.096V reference sets the full-scale input voltage.
offers software-programmable, power-down options as
shown in Table 5.

______________________________________________________________________________________ 11
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
MAX1167/MAX1168

REFCAP AVDD DVDD

REFERENCE BUFFER

REF
AGND MAX1167

AIN0

AIN1
ANALOG-INPUT
DAC COMPARATOR
MULTIPLEXER
AIN2

AZ
AIN3 RAIL

ANALOG-SWITCH FINE TIMING

BIAS

SCLK SUCCESSIVE-APPROXIMATION
MULTIPLEXER OUTPUT DOUT
REGISTER
OSCILLATOR

ACCUMULATOR

CS CONTROL
EOC

MEMORY

DIN INPUT REGISTER

AGND DGND

Figure 3. MAX1167 Functional Diagram

Track/Hold (T/H) The time required for the T/H to acquire an input signal
In track mode, the analog signal is acquired on the is a function of how quickly its input capacitance is
internal hold capacitor. In hold mode, the T/H switches charged. If the input signal’s source impedance is high,
open and the capacitive digital-to-analog converter the acquisition time lengthens and more time must be
(DAC) samples the analog input. allowed between conversions. The acquisition time
During the acquisition, the analog input (AIN_) charges (tACQ) is the maximum time the device takes to acquire
capacitor CDAC. At the end of the acquisition interval the signal. Use the following formula to calculate acqui-
the T/H switches open. The retained charge on CDAC sition time:
represents a sample of the input. tACQ = 11(RS + RIN + RDS(ON)) ✕ 45pF + 0.3µs
In hold mode, the capacitive DAC adjusts during the where R IN = 340Ω, R S = the input signal’s source
remainder of the conversion cycle to restore node impedance, RDS(ON) = 60Ω, and tACQ is never less
ZERO to zero within the limits of 16-bit resolution. At the than 729ns. A source impedance of less than 200Ω
end of the conversion, force CS high and then low to does not significantly affect the ADC’s performance.
reset the T/H switches back to track mode (AIN_),
where CDAC charges to the input signal again.

12 ______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters

MAX1167/MAX1168
REFCAP AVDD DVDD

REFERENCE BUFFER

REF
AGND MAX1168

AIN0
AIN1
AIN2
AIN3 ANALOG-INPUT
DAC COMPARATOR
AIN4 MULTIPLEXER

AIN5
AIN6 AZ
RAIL
AIN7

ANALOG-SWITCH FINE TIMING

BIAS

SCLK SUCCESSIVE-APPROXIMATION
MULTIPLEXER OUTPUT DOUT
REGISTER
OSCILLATOR

ACCUMULATOR

CS EOC
CONTROL
DSEL DSPX

DSPR
MEMORY

DIN INPUT REGISTER

AGND DGND

Figure 4. MAX1168 Functional Diagram

The MAX1168 features a 16-bit-wide data-transfer periodic signals with bandwidths exceeding the ADC’s
mode that includes a longer acquisition time (11.5 sampling rate by using undersampling techniques. To
clock cycles). Longer acquisition times are useful in avoid aliasing of unwanted, high-frequency signals into
applications with input source resistances greater than the frequency band of interest, use anti-alias filtering.
1kΩ. Noise increases when using large source resis-
tances. To improve the input signal bandwidth under Analog Input Protection
AC conditions, drive AIN_ with a wideband buffer Internal protection diodes, which clamp the analog
(>10MHz) that can drive the ADC’s input capacitance input to AVDD or AGND, allow the input to swing from
and settle quickly. (AGND - 0.3V) to (AVDD + 0.3V) without damaging the
device. If the analog input exceeds 300mV beyond the
Input Bandwidth supplies, limit the input current to 10mA.
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, making possible the digitization of
high-speed transient events and the measurement of

______________________________________________________________________________________ 13
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
MAX1167/MAX1168

AIN0 CS CS
AIN1 SCLK SCLK
AIN0 CS CS AIN2 DSPX DSPX
ANALOG AIN1 SCLK SCLK ANALOG AIN3
INPUTS AIN2 DOUT DOUT INPUTS AIN4 DOUT DOUT
AIN3 AIN5 EOC EOC
EOC EOC
DIN AIN6
DIN
AIN7
MAX1167 DIN DIN
REF MAX1168
16
1μF 8 DSEL
AGND DSPR
+5V AVDD
AGND REF
1μF
0.1μF DGND AGND
+5V AVDD
+5V DVDD REFCAP AGND
0.1μF DGND
0.1μF 0.1μF +5V DVDD REFCAP

0.1μF 0.1μF
GND
GND

Figure 5. MAX1167 Typical Operating Circuit Figure 6. MAX1168 T ypical Operating Circuit

In addition to the standard 3-wire serial interface modes,

MUX REF the MAX1168 includes a DSPR input and a DSPX output
RDSON TRACK CAPACITIVE for communicating with DSPs in external clock mode and
AIN_ DAC a DSEL input to determine 8-bit-wide or 16-bit-wide data-
ZERO
CMUX transfer mode. When not using the MAX1168 in the DSP
HOLD CDAC interface mode, connect DSPR to DVDD and leave DSPX
RIN
unconnected.
CSWITCH AGND

HOLD TRACK Command/Configuration/Control Register

Table 1 shows the contents of the command/configura-
AUTOZERO
tion/control register and the state of each bit after initial
RAIL power-up. Tables 2–6 define the control and configuration
of the device for each bit. Cycling the power supplies
resets the command/configuration/control register to the
Figure 7. Equivalent Input Circuit power-on-reset default state.
Initialization After Power-Up
Digital Interface A logic high on CS places the MAX1167/MAX1168 in
The MAX1167/MAX1168 feature an SPI/QSPI/ the shutdown mode chosen by the power-down bits,
MICROWIRE-compatible, 3-wire serial interface. The and places DOUT in a high-impedance state. Drive CS
MAX1167 digital interface consists of digital inputs CS, low to power up and enable the MAX1167/MAX1168
SCLK, and DIN and outputs DOUT and EOC. The before starting a conversion. In internal reference
MAX1167 operates in the following modes: mode, allow 5ms for the shutdown internal reference
and/or buffer to wake and stabilize before starting a
• SPI interface with external clock
conversion. In external reference mode (or if the inter-
• SPI interface with internal clock nal reference is already on), no reference settling time
• SPI interface with internal clock and scan mode is needed after power-up.

Table 1. Command/Configuration/Control Register

BIT7 (MSB) BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 (LSB)
COMMAND
CH SEL2 CH SEL1 CH SEL0 SCAN1 SCAN0 REF/PD_SEL1 REF/PD SEL0 INT/EXT CLK
POWER-UP
0 0 0 0 0 1 1 0
STATE

14 ______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters

MAX1167/MAX1168
Table 2. Channel Select Table 3. MAX1167 Scan Mode, Internal
BIT7 BIT6 BIT5 CHANNEL Clock Only
CH SEL2 CH SEL1 CH SEL0 AIN_ BIT4 BIT3
ACTION
0 0 0 0 SCAN1 SCAN0
0 0 1 1 Single channel, no scan 0 0
0 1 0 2 Sequentially scan channels 0 through N
0 1
0 1 1 3 (N ≤ 3)
1 0 0 4 Sequentially scan channels 2 through N
1 0
1 0 1 5 (2 ≤ N ≤ 3)
1 1 0 6 Scan channel N four times 1 1
1 1 1 7

Table 4. MAX1168 Scan Mode, Internal

Clock Only (Not for DSP Mode)
BIT4 BIT3
ACTION
SCAN1 SCAN0
Single channel, no scan 0 0
Sequentially scan channels 0 through N
0 1
(N ≤ 7)
Sequentially scan channels 4 through N
1 0
(4 ≤ N ≤ 7)
Scan channel N eight times 1 1

Table 5. Power-Down Modes

BIT2 BIT1 TYPICAL TYPICAL WAKE-
REFERENCE MODE
REF/PD_ REF/PD REFERENCE SUPPLY UP TIME
(INTERNAL REFERENCE)
SEL1 SEL0 CURRENT (CREF = 1µF)

Internal reference and reference buffer on

0 0 Internal 1mA NA
between conversions
Internal reference and reference buffer off
0 1 Internal 0.6µA 5ms
between conversions
Internal reference on, reference buffer off
1 0 Internal 0.43mA 5ms
between conversions
1 1 External Internal reference and buffer always off 0.6µA NA

Table 6. Clock Modes

BIT0
INT/EXT CLOCK MODE
CLK
0 External clock
1 Internal clock

______________________________________________________________________________________ 15
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
MAX1167/MAX1168

tCSW

CS

tCSS tCP tCSH

tCL tCH

SCLK •••

tDS
tDH

DIN

tDO tTR
tDV

DOUT

Figure 8. Detailed SPI Interface Timing

when in SPI/QSPI/MICROWIRE mode and on the falling

edge of DSPR when in DSP mode. Allow 5ms for the
CS internal reference to rise and settle when powering up
from a complete shutdown (VREF = 0, CREF = 1µF).
COMPLETE CONVERSION SEQUENCE
The internal reference stays on and the buffer is shut off
DOUT on the rising edge of CS when bit 2 = 1 and bit 1 = 0.
CONVERSION 0 CONVERSION 1 The MAX1167/MAX1168 enter this mode on the rising
edge of CS. The buffer wakes up on the falling edge of
POWERED UP POWERED DOWN POWERED UP CS when in SPI/QSPI/MICROWIRE mode and on the ris-
ing edge of DSPR when in DSP mode. Allow 5ms for
VREF to settle when powering up from a complete shut-
Figure 9. Shutdown Sequence down (VREF = 0, CREF = 1µF). VREFCAP is always equal
to +4.096V in this mode.
Power-Down Modes Set both bit 2 and bit 1 to 1 to turn off the reference and
Table 5 shows the MAX1167/MAX1168 power-down reference buffer to allow connection of an external ref-
modes. Three internal reference modes and one exter- erence. Using an external reference requires no extra
nal reference mode are available. Select power-down wake-up time.
modes by writing to bits 2 and 1 in the command/con-
figuration/control register. The MAX1167/MAX1168 Operating Modes
enter the selected power-down mode on the rising External Clock 8-Bit-Wide Data-Transfer Mode
edge of CS. (MAX1167 and MAX1168)
The internal reference stays on when CS is pulled high, Force DSPR high and DSEL low (MAX1168) for SPI/
if bits 2 and 1 are set to zero. This mode allows for the QSPI/MICROWIRE interface mode. The falling edge of
fastest turn-on time. CS wakes the analog circuitry and allows SCLK to clock
in data. Ensure the duty cycle on SCLK is between 45%
Setting bit 2 = 0 and bit 1 = 1 turns both the reference and 55% when operating at 4.8MHz (the maximum
and reference buffer off when CS is brought high. This clock frequency). For lower clock frequencies, ensure
mode achieves the lowest supply current. The refer- the minimum high and low times are at least 93ns.
ence and buffer wake up on the falling edge of CS External-clock-mode conversions with

16 ______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters

MAX1167/MAX1168
CS

1 8 16 24
SCLK

MSB LSB

DIN 0

MSB LSB

DOUT

DSPR*

DSEL*
ADC
STATE tACQ tCONV IDLE
*MAX1168 ONLY

Figure 10. SPI External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing

SCLK rates less than 125kHz can reduce accuracy due External Clock 16-Bit-Wide Data-Transfer Mode
to leakage of the sampling capacitor. DOUT changes (MAX1168 Only)
from high-Z to logic low after CS is brought low. Input Force DSPR high and DSEL high for SPI/QSPI/
data latches on the rising edge of SCLK. The first SCLK MICROWIRE interface mode. Logic high at DSEL allows
rising edge begins loading data into the command/con- the MAX1168 to transfer data in 16-bit-wide words. The
figuration/control register from DIN. The devices select acquisition time is extended an extra eight SCLK cycles
the proper channel for conversion on the rising edge of in the 16-bit-wide data-transfer mode. The falling edge of
the 3rd SCLK cycle. Acquisition begins immediately CS wakes the analog circuitry and allows SCLK to clock
thereafter and ends on the falling edge of the 6th clock in data. Ensure the duty cycle on SCLK is between 45%
cycle. The MAX1167/MAX1168 sample the input and and 55% when operating at 4.8MHz (the maximum clock
begin conversion on the falling edge of the 6th clock frequency). For lower clock frequencies, ensure that the
cycle. Setup and configuration of the minimum high and low times are at least 93ns. External-
MAX1167/MAX1168 complete on the rising edge of the clock-mode conversions with SCLK rates less than
8th clock cycle. The conversion result is available (MSB 125kHz can reduce accuracy due to leakage of the sam-
first) at DOUT on the falling edge of the 8th SCLK cycle. pling capacitor. DOUT changes from high-Z to logic low
To read the entire conversion result, 16 SCLK cycles are after CS is brought low. Input data latches on the rising
needed. Extra clock pulses, occurring after the conver- edge of SCLK. The first SCLK rising edge begins loading
sion result has been clocked out and prior to the rising data into the command/configuration/control register from
edge of CS, cause zeros to be clocked out of DOUT. DIN. The devices select the proper channel for conver-
The MAX1167/ MAX1168 external clock 8-bit-wide data- sion and begin acquisition on the rising edge of the 3rd
transfer mode requires 24 SCLK cycles for completion SCLK cycle. Setup and configuration of the MAX1168
(Figure 10). completes on the rising edge of the 8th clock cycle.
Force CS high after the conversion result is read. For Acquisition ends on the falling edge of the 14th SCLK
maximum throughput, force CS low again to initiate the cycle. The MAX1168 samples the input and begins con-
next conversion immediately after the specified mini- version on the falling edge of the 14th clock cycle. The
mum time (tCSW). Forcing CS high in the middle of a conversion result is available (MSB first) at DOUT on the
conversion immediately aborts the conversion and falling edge of the 16th SCLK cycle. To read the entire
places the MAX1167/MAX1168 in shutdown. conversion result, 16 SCLK cycles are needed. Extra
clock pulses, occurring after the conversion result has
been clocked out and prior to the rising edge of CS,
cause zeros to be clocked out of DOUT.

______________________________________________________________________________________________________ 17
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
MAX1167/MAX1168

CS
1 8 16 24 32
SCLK
MSB LSB
DIN 0 X X X X X X X X
MSB LSB
DOUT

DSPR
DSEL
ADC
STATE tACQ tCONV IDLE
,
X = DON T CARE

Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)

CS
1 8 9 16 24
SCLK
2 6 25
INTERNAL
CLK
MSB LSB
DIN 1

MSB LSB
DOUT X

EOC

ADC
STATE , tACQ tCONV POWER-DOWN
IDLE
X = DON T CARE
DSPR = DVDD, DSEL = GND (MAX1168 ONLY)

Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing

The MAX1168 external clock 16-bit-wide data-transfer ing edge of SCLK. The command/configuration/control
mode requires 32 SCLK cycles for completion (Figure 11). register begins reading DIN on the first SCLK rising edge
Force CS high after the conversion result is read. For and ends on the rising edge of the 8th SCLK cycle. The
maximum throughput, force CS low again to initiate the MAX1167/MAX1168 select the proper channel for con-
next conversion immediately after the specified mini- version on the rising edge of the 3rd SCLK cycle. The
mum time (tCSW). Forcing CS high in the middle of a internal oscillator activates 125ns after the rising edge of
conversion immediately aborts the conversion and the 8th SCLK cycle. Turn off the external clock while the
places the MAX1168 in shutdown. internal clock is on. Turning off SCLK ensures the lowest
noise performance during acquisition. Acquisition begins
Internal Clock 8-Bit-Wide Data-Transfer and on the 2nd rising edge of the internal clock and ends on
Scan Mode (MAX1167 and MAX1168) the falling edge of the 6th internal clock cycle. Each bit
Force DSPR high and DSEL low (MAX1168) for the SPI/ of the conversion result shifts into memory as it becomes
QSPI/MICROWIRE interface mode. The falling edge of available. The conversion result is available (MSB first) at
CS wakes the analog circuitry and allows SCLK to clock DOUT on the falling edge of EOC. The internal oscillator
in data (Figure 12). DOUT changes from high-Z to logic and analog circuitry are shut down on the high-to-low
low after CS is brought low. Input data latches on the ris- EOC transition. Use the EOC high-to-low transition as the

18 ______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters

MAX1167/MAX1168
CS
1 8 9 16 17 24 32
SCLK
2 13 32
INTERNAL
CLK

DIN DATA XXXXXXXX

MSB LSB
DOUT X

EOC

ADC
STATE CONFIGURATION tACQ tCONV POWER-DOWN
,
X = DON T CARE
DSPR = DSEL = DVDD

Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)

CS
1 8 9 40
SCLK
2 6 24 26 30 48
INTERNAL
CLK
MSB LSB
DIN 1

MSB LSB
DOUT X

EOC

ADC
STATE CONFIGURATION tACQ tCONV tACQ tCONV POWER-DOWN
,
X = DON T CARE
DSPR = DVDD, DSEL = GND (MAX1168 ONLY)

Figure 14. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing

signal to restart the external clock (SCLK). To read the Scan mode allows multiple channels to be scanned
entire conversion result, 16 SCLK cycles are needed. consecutively or one channel to be scanned eight
Extra clock pulses, occurring after the conversion result times. Scan mode can only be enabled when using the
has been clocked out and prior to the rising edge of MAX1167/MAX1168 in the internal clock mode. Enable
CS, cause the conversion result to be shifted out again. scanning by setting bits 4 and 3 in the command/con-
The MAX1167/MAX1168 internal clock 8-bit-wide data- figuration/control register (see Tables 3 and 4). In scan
transfer mode requires 24 external clock cycles and 25 mode, conversion results are stored in memory until the
internal clock cycles for completion. completion of the last conversion in the sequence.
Force CS high after the conversion result is read. For Upon completion of the last conversion in the
maximum throughput, force CS low again to initiate the sequence, EOC transitions from high to low to indicate
next conversion immediately after the specified mini- the end of the conversion and shuts down the internal
mum time (tCSW). Forcing CS high in the middle of a oscillator. Use the EOC high-to-low transition as the sig-
conversion immediately aborts the conversion and nal to restart the external clock (SCLK). DOUT provides
places the MAX1167/MAX1168 in shutdown. the conversion results in the same order as the channel
conversion process. The MSB of the first conversion is
available at DOUT on the falling edge of EOC (Figure 14).

______________________________________________________________________________________ 19
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
MAX1167/MAX1168

CS
1 8 9 16 17 48
SCLK
2 13 32 34 45 64
INTERNAL
CLK

DIN DATA XXXXXXXX

MSB LSB
DOUT X

EOC

ADC
STATE , tACQ tCONV tACQ tCONV POWER-DOWN
X = DON T CARE

Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1168 Only)

tCSW

CS ...
tDF

tFSS

DSPR ...
tFSH

tCSS
tCSH
tCL tCH

SCLK ...
tCP tDS
tDH

DIN ...

tDV tDO tTR

DOUT
...

Figure 16. Detailed DSP-Interface Timing (MAX1168 Only)

Internal Clock 16-Bit-Wide Data-Transfer and Scan conversion on the rising edge of the 3rd SCLK cycle.
Mode (MAX1168 Only) The internal oscillator activates 125ns after the rising
Force DSPR high and DSEL low for the SPI/QSPI/ edge of the 16th SCLK cycle. Turn off the external clock
MICROWIRE interface mode. The falling edge of CS while the internal clock is on. Turning off SCLK ensures
wakes the analog circuitry and allows SCLK to clock in lowest noise performance during acquisition.
data (Figure 13). DOUT changes from high-Z to logic Acquisition begins on the 2nd rising edge of the inter-
low after CS is brought low. Input data latches on the nal clock and ends on the falling edge of the 18th inter-
rising edge of SCLK. The command/configuration/con- nal clock cycle. Each bit of the conversion result shifts
trol register begins reading DIN on the first SCLK rising into memory as it becomes available. The conversion
edge and ends on the rising edge of the 8th SCLK result is available (MSB first) at DOUT on the falling
cycle. The MAX1168 selects the proper channel for edge of EOC. The internal oscillator and analog circuitry

20 ______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters

MAX1167/MAX1168
CS

DSPR

1 8 16 24
SCLK

MSB LSB

DIN 0

MSB LSB

DOUT

DSPX

ADC
STATE tACQ tCONV IDLE

Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)

CS

DSPR
1 8 16 24 32
SCLK
MSB LSB
DIN 0 X X X X X X X X
MSB LSB
DOUT

DSPX

ADC
STATE tACQ tCONV IDLE
,
X = DON T CARE

Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)

are shut down on the EOC high-to-low transition. Use Force CS high after the conversion result is read. For
the EOC high-to-low transition as the signal to restart maximum throughput, force CS low again to initiate the
the external clock (SCLK). To read the entire conver- next conversion immediately after the specified mini-
sion result, 16 SCLK cycles are needed. Extra clock mum time (tCSW). Forcing CS high in the middle of a
pulses, occurring after the conversion result has been conversion immediately aborts the conversion and
clocked out and prior to the rising edge of CS, cause places the MAX1168 in shutdown.
the conversion result to be shifted out again. The Scan mode allows multiple channels to be scanned
MAX1168 internal-clock 16-bit-wide data-transfer mode consecutively or one channel to be scanned eight
requires 32 external clock cycles and 32 internal clock times. Scan mode can only be enabled when using the
cycles for completion. MAX1168 in internal clock mode. Enable scanning by

______________________________________________________________________________________ 21
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
rates less than 125kHz can reduce accuracy due to
MAX1167/MAX1168

leakage of the sampling capacitor. The input data

OUTPUT CODE latches on the falling edge of SCLK. The command/
FULL-SCALE configuration/control register starts reading data in on
1111...111 TRANSITION the falling edge of the first SCLK cycle immediately fol-
1111...110 lowing the falling edge of the frame sync pulse and
1111...101 ends on the falling edge of the 8th SCLK cycle. The
MAX1168 selects the proper channel for conversion on
the falling edge of the 3rd clock cycle and begins
acquisition. Acquisition continues until the rising edge
FS = VREF of the 7th clock cycle. The MAX1168 samples the input
V on the rising edge of the 7th clock cycle. On the rising
1 LSB = REF
65,536 edge of the 8th clock cycle, the MAX1168 outputs a
0000...011
0000...010 frame sync pulse at DSPX. The frame sync pulse alerts
0000...001 the DSP that the conversion results are about to be out-
0000...000 put at DOUT (MSB first) starting on the rising edge of
0 1 2 3 FS the 9th clock pulse. To read the entire conversion
INPUT VOLTAGE (LSB) FS - 3/2 LSB
result, 16 SCLK cycles are needed. Extra clock pulses,
occurring after the conversion result has been clocked
out and prior to the next rising edge of DSPR, cause
zeros to be clocked out of DOUT. The MAX1168 exter-
Figure 19. Unipolar Transfer Function, Full Scale (FS) = VREF,
Zero Scale (ZS) = GND nal clock, DSP 8-bit-wide data-transfer mode requires
24 clock cycles to complete.
setting bits 4 and 3 in the command/configuration/con- Begin a new conversion by sending a new frame sync
trol register (see Tables 3 and 4). In scan mode, conver- pulse to DSPR followed by new configuration data.
sion results are stored in memory until the completion of Send the new DSPR pulse immediately after reading
the last conversion in the sequence. Upon completion of the conversion result to realize maximum throughput.
the last conversion in the sequence, EOC transitions Sending a new frame sync pulse in the middle of a con-
from high to low to indicate the end of the conversion version immediately aborts the current conversion and
and shuts down the internal oscillator. Use the EOC begins a new one. A rising edge on CS in the middle of
high-to-low transition as the signal to restart the external a conversion aborts the current conversion and places
clock (SCLK). DOUT provides the conversion results in the MAX1168 in shutdown.
the same order as the channel conversion process. The DSP 16-Bit-Wide Data-Transfer Mode (External
MSB of the first conversion is available at DOUT on the Clock Mode, MAX1168 Only)
falling edge of EOC. Figure 15 shows the timing Figure 16 shows the DSP-interface timing diagram.
diagram for 16-bit-wide data transfer in scan mode. Logic low at DSPR on the falling edge of CS enables
DSP 8-Bit-Wide Data-Transfer Mode (External Clock DSP interface mode. After the MAX1168 enters DSP
Mode, MAX1168 Only) mode, CS can remain low for the duration of the con-
Figure 16 shows the DSP-interface timing diagram. version process and each subsequent conversion. The
Logic low at DSPR on the falling edge of CS enables acquisition time is extended an extra eight SCLK cycles
DSP interface mode. After the MAX1168 enters DSP in the 16-bit-wide data-transfer mode. Drive DSEL high
mode, CS can remain low for the duration of the conver- to select the 16-bit-wide data-transfer mode. A sync
sion process and each subsequent conversion. Drive pulse from the DSP at DSPR wakes the analog circuitry
DSEL low to select the 8-bit data-transfer mode. A sync and allows SCLK to clock in data (Figure 18). The
pulse from the DSP at DSPR wakes the analog circuitry frame sync pulse also alerts the MAX1168 that incom-
and allows SCLK to clock in data (Figure 17). The frame ing data is about to be sent to DIN. Ensure the duty
sync pulse alerts the MAX1168 that incoming data is cycle on SCLK is between 45% and 55% when operat-
about to be sent to DIN. Ensure the duty cycle on SCLK ing at 4.8MHz (the maximum clock frequency). For
is between 45% and 55% when operating at 4.8MHz lower clock frequencies, ensure the minimum high and
(the maximum clock frequency). For lower clock fre- low times are at least 93ns. External-clock-mode con-
quencies, ensure the minimum high and low times are at versions with SCLK rates less than 125kHz can reduce
least 93ns. External clock mode conversions with SCLK accuracy due to leakage of the sampling capacitor.

22 ______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters

MAX1167/MAX1168
I/O CS I/O CS
SCK SCLK SK SCLK
MISO DOUT SI DOUT
SPI VDD MICROWIRE

MAX1167 MAX1167
MAX1168 MAX1168
SS

Figure 20a. SPI Connections Figure 20b. MICROWIRE Connections

1ST BYTE READ 2ND BYTE READ

1 4 6 8 12 16
SCLK
CS

0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7

DOUT*
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z

3RD BYTE READ

20 24

HIGH-Z
D7 D6 D5 D4 D3 D2 D1 D0
LSB

Figure 20c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)

The input data latches on the falling edge of SCLK. The Begin a new conversion by sending a new frame sync
command/configuration/control register starts reading pulse to DSPR followed by new configuration data.
data in on the falling edge of the first SCLK cycle immedi- Send the new DSPR pulse immediately after reading
ately following the falling edge of the frame sync pulse the conversion result to realize maximum throughput.
and ends on the falling edge of the 16th SCLK cycle. The Sending a new frame sync pulse in the middle of a con-
MAX1168 selects the proper channel for conversion on version immediately aborts the current conversion and
the falling edge of the 3rd clock cycle and begins acqui- begins a new one. A rising edge on CS in the middle of
sition. Acquisition continues until the rising edge of the a conversion aborts the current conversion and places
15th clock cycle. The MAX1168 samples the input on the the MAX1168 in shutdown.
rising edge of the 15th clock cycle. On the rising edge of
the 16th clock cycle, the MAX1168 outputs a frame sync Output Coding and Transfer Function
pulse at DSPX. The frame sync pulse alerts the DSP that The data output from the MAX1167/MAX1168 is straight
the conversion results are about to be output at DOUT binary. Figure 19 shows the nominal transfer function.
(MSB first) starting on the rising edge of the 17th clock Code transitions occur halfway between successive
pulse. To read the entire conversion result, 16 SCLK integer LSB values (V REF = +4.096V, and 1 LSB =
cycles are needed. Extra clock pulses, occurring after the +62.5µV or 4.096V / 65,536V).
conversion result has been clocked out and prior to the
next rising edge of DSPR, cause zeros to be clocked out
of DOUT. The MAX1168 external clock, DSP 16-bit-wide
data-transfer mode requires 32 clock cycles to complete.

______________________________________________________________________________________ 23
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
MAX1167/MAX1168

Table 7. Detailed SSPCON Register Contents

CONTROL BIT SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)

WCOL BIT7 X Write Collision Detection Bit

SSPOV BIT6 X Receive Overflow Detection Bit

Synchronous Serial-Port Enable Bit:

0: Disables serial port and configures these pins as I/O port pins.
SSPEN BIT5 1
1: Enables serial port and configures SCK, SDO, and SCI pins as serial
port pins.
CKP BIT4 0 Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
SSPM3 BIT3 0
SSPM2 BIT2 0 Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and
SSPM1 BIT1 0 selects fCLK = fOSC / 16.
SSPM0 BIT0 1
X = Don’t care.

Applications Information When using the internal clock mode, the internal oscilla-
tor controls the acquisition and conversion processes,
Internal Reference while the external oscillator shifts data in and out of the
The internal bandgap reference provides a buffered MAX1167/MAX1168. Turn off the external clock (SCLK)
+4.096V. Bypass REFCAP with a 0.1µF capacitor to when the internal clock is on to realize lowest noise per-
AGND and REF with a 1µF capacitor to AGND. For best formance. The internal clock remains off in external
results, use low-ESR, X5R/X7R ceramic capacitors. clock mode.
Allow 5ms for the reference and buffer to wake up from
full power-down (see Table 5). Input Buffer
Most applications require an input-buffer amplifier to
External Reference achieve 16-bit accuracy. The input amplifier must have
The MAX1167/MAX1168 accept an external reference a slew rate of at least 2V/µs and a unity-gain bandwidth
with a voltage range between +3.8V and AVDD. Connect of at least 10MHz to complete the required output-volt-
the external reference directly to REF. Bypass REF to age change before the end of the acquisition time.
AGND with a 10µF capacitor. When not using a low-ESR At the beginning of the acquisition, the internal sam-
bypass capacitor, use a 0.1µF ceramic capacitor in paral- pling capacitor array connects to AIN_ (the amplifier
lel with the 10µF capacitor. Noise on the reference input), causing some disturbance on the output of the
degrades conversion accuracy. buffer. Ensure the sampled voltage has settled before
The input impedance at REF is 37kΩ for DC currents. the end of the acquisition time.
During a conversion, the external reference at REF
must deliver 118µA of DC load current and have an out-
put impedance of 10Ω or less.
For optimal performance, buffer the reference through CS CS
an op amp and bypass the REF input. Consider the SCK SCLK
equivalent input noise (40µV RMS ) of the MAX1167/ MISO DOUT
QSPI VDD
MAX1168 when choosing a reference.
MAX1167
Internal/External Oscillator MAX1168
Select either an external (0.1MHz to 4.8MHz) or the SS
internal 4MHz (typ) clock to perform conversions
(Table 6). The external clock shifts data in and out of
the MAX1167/MAX1168 in either clock mode. Figure 21a. QSPI Connections

24 ______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters

MAX1167/MAX1168
Table 8. Detailed SSPSTAT Register Contents

CONTROL BIT SETTINGS SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)

SPI Data-Input Sample Phase. Input data is sampled at the middle of

SMP BIT7 0
the data output time.
SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the
CKE BIT6 1
serial clock.
D/A BIT5 X Data Address Bit
P BIT4 X Stop Bit
S BIT3 X Start Bit
R/W BIT2 X Read/Write Bit Information
UA BIT1 X Update Address
BF BIT0 X Buffer-Full Status Bit
X = Don’t care.

SCLK 1 4 6 8 12 16 20 24
CS

HIGH-Z
DOUT* D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SAMPLING INSTANT MSB LSB
*WHEN CS IS HIGH, DOUT = HIGH-Z

Figure 21b. QSPI Interface Timing Sequence (External Clock, 8-Bit Data Transfer, CPOL = CPHA = 0)

Digital Noise reduce linearity errors due to finite amplifier gain, use
Digital noise can couple to AIN_ and REF. The conversion amplifier circuits with sufficient loop gain at the fre-
clock (SCLK) and other digital signals active during input quencies of interest.
acquisition contribute noise to the conversion result.
Noise signals, synchronous with the sampling interval, DC Accuracy
result in an effective input offset. Asynchronous signals To improve DC accuracy, choose a buffer with an offset
produce random noise on the input, whose high-frequen- much less than the MAX1167/MAX1168s’ offset (±10mV
cy components can be aliased into the frequency band max for +5V supply), or whose offset can be trimmed
of interest. Minimize noise by presenting a low imped- while maintaining stability over the required temperature
ance (at the frequencies contained in the noise signal) at range.
the inputs. This requires bypassing AIN_ to AGND, or
buffering the input with an amplifier that has a small-sig-
VDD VDD
nal bandwidth of several megahertz (doing both is prefer-
able). AIN has a typical bandwidth of 4MHz.
SCLK SCK
Distortion
Avoid degrading dynamic performance by choosing an DOUT SDI
amplifier with distortion much less than the total har- CS I/O
PIC16/17
monic distortion of the MAX1167/MAX1168 at the fre-
quencies of interest (THD = -100dB at 1kHz). If the MAX1167
chosen amplifier has insufficient common-mode rejec- MAX1168
tion, which results in degraded THD performance, use
the inverting configuration (positive input grounded) to GND
eliminate errors from this source. Low-temperature-
coefficient, gain-setting resistors reduce linearity errors
caused by resistance changes due to self-heating. To Figure 22a. SPI-Interface Connection for a PIC16/PIC17

______________________________________________________________________________________ 25
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
MAX1167/MAX1168

1ST BYTE READ 2ND BYTE READ

1 4 6 8 12 16
SCLK
CS

0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8

DOUT*
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z

3RD BYTE READ

20 24

HIGH-Z
D7 D6 D5 D4 D3 D2 D1 D0
LSB

Figure 22b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)

QSPI Interface
EXTERNAL Using the high-speed QSPI interface with CPOL = 0 and
CLOCK CPHA = 0, the MAX1167/MAX1168 support a maximum
f SCLK of 4.8MHz. Figure 21a shows the MAX1167/
MAX1168 connected to a QSPI master, and Figure 21b
SCLK SCLK shows the associated interface timing.
TFS DSPR
RFS DSPX
PIC16 with SSP Module and PIC17
DSP
DT DIN MAX1168 Interface
DR DOUT The MAX1167/MAX1168 are compatible with a
FL1 CS PIC16/PIC17 controller (µC), using the synchronous seri-
al-port (SSP) module.
To establish SPI communication, connect the controller
Figure 23. DSP Interface Connection
as shown in Figure 22a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
Serial Interfaces port control register (SSPCON) and synchronous serial-
SPI and MICROWIRE Interfaces port status register (SSPSTAT) to the bit patterns shown
When using the SPI (Figure 20a) or MICROWIRE (Figure in Tables 7 and 8.
20b) interfaces, set CPOL = 0 and CPHA = 0. Drive CS In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data to
low to power on the MAX1167/MAX1168 before starting a be synchronously transmitted and received simultane-
conversion (Figure 20c). Three consecutive 8-bit-wide ously. Three consecutive 8-bit-wide readings (Figure
readings are necessary to obtain the entire 16-bit result 22b) are necessary to obtain the entire 16-bit result from
from the ADC. DOUT data transitions on the serial clock’s the ADC. DOUT data transitions on the serial clock’s
falling edge. The first 8-bit-wide data stream contains all falling edge and is clocked into the µC on SCLK’s rising
leading zeros. The 2nd 8-bit-wide data stream contains edge. The first 8-bit-wide data stream contains all zeros.
the MSB through D6. The 3rd 8-bit-wide data stream con- The 2nd 8-bit-wide data stream contains the MSB
tains D5 through D0 followed by S1 and S0. through D6. The 3rd 8-bit-wide data stream contains bits
D5 through D0 followed by S1 and S0.

26 ______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters

MAX1167/MAX1168
EFFECTIVE NUMBER OF BITS (ENOB)
16
AIN_ AIN_ CS CS
14 SCLK SCLK
REF
12 1μF DOUT DOUT
+5V AVDD
EFFECTIVE BITS

10 MAX1167
MAX1168
8 0.1μF 10Ω

6 AGND
DVDD
4 AGND
0.1μF DGND
2
fSAMPLE = 200ksps
0
0.1 1 10 100
GND
FREQUENCY (kHz)

Figure 24. Effective Bits vs. Frequency Figure 25. Powering AVDD and DVDD from a Single Supply

DSP Interface Aperture Definitions

The DSP mode of the MAX1168 only operates in exter- Aperture jitter (tAJ) is the sample-to-sample variation in
nal clock mode. Figure 23 shows a typical DSP interface the time between samples. Aperture delay (tAD) is the
connection to the MAX1168. Use the same oscillator as time between the falling edge of the sampling clock
the DSP to provide the clock signal for the MAX1168. and the instant when the actual sample is taken.
The DSP provides the falling edge at CS to wake the
MAX1168. The MAX1168 detects the state of DSPR on Signal-to-Noise Ratio
the falling edge of CS (Figure 17). Logic low at DSPR For a waveform perfectly reconstructed from digital
places the MAX1168 in DSP mode. After the MAX1168 samples, signal-to-noise ratio (SNR) is the ratio of the
enters DSP mode, CS can be left low. A frame sync full-scale analog input (RMS value) to the RMS quanti-
pulse from the DSP to DSPR initiates a conversion. The zation error (residual error). The ideal, theoretical mini-
MAX1168 sends a frame sync pulse from DSPX to the mum analog-to-digital noise is caused by quantization
DSP signaling that the MSB is available at DOUT. Send noise error only and results directly from the ADC’s res-
another frame sync pulse from the DSP to DSPR to olution (N bits):
begin the next conversion. The MAX1168 does not oper- SNR = (6.02 ✕ N + 1.76)dB
ate in scan mode when using DSP mode. In reality, there are other noise sources besides quanti-
Definitions zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
Integral Nonlinearity signal to the RMS noise, which includes all spectral
Integral nonlinearity (INL) is the deviation of the values components minus the fundamental, the first five har-
on an actual transfer function from a straight line. This monics, and the DC offset.
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function, Signal-to-Noise Plus Distortion
once offset and gain errors have been nullified. The Signal-to-noise plus distortion (SINAD) is the ratio of the
static linearity parameters for the MAX1167/MAX1168 fundamental input frequency’s RMS amplitude to the
are measured using the end-point method. RMS equivalent of all the other ADC output signals:
SINAD (dB) = 20 ✕ log [SignalRMS / (Noise +
Differential Nonlinearity Distortion)RMS]
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of ±1 LSB. A
DNL error specification of ±1 LSB guarantees no miss-
ing codes and a monotonic transfer function.

______________________________________________________________________________________ 27
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Effective Number of Bits Supplies, Layout, Grounding, and
MAX1167/MAX1168

Effective number of bits (ENOB) indicates the global Bypassing

accuracy of an ADC at a specific input frequency and Use printed circuit (PC) boards with separate analog
sampling rate. An ideal ADC’s error consists of quanti- and digital ground planes. Do not use wire-wrap
zation noise only. With an input range equal to the full- boards. Connect the two ground planes together at the
scale range of the ADC, calculate the ENOB as follows: MAX1167/MAX1168 AGND terminal. Isolate the digital
ENOB = (SINAD - 1.76) / 6.02 supply from the analog with a low-value resistor (10Ω)
or ferrite bead when the analog and digital supplies
Figure 24 shows the ENOB as a function of the come from the same source (Figure 25).
MAX1167/MAX1168s’ input frequency.
Constraints on sequencing the power supplies and
Total Harmonic Distortion inputs are as follows:
Total harmonic distortion (THD) is the ratio of the RMS • Apply AGND before DGND.
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as: • Apply AIN_ and REF after AV DD and AGND are
present.
⎡
(V22 + V32 + V42 + V52 ) ⎤⎥ • DVDD is independent of the supply sequencing.
THD = 20 × log ⎢
⎢ V1 ⎥ Ensure that digital return currents do not pass through
⎢⎣ ⎥⎦ the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
where V1 is the fundamental amplitude and V2 through ground trace impedance of only 0.05Ω creates an error
V5 are the 2nd- through 5th-order harmonics. voltage of about 250µV and a 4 LSB error with a +4.096V
full-scale system.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the The board layout should ensure that digital and analog
RMS amplitude of the fundamental (maximum signal signal lines are kept separate. Do not run analog and dig-
component) to the RMS value of the next-largest fre- ital lines (especially the SCLK and DOUT) parallel to one
quency component. another. If one must cross another, do so at right angles.
The ADC’s high-speed comparator is sensitive to high-
frequency noise on the AVDD power supply. Bypass an
excessively noisy supply to the analog ground plane
with a 0.1µF capacitor in parallel with a 1µF to 10µF
low-ESR capacitor. Keep capacitor leads short for best
supply-noise rejection.

28 ______________________________________________________________________________________
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Pin Configurations

MAX1167/MAX1168
TOP VIEW
DOUT 1 16 DVDD DSPR 1 24 N.C.

SCLK 2 15 DGND DSEL 2 23 DSPX

DIN 3 14 CS DOUT 3 22 DVDD

EOC 4 MAX1167 13 AVDD SCLK 4 21 DGND

AIN0 5 12 AGND DIN 5 MAX1168 20 CS

AIN1 6 11 AGND EOC 6 19 AVDD

AIN2 7 10 REFCAP AIN0 7 18 AGND

AIN3 8 9 REF AIN1 8 17 AGND

QSOP AIN2 9 16 REFCAP

AIN3 10 15 REF

AIN4 11 14 AIN7

AIN5 12 13 AIN6

QSOP

Chip Information Package Information

TRANSISTOR COUNT: 20,760 For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
PROCESS: BiCMOS “-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
16 QSOP E16-1
21-0055
24 QSOP E24-1

______________________________________________________________________________________ 29
 Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Revision History
MAX1167/MAX1168

REVISION REVISION PAGES

DESCRIPTION
NUMBER DATE CHANGED
0 8/03 Initial release. —
Changed 2.9mA at 200ksps to 3.6mA at 200ksps, 1.45mA at 100ksps to 1.85mA at
100ksps, and 145μA at 10ksps to 185μA to 10ksps in the General Description and 1
Features sections.
1 10/09 Removed the ±1.2 INL LSB and ±2 INL LSB packages from the Ordering Information
1, 29
table.
Updated the Electrical Characteristics table to include the reference buffer and GBD
2–6
at -40°C.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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