ADC4320/ADC4322/

ADC4325

Very High Speed 16-Bit,

Sampling A/D Converters
in a Space-Saving 46-Pin Hybrid Package

Introduction
The ADC4320, ADC4322, and ADC4325 are complete 16-bit, 1 MHz, 2 MHz,
and 500 kHz A/D converter subsystems with a built-in sample-and-hold amplifier
in a space-saving 46-pin hybrid package. They offer pin-programmable input
voltage ranges of ±2.5V, ±5V, ±10V and 0 to +10V, and have been designed for
use in applications, such as ATE, digital oscilloscopes, medical imaging, radar,
sonar, and analytical instrumentation, requiring high speed and high resolution
front ends. The ADC4322 is capable of digitizing a 1 MHz signal at a 2 MHz
sampling rate with a guarantee of no missing codes from 0°C to +70°C, or in an
extended temperature range version, from –25°C to +85°C. Equally impressive
in frequency domain applications, the ADC4325 features 91 dB minimum signal-
to-noise ratio with input signals from DC to 100 kHz. Features
The ADC432X Series utilizes the latest semiconductor technologies to produce ❑ 2 MHz, 1 MHz, and 500 kHz
a cost-effective, high performance part in a 46-pin hybrid package. They are de- Conversion Rates
signed around a two-pass, sub-ranging architecture that integrates a low distor-
❑ 16-Bit Resolution
tion sample-and-hold amplifier, precision voltage reference, ultra-stable 16-bit
linear reference D/A converter, all necessary timing circuitry and tri-state ❑ 0.003% Maximum Integral
CMOS/TTL compatible output lines for ease of system integration. Nonlinearity
❑ No Missing Codes
Superior performance and ease-of-use make the ADC432X Series the ideal so-
lution for those applications requiring a sample-and-hold amplifier directly at the ❑ Peak Distortion: –92 dB Max.
input to the A/D converter. Having the S/H amplifier integrated with the A/D con- (100 kHz Input)
verter benefits the system designer in two ways. First, the S/H has been de- ❑ Signal to Noise Ratio:
signed specifically to complement the performance of the A/D converter; for ex- 86 dB (ADC4322) Min.
ample, the acquisition time, hold mode settling and droop rate have been opti- 89 dB (ADC4320) Min.
mized for the A/D converter, resulting in exceptional overall performance. 91 dB (ADC4325) Min.
Second, the designer achieves true 16-bit performance, avoiding degradation ❑ Total Harmonic Distortion:
due to ground loops, signal coupling, jitter and digital noise introduced when (100 kHz Input)
separate S/H and A/D converters are interconnected. Furthermore, the accura- –86 dB (ADC4320) Max.
cy, speed, and quality of the ADC432X Series are fully ensured by thorough, –90 dB (ADC4325) Max.
computer-controlled factory tests of each unit. ❑ TTL/CMOS Compatibility
❑ Low Noise
S/H Control
S/H IN 3
+ +
❑ Electromagnetic/Electrostatic
S/H IN 1 ∑ –1 Shielding
+
S/H IN 2 S/H ADC Clk
DNC
Applications
10-Bit
9-Bit
Data
❑ Digital Signal Processing
–0.2 +1 Trigger
Flash ADC
Transfer
❑ Sampling Oscilloscopes
+ +
Pass1/Pass2
Lo Byte EN ❑ Automatic Test Equipment
∑ ∑ –6.4 –4
–
MUX Amp Gate Hi Byte EN ❑ High-Resolution Imaging
+ Array
EXT OFF ADJ Residue Amp O/U Flow
❑ Analytical Instrumentation
B1 ❑ Medical Instrumentation
9-Bit Data
9-Bit DAC B1-B16 ❑ CCD Detectors
16-Bit Linear
❑ IR Imaging
❑ Sonar/Radar

+REF OUT Timing

–REF OUT Reference Circuit
Ext Gain Adj

Figure 1. Functional Block Diagram.

ADC4320/ADC4322/
ADC4325
Specifications1

SPECIFICATION ADC4325 ADC4320 ADC4322

ANALOG INPUT
Input Voltage Range
Bipolar ±2.5V, ±5V, ±10V ±2.5V, ±5V, ±10V ±2.5V, ±5V, ±10V
Unipolar 0 to +10V 0 to +10V 0 to +10V
Maximum Input Without Damage ±15.5V ±15.5V ±15.5V
Input Impedance
±2.5V 750Ω 750Ω 750 Ω
±5.0V, 0-10V 1.5 KΩ 1.5 KΩ 1.5 KΩ
±10V 3 kΩ 3 kΩ 3 kΩ
Offset and Gain Adj. Sensitivity 300 ppm FSR/V 300 ppm FSR/V 300 ppm FSR/V

DIGITAL INPUTS
Compatibility TTL, HCT, and ACT TTL, HCT, and ACT TTL, HCT, and ACT
Logic “0” +0.8V Max. +0.8V Max. +0.8V Max.
Logic “1” +2.0V Min. +2.0V Min. +2.0V Min.
Trigger Negative Edge Triggered Negative Edge Triggered Negative Edge Triggered
Loading 2 HCT Loads 2 HCT Loads 2 HCT Loads
TriggerPulse Width 100 ns Min. 100 ns Min. 50 ns Min.
High Byte Enable Active Low, B1-B8, B1 Active Low, B1-B8, B1 Active Low, B1-B8, B1
Low Byte Enable Active Low, B9-B16 Active Low, B9-B16 Active Low, B9-B16

DIGITAL OUTPUTS
Fan-Out 1 TTL Load 1 TTL Load 1 TTL Load
Logic “0” +0.4V +0.4V +0.4V
Logic “1” +2.4V +2.4V +2.4V
Output Coding Binary, Offset Binary, Binary, Offset Binary, Binary, Offset Binary,
2’s Complement 2’s Complement 2’s Complement
Transfer Pulse Data valid on positive edge Data valid on positive edge Data valid on positive edge
Over/Under Flow Valid = logic “0” (occurs only Valid = logic “0” (occurs only Valid = logic “0” (occurs only
when ±FS have been exceeded) when ±FS have been exceeded) when ±FS have been exceeded)

DYNAMIC
CHARACTERISTICS2
Maximum Throughput Rate 500 kHz 1.0 MHz 2.0 MHz
A/D Conversion Time 1.1 µs Typ. 620 ns Typ. 300 ns Typ.
S/H Acquisition Time 900 ns Typ. 380 ns Typ. 200 ns Typ.
S/H Aperture Delay 15 ns Max. 15 ns Max. 15 ns Max.
S/H Aperture Jitter 5 ps RMS Max. 5 ps RMS Max. 5 ps RMS Max.
S/H Feedthrough3 –90 dB Max.; –96 dB Typ. –90 dB Max.; –96 dB Typ. –90 dB Max.; –96 dB Typ.
Full Power Bandwidth 2.6 MHz Min. 3 MHz Min. 6 MHz Min.
Small Signal Bandwidth 2.6 MHz Min. 6 MHz Min. 8 MHz Min.
Signal to Noise Ratio4
100 kHz Input @ 0 dB 91 dB Min.;93 dB Typ. 89 dB Min.; 92 dB Typ. 86 dB Min.; 88 dB Typ.
495 kHz Input @ –10 dB – 79 dB Min.; 82 dB Typ. 76 dB Min.; 78 dB Typ.
980 kHz Input @ –10 dB – – 75 dB Min.; 78 dB Typ.
Peak Distortion4
100 kHz Input @ 0 dB –92 dB Max.; –97 dB Typ. –92 dB Max.; –97 dB Typ. –92 dB Max.; 97 dB Typ.
495 kHz Input @ –10 dB – –84 dB Max.; –95 dB Typ. –84 dB Max.; –95 dB Typ.
980 kHz Input @ –10 dB – – –81 dB Max.; –88 dB Typ.
Total Harmonic Distortion4
100 kHz Input @ 0 dB –90 dB Max.; –95 dB Typ. –86 dB Max.; –94 dB Typ. –86 dB Max. –94 dB Typ.
495 kHz Input @ –10 dB – –79 dB Max.; –86 dB Typ. –80 dB Max.; –88 dB Typ.
980 kHz Input @ –10 dB – – –80 dB Max.; –85 dB Typ.
THD + Noise5
100 kHz Input @ 0 dB 88 dB Min.; 91 dB Typ. 84 dB Min.; 91 dB Typ. 83 dB Min.; 87 dB Typ.
495 kHz Input @ –10 dB – 76 dB Min.; 81 dB Typ. 75 dB Min.; 77 dB Typ.
980 kHz Input @ –10 dB – – 74 dB Min.; 77dB Typ.
SPECIFICATION (CONT.) ADC4325 ADC4320 ADC4322
Step Response6 800 ns Max. to 1 LSB 500 ns Max. to 1 LSB 250 ns Max. to 2 LSBs

INTERNAL REFERENCE9
Voltage +5V, ±0.5% Max. +5V, ±0.5% Max. +5V, ±0.5% Max.
Stability 15 ppm/°C Max. 15 ppm/°C Max. 15 ppm/°C Max.
Available Current7 1.0 mA Max. 1.0 mA Max. 1.0 mA Max.

TRANSFER CHARACTERISTICS
Resolution 16 bits 16 bits 16 bits
Integral Nonlinearity ±0.003% FSR Max.; ±0.001% Typ. ±0.003% FSR Max.; ±0.001% Typ. ±0.003% FSR Max.; ±0.001% Typ
Differential Nonlinearity ±0.75 LSB; ±0.5 LSB Typ. ±0.75 LSB; ±0.5 LSB Typ. ±0.75 LSB Max.; ±0.5 LSB Typ.
Monotonicity Guaranteed Guaranteed Guaranteed
No Missing Codes Guaranteed over the Specified Guaranteed over the Specified Guaranteed over the Specified
Temperature Range Temperature Range Temperature Range
Offset Error ±0.1% FSR Max. (Adj. to Zero) ±0.1% FSR Max. (Adj. to Zero) ±0.1% FSR Max. (Adj. to Zero)
Gain Error ±0.1% FSR Max. (Adj. to Zero) ±0.1% FSR Max. (Adj. to Zero) ±0.1% FSR Max. (Adj. to Zero)
Noise8
10V p-p FSR 55 µV RMS Typ.; 70 µV RMS Max. 65 µV RMS Typ.; 80 µV RMS Max. 90 µV RMS Typ.; 110 µV Max.
5V p-p FSR 45 µV RMS Typ.; 55 µV RMS Max. 50 µV RMS Typ.; 60 µV RMS Max. 65 µV RMS Typ., 80 µV Max.

STABILITY
Differential Nonlinearity TC ±1 ppm/°C Max. ±1 ppm/°C Max. ±1 ppm/°C Max.
Offset TC ±15 ppm/°C Max. ±15 ppm/°C Max. ±15 ppm/°C Max.
Gain TC ±15 ppm/°C Max. ±15 ppm/°C Max. ±15 ppm/°C Max.
Warm-Up Time 5 Min. Max. 5 Min. Max. 5 Min. Max.
Supply Rejection per % change in
any supply Offset & Gain ±20 ppm/% Max. ±20 ppm/% Max. ±20 ppm/% Max.

POWER REQUIREMENTS
±15V Supplies9 14.55V Min., 15.45V Max. 14.55V Min., 15.45V Max. 14.55V Min., 15.45V Max.
+5V Supplies +4.75V Min., +5.25V Max. +4.75V Min., +5.25V Max. +4.75V Min., +5.25V Max.
+15V Current Drain 63 mA Typ. 63 mA Typ. 71 mA Typ.
–15V Current Drain 54 mA Typ. 54 mA Typ. 61 mA Typ.
+5V Current Drain 67 mA Typ. 67 mA Typ. 67 mA Typ.
Total Power Consumption 2.1W Typ. 2.1W Typ. 2.3W Typ.

ENVIRONMENTAL & MECHANICAL

Specified Temperature Range10
A Version 0°C to +70°C 0°C to +70°C 0°C to +70°C
B Version –25°C to +85°C –25°C to +85°C –25°C to +85°C
Storage Temperature Range –25°C to 125°C –25°C to 125°C –25°C to 125°C
Dimensions 1.58" x 2.38" x 0.225" 1.58" x 2.38" x 0.225" 1.58" x 2.38" x 0.225"
(40.13 mm x 60.45 mm x 5.7 mm) (40.13 mm x 60.45 mm x 5.7 mm) (40.13 mm x 60.45 mm x 5.7 mm)
Case Potential Ground Ground Ground

NOTES:
1. All specifications guaranteed at 25°C unless otherwise noted and supplies at ±15V and +5V. Ordering Guide
2. All dynamic characteristics measured on the ±5V input range except the 980 kHz distortion test
are performed at the ±2.5V input range. Specified Temperature Range: 0°C to +70°C
3. Measured with a full scale step input.
Model Sampling Rate
4. See performance testing
5. THD + noise represents the ratio of the RMS value of the signal to the total RMS noise below
ADC4325A 500 kHz
the Nyquist plus the total harmonic distortion up to the 100th harmonic with an analysis band- ADC4320A 1 MHz
width of dc to the converters’ Nyquist frequency. ADC4322A 2 MHz
6. Step response represents the time required to achieve the specified accuracies after an input Specified Temperature Range: –25°C to +85°C
full scale step change.
7. Reference Load to remain stable. ADC4325B 500 kHz
8. Includes noise from S/H and A/D converter. ADC4320B 1 MHz
9. Both ±15V analog supply voltages and both ±reference voltages, Pins 2, 3, 16, and 17, must be ADC4322B 2 MHz
by-passed with low ESR tantalum capacitors. (See Figure 24)
10. The specified temperature range is guaranteed for the case temperature. Evaluation Board
Specifications subject to change without notice. ADC4322 EB-1
TYPICAL PERFORMANCE CHARACTERISTICS

Fig. 2. ADC4325 Dynamic Characteristics at 100 kHz and 0 dB Fig. 6. ADC4325 Dynamic Characteristics at 195 kHz and –6 dB
(±5V Range)

Fig. 3. ADC4320 Dynamic Characteristics at 100 kHz and 0 dB Fig. 7. ADC4320 Dynamic Characteristics at 495 kHz and –6 dB
Range.

Fig. 4. ADC4322 Dynamic Characteristics at 100 kHz and 0 dB Fig. 8. ADC4322 Dynamic Characteristics at 980 kHz and –6 dB
(±2.5V Range)

Fig. 5. ADC4322 Dynamic Characteristics at 495 kHz and 0 dB Fig. 9. ADC4320 Intermodulation Distortion at 100 kHz, 125 kHz and
(±2.5V Range) –6 dB
SPECIFICATIONS PIN # 4 5 6
RANGE S/H IN 1 S/H IN2 S/H IN 3
0V to +10V Input Input –5V Ref
±5V Input Input SIG RTN
±2.5V Input Input Input
±10V Input SIG RTN SIG RTN

Figure 13. Input Scaling Connections.

Coding and Trim Procedure

Figure 15 shows the output coding and trim calibration
voltages of the converter. For two’s complement operation,
simply use the available B1 (MSB) instead of B1 (MSB).
Refer to Figure 11 for use of external offset and gain trim
potentiometers. Voltage DACs with a ±5V output can be
easily utilized when digital control is required. The input
Figure 10. ADC4322 SFDR vs Input Level @ 195 kHz ±2.5V sensitivity of the external offset and gain control pins is 300
Range ppm FSR/V. If Offset and Gain adjusts are not used, con-
nect to Pin 14, Analog Returns.
To trim the offset of the converter, apply the offset voltage
shown in Figure 15 for the appropriate voltage range.
Adjust the offset trim potentiometer such that the 15 MSBs
are “0” and the LSB alternates equally between “0” and “1”
for the unipolar ranges or all 16 bits are in transition for the
bipolar ranges.
To trim the gain of the converter, apply the range (+FS) volt-
age shown in Figure 12 for the appropriate range. Adjust
the gain trim potentiometer such that the 15 MSBs are “1”
and the LSB alternates equally between “0” and “1”.
To check the trim procedure, apply 1/2 full scale voltage for
a unipolar range or –full scale voltage for the bipolar
ranges and check that the digital code is ±1 LSB of the
stated code.
Figure 11. ADC4322 SFDR vs Input Level @ 495 kHz ±2.5V
Range Gain Adj. R1

R1 = 50K
+5V REF
R2 = 50K
R2 C1 = 0.1 µF
Off Adj. C2 = 0.1 µF
C1 C2
Gnd.
–5V REF
Note: If not used,
connect Pins 13, 14, and 15

Figure 14. Offset and Gain Adjustment Circuit.

UNIPOLAR BINARY 0V TO +10V

MSB LSB
+FS 111111111111111* = +9.99977V
1/2 FS 1000000000000000 = +5.00000V
Offset 000000000000000* = +0.00000V
OFFSET BINARY ±2.5V Input ±5V Input
Figure 12. ADC4322 SFDR vs Input Level @ 980 kHz ±2.5V
MSB LSB
Range
+FS 111111111111111* = +2.49989V +4.99977V
INTERFACING Offset ************** = –0.00004V –0.00008V
–FS 000000000000000* = –2.49996V –4.99992V

Input Scaling 2’S COMPLEMENT ±2.5V Input ±5V Input

The converters can be configured for four input voltage MSB LSB
ranges: 0 to +10V; ±2.5V; ±5V; and ±10V. The analog +FS 011111111111111* = +2.49989V +4.99977V
input range should be scaled as close as possible to the Offset ************** = –0.00004V –0.00008V
–FS 100000000000000* = –2.49996V –4.99992V
maximum input to utilize the full dynamic range of the con-
verter. Figure 13 describes the input connections. * denotes a 0/1 or 1/0 transition
Figure 15. Coding and Trim Calibration Table.
 N N+1 The A/D converter is factory trimmed and optimized to op-
Trigger
Sample
erate with a 10V p-p input voltage range. Scaling resistors
S/H Cont
(Internal)
Hold
at the S/H inputs configure the three input ranges and pro-
A/D Clock vide a S/H output voltage to the A/D converter of 10V p-p.
(Internal)
Transfer
The first pass starts with a high-to-low transition of the trig-
Data N-1 Data N Data ger pulse. This signal places the S/H into the Hold mode
25 ns Min. and starts the timing logic. The path of the 10V p-p input
Time (ns) 0 ADC4325 1.1 µs 1.3 µs 2.0 µs signal during the first pass is through a 5:1 attenuator cir-
ADC4320 620ns 750ns 1.0µs cuit to the 10-bit ADC with an input range of 2V p-p. At
ADC4322 300 ns 400 ns 500 ns
35 ns, the ADC converts the signal and the 9 bits are
Figure 16. Timing Diagram. latched both into the logic as the MSBs and into the 16-bit
accurate DAC for the second pass.
2.4" (60.96 mm) The second pass subtracts the S/H output and the 9-bit,
0.100" (2.54 mm) Typ. (on center) 16-bit accurate DAC output with the result equal to the 9-
bit quantization error of the DAC, or 19.5 mV p-p. The
24
46
“error” voltage is then amplified by a gain of 25.6 and is
now 0.5V p-p or 1/4 the full scale range of the ADC, allow-
1.3"
1.300 ing a 2-bit overlap safety margin. When the DAC and the
Top View (33 mm)
33.02 mm
(on center) 1.6
(40.64 mm)
2V p-p
S/H In 1 S/H Amp 10V p-p
▼ 23 S/H In 2 A= -1 or -2 – 10-Bit 9
S/H In 3 ADC
+ Logic
A= -0.2 To DAC 9
0.225 Min. S/H In 1 (2nd Pass)
S/H Amp 10V p-p 1st Pass
0.225 Max. 0.018 (0.45 mm) Dia. Typ. S/H In 2
S/H In 3 A= -1 or -2

Figure 17. ADC432X Series Mechanical Diagram.

DAC In 16-Bit 0.5V p-p
9 O/U Flow
From Linear ∑ –
PIN # PIN# DAC – 10-Bit 9 16 B1-B16
Logic Logic
+ ADC
1 ANA RTN 46 +5V + B1
A= –6.4
2 +15V 45 DIG RTN A= –4 Transfer

3 –15V 44 O/U FLOW 2nd Pass

4 S/H IN 1 43 BIT 1N
5 S/H IN 2 42 BIT 1 Figure 19. Operating Principle.
6 S/H IN 3 41 BIT 2
7 SIG RTN 40 BIT 3
8 DNC* 39 BIT 4
“error” amplifier have had sufficient time to settle to 16-bit
9 ANA RTN 38 BIT 5
10 +15V 37 BIT 6
accuracy the amplified “error” voltage is then digitized by
11 –15V 36 BIT 7 the ADC with the 9-bit second pass result latched into the
12 DNC 35 BIT 8 logic. At this time the S/H returns to the sample mode to
13 EXT OFFSET ADJ 34 BIT 9 begin acquiring the next sample.
14 ANA RTN 33 BIT 10
15 EXT GAIN ADJ 32 BIT 11 The 1/4 full scale range in the second pass produces a 2-
16 +REF OUT 31 BIT 12 bit overlap of the two passes. This provides an output word
17 –REF OUT 30 BIT 13
that is accurate and linear to 16 bits. This method corrects
18 ANA RTN 29 BIT 14
19 TRIGGER 28 BIT 15
for any gain and linearity errors in the amplifying circuitry,
20 DIG RTN 27 BIT 16 as well as the 10-bit flash A/D converter. Without the use
21 DIG RTN 26 TRANSFER of this overlapping correction scheme, it would be neces-
22 HI BYTE EN 25 +5V sary that all the components in the converters be accurate
23 LO BYTE EN 24 DIG RTN
to the 16-bit level. While such a design might be possible
* DNC– Do Not Connect
to realize on a laboratory benchtop, it would be clearly im-
Figure 18. Pin Assignment. practical to achieve on a production basis. The key to the
conversion technique used in the converters is the 16-bit
PRINCIPLE OF OPERATION accurate and 16-bit linear D/A converter which serves as
The ADC432X Series converters are 16-bit sampling A/D the reference element for the conversion’s second pass.
converters with throughput rates of up to 2 MHz. These The use of proprietary sub-ranging architecture in the con-
converters are available in three externally-configured full verters results in a sampling A/D converter that offers un-
scale ranges of 5V p-p, 10V p-p and 20V p-p. Options are precedented speed and transfer characteristics at the 16-
externally- or user-programmable for bipolar and unipolar bit level.
inputs of ±2.5V, ±5V, ±10V and 0 to +10V. Two’s comple- The converter has a 3-state output structure. Users can
ment format can be obtained by utilizing B1 instead of B1. enable the eight MSBs and B1 with HIBYTEN and the
To understand the operating principles of the A/D convert- eight LSBs with LOBYTEN (both are active low). This fea-
ers, refer to the timing diagram of Figure 16 and the simpli- ture makes it possible to transfer data from the converter
fied block diagram of Figure 19. The simplified block dia- to an 8-bit microprocessor bus. However, to prevent the
gram illustrates the two successive passes in the sub- coupling of high frequency noise from the microprocessor
ranging scheme of the converters. bus into the A/D converter, the output data must be
buffered.
PERFORMANCE TESTING
In order to guarantee that all ADC432X Series converters
shipped meet or exceed published specifications, Analogic
performs a multitude of tests on each hybrid prior to ship-
ment. Such results are then sent to the customer in con-
junction with each converter as testimony of the perfor-
mance results.

Amplitude Domain Testing

The Amplitude Domain Testing is performed by means of
proprietary Automatic Test Equipment inclusive of a 22-bit
digital-to-analog converter, whose reference is traceable to
the National Institute of Standards Technology. A block di-
agram is outlined in Figure 20. By means of this test equip-
ment, Analogic can test such parameters as integral linear-
ity, differential linearity, A/D converter noise, maximum
positive and negative errors, conversion time, gain error,
offset error, power supply current, power supply rejection.
A typical “Amplitude Domain” data sheet is shown in
Figure 22. For further information on the definitions of such
specifications, please refer to the “Analogic Data
Conversion Systems Digest.”

Figure 22 “Amplitude Domain” Data Sheet.

Stimula Personal
U.U. T. RMS value of max. spurious component
Generator Computer
Peak Distortion = 20 log RMS value of input signal

Signal to Noise Ratio: Ratio, expressed in dB, between the

RMS value of the signal and the total RMS noise below the
Figure 20. “Amplitude Domain” Test System. Nyquist rate. Note that all frequency bins that are correlated
with the test frequency are removed and replaced with an
Frequency Domain Testing average of the remaining bins.
Frequency Domain Testing is performed to simulate real- Total Harmonic Distortion: Ratio, expressed in dB, be-
time applications where a constantly varying input signal is tween the RMS sum of all harmonics up to the 100th har-
applied to the converter. A block diagram of the Analogic monic and the RMS value of the signal.
“Frequency Domain” test system is shown in Figure 21. As
a result, a data sheet, such as the one reproduced in Figure Direct Harmonic Distortion: Ratio, expressed in dB, be-
23, is delivered to the customer with each converter. tween the RMS sum of all the components below the
Nyquist rate that are harmonically related to the signal and
The data sheet is divided into two sections including the na- the RMS value of the signal.
ture of the input data, the type of FFT performed and the re-
sults of the FFT test. This data can be misleading if not thor- Reflected Harmonic Distortion: Ratio, expressed in dB,
oughly understood. For example, in an audio application, one between the RMS sum of all aliased harmonics and the
of the most important parameters is the absence of aliased RMS value of the signal.
harmonic distortion. While harmonic distortion directly related Note that the estimated RMS noise, based on those fre-
to the fundamental does not produce audible discomfort, quency bins not correlated with the test signal, is first re-
aliased harmonics can be very bothersome. Such characteri- moved from the harmonic frequency bins before the above
zation is not often provided or is calculated as part of the total distortion values are calculated.
harmonic distortion, thus, misleading the end user. Analogic
definitions are summarized as follows:
Peak Distortion: Ratio, expressed in dB, between the RMS
value of the highest spurious spectral component below the
Nyquist rate and the RMS value of the input signal.

Sig. Analogic H.P.

U.U.T. Buf.
Gen. AP500 9000/300

Hard Display
Control Disk

Figure 23. “Frequency Domain” Data Sheet.

Figure 21. “Frequency Domain” Test System.
Layout Considerations It is evident that any noise in the analog ground return can
Because of the high resolution of the A/D converters, it is result in erroneous or missing codes. It is important in the
necessary to pay careful attention to the printed-circuit lay- design of the PC board to configure a low-impedance
out for the device. It is, for example, important to keep ana- ground-plane return on the printed-circuit board. It is only
log and digital grounds separate at the power supplies. at this point where the analog and digital power returns
Digital grounds are often noisy or “glitchy,” and these should be made common.
glitches can have adverse effects on the performance of The Analogic ADC4322 EB-1 evaluation board has been
the converters if they are introduced to the analog portions designed and laid out for optimum performance with the
of the A/D converter’s circuitry. At 16-bit resolution, the converter series. The board layout and schematic are
size of the voltage step between one code transition and shown in the figures below as examples of decoupling and
the succeeding one for a 5V full scale range is only 76 µV. layout techniques.
L1
+5V
P4 C1 + 25 µH + C1
TANT TANT
DGND 10 µF 16V 10 µF 16V
P5 E18 18
J1 OUFLOW
L2
+15V E17
P1 C3 + 25 µH + C4
TANT TANT E16 2 A U1 Y 18 20 J1 D15 (MSB)
AGND 6.8 µF 20V 6.8 µF 20V 3 A 17 22
U1 Y J1 D14
P2 C5 + + C6 4 A U1 Y 16 24
TANT L3 TANT AD Converter 5 A U1 Y 15 26
J1
J1
D13
D12
–15V 6.8 µF 20V 6.8 µF 20V 1 46 6 A 14 28
P3 ANARTN1 +5V2 U1 Y J1 D11
25 µH 2 45 7 A U1 Y 13 30 J1 D10
3 +15V1 DIGATN2 44 8 A 12 32
–15V1 O/UFLOW U1 Y J1 D09
C9 E5 4 43 9 A U1 Y 11 34 J1 D08
5 S/HIN1 BIT1 42 1 G1 VCC 20
S/HIN2 U1 GND +5V
6 BIT1 41 19 G2 10
E7 S/HIN3 BIT2 C15
75pF/POLYS 7 40 1µF 3
R6 E6 E8 SIGATN BIT3
8 39 J1 HIBYTEN
C10 9 DNC BIT4 38
2.5K.1% E9 ANARTN2 BIT5
TANT 10 37
+15V R7 6 6.8 µF 20V 11 +15V2 BIT6 36
+ 12 –15V2 BIT7 35
20 78 9 13 DNC BIT8 34 2 18 36
TR2

E10 OFFADJ A U2 Y J1 D07

V+

BNC1 1 E1 R5 BIT9
TR1

2 14 33 3 A 17 38
– 6 E11 ANARTN3 BIT10 U2 Y J1 D06
Sig In1 3 U4 15 32 4 A 16 40
2 2.5K.1% + GAINADJ BIT11 U2 Y J1 D05
E12 16 31 5 A 15 42
AD845 C11 +REFOUT BIT12 U2 Y J1 D04
V–

E2 17 30 6 A 14 44
TANT E13 –REFOUT BIT13 U2 Y J1 D03
4 18 29 7 A 13 46
–15V R8 6.8 µF 20V ANARTN4 BIT14 U2 Y J1 D02
19 28 8 A 12 48
+ TRIGGER BIT15 U2 Y J1 D01
20 20 27 9 A 11 50
TANT DIGRTN BIT16 U2 Y J1 D00 (LSB)
21 26 1 G1 VCC 20 +5V
6.8 µF 20V 22 DIGRTN TRANSFER 25 U2 GND
C12 HIBYTE/EN 19 G2 10 C16
C19 23 +5V1 24
R13 LOBYTE/EN DIGRTN1 74LS541 1µF 5
50KTADJ + J1 LOBYTEN
75pF/POLYS
R10 C21
2.5K.1% C13 .1µF
TANT E21
+15V R11 6 6.8 µF 20V R13 4 E22
+ 50KTADJ 6
20 78 9 5 U3
TR2

12
V+

BNC2 1 E3 R9
TR1

2 Range Jumpers 11 10
– 6 HCT00 13 U3 J1 DATASTRB
Sig In2 2 3 U5 C22 ±2.5V E7, E10 9
2.5K.1% +
C20 + .1 µF 8
AD845 C14 10 HCT00
V–

E4 TANT ±5V E7, E13 R3

TANT
–15V R12 4 6.8 µF 20V E14 6.8 µF 20V ±10V E9, E13 HCT00 +5V
1 220 8
+ E19 J1 READY
BNC3 1 R2A 20 0/+10V E7, E12 R4
U3 E20
Trigger Position for +5V E15 2 HCT00
330
2 1/2 W Res Configuration Jumpers
1 J1 25 J1
R2B 7 27 Sig In1 Direct E2, E4, E5
J1 J1
+5V 9 J1 29 J1
11 J1 31 Sig In1 AD845 E1, E4, E6
VCC J1
C7 13 J1 33 J1 2 Tone ±2.5V E1, E3, E6, E7, E11
+ Y1 15 J1 35
TANT C8 J1
12 17 J1 37 2 Tone ±5V E1, E3, E6, E8, E13
10 µF 16V .1 µF GND 2 MHz Out J1 J1
14 14 J1 19 J1 39 J1
OSC 16 Internal Trig E15
21 J1 41
HCT00

VCC C18 J1 J1
C17 + TANT
2 J1 23 J1 43 J1 External Trig E14
U3 1µF 4 47 J1 45
GND 10 µF 16V J1 J1 Normal Data E16
6 J1 49 J1
7 2’s Comp Data E17

Figure 24. ADC4322-EB1 Block Diagram

Analogic DCP
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(978) 977-3000
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© 1994, 2000 ANALOGIC Corporation
Bulletin No. 16-100571 REV 1 11/00