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Ads 127 L 18

The ADS127L14 and ADS127L18 are 24-bit, delta-sigma ADCs capable of simultaneous sampling of four or eight channels with data rates up to 512kSPS and 1365kSPS, respectively. They offer power-scalable speed modes, excellent AC performance, and low power consumption, making them suitable for various applications including test and measurement, factory automation, aerospace, and medical devices. The devices feature programmable settings, low-drift modulators, and are designed for operation in a wide temperature range.

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Ads 127 L 18

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ADS127L14, ADS127L18

SBASAM0B – MARCH 2024 – REVISED NOVEMBER 2024

ADS127L1x 512kSPS, Quad and Octal, Simultaneous-Sampling, 24-Bit ADCs

1 Features 2 Applications
• Simultaneously measure four or eight channels • Test and measurement:
• Wideband filter mode: up to 512kSPS – Data acquisition (DAQ)
• Low-latency filter mode: up to 1365kSPS – Shock and vibration instruments
• Power-scalable speed modes: – Acoustics and dynamic strain gauges
– Max speed: 512kSPS • Factory automation and control:
• 83mW (ADS127L14) – Condition monitoring
• 165mW (ADS127L18) • Aerospace and defense:
– High speed: 400kSPS – Sonar
• 64mW (ADS127L14) • Medical:
• 128mW (ADS127L18) – Electroencephalograms (EEG)
– Mid speed: 200kSPS • Grid Infrastructure:
• 37mW (ADS127L14) – Power quality analyzers
• 74mW (ADS127L18)
– Low speed: 50kSPS 3 Description
• 12mW (ADS127L14) The ADS127L14 (quad) and ADS127L18 (octal) are
• 24mW (ADS127L18) 24-bit, delta-sigma (ΔΣ), analog-to-digital converters
• AC performance with DC precision: (ADCs) based on the single-channel ADS127L11.
(High-Speed Mode) The devices provide simultaneous sampling of four
– Dynamic range at 200kSPS: 112dB (typical) or eight channels with data rates up to 512kSPS
– THD: –118dB (typical) (wideband filter mode) and 1365kSPS (low-latency
– INL: 1ppm of FSR (typical) filter mode).
– Offset drift: 10nV/°C (typical)
Package Information
– Gain drift: 0.5ppm/°C (typical)
PART NUMBER PACKAGE(1) PACKAGE SIZE
• Precharge buffered signal inputs
• Programmable by pin setting or SPI ADS127L1x RSH (VQFN, 56) 7mm × 7mm
• Frame-sync port for output data (1) For more information, see the Mechanical, Packaging, and
• Internal or external clock operation Orderable Information.
• Analog supply voltage: 2.85V to 5.5V
AVDD1 REFP REFN AVDD2 IOVDD AVDD1 REFP REFN AVDD2 IOVDD

VCM ÷2 ADS127L14 Osc Mux CLKIN VCM ÷2 ADS127L18 Osc Mux CLKIN

FSYNC
AINP0 ΔΣ AINP0 ΔΣ FSYNC
Frame-Sync DCLK Frame-Sync
AINN0 Modulator Modulator DCLK
Data Port DOUT[3:0]/GPIO[3:2] AINN0 Data Port
DOUT[7:0]/DIN3:0]/GPIO[7:2]
AINP1 DIN[1:0]/GPIO[7:4] AINP1
ΔΣ ΔΣ
AINN1 Modulator Four Modulator
AINN1
Digital MODE (SPI or Pin) MODE (SPI or Pin)
AINP2 ΔΣ Filters CS/SPEED AINP2 ΔΣ CS/SPEED
AINN2 Modulator SCLK/FLTR Modulator SCLK/FLTR
SPI or Pin AINN2 SPI or Pin
Configuration SDI/OSR0
SDO Configuration SDI/OSR0
SDO
AINP3 ΔΣ Port AINP3 ΔΣ Port
SDO/OSR1 SDO/OSR1
AINN3 Modulator Modulator Eight
GPIO0/TDM
SDO AINN3 GPIO0/TDM
SDO
Digital
GPIO1/HDR AINP4 Filters GPIO1/HDR
ΔΣ
AINN4 Modulator
ERROR ERROR
Control Control START
START AINP5 ΔΣ Logic
Logic
RESET Modulator RESET
AINN5

AINP6 ΔΣ
AVSS DGND
AINN6 Modulator

AINP7 ΔΣ
AINN7 Modulator

AVSS DGND

Functional Block Diagrams

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
ADS127L14, ADS127L18
SBASAM0B – MARCH 2024 – REVISED NOVEMBER 2024 www.ti.com

The devices offer an excellent combination of ac performance and dc precision with low power consumption.
Power-scalable speed modes allow user-optimized tradeoffs between speed, resolution and power consumption.
The wideband and low-latency filters optimize ac-signal performance or dc-signal data throughput, all from
one device. Programmable over-sampling ratio (OSR) optimizes in-band noise versus signal bandwidth. The
linear-phase wideband filter provides a usable bandwidth of 80% of the Nyquist frequency with ±0.0004dB
pass-band ripple. The low-latency filter provides 16.9 bits effective resolution at 1365kSPS with 3.9µs latency
time.
Precharge buffers on each input channel reduce analog input current and sampling noise to improve accuracy.
The low-drift modulator achieves excellent dc precision with low in-band noise and high linearity for outstanding
ac performance. Low crosstalk error reduces signal coupling between channels for improved data isolation.
The devices are programmed by simple pin connections or by the SPI port. The frame-sync data port with
selectable number of data lanes provides the conversion data in parallel or time division format. Daisy chain
operation expands the system channel count using the same number of data lanes.
The devices support cross-channel averaging to create high resolution data by averaging the original data in
combinations of two, four or eight channels.
The devices are offered in identical 7mm × 7mm VQFN packages, permitting drop-in expandability, and are fully
specified for operation over the –40°C to +125°C temperature range.

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Table of Contents
1 Features............................................................................1 6.11 IMD Measurement...................................................36
2 Applications..................................................................... 1 6.12 SFDR Measurement............................................... 36
3 Description.......................................................................1 6.13 Noise Performance................................................. 36
4 Pin Configuration and Functions...................................4 7 Detailed Description......................................................41
5 Specifications.................................................................. 8 7.1 Overview................................................................... 41
5.1 Absolute Maximum Ratings........................................ 8 7.2 Functional Block Diagram......................................... 42
5.2 ESD Ratings............................................................... 8 7.3 Feature Description...................................................42
5.3 Recommended Operating Conditions.........................9 7.4 Device Functional Modes..........................................59
5.4 Thermal Information....................................................9 7.5 Programming............................................................ 72
5.5 Electrical Characteristics...........................................10 8 Register Map.................................................................. 79
5.6 Timing Requirements................................................ 18 9 Application and Implementation.................................. 94
5.7 Switching Characteristics..........................................19 9.1 Application Information............................................. 94
5.8 Timing Diagrams....................................................... 19 9.2 Typical Application.................................................... 95
5.9 Typical Characteristics.............................................. 22 9.3 Power Supply Recommendations.............................98
6 Parameter Measurement Information.......................... 33 9.4 Layout....................................................................... 99
6.1 Offset Error Measurement........................................ 33 10 Device and Documentation Support........................101
6.2 Offset Drift Measurement..........................................33 10.1 Documentation Support........................................ 101
6.3 Gain Error Measurement.......................................... 33 10.2 Receiving Notification of Documentation Updates101
6.4 Gain Drift Measurement............................................33 10.3 Support Resources............................................... 101
6.5 NMRR Measurement................................................ 33 10.4 Trademarks........................................................... 101
6.6 CMRR Measurement................................................ 34 10.5 Electrostatic Discharge Caution............................101
6.7 PSRR Measurement................................................. 34 10.6 Glossary................................................................101
6.8 SNR Measurement................................................... 35 11 Revision History........................................................ 101
6.9 INL Error Measurement............................................ 35 12 Mechanical, Packaging, and Orderable
6.10 THD Measurement..................................................35 Information.................................................................. 101

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4 Pin Configuration and Functions

SCLK/FLTR

CS/SPEED

RESET
START
MODE

AINN0

AINP0
REFN

REFN
REFP

REFP
AVSS

AVSS
VCM
56

43
SDI/OSR0 1 42 AINN1

SDO/OSR1 2 41 AINP1

GPIO0/TDM 3 40 AINN2

GPIO1/HDR 4 39 AINP2

ERROR 5 38 AINN3

DOUT0 6 37 AINP3

DOUT1 7 36 AVSS
Thermal
DOUT2/GPIO2 8 Pad 35 AVSS

DOUT3/GPIO3 9 34 AVSS

GPIO4 10 33 AVSS

GPIO5 11 32 AVSS

DIN1/GPIO6 12 31 AVSS

DIN0/GPIO7 13 30 AVSS

DCLK 14 29 AVSS
15

28
FSYNC

CLKIN

DGND

IOVDD

CAPD

DGND

AVSS

AVDD1

AVDD2

CAPA

AVSS
Not to scale

Figure 4-1. ADS127L14 RSH Package, 56-Pin VQFN (Top View)

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SCLK/FLTR

CS/SPEED

RESET
START
MODE

AINN0

AINP0
REFN

REFN
REFP

REFP
AVSS

AVSS
VCM
56

43
SDI/OSR0 1 42 AINN1

SDO/OSR1 2 41 AINP1

GPIO0/TDM 3 40 AINN2

GPIO1/HDR 4 39 AINP2

ERROR 5 38 AINN3

DOUT0 6 37 AINP3

DOUT1 7 36 AINN4
Thermal
DOUT2/GPIO2 8 Pad 35 AINP4

DOUT3/GPIO3 9 34 AINN5

DOUT4/DIN3/GPIO4 10 33 AINP5

DOUT5/DIN2/GPIO5 11 32 AINN6

DOUT6/DIN1/GPIO6 12 31 AINP6

DOUT7/DIN0/GPIO7 13 30 AINN7

DCLK 14 29 AINP7
15

28
FSYNC

CLKIN

DGND

IOVDD

CAPD

DGND

AVSS

AVDD1

AVDD2

CAPA

AVSS

Not to scale

Figure 4-2. ADS127L18 RSH Package, 56-Pin VQFN (Top View)

Table 4-1. Pin Functions

(1)
NAME ADS127L14 PIN ADS127L18 PIN TYPE DESCRIPTION
AINN0 44 44 I Channel 0 negative analog input. See the Analog Inputs section for details.
AINN1 42 42 I Channel 1 negative analog input. See the Analog Inputs section for details.
AINN2 40 40 I Channel 2 negative analog input. See the Analog Inputs section for details.
AINN3 38 38 I Channel 3 negative analog input. See the Analog Inputs section for details.
AINN4 –- 36 I Channel 4 negative analog input. See the Analog Inputs section for details.
AINN5 –- 34 I Channel 5 negative analog input. See the Analog Inputs section for details.
AINN6 –- 32 I Channel 6 negative analog input. See the Analog Inputs section for details.
AINN7 –- 30 I Channel 7 negative analog input. See the Analog Inputs section for details.
AINP0 43 43 I Channel 0 positive analog input. See the Analog Inputs section for details.
AINP1 41 41 I Channel 1 positive analog input. See the Analog Inputs section for details.
AINP2 39 39 I Channel 2 positive analog input. See the Analog Inputs section for details.
AINP3 37 37 I Channel 3 positive analog input. See the Analog Inputs section for details.
AINP4 –- 35 I Channel 4 positive analog input. See the Analog Inputs section for details.
AINP5 –- 33 I Channel 5 positive analog input. See the Analog Inputs section for details.
AINP6 –- 31 I Channel 6 positive analog input. See the Analog Inputs section for details.
AINP7 –- 29 I Channel 7 positive analog input. See the Analog Inputs section for details.

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Table 4-1. Pin Functions (continued)

(1)
NAME ADS127L14 PIN ADS127L18 PIN TYPE DESCRIPTION
Positive analog supply 1. See the Power Supply Recommendations section for
AVDD1 23, 24 23, 24 P
details.
Positive analog supply 2. See the Power Supply Recommendations section for
AVDD2 25 25 P
details.
22, 28, 29, 30, 31,
Negative analog supply. See the Power Supply Recommendations section for
AVSS 32, 33, 34, 35, 36, 22, 28, 45, 51 P
details.
45, 51
Analog voltage regulator output bypass. See the CAPA and CAPD section for
CAPA 26, 27 26, 27 P
details.
CAPD 20 20 P Digital voltage regulator output bypass. See the CAPA and CAPD section for details.
CLKIN 16 16 I Clock input. See the Clock Operation section for details.
SPI mode: Active-low chip select. See the SPI Programming section for details.
CS/SPEED 55 55 I Hardware mode (tri-state input): Speed range select.
See the Hardware Programming section for details.
DCLK 14 14 O Frame-sync bit clock output. See the Frame-Sync Data Port section for details.
DGND 17, 21 17, 21 GND Digital ground.
Daisy-chain data input 0. See the Frame-Sync Data Port section for details.
DIN0/GPIO7 13 –- I/O
General-purpose input-output 7. See the GPIO section for details.
Daisy-chain data input 1. See the Frame-Sync Data Port section for details.
DIN1/GPIO6 12 –- I/O
General-purpose input-output 6. See the GPIO section for details.
DOUT0 6 6 O Data output 0. See the Frame-Sync Data Port section for details.
DOUT1 7 7 O Data output 1. See the Frame-Sync Data Port section for details.
Data output 2. See the Frame-Sync Data Port section for details.
DOUT2/GPIO2 8 8 I/O
General-purpose input-output 2. See the GPIO section for details.
Data output 3. See the Frame-Sync Data Port section for details.
DOUT3/GPIO3 9 9 I/O
General-purpose input-output 3. See the GPIO section for details.
Data output 4 and daisy-chain data input 3. See the Frame-Sync Data Port section
DOUT4/DIN3/GPIO4 –- 10 I/O for details.
General-purpose input-output 4. See the GPIO section for details.
Data output 5 and daisy-chain data input 2. See the Frame-Sync Data Port section
DOUT5/DIN2/GPIO5 –- 11 I/O for details.
General-purpose input-output 5. See the GPIO section for details.
Data output 6 and daisy-chain data input 1. See the Frame-Sync Data Port section
DOUT6/DIN1/GPIO6 –- 12 I/O for details.
General-purpose input-output 6. See the GPIO section for details.
Data output 7 and daisy-chain data input 0. See the Frame-Sync Data Port section
DOUT7/DIN0/GPIO7 –- 13 I/O for details.
General-purpose input-output 7. See the GPIO section for details.
Open-drain output error signal. See the ERROR Pin and ERR_FLAG Bit section for
ERROR 5 5 O
details.
FSYNC 15 15 O Frame-sync word clock output. See the Frame-Sync Data Port section for details.
General purpose input-output 0. See the GPIO section for details.
GPIO0/TDM 3 3 I/O Hardware mode (tri-state input): TDM ratio select.
See the Hardware Programming section for details.
General purpose input-output 1. See the GPIO section for details.
GPIO1/HDR 4 4 I/O Hardware mode (tri-state input): Data header select.
See the Hardware Programming section for details.
GPIO4 10 –- I/O General-purpose input-output 4. See the GPIO section for details.
GPIO5 11 –- I/O General-purpose input-output 5. See the GPIO section for details.
Digital I/O supply voltage. See the Power Supply Recommendations section for
IOVDD 18, 19 18, 19 P
details.
Tri-state input. Configuration mode select:
MODE 54 54 I 1 = SPI program mode
0 or float = Hardware program mode
REFN 47, 48 47, 48 I Negative reference voltage input. See the Reference Voltage section for details.
REFP 49, 50 49, 50 I Positive reference voltage input. See the Reference Voltage section for details.
RESET 52 52 I Reset input, active low. See the RESET Pin section for details.

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Table 4-1. Pin Functions (continued)

(1)
NAME ADS127L14 PIN ADS127L18 PIN TYPE DESCRIPTION
SPI mode: Serial clock input. See the SPI Programming section for details.
SCLK/FLTR 56 56 I Hardware mode (tri-state input): Filter mode select.
See the Hardware Programming section for details.
SPI mode: Serial data input. See the SPI Programming section for details.
SDI/OSR0 1 1 I Hardware mode (tri-state input): Filter OSR0 select.
See the Hardware Programming section for details.
SPI mode: Serial data output. See the SPI Programming section for details.
SDO/OSR1 2 2 I/O Hardware mode (tri-state input): Filter OSR1 select.
See the Hardware Programming section for details.
START 53 53 I Conversion control. See the Synchronization section for details.
VCM 46 46 O Common-mode voltage output. See the VCM Output Voltage section for details.
Thermal Pad — Thermal power pad. Connect thermal pad to AVSS.

(1) I = input, O = output, I/O = bidirectional input-output, P = power, GND = ground.

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5 Specifications
5.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN MAX UNIT
AVDD1 to AVSS –0.3 6.5
AVDD2 to AVSS –0.3 6.5
Power supply voltage V
AVSS to DGND –3 0.3
IOVDD to DGND –0.3 2.2
Analog input voltage AINPx, AINNx, REFP, REFN AVSS – 0.3 AVDD1 + 0.3 V
CAPA to AVSS AVSS 1.65
Analog output voltage CAPD to DGND DGND 1.65 V
VCM to AVSS AVSS AVDD1
Digital input/output voltage To DGND DGND – 0.3 2.2 V
Input current Continuous, any pin except power-supply pins(2) –10 10 mA
Junction, TJ 150
Temperature °C
Storage, Tstg –65 150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional – this may affect device reliability, functionality, performance, and shorten the device
lifetime.
(2) Analog input pins AINPx, AINNx, REFP, and REFN are diode-clamped to AVDD1 and AVSS. Limit the input current to 10mA in the
event the analog input voltage is ≥ AVDD1 + 0.3V or ≤ AVSS – 0.3V. Digital I/O pins are diode-clamped to DGND only. Limit the input
current to 10mA in the event the digital pin voltage is below DGND – 0.3V.

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) 1000

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

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5.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
Max-speed mode 4.5 5.5
High-speed mode 4.5 5.5
AVDD1 to AVSS V
Mid-speed mode 3 5.5
Low-speed mode 2.85 5.5
Analog power supply
AVDD1 to DGND 1.65 V
Bipolar supply AVSS / AVDD1 ratio 1.2 |V/V|
AVDD2 to AVSS 1.74 5.5 V
AVSS to DGND –2.75 0 V
Digital power supply IOVDD to DGND 1.65 1.95 V
ANALOG INPUTS

VAINPn, Input buffer off AVSS – 0.05 AVDD1 + 0.05

Absolute input voltage V
VAINNn Input buffer on AVSS + 0.1 AVDD1 – 0.1

Differential input voltage 1x input range –VREF VREF

VINn V
VIN = VAINPn – VAINNn 2x input range –2∙VREF 2∙VREF
VOLTAGE REFERENCE INPUTS

Differential reference voltage Low-reference range 0.5 2.5 2.75

VREF V
VREF = VREFP – VREFN High-reference range 1 4.096 AVDD1 – AVSS
VREFN Negative reference voltage AVSS – 0.05 V
REFP buffer off AVDD1 + 0.05
VREFP Positive reference voltage V
REFP buffer on AVDD1 – 0.7
CLOCK SIGNAL
Max-speed mode 0.5 32.768 33.66
High-speed mode 0.5 25.6 26.3
fCLK Clock frequency MHz
Mid-speed mode 0.5 12.8 13.15
Low-speed mode 0.5 3.2 3.29
DIGITAL INPUTS
Input voltage 0 IOVDD V
TEMPERATURE RANGE
Operational –50 125
TA Ambient temperature °C
Specification –40 125

5.4 Thermal Information

ADS127L14, ADS127L18
THERMAL METRIC (1) VQFN (RSH) UNIT
56 PINS
RθJA Junction-to-ambient thermal resistance 23.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 11.5 °C/W
RθJB Junction-to-board thermal resistance 6.3 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 6.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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5.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD1 = 5V, AVDD2 = 1.8V to 5V, AVSS = 0V, IOVDD = 1.8V, VIN = 0V, VCM = 2.5V, VREFP = 4.096V,
VREFN = 0V, high-reference range, 1x input range, all speed modes, all channels active, input precharge buffers on, and
reference precharge buffer on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS, MAX-SPEED MODE
Input buffers off 125
Input current, µA/V
Input buffers off, 2x input range 60
differential input voltage
Input buffers on ±2 µA
Input buffers off 5
Input current drift, nA/V/°C
Input buffers off, 2x input range 2
differential input voltage
Input buffers on 20 nA/°C
Input buffers off 6.5
Input current, µA/V
Input buffers off, 2x input range 3
common-mode input voltage
Input buffers on ±2 µA
ANALOG INPUTS, HIGH-SPEED MODE
Input buffers off 95
Input current, µA/V
Input buffers off, 2x input range 47
differential input voltage
Input buffers on ±1.5 µA
Input buffers off 3
Input current drift, nA/V/°C
Input buffers off, 2x input range 1.5
differential input voltage
Input buffers on 5 nA/°C
Input buffers off 5
Input current, µA/V
Input buffers off, 2x input range 2.5
common-mode input voltage
Input buffers on ±1.5 µA
ANALOG INPUTS, MID-SPEED MODE
Input buffers off 47
Input current, µA/V
Input buffers off, 2x input range 25
differential input voltage
Input buffers on ±1.5 µA
Input buffers off 2
Input current drift, nA/V/°C
Input buffers off, 2x input range 1
differential input voltage
Input buffers on 5 nA/°C
Input buffers off 2.5
Input current, µA/V
Input buffers off, 2x input range 1.3
common-mode input voltage
Input buffers on ±1.5 µA
ANALOG INPUTS, LOW-SPEED MODE
Input buffers off 12
Input current, µA/V
Input buffers off, 2x input range 6
differential input voltage
Input buffers on ±0.4 µA
Input buffers off 1
Input current drift, nA/V/°C
Input buffers off, 2x input range 0.5
differential input voltage
Input buffers on 0.2 nA/°C
Input buffers off 0.6
Input current, µA/V
Input buffers off, 2x input range 0.3
common-mode input voltage
Input buffers on ±0.4 µA

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5.5 Electrical Characteristics (continued)

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD1 = 5V, AVDD2 = 1.8V to 5V, AVSS = 0V, IOVDD = 1.8V, VIN = 0V, VCM = 2.5V, VREFP = 4.096V,
VREFN = 0V, high-reference range, 1x input range, all speed modes, all channels active, input precharge buffers on, and
reference precharge buffer on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL CHARACTERISTICS
Resolution OSR ≥ 32 24 Bits
en DC Noise See the Noise Performance section for details
fIN = 50Hz (±1Hz), fDATA = 50SPS, sinc3 filter 100
NMRR Normal-mode rejection ratio dB
fIN = 60Hz (±1Hz), fDATA = 60SPS, sinc3 filter 100
MAX-SPEED MODE (fCLK = 32.768MHz)
Wideband filter 4 512 kSPS
fDATA Data rate
Low-latency filter 0.1024 1365.3 kSPS
Offset error TA = 25°C –250 ±60 250 µV
Offset drift 25 150 nV/°C
ppm of
Gain error TA = 25°C –2500 ±200 2500
FSR
ppm of
Gain drift 1 3.0
FSR/°C
ppm of
INL Integral nonlinearity (1) 4 6.5
FSR
Wideband filter 109.5 111.5
Wideband filter,
107.5
VREF = 2.5V
Wideband filter,
VREF = 2.5V, 108.5
Inputs shorted, 2x input range
DR Dynamic range OSR = 64, dB
fDATA = 256kSPS Low-latency filter 112 114.5
Low-latency filter,
110
VREF = 2.5V
Low-latency filter,
VREF = 2.5V, 111
2x input range
Wideband filter 108.5
Wideband filter,
105.5
VREF = 2.5V
Wideband filter,
fIN = 1kHz, VREF = 2.5V, 106.5
VIN = –0.2dBFS, 2x input range
SNR Signal-to-noise ratio OSR = 64, dB
fDATA = 256kSPS Low-latency filter 111
Low-latency filter,
108
VREF = 2.5V
Low-latency filter
VREF = 2.5V, 109
2x input range
fIN = 1kHz, VREF = 2.5V –108 –99 dB
VIN = –0.2dBFS,
THD Total harmonic distortion OSR = 64,
fDATA = 200kSPS, VREF = 4.096V –106 –100 dB
9 harmonics

fIN = 9.7kHz and 10.3kHz, Second-order terms –120

IMD Intermodulation distortion dB
VIN = –6.5dBFS Third-order terms –110
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dBFS, OSR = 64 110 dB
Crosstalk fIN = 1kHz, VIN = –0.2dbFS (3) –120 dB
At dc 92 115
CMRR Common-mode rejection ratio Up to 10kHz 110 dB
At dc, 2x input range 105

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5.5 Electrical Characteristics (continued)

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD1 = 5V, AVDD2 = 1.8V to 5V, AVSS = 0V, IOVDD = 1.8V, VIN = 0V, VCM = 2.5V, VREFP = 4.096V,
VREFN = 0V, high-reference range, 1x input range, all speed modes, all channels active, input precharge buffers on, and
reference precharge buffer on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD1, dc 98
PSRR Power-supply rejection ratio AVDD2, dc 130 dB
IOVDD, dc 108
HIGH-SPEED MODE (fCLK = 25.6MHz)
Wideband filter 3.125 400
fDATA Data rate kSPS
Low-latency filter 0.08 1067
Offset error TA = 25°C –200 ±30 200 µV
Offset drift 10 35 nV/°C
ppm of
Gain error TA = 25°C –2500 ±200 2500
FSR
ppm of
Gain drift 0.5 1.0
FSR/°C
ppm of
INL Integral nonlinearity (1) 1 2.8
FSR
Wideband filter 110 112
Wideband filter,
108
VREF = 2.5V
Wideband filter,
VREF = 2.5V, 108.5
Inputs shorted, 2x input range
DR Dynamic range OSR = 64, dB
fDATA = 200kSPS Low-latency filter 113 114.5
Low-latency filter,
110.5
VREF = 2.5V
Low-latency filter,
VREF = 2.5V, 111
2x input range
Wideband filter 110.5
Wideband filter,
106
VREF = 2.5V
Wideband filter,
fIN = 1kHz, VREF = 2.5V, 107.5
VIN = –0.2dBFS, 2x input range
SNR Signal-to-noise ratio OSR = 64, dB
fDATA = 200kSPS Low-latency filter 112.5
Low-latency filter,
108.5
VREF = 2.5V
Low-latency filter,
VREF = 2.5V, 110
2x input range
fIN = 1kHz, VREF = 2.5V –118 –108 dB
VIN = –0.2dBFS,
THD Total harmonic distortion OSR = 64,
fDATA = 200kSPS, VREF = 4.096V –118 –108 dB
9 harmonics

fIN = 9.7kHz and 10.3kHz, Second-order terms –125 dB

IMD Intermodulation distortion
VIN = –6.5dBFS Third-order terms –115 dB
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dBFS, OSR = 64 120 dB
Crosstalk fIN = 1kHz, VIN = –0.2dbFS (3) –130 dB
At dc 105 120
CMRR Common-mode rejection ratio Up to 10kHz 120 dB
At dc, 2x input range 105

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5.5 Electrical Characteristics (continued)

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD1 = 5V, AVDD2 = 1.8V to 5V, AVSS = 0V, IOVDD = 1.8V, VIN = 0V, VCM = 2.5V, VREFP = 4.096V,
VREFN = 0V, high-reference range, 1x input range, all speed modes, all channels active, input precharge buffers on, and
reference precharge buffer on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD1, dc 118
PSRR Power-supply rejection ratio AVDD2, dc 130 dB
IOVDD, dc 113
MID-SPEED MODE (fCLK = 12.8MHz)
Wideband filter 1.5625 200
fDATA Data rate kSPS
Low-latency filter 0.08 533.3
Offset error TA = 25°C –150 ±30 150 µV
Offset drift 5 30 nV/°C
ppm of
Gain error TA = 25°C –2500 ±200 2500
FSR
ppm of
Gain drift 0.25 0.5
FSR/°C
ppm of
INL Integral nonlinearity (1) 0.6 1.8
FSR
Wideband filter 110 112
Wideband filter,
108.5
VREF = 2.5V
Wideband filter,
VREF = 2.5V 108.5
Inputs shorted, 2x input range
DR Dynamic range OSR = 64, dB
fDATA = 100kSPS Low-latency filter 112.5 114.5
Low-latency filter,
111
VREF = 2.5V
Low-latency filter,
VREF = 2.5V, 111
2x input range
Wideband filter 110.5
Wideband filter,
106.5
VREF = 2.5V
Wideband filter,
fIN = 1kHz, VREF = 2.5V, 108
VIN = –0.2dbFS, 2x input range
SNR Signal-to-noise ratio OSR = 64, dB
fDATA = 100kSPS Low-latency filter 113
Low-latency filter,
109
VREF = 2.5V
Low-latency filter,
VREF = 2.5V, 110.5
2x input range
fIN = 1kHz, VREF = 2.5V –125 –118 dB
VIN = –0.2dBFS,
THD Total harmonic distortion OSR = 64,
fDATA = 200kSPS, VREF = 4.096V –122 –116 dB
9 harmonics

fIN = 9.7kHz and 10.3kHz, Second-order terms –125

IMD Intermodulation distortion dB
VIN = –6.5dbFS Third-order terms –115
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dbFS, OSR = 64 123 dB
Crosstalk fIN = 1kHz, VIN = –0.2dbFS (3) –130 dB
At dc 114 125
CMRR Common-mode rejection ratio Up to 10kHz 120 dB
At dc, 2x input range 105

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5.5 Electrical Characteristics (continued)

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD1 = 5V, AVDD2 = 1.8V to 5V, AVSS = 0V, IOVDD = 1.8V, VIN = 0V, VCM = 2.5V, VREFP = 4.096V,
VREFN = 0V, high-reference range, 1x input range, all speed modes, all channels active, input precharge buffers on, and
reference precharge buffer on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD1, dc 125
PSRR Power-supply rejection ratio AVDD2, dc 130 dB
IOVDD, dc 112
LOW-SPEED MODE (fCLK = 3.2MHz)
Wideband filter 0.390625 50
fDATA Data rate kSPS
Low-latency filter 0.01 133.3
Offset error TA = 25°C –150 ±30 150 µV
Offset drift 5 30 nV/°C
ppm of
Gain error TA = 25°C –2500 ±200 2500
FSR
ppm of
Gain drift 0.25 0.6
FSR/°C
ppm of
INL Integral nonlinearity (1) 0.6 1.4
FSR
Wideband filter 110 112
Wideband filter,
108
VREF = 2.5V
Wideband filter,
VREF = 2.5V, 109
Inputs shorted, 2x input range
DR Dynamic range OSR = 64, dB
fDATA = 25kSPS Low-latency filter 112.5 115
Low-latency filter,
110.5
VREF = 2.5V
Low-latency filter,
VREF = 2.5V, 111.5
2x input range
Wideband filter 111
Wideband filter,
107
VREF = 2.5V
Wideband filter,
fIN = 1kHz, VREF = 2.5V, 108.5
VIN = –0.2dBFS, 2x input range
SNR Signal-to-noise ratio dB
OSR = 64, Low-latency filter 113.5
fDATA = 25kSPS
Low-latency filter,
109.5
VREF = 2.5V
Low-latency filter,
VREF = 2.5V, 111
2x input range
fIN = 1kHz, VREF = 2.5V –125 –118 dB
VIN = –0.2dBFS,
THD Total harmonic distortion OSR = 64,
fDATA = 25kSPS, VREF = 4.096V –125 –118 dB
9 harmonics

fIN = 9.7kHz and 10.3kHz, Second-order terms –125 dB

IMD Intermodulation distortion
VIN = –6.5dBFS Third-order terms –120 dB
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dBFS, OSR = 64 125 dB
Crosstalk fIN = 1kHz, VIN = –0.2dbFS (3) –130 dB
At dc 118 130
CMRR Common-mode rejection ratio Up to 10kHz 120 dB
At dc, 2x input range 105

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5.5 Electrical Characteristics (continued)

REFP and REFN High-speed mode 20

REFP buffer off nA/℃/ch
input current drift Mid-speed mode 15
Low-speed mode 15
REFP input current drift REFP buffer on 10 nA/℃/ch
INTERNAL OSCILLATOR
fOSC Oscillator frequency 25.4 25.6 25.8 MHz
VCM OUTPUT VOLTAGE
Output voltage (AVDD1 + AVSS) / 2 V
Accuracy –1% ±0.1% 1%
Voltage noise 1kHz bandwidth 25 µVRMS
Start-up time CL = 100nF 1 ms
Capacitive load 100 nF
Resistive load 2 kΩ
Short-circuit current limit 10 mA
DIGITAL INPUTS/OUTPUTS
VIL Logic-low input level 0.3 IOVDD V
VIH Logic-high input level 0.7 IOVDD V
ILEAK External leakage current Tri-state pins, floating input state -5 5 µA
CLOAD Capacitive load Tri-state pins, floating input state 50 pF
REXT Pull-up or pull-down resistance Tri-state pins, logic low or high state 0 3 kΩ
OUT_DRV = 0b, IOL = 2mA 0.2 ∙ IOVDD
VOL Logic-low output level V
OUT_DRV = 1b, IOL = 1mA 0.2 ∙ IOVDD
OUT_DRV = 0b, IOH = –2mA 0.8 ∙ IOVDD
VOH Logic-high output level OUT_DRV = 1b, IOH = –1mA 0.8 ∙ IOVDD V
ERROR pin, IOH = –2µA 0.8 ∙ IOVDD
Input hysteresis 150 mV
Input current –1 1 µA

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5.5 Electrical Characteristics (continued)

Wideband filter High-speed mode 1.6 2.0

OSR = 32 Mid-speed mode 0.8 1
Low-speed mode 0.2 0.35
mA/ch
Max-speed mode 0.6 0.8
IIOVDD IOVDD current Low-latency filter High-speed mode 0.5 0.7
OSR = 32 Mid-speed mode 0.20 0.35
Low-speed mode 0.05 0.15
External clock 15
Standby mode µA
Internal oscillator 50
Power-down mode 35 µA

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5.5 Electrical Characteristics (continued)

(1) Best-fit method.

(2) Stop-band attenuation as provided by the digital filter. Input frequencies in the stop band intermodulate with the chop frequency
beginning at fMOD / 32, which results in stop-band attenuation <106dB. See the Stop-Band Attenuation figure for details.
(3) Crosstalk measured on one shorted-input channel with three (ADS127L14) and seven (ADS127L18) active channels.

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5.6 Timing Requirements

1.65V ≤ IOVDD ≤ 1.95V, over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
CLOCK
tc(CLKIN) CLKIN period 15 2000 ns
tw(CLKINL) Pulse duration, CLKIN low 6.5 ns
tw(CLKINH) Pulse duration, CLKIN high 6.5 ns
ADC clock period, max-speed mode 29.7 2000
ADC clock period, high-speed mode 38 2000
tc(CLK) (1) ns
ADC clock period, mid-speed mode 76 2000
ADC clock period, low-speed mode 304 2000
Pulse duration, CLK low, max-speed mode 13.2
Pulse duration, CLK low, high-speed mode 17
tw(CLKL) ns
Pulse duration, CLK low, mid-speed mode 34
Pulse duration, CLK low, low-speed mode 128
Pulse duration, CLK high, max-speed mode 13.2
Pulse duration, CLK high, high-speed mode 17
tw(CLKH) ns
Pulse duration, CLK high, mid-speed mode 34
Pulse duration, CLK high, low-speed mode 128
FRAME-SYNC (DATA PORT)
DCLK period, stand-alone operation 15 ns
tc(DCLK)
DCLK period, daisy-chain operation 29.7 ns
SPI (CONFIGURATION PORT)
tc(SCLK) SCLK period 75 ns
tw(SCL) Pulse duration, SCLK low 25 ns
tw(SCH) Pulse duration, SCLK high 25 ns
td(CSSC) Delay time, first SCLK rising edge after CS falling edge 20 ns
tsu(DI) Setup time, SDI valid before SCLK falling edge 6 ns
th(DI) Hold time, SDI valid after SCLK falling edge 8 ns
td(SCCS) Delay time, CS rising edge after final SCLK falling edge 20 ns
tw(CSH) Pulse duration, CS high 20 ns
START PIN
tw(STL) Pulse duration, START low 4 tCLK
tw(STH) Pulse duration, START high 4 tCLK
tsu(STCL) Setup time, START rising edge before CLKIN rising edge (2) 4 ns
th(STCL) Hold time, START rising edge after CLKIN rising edge (2) 6 ns
Setup time, START falling edge or STOP bit set before FSYNC rising edge to stop next
tsu(STFS) 24 tCLK
conversion (start/stop conversion mode)
RESET PIN
tw(RSL) Pulse duration, RESET low 4 tCLK

(1) fCLK is the main ADC clock.

(2) To avoid synchronization uncertainty, avoid driving START high between the setup and hold time specifications.

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5.7 Switching Characteristics

1.65V ≤ IOVDD ≤ 1.9V, over operating ambient temperature range, OUT_DRV = 0b, CLOAD = 20pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLOCK
tC(CLK) ADC clock period (programmable) (1) 1, 2, 3, 4 or 8 / fCLKIN or / fOSC
FRAME-SYNC (DATA PORT)
tc(FSYNC) FSYNC period 1 / fDATA ns
tw(FSYNCH) Pulse duration, FSYNC high 0.5 / fDATA ns
tw(FSYNCL) Pulse duration, FSYNC low 0.5 / fDATA ns
tp(FSDC) Propagation delay time, FSYNC rising edge to DCLK falling edge –1 1 ns
tc(DCLK) DCLK period (programmable) (1) 1, 2, 4, or 8 / fCLKIN or / fOSC
tw(DCLKH) Pulse duration, DCLK low 0.5 ∙ tC(DCLK) ns
tw(DCLKL) Pulse duration, DCLK high 0.5 ∙ tC(DCLK) ns
th(DCDO) Hold time, DCLK falling edge to previous DOUT invalid –2 ns
tp(DCDO) Propagation delay time, DCLK falling edge to new DOUT valid 7 ns
SPI (CONFIGURATION PORT)
tp(CSDO) Propagation delay time, CS falling edge to SDO driven state 16 ns
tp(CSDOZ) Propagation delay time, CS rising edge to SDO tri-state 16 ns
tp(SCDO) Propagation delay time, SCLK rising edge to valid SDO 20 ns
START PIN
Propagation delay time, START falling edge to FSYNC signal stop
tp(STFS1) 11 tCLK
(Start/stop mode)
Propagation delay time, START falling edge to DCLK signal stop
tp(STDC) 7 tCLK
(Start/stop mode)
Propagation delay time, START rising edge to FSYNC rising edge
tp(STFS2) See the Digital Filter section
(first conversion ready)
RESET PIN
Propagation delay time, RESET rising edge to FSYNC falling edge
tp(RSFS) 104 tCLK
(ADC ready)

(1) Daisy-chaining requires external clock operation and CLK_DIV[2:0], DCLK_DIV[1:0] = divide by 1.

5.8 Timing Diagrams

tc(CLKIN), tc(CLK) tw(CLKINL), tw(CLKL)

CLKIN, CLK

tw(CLKINH), tw(CLKH)

Figure 5-1. Clock Timing Requirements

tc(FSYNC)
tw(FSYNCH) tw(FSYNCL)

FSYNC

tp(FSDC) tw(DCLKH) tw(DCLKL)

DCLK

tc(DCLK)
th(DCDO)

DOUT MSB MSB

tp(DCDO)

Figure 5-2. Frame-Sync Port Switching Characteristics

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tw(CSH)

td(CSSC) tc(SCLK) td(SCCS)

tw(SCH)

SCLK

tsu(DI) tw(SCL)

SDI MSB

th(DI)

Figure 5-3. SPI Timing Requirements

SCLK

tp(CSDO) tp(SCDO) tp(CSDOZ)

SDO MSB

Figure 5-4. SPI Switching Characteristics

tw(STL) tw(STH)
th(STCL)

START

tsu(STCL)

CLK

tsu(STFS)

FSYNC

Figure 5-5. START Pin Timing Requirements

START

tp(STFS2)

tp(STFS1)

FSYNC

tp(STDC)

DCLK

Figure 5-6. START Pin Switching Characteristics

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Software
Reset

RESET

tw(RSL)

DCLK

FSYNC

tp(RSFS)

Figure 5-7. RESET Pin Timing Requirements and Switching Characteristic

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5.9 Typical Characteristics

AVDD1 = AVDD2 = 5V, AVSS = 0V, IOVDD = 1.8V, VREF = 4.096V, high-reference range, high-speed mode, wideband filter,
OSR = 32, 1x input range, input precharge buffers on, reference precharge buffer off, and TA = 25°C. Data represent typical
channel performance (unless otherwise noted).

0 0

-20 -20

-40 -40

-60 -60
Amplitude (dB)

Amplitude (dB)
-80 -80

-100 -100

-120 -120

-140 -140

-160 -160

-180 -180
0 30 60 90 120 150 180 210 240 270 0 10 20 30 40 50 60 70 80 90 100
Frequency (kHz) Frequency (Hz)
Wideband filter (262,144 samples) 0 - 100Hz, wideband filter (262,144 samples)
Figure 5-8. Max-Speed Mode, Shorted FFT Figure 5-9. Max-Speed Mode, Shorted FFT
0 0

-20 -20

-40 -40

-60 -60
Amplitude (dB)

Amplitude (dB)

-80 -80

-100 -100

-120 -120

-140 -140

-160 -160

-180 -180
0 30 60 90 120 150 180 210 240 270 0 30 60 90 120 150 180 210 240 270
Frequency (kHz) Frequency (kHz)
Wideband filter, VREF = 2.5V, 2x range (262,144 samples) Sinc4 filter (262,144 samples)
Figure 5-10. Max-Speed Mode, Shorted FFT Figure 5-11. Max-Speed Mode, Shorted FFT
0 20
-20

-40 16

-60
Amplitude (dB)

Population (%)

-80 12

-100
8
-120

-140
4
-160

-180
0 30 60 90 120 150 180 210 240 270 0
-80
-60
-40
-20
-140
-120
-100

0
20
40
60
80
100
120
140

Frequency (kHz)
Fundamental = –0.2dBFS, 1kHz (262,144 samples) Codes
OSR = 64 (262,144 samples)
Figure 5-12. Max-Speed Mode, Full-Scale FFT
Figure 5-13. Max-Speed Mode, Shorted Noise Histogram

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5.9 Typical Characteristics (continued)

0 0

-20 -20

-40 -40

-60 -60
Amplitude (dB)

Amplitude (dB)
-80 -80

-100 -100

-120 -120

-140 -140

-160 -160

-180 -180
0 20 40 60 80 100 120 140 160 180 200 0 10 20 30 40 50 60 70 80 90 100
Frequency (kHz) Frequency (Hz)
Wideband filter (262,144 samples) 0 - 100Hz, wideband filter (262,144 samples)
Figure 5-14. High-Speed Mode, Shorted FFT Figure 5-15. High-Speed Mode, Shorted FFT
0 0

-20 -20

-40 -40

-60 -60
Amplitude (dB)

Amplitude (dB)

-80 -80

-100 -100

-120 -120

-140 -140

-160 -160

-180 -180
0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200
Frequency (kHz) Frequency (kHz)
VREF = 2.5V, 2x range, wideband filter (262,144 samples) Sinc4 filter (262,144 samples)
Figure 5-16. High-Speed Mode, Shorted FFT Figure 5-17. High-Speed Mode, Shorted FFT
0 20
-20

-40 16

-60
Amplitude (dB)

Population (%)

-80 12

-100
8
-120

-140
4
-160

-180
0 20 40 60 80 100 120 140 160 180 200 0
-80
-60
-40
-20
-140
-120
-100

0
20
40
60
80
100
120
140

Frequency (kHz)
Fundamental = –0.2dBFS, 1kHz (262,144 samples) Codes
OSR = 64 (262,144 samples)
Figure 5-18. High-Speed Mode, Full-Scale FFT
Figure 5-19. High-Speed Mode, Shorted Noise Histogram

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5.9 Typical Characteristics (continued)

0 0

-20 -20

-40 -40

-60 -60
Amplitude (dB)

Amplitude (dB)
-80 -80

-100 -100

-120 -120

-140 -140

-160 -160

-180 -180
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Frequency (kHz) Frequency (Hz)
Wideband filter (131,072 samples) 0 - 100Hz, wideband filter (131,072 samples)
Figure 5-20. Mid-Speed Mode, Shorted FFT Figure 5-21. Mid-Speed Mode, Shorted FFT
0 0

-20 -20

-40 -40

-60 -60
Amplitude (dB)

Amplitude (dB)

-80 -80

-100 -100

-120 -120

-140 -140

-160 -160

-180 -180
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Frequency (kHz) Frequency (kHz)
VREF = 2.5V, 2x range, Wideband filter (131,072 samples) Sinc4 filter (131,072 samples)
Figure 5-22. Mid-Speed Mode, Shorted FFT Figure 5-23. Mid-Speed Mode, Shorted FFT
0 20
-20

-40 16

-60
Amplitude (dB)

Population (%)

-80 12

-100
8
-120

-140
4
-160

-180
0 10 20 30 40 50 60 70 80 90 100 0
-80
-60
-40
-20
-140
-120
-100

0
20
40
60
80
100
120
140

Frequency (kHz)
Fundamental = –0.2dBFS, 1kHz (262,144 samples) Codes
OSR = 64 (262,144 samples)
Figure 5-24. Mid-Speed Mode, Full-Scale FFT
Figure 5-25. Mid-Speed Mode, Shorted Noise Histogram

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5.9 Typical Characteristics (continued)

0 0

-20 -20

-40 -40

-60 -60

Amplitude (dB)
Amplitude (dB)

-80 -80

-100 -100

-120 -120

-140 -140

-160 -160

-180 -180
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 0 10 20 30 40 50 60 70 80 90 100
Frequency (kHz) Frequency (Hz)

Wideband filter (32,768 samples) 0 - 100Hz, wideband filter (32,768 samples)

Figure 5-26. Low-Speed Mode, Shorted FFT Figure 5-27. Low-Speed Mode, Shorted FFT

0 0

-20 -20

-40 -40

-60 -60
Amplitude (dB)

Amplitude (dB)

-80 -80

-100 -100

-120 -120

-140 -140

-160 -160

-180 -180
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25
Frequency (kHz) Frequency (kHz)
VREF = 2.5V, 2x range, wideband filter (32,768 samples) Sinc4 filter (32,768 samples)
Figure 5-28. Low-Speed Mode, Shorted FFT Figure 5-29. Low-Speed Mode, Shorted FFT
0 20

-20
16
-40

-60
Population (%)
Amplitude (dB)

12
-80

-100
8
-120

-140 4
-160

-180 0
-80
-60
-40
-20
-140
-120
-100

0
20
40
60
80
100
120
140

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25

Frequency (kHz) Codes
Fundamental = –0.2dBFS, 1kHz (65,536 samples) OSR = 64 (262,144 samples)

Figure 5-30. Low-Speed Mode, Full-Scale FFT Figure 5-31. Low-Speed Mode, Shorted Noise Histogram

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5.9 Typical Characteristics (continued)

80 80
Max-Speed Mode Max-Speed Mode
70 High-Speed Mode 70 High-Speed Mode
Mid-Speed Mode Mid-Speed Mode
60 Low-Speed Mode 60 Low-Speed Mode
Population (%)

Population (%)
50 50

40 40

30 30

20 20

10 10

0 0
7

6
7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9
Noise (V-RMS) Noise (V-RMS)
Wideband filter, OSR = 64, 30 units Sinc4 filter, OSR = 64, 30 units
Figure 5-32. Integrated Noise Histogram Figure 5-33. Integrated Noise Histogram
9 6.5
Max-Speed Mode Max-Speed Mode
High-Speed Mode High-Speed Mode
8.5 Mid-Speed Mode Mid-Speed Mode
Low-Speed Mode 6 Low-Speed Mode
8
Noise (V-RMS)

Noise (V-RMS)

7.5 5.5

7
5
6.5

6 4.5
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Te mperature (C) Te mperature (C)
Wideband filter, OSR = 64 Sinc4 filter, OSR = 64
Figure 5-34. Integrated Noise vs. Temperature Figure 5-35. Integrated Noise vs. Temperature
100 80
Max-Speed Mode Mid-Speed Mode
90 High-Speed Mode Low-Speed Mode
70
80
60
70
Population (%)

Population (%)

60 50

50 40
40
30
30
20
20
10 10

0 0
111

111.25

111.75

112

112.25

112.75

113
111.5

112.5

111

112

112.25

112.75

113

113.25
110.5

111.5

112.5

Dynamic Range (dB) Dynamic Range (dB)

OSR = 64, 30 units OSR = 64, 30 units
Figure 5-36. Dynamic Range Histogram Figure 5-37. Dynamic Range Histogram

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5.9 Typical Characteristics (continued)

8 80
Low-speed mode, low-reference range Max-Speed Mode
7.75 High-speed mode, low-reference range 70 High-Speed Mode
Low-speed mode, high-reference range Mid-Speed Mode
High-speed mode, high-reference range 60 Low-Speed Mode
7.5
Noise (V-RMS)

Population (%)
50
7.25
40
7
30
6.75
20
6.5
10

6.25 0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

-60

-20
-140

-100

100

140
VREF (V)
Offset Error (V)
Wideband filter, OSR = 64
30 units
Figure 5-38. Integrated Noise vs. VREF
Figure 5-39. Offset Voltage Histograms
100 50
Max-Speed Mode Max-Speed Mode
90 High-Speed Mode High-Speed Mode
80 Mid-Speed Mode 40 Mid-Speed Mode
Low-Speed Mode Low-Speed Mode
70
Population (%)

Population (%)

60 30
50
40 20
30
20 10
10
0 0
<10

-1200

-900

-600

-300

1200
300

600

900
0

Offset Voltage Drift (nV/C)

30 units Gain Error (ppm of FSR)
Input buffers ON, 30 units
Figure 5-40. Offset Voltage Drift Histograms
Figure 5-41. Gain Error Histograms
50 100
Max-Speed Mode Max-Speed Mode
High-Speed Mode 90 High-Speed Mode
40 MId-Speed Mode 80 Mid-Speed Mode
Low-Speed Mode Low-Speed Mode
70
Population (%)
Population (%)

30 60
50

20 40
30

10 20
10

0 0
<0.3

0.6

0.9

1.2

1.5

1.8

2.1
-1200

-900

-600

-300

1200
300

600

900
0

Gain Drift (ppm of FSR/C)

Gain Error (ppm of FSR) Input buffers ON, 30 units
Input buffers OFF, 30 units
Figure 5-43. Gain Drift Histograms
Figure 5-42. Gain Error Histograms

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5.9 Typical Characteristics (continued)

100 100
Max-Speed Mode
90 High-Speed Mode 80

80 Mid-Speed Mode 60
Low-Speed Mode

Gain Error (ppm of FSR)

70 40
Population (%)

60 20

50 0

40 -20
-40
30
-60
20
-80
10
-100
0 10 15 20 25 30
<0.3

0.6

0.9

1.2

1.5

1.8

2.1

Clock Frequency (MHz)

Gain Drift (ppm of FSR/C)
High-speed mode, gain error normalized at 25.6MHz
Input buffers OFF 30 units
Figure 5-45. Gain Error vs. Clock Frequency
Figure 5-44. Gain Drift Histograms
80 80
High-Speed Mode High-Speed Mode
70 Max-Speed Mode 70 Max-Speed Mode

60 60
Population (%)
Population (%)

50 50

40 40

30 30

20 20

10
10
0
0
-122

-120

-118

-116

-114

-112

-110

-108

-106

-104

-102

-100
-122

-120

-118

-116

-114

-112

-110

-108

-106

-104

-102

-100

THD (dB)
THD (dB)
VREF = 4.096V, 30 units
VREF = 2.5V, 30 units
Figure 5-47. THD Histogram
Figure 5-46. THD Histogram
50 60
Mid-Speed Mode Mid-Speed Mode
Low-Speed Mode Low-Speed mode
50
40

40
Population (%)

Population (%)

30
30
20
20

10
10

0 0
-134

-132

-130

-128

-126

-124

-122

-120

-118

-116

-114

-112

-134

-132

-130

-128

-126

-124

-122

-120

-118

-116

-114

-112

THD (dB) THD (dB)

VREF = 2.5V, 30 units VREF = 4.096V, 30 units
Figure 5-48. THD Histogram Figure 5-49. THD Histogram

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5.9 Typical Characteristics (continued)

-110 -80
Max-Speed Mode Mid-Speed Mode Max-Speed Mode 3
High-Speed Mode Low-Speed Mode High-Speed Mode 3
-115 Mid-Speed Mode 3
-90
Low-Speed Mode 3
-120
-100

THD (dB)
THD (dB)

-125
-110
-130

-120
-135

-140 -130
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -40 -20 0 20 40 60 80 100 120 140
Signal Amplitude (dBFS) Te mperature (C)

Figure 5-50. THD vs. Signal Amplitude Figure 5-51. THD vs. Temperature

0 8
Max-Speed Mode
-20 6 High-Speed Mode
Mid-Speed Mode
-40
4 Low-Speed Mode
-60
INL (ppm of FSR)
Amplitude (dB)

2
-80
0
-100

-120 -2

-140 -4
-160
-6
-180
0 5 10 15 20 25 30 35 40 45 50 -8
Frequency (kHz) -4 -3 -2 -1 0 1 2 3 4
Differential Input Voltage (V)
High-speed mode, OSR = 64
VREF = 4.096V, 1x input range
Figure 5-52. IMD FFT
Figure 5-53. INL vs. Input Voltage
8 100
Max-Speed Mode Max-Speed Mode
High-Speed Mode 90 High-Speed Mode
6
Mid-Speed Mode 80 Mid-Speed Mode
4 Low-Speed Mode Low-Speed Mode
70
INL (ppm of FSR)

Population (%)

2 60

0 50
40
-2
30
-4 20

-6 10
0
-8
<0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-5 -4 -3 -2 -1 0 1 2 3 4 5
INL (ppm of FSR)
Differential Input Voltage (V)
Figure 5-55. INL Histograms
VREF = 2.5V, 2x input range
Figure 5-54. INL vs. Input Voltage

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5.9 Typical Characteristics (continued)

140 1000
Max-Speed Mode, AINP and AINN
800 High-Speed Mode, AINP and AINN
120
600 Mid-Speed Mode, AINP and AINN
Low-Speed Mode, AINP and AINN
100 400

Input Current (A)

CMRR (dB)

200
80
0
60
-200

40 -400
Max-Speed Mode
High-Speed Mode -600
20 Mid-Speed Mode -800
Low-Speed Mode
0 -1000
0.01 0.1 1 10 100 1000 10000 -5 -4 -3 -2 -1 0 1 2 3 4 5
Input Frequency (kHz) Differential Input Voltage (V)
Sinc4 filter Input buffers OFF
Figure 5-56. CMRR vs. Frequency Figure 5-57. Input Current vs. Input Voltage
8 350
Max-Speed Mode, AINP and AINN Max-Speed Mode Mid-Speed Mode
7 High-Speed Mode Low-Speed Mode
High-Speed Mode, AINP and AINN 300
6 Mid-Speed Mode, AINP and AINN
Low-Speed Mode, AINP and AINN
5 250
Input Current (A)
Input Current (A)

4
200
3
2 150
1
100
0
-1 50
-2
0
-3 -40 -20 0 20 40 60 80 100 120 140
-5 -4 -3 -2 -1 0 1 2 3 4 5 Te mperature (C)
Differential Input Voltage (V)
VIN = 2.5V, input buffers OFF
Input buffers ON
Figure 5-59. Input Current vs. Temperature
Figure 5-58. Input Current vs. Input Voltage
4 10
Max-Speed Mode Max-Speed Mode
High-Speed Mode 9 High-Speed Mode
Mid-Speed Mode 8 Mid-Speed Mode
Low-Speed Mode Low-Speed Mode
REFP Input Current (mA)

3
7
Input Current (A)

6
2 5
4
3
1
2
1
0 0
-40 -20 0 20 40 60 80 100 120 140 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Te mperature (C) VREF (V)
Input buffers ON ADS127L18, REFP buffer OFF
Figure 5-60. Input Current vs. Temperature Figure 5-61. REFP Input Current vs. Reference Voltage

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5.9 Typical Characteristics (continued)

60 80
Max-Speed Mode TA = -40C
High-Speed Mode 70 TA = 25C
40 Mid-Speed Mode TA = 125C
Low-Speed Mode 60
REFP Input Current (uA)

Population (%)
50

0 40

30
-20
20

-40 10

0
-60

-0.25

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0.25
1 1.5 2 2.5 3 3.5 4 4.5
VREF (V)
Oscillator Error (%)
ADS127L18, REFP buffer ON 30 units
Figure 5-62. REFP Input Current vs. Reference Voltage Figure 5-63. Oscillator Frequency Histogram
40 140
TA = -40C
35 TA = 25C 120
TA = 125C
30 100
Population (%)

25
PSRR (dB)

80
20
60
15
40
10
AVDD1
20 AVDD2
5 IOVDD
0
0 0.01 0.1 1 10 100 1000
-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

Power Supply Frequency (kHz)

VCM Voltage Error (%)

High-speed mode, sinc4 filter

30 units Figure 5-65. PSRR vs. Power Supply Frequency

Figure 5-64. VCM Output Voltage Histogram

90 70
ADS127L18 AVDD1 ADS127L14 AVDD1 ADS127L18 AVDD1 ADS127L14 AVDD1
80 ADS127L18 AVDD2 ADS127L14 AVDD2 ADS127L18 AVDD2 ADS127L14 AVDD2
60
ADS127L18 IOVDD ADS127L14 IOVDD ADS127L18 IOVDD ADS127L14 IOVDD
Power Supply Current (mA)

Power Supply Current (mA)

70
50
60

50 40

40 30
30
20
20
10
10

0 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Te mperature (C) Te mperature (C)
Input and reference buffers ON Input and reference buffers ON
Figure 5-66. Max-Speed Mode Power Supply Currents vs. Figure 5-67. High-Speed Mode Power Supply Currents vs.
Temperature Temperature

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5.9 Typical Characteristics (continued)

40 12
ADS127L18 AVDD1 ADS127L14 AVDD1 ADS127L18 AVDD1 ADS127L14 AVDD1
35 ADS127L18 AVDD2 ADS127L14 AVDD2 ADS127L18 AVDD2 ADS127L14 AVDD2
ADS127L18 IOVDD ADS127L14 IOVDD 10 ADS127L18 IOVDD ADS127L14 IOVDD
Power Supply Current (mA)

Power Supply Current (mA)

30
8
25

20 6

15
4
10
2
5

0 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Te mperature (C) Te mperature (C)
Input and reference buffers ON Input and reference buffers ON
Figure 5-68. Mid-Speed Mode Power Supply Currents vs. Figure 5-69. Low-Speed Mode Power Supply Currents vs.
Temperature Temperature
10 5
Max-Speed Mode Max-Speed Mode
High-Speed Mode High-Speed Mode
8 Mid-Speed Mode 4 Mid-Speed Mode
Low-Speed Mode Low-Speed Mode
IOVDD Current (mA)

IOVDD Current (mA)

6 3

4 2

2 1

0 0
20 100 1000 5000 10 100 1000 5000
OSR OSR
Wideband filter Sinc4 filter
Figure 5-70. ADS127L14 IOVDD Current vs. Temperature Figure 5-71. ADS127L14 IOVDD Current vs. Temperature
18 8
Max-Speed Mode Max-Speed Mode
High-Speed Mode 7 High-Speed Mode
15 Mid-Speed Mode Mid-Speed Mode
Low-Speed Mode 6 Low-Speed Mode
IOVDD Current (mA)

IOVDD Current (mA)

12
5

9 4

3
6
2
3
1

0 0
20 100 1000 5000 10 100 1000 5000
OSR OSR
Wideband filter Sinc4 filter
Figure 5-72. ADS127L18 IOVDD Current vs. Temperature Figure 5-73. ADS127L18 IOVDD Current vs. Temperature

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6 Parameter Measurement Information

6.1 Offset Error Measurement
Offset error is measured with the ADC inputs externally shorted together. The input common-mode voltage is
fixed to the mid-point of the AVDD1 and AVSS power-supply range. Offset error is specified at TA = 25°C.
6.2 Offset Drift Measurement
Offset drift is defined as the change in offset voltage measured at multiple points over the specified temperature
range. Offset drift is calculated using the box method where a box is formed over the maximum and minimum
offset voltages and specified temperature range. The box method specifies limits for the temperature error but
does not specify the exact shape and slope of the device under test. Equation 1 shows the offset drift calculation
using the box method.

Offset Drift (nV/°C) = 109 · (VOFSMAX – VOFSMIN) / (TMAX – TMIN) (1)

where:
• VOFSMAX and VOFSMIN = Maximum and minimum offset voltages over the specified temperature range
• TMAX and TMIN = Maximum and minimum temperatures
6.3 Gain Error Measurement
Gain error is defined as the difference between the actual and the ideal slopes of the ADC transfer function. Gain
error is measured by applying dc test voltages at –95% and 95% of FSR. The error is calculated by subtracting
the difference of the dc test voltages (ideal slope) from the difference in the ADC output voltages (actual slope).
The difference in the slopes is divided by the ideal slope and multiplied by 106 to convert the error to ppm of
FSR. Errors resulting from the ADC reference voltage are excluded from the gain error measurement. The gain
error is specified at TA = 25°C. Equation 2 shows the calculation of gain error:

Gain Error (ppm of FSR) = 106 · (ΔVOUT – ΔVIN) / ΔVIN (2)

where:
• ΔVOUT = Difference of two ADC output voltages
• ΔVIN = Difference of two input test voltages
6.4 Gain Drift Measurement
Gain drift is defined as the change of gain error measured at multiple points over the specified temperature
range. The box method is used in which a box is formed over the maximum and minimum gain errors over the
specified temperature range. The box method specifies limits for the temperature error but does not specify the
exact shape and slope of the device under test. Equation 3 describes the gain drift calculation using the box
method.

Gain Drift (ppm/°C) = (GEMAX – GEMIN) / (TMAX – TMIN) (3)

where:
• GEMAX and GEMIN = Maximum and minimum gain errors over the specified temperature range
• TMAX and TMIN = Maximum and minimum temperatures
6.5 NMRR Measurement
Normal-mode rejection ratio (NMRR) specifies the ability of the ADC to reject normal-mode input signals at
specific frequencies. These input frequencies are usually expressed at 50Hz and 60Hz. Normal-mode rejection
is uniquely determined by the frequency response of the digital filter. In this case, nulls in the frequency response
of the low-latency sinc3 filter option located at 50Hz and 60Hz provide rejection at these frequencies.

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6.6 CMRR Measurement

Common-mode rejection ratio (CMRR) specifies the ability of the ADC to reject common-mode input signals.
CMRR is expressed as dc and ac parameters. For measurement of CMRR (dc), three common-mode test
voltages are applied with the inputs externally shorted together. These test voltages are equal to AVSS + 50mV,
(AVDD1 + AVSS) / 2, and AVDD1 – 50mV. The maximum change of the ADC offset voltage is recorded versus
the change in common-mode test voltage. Equation 4 shows how CMRR (dc) is computed.

CMRR (dc) (dB) = 20 · log(ΔVCM / ΔVOS) (4)

where:
• ΔVCM = Change of dc common-mode test voltage
• ΔVOS = Change of corresponding offset voltage
For the measurement of CMRR (ac), an ac common-mode signal is applied at various test frequencies at 95%
full-scale range. An FFT is computed from the ADC data with the common-mode signal applied. Equation 5
shows that the nine largest amplitude spurious frequencies in the frequency spectrum are summed as powers.
These frequencies are then related to the amplitude of the common-mode test signal.

PSRR (ac) (dB) = 20 · log(VCM / VO) (5)

where:
• VCM (RMS) = Common-mode input signal amplitude
• VO (RMS) = Root-sum-square amplitude of spurious frequencies = √(V0 2 + V1 2 + ...V8 2)
6.7 PSRR Measurement
Power-supply rejection ratio (PSRR) specifies the ability of the ADC to reject power-supply interference. PSRR
is expressed as ac and dc parameters. For PSRR (dc) measurement, the power-supply voltage is changed over
the minimum, nominal, and maximum specified voltage ranges with the inputs externally shorted together. The
maximum change of ADC offset voltage is recorded versus the change in power-supply voltage. PSRR (dc) is
computed as shown in Equation 6 as the ratio of change of the power-supply voltage step to the change of offset
voltage.

PSRR (dc) (dB) = 20 · log(ΔVPS / ΔVOS) (6)

where:
• ΔVPS = Change of power-supply voltage
• ΔVOS = Change of offset voltage
For the measurement of PSRR (ac), the power-supply voltage is modulated by a 100mVpp (35mVRMS) signal at
various test frequencies. An FFT of the ADC data with power-supply modulation is performed. Equation 7 shows
that the nine largest amplitude spurious frequencies in the frequency spectrum are summed as powers. These
frequencies are then related to the amplitude of the power-supply modulation signal.

PSRR (ac) (dB) = 20 · log(VPS / VO) (7)

where:
• VPS (RMS) = 35mV ac power-supply modulation signal
• VO (RMS) = Root-sum-square amplitude of spurious frequencies = √(V0 2 + V1 2 + ...V8 2)

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6.8 SNR Measurement

Signal-to-noise ratio (SNR) is a measure of noise performance with a full-scale ac input signal. For the SNR
measurement, a –0.2dBFS, 1kHz test signal is used with VCM equal to the mid-supply voltage. Equation 8 shows
that SNR is the rms value ratio of the input signal to the root-sum-square of all other frequency components
derived from the FFT result of the ADC output samples. DC and harmonics of the original signal are excluded
from the SNR calculation. If an FFT window function is used because of non-coherent sampling, the spectral
leakage bins surrounding the original signal are removed to calculate SNR.

SNR (dB) = 20 · log(VIN / en) (8)

where:
• VIN = Input test signal
• en = Root-sum-square of frequency components excluding dc and signal harmonics
6.9 INL Error Measurement
Integral nonlinearity (INL) error specifies the linearity of the ADC dc transfer function. INL is measured by
applying a series of dc test voltages over the ADC input range. INL is the difference between a set of dc
test voltages [VIN(N)] to the corresponding set of output voltages [VOUT(N)] computed from the slope and offset
transfer function of the ADC. Equation 9 shows the end-point method of calculating INL error.

INL (ppm of FSR) = Maximum absolute value of INL test series [106 · (VIN(N) – VOUT(N)) / FSR] (9)

where:
• N = Index of dc test voltage
• [VIN(N)] = Set of test voltages over the FSR range of –95% to 95%
• [VOUT(N)] = Set of corresponding ADC output voltages
• FSR (full-scale range) = 2 · VREF (1x input range) or 4 · VREF (2x input range)
The INL best-fit method uses a least-squared error (LSE) calculation to determine a new straight line. This line
minimizes the root-sum-square of the INL errors above and below the original end-point line.
6.10 THD Measurement
Total harmonic distortion (THD) specifies the dynamic linearity of the ADC with an ac input signal. For the THD
measurement, a –0.2dBFS, 1kHz differential input signal with VCM equal to the mid-supply voltage is applied. A
sufficient number of data points are collected to yield an FFT result with frequency bin widths of 5Hz or less. The
5Hz bin width reduces the noise in the harmonic bins for consistent THD measurements. As shown in Equation
10, THD is calculated as the ratio of the root-sum-square amplitude of harmonics to the input signal amplitude.

THD (dB) = 20 · log(VH / VIN) (10)

where:
• VH = Root-sum-square of harmonics: √(V2 2+V3 2+ ...Vn 2), where Vn = The ninth harmonic voltage
• VIN = Input signal fundamental

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6.11 IMD Measurement

Intermodulation distortion (IMD) specifies the mixing effect of two input signals. Signal mixing is caused by
ADC nonlinearity resulting in new sum and difference frequencies not contained in the original signal. The IMD
second-order terms are (f1 + f2) and (f1 – f2). The IMD third-order terms are (2f1 + f2), (2f1 – f2), (f1 + 2f2), and (f1
– 2f2). Test signals f1 = 9.7kHz and f2 = 10.3kHz are at –6.5dBFS. Equation 11 shows the IMD calculation.

IMD2 (dB) = 20 · log(V2 / VIN) (11)

IMD3 (dB) = 20 · log(V3 / VIN)

where:
• IMD2 = Second-order IMD
• IMD3 = Third-order IMD
• V2 = Root-sum-square of second-order terms
• V3 = Root-sum-square of third-order terms
• VIN = Sum amplitude of the input test signals
6.12 SFDR Measurement
Spurious-free dynamic range (SFDR) is the ratio of the rms value of a single-tone ac input to the highest
spurious signal in the ADC frequency spectrum. SFDR measurement includes harmonics of the original signal.
For the SFDR measurement, a –0.2dBFS, 1kHz input signal with VCM equal to the mid-supply voltage is applied.
As shown in Equation 12, SFDR is the ratio of the rms values of the input signal to the single highest spurious
signal, including harmonics of the original signal.

SFDR (dB) = 20 · log(VIN / VSPUR) (12)

where:
• VIN = Input test signal
• VSPUR = Single highest spurious level
6.13 Noise Performance
The ADCs offer four speed modes allowing trade-offs between power consumption, bandwidth, and resolution.
The modes are max speed, high speed, mid speed, and low speed, with decreasing levels of device power
consumption. The wideband filter offers data rates up to 512kSPS in max-speed mode, 400kSPS in high-speed
mode, 200kSPS in mid-speed mode, and 50kSPS in low-speed mode.
The low-latency sinc4 filter offers data rates up to 1.365MSPS in max-speed mode, 1.066MSPS in high-speed
mode, 533kSPS in mid-speed mode, and 133kSPS in low-speed mode.
The programmable oversampling ratio (OSR) establishes the output data rate and associated signal bandwidth
that in turn determines total noise performance. Increasing the OSR lowers the signal bandwidth and total noise
by averaging more samples from the modulator to yield one conversion result.
Table 6-1 through Table 6-5 summarize the noise performance of the filters. Noise performance is illustrated
with 1x input range and a 4.096V reference voltage. In comparison, decreasing the reference voltage to 2.5V
decreases dynamic range by 4dB (typical). Operation in 2x input range and a 2.5V reference voltage decreases
dynamic range by 3dB (typical) compared to the 1x input range and 4.096V reference voltage.
Noise data are the result of the standard deviation (rms) of the conversion data with inputs shorted and biased
to the mid-supply voltage. Noise data are representative of typical performance at TA = 25°C. A minimum of
8,192 or 10 seconds of consecutive conversions (whichever occurs first) are used to measure RMS noise (en).
Because of the statistical nature of noise, repeated noise measurements yield higher or lower noise results.
Equation 13 converts RMS noise to dynamic range (dB) and Equation 14 converts RMS noise to effective
resolution (bits).

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Dynamic Range (dB) = 20 · log[FSR / (2 · √2 · en)] (13)

Effective Resolution (bits) = log2(FSR / en) (14)

where:
• FSR = 2 · VREF (1x input range)
• FSR = 4 · VREF (2x input range)
• en = Noise voltage (RMS)
When evaluating ADC noise performance, consider the effect of the external buffer and amplifier noise to the
total noise performance. The noise performance of the ADC is evaluated in isolation by selecting the input short
test connection of the input multiplexer.
Table 6-1. Wideband Filter Noise Performance (VREF = 4.096V, 1x Input Range)
fCLK DATA RATE NOISE DYNAMIC RANGE EFFECTIVE RESOLUTION
MODE OSR
(MHz) (kSPS) (en, µVRMS) (dB) (Bits)
Max speed 32.768 512 10.9 108.5 19.5
High speed 25.6 400 10.8 108.6 19.5
32
Mid speed 12.8 200 10.5 108.8 19.6
Low speed 3.2 50 10.4 108.9 19.6
Max speed 32.768 256 7.48 111.8 20.1
High speed 25.6 200 7.33 111.9 20.1
64
Mid speed 12.8 100 7.21 112.1 20.1
Low speed 3.2 25 7.17 112.1 20.1
Max speed 32.768 128 5.17 115.0 20.6
High speed 25.6 100 5.14 115.0 20.6
128
Mid speed 12.8 50 5.02 115.2 20.6
Low speed 3.2 12.5 5.02 115.2 20.6
Max speed 32.768 64 3.64 118.0 21.1
High speed 25.6 50 3.59 118.1 21.1
256
Mid speed 12.8 25 3.55 118.2 21.1
Low speed 3.2 6.25 3.55 118.2 21.1
Max speed 32.768 32 2.56 121.1 21.6
High speed 25.6 25 2.55 121.1 21.6
512
Mid speed 12.8 12.5 2.49 121.3 21.6
Low speed 3.2 3.125 2.49 121.3 21.6
Max speed 32.768 16 1.73 124.5 22.2
High speed 25.6 12.5 1.80 124.1 22.1
1024
Mid speed 12.8 6.25 1.73 124.5 22.2
Low speed 3.2 1.5625 1.75 124.4 22.2
Max speed 32.768 8 1.37 126.5 22.5
High speed 25.6 6.25 1.28 127.1 22.6
2048
Mid speed 12.8 3.125 1.26 127.2 22.6
Low speed 3.2 0.78125 1.26 127.2 22.6
Max speed 32.768 4 0.930 129.9 23.1
High speed 25.6 3.125 0.917 130.0 23.1
4096
Mid speed 12.8 1.5625 0.900 130.2 23.1
Low speed 3.2 0.390625 0.890 130.3 23.1

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Table 6-2. Sinc4 Filter Noise Performance (VREF = 4.096V, 1x Input Range)
fCLK DATA RATE NOISE DYNAMIC RANGE EFFECTIVE RESOLUTION
MODE OSR
(MHz) (kSPS) (en, µVRMS) (dB) (Bits)
Max speed 32.768 1365.3 65.1 93.0 16.9
High speed 25.6 1066.6 66.1 92.8 16.9
12
Mid speed 12.8 533.3 65.3 92.9 16.9
Low speed 3.2 133.33 65.3 92.9 16.9
Max speed 32.768 1024 25.1 101.2 18.3
High speed 25.6 800 25.1 101.3 18.3
16
Mid speed 12.8 400 24.6 101.4 18.3
Low speed 3.2 100 24.7 101.4 18.3
Max speed 32.768 682.67 10.4 108.9 19.6
High speed 25.6 533.3 10.3 108.9 19.6
24
Mid speed 12.8 266.67 10.1 109.1 19.6
Low speed 3.2 66.67 10.1 109.1 19.6
Max speed 32.768 512 8.05 111.1 20.0
High speed 25.6 400 7.83 111.4 20.0
32
Mid speed 12.8 200 7.78 111.4 20.0
Low speed 3.2 50 7.76 111.4 20.0
Max speed 32.768 256 5.46 114.5 20.5
High speed 25.6 200 5.44 114.5 20.5
64
Mid speed 12.8 100 5.30 114.8 20.6
Low speed 3.2 25 5.30 114.8 20.6
Max speed 32.768 128 3.79 117.7 21.0
High speed 25.6 100 3.76 117.7 21.1
128
Mid speed 12.8 50 3.68 117.9 21.1
Low speed 3.2 12.5 3.62 118.1 21.1
Max speed 32.768 64 2.74 120.5 21.5
High speed 25.6 50 2.69 120.6 21.5
256
Mid speed 12.8 25 2.63 120.8 21.6
Low speed 3.2 6.25 2.62 120.9 21.6
Max speed 32.768 32 1.90 123.7 22.0
High speed 25.6 25 1.89 123.7 22.0
512
Mid speed 12.8 12.5 1.86 123.8 22.1
Low speed 3.2 3.125 1.84 123.9 22.1
Max speed 32.768 16 1.34 126.7 22.5
High speed 25.6 12.5 1.34 126.7 22.5
1024
Mid speed 12.8 6.25 1.33 126.8 22.6
Low speed 3.2 1.56 1.32 126.8 22.6
Max speed 32.768 8 0.98 129.4 23.0
High speed 25.6 6.25 0.95 129.7 23.0
2048
Mid speed 12.8 3.125 0.93 129.9 23.1
Low speed 3.2 0.78 0.92 130.0 23.1
Max speed 32.768 4 0.70 132.3 23.5
High speed 25.6 3.125 0.69 132.5 23.5
4096
Mid speed 12.8 1.563 0.66 132.8 23.6
Low speed 3.2 0.39 0.66 132.8 23.6

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Table 6-3. Sinc4 + Sinc1 Filter Performance (VREF = 4.096V, 1x Input Range)
fCLK DATA RATE NOISE (en) DYNAMIC RANGE EFFECTIVE RESOLUTION
MODE OSR
(MHz) (kSPS) (µVRMS) (dB) (Bits)
Max speed 32.768 256 6.77 112.6 20.2
High speed 25.6 200 6.62 112.8 20.2
64
Mid speed 12.8 100 6.60 112.8 20.2
Low speed 3.2 25 6.50 113.0 20.3
Max speed 32.768 128 5.16 115.0 21.0
High speed 25.6 100 5.13 115.0 20.6
128
Mid speed 12.8 50 5.07 115.1 20.6
Low speed 3.2 12.5 5.02 115.2 20.6
Max speed 32.768 51.2 3.39 118.6 21.2
High speed 25.6 40 3.35 118.7 21.2
320
Mid speed 12.8 20 3.29 118.9 21.2
Low speed 3.2 5 3.28 118.9 21.3
Max speed 32.768 25.6 2.42 121.6 21.7
High speed 25.6 20 2.39 121.7 21.7
640
Mid speed 12.8 10 2.35 121.8 21.7
Low speed 3.2 2.5 2.36 121.8 21.7
Max speed 32.768 12.8 1.74 124.4 22.2
High speed 25.6 10 1.73 124.5 22.2
1280
Mid speed 12.8 5 1.69 124.7 22.2
Low speed 3.2 1.25 1.68 124.7 22.2
Max speed 32.768 5.12 1.10 128.4 22.8
High speed 25.6 4 1.09 128.5 22.8
3200
Mid speed 12.8 2 1.07 128.7 22.9
Low speed 3.2 0.5 1.07 128.7 22.9
Max speed 32.768 2.56 0.79 131.3 23.3
High speed 25.6 2 0.78 131.4 23.3
6400
Mid speed 12.8 1 0.77 131.5 23.3
Low speed 3.2 0.25 0.77 131.5 23.3
Max speed 32.768 1.28 0.57 134.1 23.8
High speed 25.6 1 0.56 134.3 23.8
12800
Mid speed 12.8 0.5 0.55 134.4 23.8
Low speed 3.2 0.125 0.54 134.6 23.9
Max speed 32.768 0.512 0.37 137.9 24.4
High speed 25.6 0.4 0.37 137.9 24.4
32000
Mid speed 12.8 0.2 0.37 137.9 24.4
Low speed 3.2 0.05 0.37 137.9 24.4

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Table 6-4. Sinc3 Filter Performance (VREF = 4.096V, 1x Input Range)

fCLK DATA RATE NOISE (en) DYNAMIC RANGE EFFECTIVE RESOLUTION
MODE OSR
(MHz) (SPS) (µVRMS) (1) (dB) (Bits)
Max speed 32.768 614.4 0.32 139.1 24.6
High speed 25.6 480 0.32 139.1 24.6
26667
Mid speed 12.8 240 0.32 139.1 24.6
Low speed 3.2 60 0.32 139.1 24.6
Max speed 32.768 512 0.32 139.1 24.6
High speed 25.6 400 0.31 139.4 24.7
32000
Mid speed 12.8 200 0.31 139.4 24.7
Low speed 3.2 50 0.31 139.4 24.7

(1) Noise data is limited to the 24-bit quantization levels: 4.096V / 223 codes = 0.488μV / code.
Table 6-5. Sinc3 + Sinc1 Filter Performance (VREF = 4.096V, 1x Input Range)
fCLK DATA RATE NOISE (en) DYNAMIC RANGE EFFECTIVE RESOLUTION
MODE OSR
(MHz) (SPS) (µVRMS) (1) (dB) (Bits)
Max speed 32.768 170.6 0.25 141.3 25.0
High speed 25.6 133.3 0.25 141.3 25.0
96000
Mid speed 12.8 66.6 0.25 141.3 25.0
Low speed 3.2 16.6 0.25 141.3 25.0
Max speed 32.768 102.4 0.24 141.6 25.0
High speed 25.6 80 0.25 141.3 25.0
160000
Mid speed 12.8 40 0.25 141.3 25.0
Low speed 3.2 10 0.25 141.3 25.0

(1) Noise data is limited to the 24-bit quantization levels: 4.096V / 223 codes = 0.488μV / code.

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7 Detailed Description
7.1 Overview
The ADS127L14 and ADS127L18 are quad and octal, 24-bit, high-resolution, simultaneous-sampling, delta-
sigma (ΔΣ) analog-to-digital converters (ADCs). The devices offer an excellent combination of dc accuracy, ac
resolution, and wide signal bandwidth for synchronized, multichannel data acquisition systems. The ADCs are
optimized for high resolution and wide signal bandwidths with low power consumption.
The Functional Block Diagram shows the device features. The devices consist of four or eight independent
delta-sigma ADCs from which data is read through a frame-sync data port. Each ADC has programmable digital
filters that provide sample rates up to 512kSPS in wideband filter mode and 1365.3kSPS in low-latency filter
mode. Four selectable power-scalable speed modes allow optimization of signal bandwidth, resolution, and
power consumption.
Signal and reference voltage input precharge buffers of each ADC channel reduce analog input current and
sampling noise to allow the use of low bandwidth signal drivers. The VCM output is a buffered mid-supply
voltage used to drive the common-mode voltage of external buffers and gain stages.
The multibit ΔΣ modulator measures the differential input signal, VIN = (VAINP – VAINN), against the differential
reference, VREF = (VREFP – VREFN). The modulator produces low-resolution, high-frequency data. Noise shaping
of the modulator shifts the quantization noise of the low-resolution data to an out-of-band frequency range where
the digital filter removes this noise. The noise remaining within the pass band is low-level thermal noise. The
digital filter decimates and filters the modulator data to provide high-resolution output data.
The digital filter has two filter modes: low-latency filter (typically used for dc signal measurement) and wideband
filter (typically used for ac signal measurement). The low-latency filter is a variable-order sinc filter with
filter options for sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1. This filter allows optimization between noise
performance, conversion latency, and signal bandwidth. The wideband filter is a multi-stage, linear phase finite
impulse response (FIR) filter. This filter provides outstanding frequency response characteristics with low pass-
band ripple, narrow transition-band, and high stop-band attenuation. The devices allow power-of-2 related data
rates between channels.
The MODE pin selects the method of device configuration: by hardware pin settings or by the SPI serial
interface.
The frame-sync data port provides the conversion data using four or eight data lanes or time division multiplex
(TDM) format to reduce the number of data lanes. Daisy-chain multiple devices by routing the DOUTx pins to the
DINx pins of the chained devices.
The device supports external clock operation for ac or dc signal applications and internal oscillator operation for
dc signal applications. The START pin simultaneously synchronizes the ADC channels. The RESET pin resets
the ADC.
Cyclic redundancy check (CRC) error detection is available for the frame-sync port and the SPI configuration
port. The register map CRC operates in the background to detect unintended changes to the register values
after the initial values are uploaded to the device. The open-drain ERROR output pin asserts low when an ADC
error is detected.
Eight general-purpose input/output (GPIO) pins are available. Two GPIOs are standalone pins and the remaining
six GPIO pins are multiplexed with the frame-sync DINx and DOUTx pins.
The AVDD1 supply voltage powers the precharge buffers and the input sampling switches. AVDD2 powers
the modulators through an internal voltage regulator. The IOVDD supply voltage is the digital I/O voltage and
also powers the digital cores through a second voltage regulator. The internal regulators reduce overall power
consumption and maintain consistent levels of device performance under varying power supply conditions.

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7.2 Functional Block Diagram

AVDD1 REFP REFN CAPA AVDD2 CAPD IOVDD

LDO LDO
VCM ÷2

Osc Mux CLKIN

FSYNC
Wideband
AINP0 24-bit ΔΣ Filter DCLK
Modulator Low-latency DOUT0
AINN0 Filter DOUT1
FSYNC DOUT2/GPIO2
Wideband DOUT3/GPIO3 (ADS127L14)
Data Port
AINP1 24-bit ΔΣ Filter
Modulator DOUT4/DIN3/GPIO4 (GPIO4)
Low-latency
DOUT5/DIN2/GPIO5 (GPIO5)
AINN1 Filter
DOUT6/DIN1/GPIO6 (DIN1/GPIO6)
Wideband DOUT7/DIN0/GPIO7 (DIN0/GPIO7)
AINP2 24-bit ΔΣ Filter
Modulator Low-latency
AINN2 Filter
GPIO
Wideband
AINP3 24-bit ΔΣ Filter
Modulator Low-latency GPIO0/TDM
SDO
AINN3 Filter
GPIO1/HDR
CS/SPEED
SPI or Pin
SCLK/FLTR
Control
SDI/OSR0
SDO
SDO/OSR1
Wideband
(ADS127L18) AINP7 24-bit ΔΣ Filter MODE
Modulator Low-latency Control ERROR
AINN7 Filter Logic START
RESET

AVSS DGND

7.3 Feature Description

7.3.1 Analog Inputs (AINP, AINN)
The analog inputs of the ADC channels are differential, with the input defined as a difference voltage: VIN = VAINP
– VAINN. For best performance, drive the input with a differential signal with the common-mode voltage centered
to mid-supply (AVDD1 + AVSS) / 2. Tie unused inputs to ground or a dc voltage within the AVSS to AVDD1
power supply range.
The ADC accepts either unipolar or bipolar input signals by configuring the AVDD1 and AVSS power supplies
accordingly. Figure 7-1 illustrates an example of a differential signal in unipolar supply configuration. Symmetric
input voltage headroom is provided when the common-mode voltage is equal to mid-supply (AVDD1 / 2). For
unipolar operation, use AVDD1 = 5V and AVSS = 0V (mid- and low-speed modes offer the option of reduced
AVDD1 supply voltage). The VCM pin provides a buffered common-mode voltage to level-shift the signal voltage
in the external driver stage.
Figure 7-2 illustrates an example of a differential signal in bipolar supply configuration. The common-mode
voltage of the signal is normally 0V. For bipolar operation, use AVDD1 and AVSS = ±2.5V (mid- and low-speed
modes offer the option of reduced AVDD1 – AVSS supply voltage).

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AVDD1
AVDD1

AINP AINP

VCM VCM
AVDD1 / 2 0V

AINN AINN

AVSS
AVSS = 0 V

Figure 7-1. Unipolar Differential Input Signal Figure 7-2. Bipolar Differential Input Signal

In both bipolar and unipolar configurations, the ADC accepts single-ended input signals by tying the AINN input
to AVSS, ground, or to mid-supply. However, because AINN is a fixed voltage, the full differential input swing
range is not obtained. Thus, the ADC dynamic range is limited to the voltage swing of the AINP input (±2.5V or
0V to 5V for a 5V supply).
The circuit of Figure 7-3 shows the simplified analog input circuit of the ADC channels. Diodes protect the analog
inputs from electrostatic discharge (ESD) events that occur during the manufacturing process and during printed
circuit board (PCB) assembly when manufactured in an ESD-controlled environment. If the inputs are driven
below AVSS – 0.3 V, or above AVDD1 + 0.3 V, the protection diodes potentially conduct. If these conditions are
possible, use external clamp diodes, series resistors, or both to limit the input current to the value shown in the
Absolute Maximum Ratings section.
CHn_MUX[2:0] bits 6:4 of CHn_CFG1 register
(address = channel n × 08h + 11h
000b = Normal polarity (default)
001b = Inverted polarity
010b = Offset test
011b = CMRR test to AINPn
100b = CMRR test to AINNn
101b = –FS test CHn_BUFP bit 0 of CHn_CFG1 register
110b = +FS test (address = channel n × 08h + 11h)
AVDD1 0b = buffer OFF (default)
111b = +FS test
1b = buffer ON

S13
SW
S1 S11
CIN
Simplified input
AINPn SW
S2
S14 sampling network
S12
SW

SW
S3 S10

AINNn SW
S4

SW
S5

SW
S6 CHn_BUFN bit 1 of CHn_CFG1 register
VREFP
(address = channel n × 08h + 11h)
AVSS 0b = buffer OFF (default)
SW
S7
1b = buffer ON

VREFN SW
S8

S9
SW
AVDD1 + AVSS
2

Figure 7-3. Analog Input Circuit

The input multiplexers of the ADC channels are independently configurable. The multiplexer offers the option
of normal or reverse signal polarities and internal test modes. The test modes are used for ADC performance
testing and diagnostics. The input-short test mode verifies noise and offset errors by shorting the inputs to
mid-supply voltage. Full-scale range is tested by selecting the +FS or –FS connection. To avoid clipped output
codes during evaluation, reduce the value of the gain registers or program the ADC to the extended range mode.
The CMRR test mode verifies CMRR performance by shorting the inputs together and the user applying a dc

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or ac test signal to the AINPn or AINNn input. The resulting data is analyzed by the user to determines CMRR
performance. Enable the input precharge buffers for best accuracy when using the test modes.
Table 7-1 shows the switch configurations of the input multiplexer circuit of Figure 7-3.
Table 7-1. Input Multiplexer Configurations
CHn_MUX[2:0] BITS CLOSED SWITCHES DESCRIPTION
000b S1, S4 Normal polarity input
001b S2, S3 Reverse polarity input
010b S9, S10 Input short for offset voltage and noise test
011b S1, S10 Input short with user applied signal to AINPn for CMRR test
100b S4, S10 Input short with user applied signal to AINNn for CMRR test
101b S6, S7 –FS dc signal for gain test
110b S5, S8 +FS dc signal for gain test
111b S5, S8 +FS dc signal for gain test

The input sampling capacitor CIN is part of the simplified input sampling network denoted in the dashed box
of Figure 7-3. The instantaneous charge demand of CIN requires the signal to settle within a half cycle of
the modulator frequency t = 1 / (2 · fMOD). To satisfy this requirement, the driver bandwidth is typically much
larger than the original signal frequency. The bandwidth of the driver is determined as sufficient when the THD
and SNR data sheet performance are achieved. Because the modulator sampling rate is eight times slower in
low-speed mode compared to high-speed mode, more time is available for driver settling.
The charge required by the input sampling capacitor is modeled as an average input current of the ADC
inputs. As shown in Equation 15 and Equation 16, the input current is comprised of differential and absolute
components.

Input Current (Differential Input Voltage) = fMOD · CIN · 106 (μA/V) (15)

where:
• fMOD = fCLK / 2
• CIN = 7.4pF (1x input range), 3.6pF (2x input range)

Input Current (Absolute Input Voltage) = fMOD · CCM · 106 (μA/V) (16)

where:
• fMOD = fCLK / 2
• CCM = 0.35pF (1x input range), 0.17pF (2x input range)
For fMOD = 12.8MHz (high-speed mode), CIN = 7.4pF and CCM = 0.3pF, the input current resulting from the
differential voltage is 95μA/V and the input current resulting from the absolute voltage is 4.5μA/V. For example, if
AINPn = 4.5V and AINNn = 0.5 , then VIN = 4V. The total AINPn input current = (4V · 95μA/V) + (4.5V · 4.5μA/V)
= 400μA. The total AINNn current is (–4V · 95μA/V) + (0.5 · 4.5μA/V) = –378μA.
The device incorporates input precharge buffers to significantly reduce the charge required by capacitor CIN. In
operation, the precharge buffers provide the charging current. Near the end of the sampling phase, capacitor
CIN is nearly fully charged. The buffers are disconnected (S11 and S12 of Figure 7-3 in up positions) to allow the
external driver to provide the fine charge to the capacitor. When the sample phase is completed, the sampling
capacitor is discharged to complete the cycle, at which time the sample process repeats. The operation of the
precharge buffers reduces the input current by more than 99%, and in many cases leads to improved THD
and SNR performance. The precharge buffers are enabled by the CHn_BUFP and CHn_BUFN bits of the
CHn_CFG1 register. If the AINN input of any channel is tied to ground or to a low-impedance source, disable the
AINN buffer to reduce power consumption. A single-ended input application is an example of a low-impedance
source.

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7.3.1.1 Input Range

The input range of the ADC is programmable, defined as VIN = ±VREF or as VIN = ±2VREF. The ±2VREF input
range doubles the usable input range when using a 2.5V reference voltage. The ±2VREF input range typically
improves dynamic range by +1dB. However, the inputs are required to be driven to the AVDD1 and AVSS supply
rails to achieve full dynamic range (with a 2.5V reference voltage). Compared to operation with a 2.5V reference
voltage, dynamic range performance improves by using 4.096V (+4dB) or 5V (+6dB) reference voltages. The
±2VREF range selection is internally forced to the ±VREF range when the high-reference range is selected (used
for 4.096V or 5V reference voltages). See the CHn_INP_RNG bits of the CHn_CFG1 registers to program the
input range.
In some ADC configurations, the available input range exceeds the power supply voltage. An example is when
using a 3V AVDD1 power supply with a 2.5V reference voltage in the ±2VREF mode. In this case, the full ±2VREF
input range is not available.
The ADC channels have the option to extend the input range by 25%. This mode provides additional headroom
for the signal. Output data are scaled such that the positive and negative full-scale output codes (7FFFFFh and
800000h) occur at:

VIN = ±1.25 × k × VREF (17)

where:
• k = 1 or 2, depending on the ±VREF or ±2VREF range selection
See the CHn_CFG1 register to program the extended range option.
When the signal exceeds 110% of normal full-scale range in the extended range mode, the ADC provides valid
conversion results, but SNR performance degrades due to modulator saturation. The MOD_FLAG bit of the
frame-sync STATUS byte indicates when modulator saturation is occurring. See the Frame-Sync STATUS byte
for details. Figure 7-4 shows SNR performance versus input amplitude in the extended range mode.
10

-10
Relative SNR (dB)

-20

-30

-40

-50

-60
100 105 110 115 120 125
Input Amplitude (% of FS)

Figure 7-4. Extended Range SNR Performance

7.3.2 Reference Voltage (REFP, REFN)

A reference voltage is required for operation. The reference voltage input is differential, defined as: VREF = VREFP
– VREFN, and is applied to the REFP and REFN inputs for all channels. See the Reference Voltage Range
section for details of the reference voltage operating range.
As shown in Figure 7-5, the reference input sampling structure is similar to the analog input structure. ESD
diodes protect the reference inputs and turn on when the reference pin voltage thresholds are exceeded. To
keep these diodes off, make sure the reference pin voltages do not go below AVSS by more than 0.3V or above
AVDD1 by 0.3V. If these conditions are possible, use external clamp diodes, series resistors, or both to limit the
input current to the specified value.

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REFP_BUF bit 1 of GEN_CFG register (address = 08h)
0b = buffer OFF (default)
AVDD1 1b = buffer ON

S2
S1
CREF
REFP Simplified reference
S3
sampling network

REFN

AVSS

Figure 7-5. Reference Input Circuit

The reference voltage is sampled by a sampling capacitor CREF. In unbuffered mode, current flows through the
reference inputs to charge the sampling capacitor. The current consists of a dc component and an ac component
that varies with the frequency of the modulator sampling clock. See the Electrical Characteristics table for the
reference input current specification.
Charging the reference sampling capacitor requires the external reference driver to settle at the end of the
sample phase t = 1 / (2 · fMOD). Incomplete settling of the reference voltage increases gain error and gain error
drift. Operation in the lower speed mode reduces the modulator sampling clock frequency, therefore allowing
more time for the reference driver to settle.
A precharge buffer option is available for the REFP input to reduce the charge drawn by the sampling capacitor.
The precharge buffer provides the coarse charge for the reference sampling capacitor CREF. Halfway through
the sample phase, the precharge buffer is bypassed (S1 is in an up position as demonstrated in Figure 7-5). At
this time, the external driver provides the fine charge to the sampling capacitor. Because the buffer reduces the
charge demand of the sampling capacitor, the bandwidth requirement of the external driver is greatly reduced.
The sampling current flowing through the REFN input is not reduced by the REFP buffer. Because many
applications ground REFN, or connect REFN to AVSS, a precharge buffer for REFN is not necessary. For
applications when REFN is not low-impedance, buffer the REFN input.
7.3.2.1 Reference Voltage Range
Optimize the ADC performance by selecting a reference voltage range: low-reference range or high-reference
range. Program the range to match the reference voltage, such as 2.5V or 4.096V. The low range accepts
voltages from 0.5V to 2.75V, and the high range accepts voltages 1V to AVDD1 – AVSS. For cases where the
ranges overlap, such as 2.5V, use the low-reference range for best performance. Program the REF_RNG bit of
the GEN_CFG1 register to select the reference voltage range. When the high-reference range is selected, the
input range is forced to VIN = ±VREF.
7.3.3 Clock Operation
Figure 7-6 shows the clock diagram. The input clock multiplexer selects the external clock signal of the CLKIN
pin or the internal clock oscillator signal. The signal is routed to all ADC channels. The clock dividers program
the main ADC clock frequency (fCLK) and the frequency of the frame-sync port DCLK signal (fDCLK). fCLK is
divided by 2 to derive the modulator sampling clock frequency (fMOD). fCLK is also divided by 32 to drive a
free-running counter for clock signal diagnostics (CLK_CNT register).

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DCLK_DIV[1:0] bits 6,5 of DP_CFG2 register

(address = 0Ch)
00b = fCLK / 1 (default)
01b = fCLK / 2
10b = fCLK / 4
11b = fCLK / 8 Data Port
Clock fDCLK
CLKIN pin Divider
8-bit CLK_CNT Register
÷ 32 counter
ADC (address = 03h)
1
25.6MHz Clock fCLK
Internal Oscillator 0 Divider
÷2 fMOD

CLK_SEL bit 3 of CLK_CFG register CLK_DIV[2:0] bits 2:0 of CLK_CFG register

(address = 0Dh) (address = 0Dh)
0b = Internal clock (default) 000b = fCLK / 1 (default)
1b = External clock 001b = fCLK / 2
010b = fCLK / 3
011b = fCLK / 4
100b = fCLK / 8

Figure 7-6. Clock Block Diagram

The speed modes determine the maximum allowable clock frequency. See the Speed Modes section for the
clock frequencies of each speed mode.
7.3.3.1 Clock Dividers
The ADC provides two clock dividers, one divider for the ADC clock and one divider for the DCLK signal of the
frame-sync port.
The ADC clock frequency is divided by 1, 2, 3, 4 or 8 using the CLK_DIV[2:0] bits. For clock divider values > 1,
ADC synchronization has uncertainty due to the unknown phase of the divided clock signal. However, the ADC
channels within the device are synchronized together. To avoid synchronization uncertainty, use the divide by 1
option. In addition, daisy chain operation of the frame-sync port requires the divide by1 option.
The DCLK frequency is divided by 1, 2, 4, or 8 using the DCLK_DIV[1:0] bits. DCLK can be operated faster
compared to the ADC clock to support high rates of data transfer.
7.3.3.2 Internal Oscillator
The ADC provides an internal oscillator to operate the ADC. Because of the clock jitter, the internal oscillator is
recommended only for measurement of dc signals. Use an external clock for measurement of ac signals. In SPI
mode, default operation is the internal oscillator and is changed to external clock by setting the CLK_SEL bit =
1b. In the hardware programming mode, external clock operation is the default. Because the internal oscillator
is 25.6MHz fixed frequency, program the ADC clock divider according to the requirements of the selected speed
mode.
When changing the clock mode from an external clock to the internal oscillator, maintain the external clock after
changing the clock mode. Maintain the clock mode for at least four cycles after the SPI register write command
that changed the clock mode. After the clock mode change, the ADC ignores the control inputs (the START and
RESET pins) for a period of 150μs. This time period allows the internal oscillator to stabilize.
7.3.3.3 External Clock
The ADC provides external clock operation. To select external clock operation in SPI programming mode, set the
CLK_SEL bit to 1 and apply the clock signal to the CLKIN pin. In the hardware programming mode, only external
clock operation is possible.
If desired, decrease the clock frequency from nominal specified frequency to yield specific data rates between
the available OSR values. When doing so, the conversion noise at the reduced data rate is the same as the
original frequency. Reduction of conversion noise is only possible by increasing the digital filter OSR value or
changing the speed or filter modes.
Clock jitter results in timing variations of the modulator sampling that leads to degraded SNR performance. A
low-jitter clock is essential to meet data sheet SNR performance. For example, with a 200kHz signal frequency,
an external clock with < 10ps (rms) jitter is required. For lower signal frequencies, the clock jitter is relaxed

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by –20dB per decade of signal frequency reduction. For example, with fIN = 20kHz, a clock with 100ps jitter
is acceptable. Many types of RC oscillators exhibit high levels of jitter that are to be avoided for ac signal
measurement. Instead, use a crystal oscillator or an integrated circuit clock source. Avoid ringing at the clock
input. A series resistor placed at the output of the clock buffer helps reduce ringing.
7.3.4 Power-On Reset (POR)
The ADC uses power-supply monitors to detect power-on and brownout events. Power-on or power-cycling the
IOVDD supply results in device reset. Power-on or power-cycling the analog power supplies does not result in
device reset.
Figure 7-7 shows the IOVDD and regulated CAPD power-on voltage thresholds. When the voltages exceed the
thresholds, the ADC is released from reset after a time delay of td(RSSC). If the START pin is high, the ADC starts
the conversion process and supplies data to the data port. The POR_FLAG bit of the SPI STATUS register and
the PWR_FLAG of the data port header byte indicate device POR. Although not necessary for operation, write
1b to the POR_FLAG bit to clear the flag to detect the next POR event. The PWR_FLAG of the data port status
byte remains disabled in hardware programming mode.
IOVDD – DGND +

1.56 V typ. –

VCAPD – DGND +

1.35 V typ. –

POR_FLAG latched

ALV_FLAG latched

PWR_FLAG latched

ADC readiness ADC ready

td(RSSC)

Figure 7-7. Digital Supply Threshold

Figure 7-8 shows the analog power supply power-on thresholds. Four monitors are used for four supply
conditions (AVDD1 – DGND), (AVDD1 – AVSS), (AVDD2 – AVSS), and the regulated CAPA voltage (CAPA
– AVSS). The ALV_FLAG bit (SPI STATUS register) and the PWR_FLAG (data port header byte) latch to 1b
when the analog supply voltages are below the threshold values. Although not necessary for operation, write
1b to the ALV_FLAG bit to clear the flag to detect the next analog supply low-voltage condition. Power cycling
the analog power supplies does not reset the ADC. Because a low voltage on the IOVDD supply resets the
internal analog LDO (CAPA), the analog low-voltage flag (ALV_FLAG) is also set. The PWR_FLAG of the data
port status byte is disabled when the device is operated in the hardware programming mode.
AVDD1 – AVSS +

2.17 V typ. –

AVDD1 – DGND +

1.31 V typ. –

AVDD2 – AVSS +

1.38 V typ. –

VCAPA – AVSS +

1.21 V typ. –

ALV_FLAG latched

Figure 7-8. Analog Supply Threshold

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7.3.5 VCM Output Voltage

The VCM pin is a buffered dc output voltage equal to the mid-point of AVDD1 and AVSS. The VCM output
is a voltage to level-shift the signal, commonly used as the VCM input for a fully differential amplifier (FDA).
The VCM output is enabled by the VCM bit of the GEN_CFG1 register. If VCM is not used, leave the pin
unconnected and disabled.
7.3.6 GPIO
The ADC provides eight general-purpose, digital input/output (GPIO) pins. The GPIO voltage levels are IOVDD
and DGND. Figure 7-9 shows the GPIO block diagram.
GPIO Direction Register
(register address = 0Fh)
GPIO Enable Register
0: GPIOn is an output (register address = 10h)
1: GPIOn is an input
0: GPIOn not enabled
IOVDD 1: GPIOn enabled
GPIO Write Data Register Write SW
(register address = 0Eh)
EN
SW
GPIOn pin

GPIO Read Data Register

SW
(register address = 04h) SW
EN
Read

Other Pin Functions

Figure 7-9. GPIO Block Diagram

The GPIO pins are enabled by the GPIO EN register and are programmable as inputs or outputs by the GPIO
DIR register. The GPIO pins are read by the GPIO RD register and written by the GPIO WR register. When
programmed as an output, a GPIO read register operation returns the value of the GPIO pin voltage. The GPIO
pins are multiplexed with other functions, and when GPIO is enabled, have highest priority over other functions.
As with all digital inputs, do not let the GPIO pins float when configured as inputs. Figure 7-10 shows the GPIO
pin locations.

3 4 5 6 7 8 9 10 11 12 13
GPIO0/TDM

GPIO1/HDR

ERROR

DOUT0

DOUT1

DOUT2/GPIO2

DOUT3/GPIO3

GPIO4

GPIO5

DIN1/GPIO6

DIN0/GPIO7

GPIO Pins GPIO Pins

Figure 7-10. GPIO Pins (ADS127L14 pins shown)

7.3.7 Modulator
The modulator is a switched-capacitor, third-order architecture achieving excellent noise and linearity
performance with low power consumption. As with most modulators, when overranged with a high amplitude
signal or with an out-of-band signal, modulator saturation potentially occurs. When saturated, the in-band signal
still converts, however the noise floor increases. Figure 7-11 illustrates the amplitude limit for out-of-band signals
to avoid modulator saturation and increased noise. The amplitude limit for dc and in-band signals is 1dB above
full-scale range.

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5

-5

Amplitude (dBFS)
-10

-15

-20

-25
0.01 0.1 1
fIN /fMOD (Hz)

Figure 7-11. Amplitude Limit to Avoid Modulator Saturation

Modulator saturation is reported by the MOD_FLAG bit of the data port status header of each channel. The
saturation status is latched during the conversion period and updated for each new conversion. Use an analog
filter at the ADC inputs to filter the out-of-band signals to prevent increased noise. The Typical Application
section shows an example of a fourth-order bandwidth limiting antialias filter.
7.3.8 Digital Filter
The digital filter bandwidth-limits (filters) and decimates (data rate reduction) the modulator low-resolution data
to yield high-resolution, lower-speed ADC output data. The oversampling ratio (OSR) determines the amount of
filtering and decimation that affects signal bandwidth, in-band noise, and ADC output data rate. The ADC output
data rate is defined by: fDATA = fMOD / OSR.
The ADC provides two filter types: a wideband filter and a low-latency filter. The filters optimize the frequency
characteristics (wideband filter - flat passband) or the time-domain characteristics (low-latency filter - fast
response time). All ADC channels must be the same filter type, however different data rates are allowed as
long as the data rates are in ratios of 2x, where x = 0, 1, 2, 3, and so on. The filter type is programmable by the
CHn_CFG2 registers, where n = channel number.
7.3.8.1 Wideband Filter
The wideband filter is a multistage FIR design featuring linear phase response, flat pass-band amplitude, narrow
transition band, and high stop-band attenuation. Because of these characteristics, it is the recommended filter
for measuring ac signals. The ADC provides eight programmable OSR values and four speed modes, offering a
range of data rate, bandwidth and resolution options.
Figure 7-12 through Figure 7-16 illustrate the frequency response of the wideband filter. Figure 7-12 shows
details of the pass-band ripple. Figure 7-13 shows the frequency response at the transition band.

0.002 0

0.0015 -20

0.001 -40
Amplitude (dB)
Amplitude (dB)

0.0005 -60

0 -80

-0.0005 -100

-0.001 -120

-0.0015 -140

-0.002 -160
0 0.1 0.2 0.3 0.4 0.5 0.4 0.42 0.44 0.46 0.48 0.5 0.52
Normalized Frequency (fIN /f DATA ) Normalized Frequency (f IN /f DATA )

Figure 7-12. Wideband Filter Pass-Band Ripple Figure 7-13. Wideband Filter Transition Band

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Figure 7-14 shows the frequency response to fDATA for OSR ≥ 64. The stop band begins at fDATA / 2 to prevent
aliasing at the Nyquist frequency. Figure 7-15 shows the stop-band attenuation to fMOD for OSR = 32. In the
stop-band region, out-of-band input frequencies mix with multiples of the fMOD / 32 chop frequency. This process
creates a pattern of stop-band response peaks that exceed the attenuation provided by the digital filter. The
width of the response peaks is twice the filter bandwidth. Stop-band attenuation is improved when used in
conjunction with an antialias filter at the ADC input.

0 0

-20
-20
-40
Amplitude (dB)

Amplitude (dB)
-60
-40

-80

-100 -60

-120
-80
-140

-160 -100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Normalized Frequency (f IN /f DATA ) Normalized Frequency (f in /f mod )

OSR ≥ 64 OSR = 32

Figure 7-14. Wideband Filter Frequency Response Figure 7-15. Wideband Filter Stop-Band

Figure 7-16 shows the filter response centered at fMOD, where the filter response repeats. If not removed by an
antialiasing filter, input frequencies at fMOD appear as aliased frequencies in the pass band. Aliasing also occurs
by input frequencies occurring at multiples of fMOD. These frequency bands are defined by:

Alias frequency bands: (N · fMOD) ± fBW (18)

where:
• N = 1, 2, 3, and so on
• fMOD = Modulator sampling frequency
• fBW = Filter bandwidth
0

-20

-40
Amplitude (dB)

-60

-80

-100

-120

-140

-160
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
Normalized Frequency (f IN /f DATA − f MOD )

Figure 7-16. Wideband Filter Frequency Response Centered at fMOD

The group delay of the filter is the time for a signal to propagate from the input to the output of the filter.
Because the filter is a linear-phase design, the envelope of a multifrequency complex signal is undistorted by
filter processing. The group delay (expressed in units of time) is constant versus signal frequency and is equal to

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34 / fDATA. Be aware that after a step input is applied to the ADC inputs, fully settled data occurs 68 data periods
later. Figure 7-17 shows the filter group delay (34 / fDATA) and the settling time for a step input (68 / fDATA).
110
100
90
Final Value
80
70
Group Delay

Amplitude (%)
60
50
40
30
20
Initial Value
10
0
-10
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68
Data Periods (1\f DATA )

Figure 7-17. Wideband Filter Step Response

The digital filter restarts when the ADC is synchronized. After synchronization, the filter discards the next 68
conversions to account for filter settling time. The Latency Time column of Table 7-2 lists the time for the first
conversion to appear on the frame-sync port after synchronization. The latency time includes an initial overhead
time for filter reset. The first data is fully settled data. If a step input occurs while continuously converting, then
the next 69 conversions are partially settled data.
Table 7-2. Wideband Filter Characteristics
(1)
fCLK DATA RATE –0.1dB FREQUENCY –3dB FREQUENCY LATENCY TIME
MODE OSR
(MHz) (kSPS) (kHz) (kHz) (µs)
Max speed 32.768 512 211.2 223.9 134.2
High speed 25.6 400 165 174.96 171.8
32
Mid speed 12.8 200 82.5 87.48 343.5
Low speed 3.2 50 20.63 21.87 1374
Max speed 32.768 256 105.6 112.0 267.0
High speed 25.6 200 82.5 87.48 341.8
64
Mid speed 12.8 100 41.25 43.74 683.5
Low speed 3.2 25 10.31 10.94 2734
Max speed 32.768 128 52.8 55.99 532.0
High speed 25.6 100 41.25 43.74 681.0
128
Mid speed 12.8 50 20.63 21.87 1362
Low speed 3.2 12.5 5.1562 5.468 5448
Max speed 32.768 64 26.4 28.00 1064
High speed 25.6 50 20.625 21.87 1362
256
Mid speed 12.8 25 10.31 10.93 2724
Low speed 3.2 6.25 2.578 2.734 10895
Max speed 32.768 32 13.2 14.00 2126
High speed 25.6 25 10.312 10.935 2721
512
Mid speed 12.8 12.5 5.156 5.467 5443
Low speed 3.2 3.125 1.289 1.367 21770

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Table 7-2. Wideband Filter Characteristics (continued)

(1)
fCLK DATA RATE –0.1dB FREQUENCY –3dB FREQUENCY LATENCY TIME
MODE OSR
(MHz) (kSPS) (kHz) (kHz) (µs)
Max speed 32.768 16 6.6 7.998 4251
High speed 25.6 12.5 5.156 5.467 5441
1024
Mid speed 12.8 6.25 2.578 2.734 10883
Low speed 3.2 1.5625 0.645 0.6834 43530
Max speed 32.768 8 3.3 3.499 8501
High speed 25.6 6.25 2.578 2.734 10881
2048
Mid speed 12.8 3.125 1.289 1.367 21762
Low speed 3.2 0.78125 0.322 0.3417 87050
Max speed 32.768 4 1.65 1.750 17001
High speed 25.6 3.125 1.289 1.367 21761
4096
Mid speed 12.8 1.5625 0.645 0.6834 43522
Low speed 3.2 0.390625 0.161 0.1709 174090

(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.
7.3.8.2 Low-Latency Filter (Sinc)
The low-latency filter is a cascaded-integrator-comb (CIC) topology with the main attribute of minimal delay
(latency) as the input data propagates through the filter. The CIC filter is also known as a sinc filter because of
the characteristic sinx/x (sinc) frequency response. The device offers the choice of four sinc filter configurations:
sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1. These configurations provide trade-offs of acquisition time, noise
performance, and line-cycle rejection.
Latency time is measured from the time of device synchronization to the rising edge of FSYNC, at which time
settled data are first available. The latency time is short compared to the wideband filter, making the filter useful
for fast acquisition of dc signals. There is no need to discard data after synchronization because the data are
settled. Detailed latency data for each sinc filter mode are given in Sinc4 Filter through Sinc3 + Sinc1 Filter
sections.
If the input signal changes while continuously converting, then the next several conversions are partially settled.
The number of conversions required for fully settled data is determined by rounding the latency time value to the
next whole number of conversion periods.
Equation 19 shows the general expression of the sinc-filter frequency response. For single-stage sinc filter
options (for example, the single-stage sinc3 or sinc4 filter), the second stage is not used.

n
sin Aπf ABπf
sin
fMOD fMOD
H(f) =
Asin πf Bsin Aπf
fMOD fMOD
(19)

where:
• n = Stage 1 filter order (3 or 4)
• f = Signal frequency
• A = Stage 1 OSR
• B = Stage 2 OSR
• fMOD = fCLK / 2

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7.3.8.2.1 Sinc4 Filter

The sinc4 filter performs averaging and decimation of the modulator data to produce data rates up to
1365.3kSPS in max-speed mode, 1066.6kSPS in high-speed mode, 533.3kSPS in mid-speed mode and
133.333kSPS in low-speed mode. Increasing the OSR value decreases the ADC data rate that reduces signal
bandwidth and total noise resulting from increased data averaging and decimation.
Table 7-3 lists the sinc4 filter characteristics.
Table 7-3. Sinc4 Filter Characteristics
fCLK DATA RATE –3-dB FREQUENCY LATENCY TIME
MODE OSR (1)
(MHz) (kSPS) (kHz) (μs)
Max speed 32.768 1365.3 310.2 3.9
High speed 25.6 1066.6 242.3 5.1
12
Mid speed 12.8 533.3 121.2 10.1
Low speed 3.2 133.33 30.3 40.5
Max speed 32.768 1024 232.7 4.9
High speed 25.6 800 181.8 6.3
16
Mid speed 12.8 400 90.9 12.6
Low speed 3.2 100 22.7 50.5
Max speed 32.768 682.67 155.1 6.9
High speed 25.6 533.3 121.2 8.9
24
Mid speed 12.8 266.67 60.6 17.1
Low speed 3.2 66.67 15.1 70.8
Max speed 32.768 512 116.3 8.9
High speed 25.6 400 90.9 11.4
32
Mid speed 12.8 200 45.4 22.8
Low speed 3.2 50 11.4 91.4
Max speed 32.768 256 58.2 16.6
High speed 25.6 200 45.4 21.3
64
Mid speed 12.8 100 22.7 42.6
Low speed 3.2 25 5.68 171
Max speed 32.768 128 29.1 32.3
High speed 25.6 100 22.7 41.3
128
Mid speed 12.8 50 11.4 82.6
Low speed 3.2 12.5 2.84 331
Max speed 32.768 64 14.5 63.6
High speed 25.6 50 11.4 81.4
256
Mid speed 12.8 25 5.68 163
Low speed 3.2 6.25 1.42 651
Max speed 32.768 32 7.27 126
High speed 25.6 25 5.68 162
512
Mid speed 12.8 12.5 2.84 324
Low speed 3.2 3.125 0.710 1294
Max speed 32.768 16 3.64 251
High speed 25.6 12.5 2.84 321
1024
Mid speed 12.8 6.25 1.42 643
Low speed 3.2 1.5625 0.355 2570

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Table 7-3. Sinc4 Filter Characteristics (continued)

fCLK DATA RATE –3-dB FREQUENCY LATENCY TIME
MODE OSR (1)
(MHz) (kSPS) (kHz) (μs)
Max speed 32.768 8 1.82 501
High speed 25.6 6.25 1.42 641
2048
Mid speed 12.8 3.125 0.710 1282
Low speed 3.2 0.7813 0.178 5130
Max speed 32.768 4 0.909 1001
High speed 25.6 3.125 0.710 1281
4096
Mid speed 12.8 1.563 0.355 2562
Low speed 3.2 0.391 0.089 10250

(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.

Because the amount of data averaging is reduced for OSR values equal to 12, 16, and 24, full 24-bit output data
resolution is not available. Table 7-4 summarizes the output data resolution for low OSR values.
Table 7-4. Sinc4 Data Resolution
OSR RESOLUTION (BITS)
12 19
16 20
24 23
≥32 24

Figure 7-18 and Figure 7-19 show the sinc4 frequency response for OSR = 32. The frequency response consists
of a series of response nulls occurring at multiples of fDATA with a series of decaying peaks in between. At the
null frequencies, the filter has zero gain. A folded image of the filter response appears when fIN/fDATA > OSR/2,
as illustrated in the frequency plot of Figure 7-19 for OSR = 32. 0dB attenuation occurs at input frequencies near
n × fMOD (n = 1, 2, 3, and so on). If signals are present at these frequencies, the signal is aliased to the pass
band.

0 0

-20 -20

-40 -40
Amplitude (dB)

Amplitude (dB)

-60 -60

-80 -80

-100 -100

-120 -120

-140 -140

-160 -160
0 1 2 3 4 0 4 8 12 16 20 24 28 32
Normalized Frequency (f IN /f DATA ) Normalized Frequency (fIN /f DATA )

Figure 7-18. Sinc4 Frequency Response Figure 7-19. Sinc4 Frequency Response to fMOD
(OSR = 32) (OSR = 32)

7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter

The sinc4 + sinc1 filter is the cascade of the sinc4 filter and a sinc1 filters. The fixed OSR of the sinc4 stage
(OSR = 32) multiplied by the OSR of the sinc1 stage determines the ADC output data rate. The sinc4 + sinc1
filter mode has shorter latency time than the single-stage sinc4 filter. Table 7-5 summarizes the sinc4 + sinc1
filter characteristics.

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Table 7-5. Sinc4 + Sinc1 Cascade Filter Characteristics

fCLK OSR DATA RATE –3dB FREQUENCY LATENCY TIME
MODE (1)
(MHz) (A × B)(2) (kSPS) (kHz) (µs)
Max speed 32.768 256 87.49 10.9
High speed 25.6 64 200 68.35 13.9
Mid speed 12.8 (32 × 2) 100 34.18 27.9
Low speed 3.2 25 8.544 111
Max speed 32.768 128 52.44 14.8
High speed 25.6 128 100 40.97 19.0
Mid speed 12.8 (32 × 4) 50 20.49 37.9
Low speed 3.2 12.5 5.121 152
Max speed 32.768 51.2 22.36 26.5
High speed 25.6 320 40 17.47 34.0
Mid speed 12.8 (32 × 10) 20 8.735 67.9
Low speed 3.2 5 2.184 272
Max speed 32.768 25.6 11.28 46.0
High speed 25.6 640 20 8.814 58.9
Mid speed 12.8 (32 × 20) 10 4.407 118
Low speed 3.2 2.5 1.102 471
Max speed 32.768 12.8 5.658 85.1
High speed 25.6 1280 10 4.420 109
Mid speed 12.8 (32 × 40) 5 2.210 218
Low speed 3.2 1.25 0.552 871
Max speed 32.768 5.12 2.266 202
High speed 25.6 3200 4 1.770 259
Mid speed 12.8 (32 × 100) 2 0.885 517
Low speed 3.2 0.5 0.221 2068
Max speed 32.768 2.56 1.133 398
High speed 25.6 6400 2 0.885 509
Mid speed 12.8 (32 × 200) 1 0.443 1018
Low speed 3.2 0.25 0.111 4075
Max speed 32.768 1.28 0.566 788
High speed 25.6 12800 1 0.442 1008
Mid speed 12.8 (32 × 400) 0.5 0.221 2017
Low speed 3.2 0.125 0.055 8069
Max speed 32.768 0.512 0.226 1960
High speed 25.6 32000 0.4 0.177 2508
Mid speed 12.8 (32 × 1000) 0.2 0.089 5018
Low speed 3.2 0.05 0.022 20070

(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.
(2) A = First stage OSR, B = Second stage OSR.

Figure 7-20 illustrates the frequency response of the sinc4 + sinc1 filter for three OSR values. The combined
frequency response is the overlaid response of the sinc4 and sinc1 filters. For low OSR values, the response
profile is dominated by the roll-off of the sinc4 filter. Nulls in the frequency response occur at n · fDATA, n = 1, 2, 3,
and so on. At the null frequencies, the filter has zero gain.

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-20

-40

Amplitude (dB)
-60

-80

-100

-120
OSR = 2
-140 OSR = 20
OSR = 200
-160
0 1 2 3 4 5 6
Normalized Frequency (f IN /f DATA )

Figure 7-20. Sinc4 + Sinc1 Frequency Response

7.3.8.2.3 Sinc3 Filter

The sinc3 filter mode is a single-stage filter. The sinc3 filter provides several data rate options including 400SPS,
60SPS, and 50SPS for line-cycle noise rejection. 10SPS is achieved by slowing the ADC clock to 10/50 x
3.2MHz = 0.64MHz in low-speed mode. Because of the large width of the frequency response notch, excellent
line-frequency NMRR and CMRR is achieved. Table 7-6 summarizes the characteristics of the sinc3 filter.
Table 7-6. Sinc3 Filter Characteristics
NMRR AT FIRST NULL (dB)
fCLK DATA RATE –3dB FREQUENCY LATENCY
MODE OSR 2% CLOCK 6% CLOCK
(MHz) (SPS) (Hz) (ms)
TOLERANCE TOLERANCE
Max speed 32.768 614.4 161.3 4.88
High speed 25.6 480 126 6.25
26667 100 71
Mid speed 12.8 240 63.0 12.5
Low speed 3.2 60 15.7 50.0
Max speed 32.768 512 134 5.86
High speed 25.6 400 105 7.50
32000 100 71
Mid speed 12.8 200 252 15
Low speed 3.2 50 13.1 60.0

Figure 7-21 shows the frequency response of the sinc3 filter (OSR = 32000). Figure 7-22 shows the detailed
response in the region of 0.9 to 1.1 · fIN / fDATA.

0 0

-20 -20

-40 -40
Amplitude (dB)

Amplitude (dB)

-60 -60

-80 -80

-100 -100

-120 -120

-140 -140

-160 -160
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.9 0.92 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 1.1
Normalized Frequency (f IN /f DATA ) Normalized Frequency (f IN /f DATA )

Figure 7-21. Sinc3 Frequency Response Figure 7-22. Detail Sinc3 Frequency Response
(OSR = 32000) (OSR = 32000)

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7.3.8.2.4 Sinc3 + Sinc1 Filter

The sinc3 + sinc1 filter mode is the cascade of the sinc3 and a sinc1 filter. The OSR of the sinc3 stage is
fixed (OSR = 32000) and the OSR of the sinc1 stage is programmable to 3 and 5. Table 7-7 summarizes the
characteristics of the sinc3 + sinc1 filter.
Table 7-7. Sinc3 + Sinc1 Filter Characteristics
NMRR AT FIRST NULL (dB)
fCLK OSR DATA RATE –3dB FREQUENCY LATENCY
MODE 2% CLOCK 6% CLOCK
(MHz) (A × B) (1) (SPS) (Hz) (ms)
TOLERANCE TOLERANCE
Max speed 32.768 170 69 9.77
High speed 25.6 96000 133.3 54 12.5
34 26
Mid speed 12.8 (32000 × 3) 66.6 27 25
Low speed 3.2 16.7 6.7 100
Max speed 32.768 102 43.5 13.7
High speed 25.6 160000 80 34 17.5
34 26
Mid speed 12.8 (32000 × 5) 40 17 35
Low speed 3.2 10 4.2 140

(1) A = First stage OSR, B = Second stage OSR.

Figure 7-23 shows the frequency response of the sinc3 + sinc1 filter. The frequency response exhibits the
characteristic sinc filter response lobes and nulls. The nulls occur at fDATA and at multiples thereof. Figure 7-24
shows the detailed response in the region of 0.9 to 1.1 · fIN / fDATA.

0 0

-20 -20

-40 -40
Amplitude (dB)

Amplitude (dB)

-60 -60

-80 -80

-100 -100

-120 -120

-140 -140

-160 -160
0 1 2 3 4 5 6 7 8 9 0.9 0.92 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 1.1
Normalized Frequency (f IN /f DATA ) Normalized Frequency (f IN /f DATA )

Figure 7-23. Sinc3 + Sinc1 Frequency Response Figure 7-24. Detail Sinc3 + Sinc1 Frequency
Response

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7.4 Device Functional Modes

7.4.1 Reset
The ADC performs an automatic reset at power-on. Manual reset is also performed by the RESET pin or by the
SPI port. The control logic, digital filter, SPI, data port operation, and user registers are reset to default values.
The hardware programming pins used to program the device are also re-scanned. Device reset is confirmed by
the POR_FLAG of the SPI STATUS register. See Figure 5-7 for details when the ADC is available for operation
after reset.
7.4.1.1 RESET Pin
The RESET pin is an active-low input that resets the ADC. The RESET pin is a Schmitt-triggered input designed
to reduce noise sensitivity. See Figure 5-7 for RESET pin timing and for the start of SPI communications after
reset. Because the ADC performs an automatic reset at power-on, a manual reset is not required.
7.4.1.2 Reset by SPI Register
The device is reset through SPI operation by writing 01011000b to the CONTROL register. Reset takes effect at
the end of the frame at the time CS is taken high. Writing any other value to the register does not result in device
reset.
7.4.1.3 Reset by SPI Input Pattern
The device is also reset through SPI by a special input pattern. The input pattern does not follow the input
command format. To reset, input a minimum of 1024 consecutive ones, followed by taking CS high at which time
reset occurs. Figure 7-25 shows the reset pattern.

CS Reset

1 1024

SCLK

SDI

Figure 7-25. SPI Reset Pattern

7.4.2 Idle and Standby Modes

When conversions are stopped, the ADC has the option to idle the conversions or to enter standby mode. The
mode is a global setting for all channels programmed by the STBY_MODE bit of the GEN_CFG2 register. In idle
mode, the analog circuit is fully biased and operational, including sampling of the signal and voltage reference
inputs. Only the digital filter is idle. When conversions are started, the digital filter is restarted to begin the
conversion process.
When conversions are stopped in standby mode, sampling of the signal and reference voltage stop to conserve
power. When conversions are restarted, sampling of the signal and reference voltages resume. Exiting standby
mode adds 24fCLK cycles to the conversion latency time of the filter.
7.4.3 Power-Down
Channels are individually powered down by the CHn_PWDN bits of the respective CHn_CFG2 configuration
registers. The analog section of the channel is disabled and the output data are the last known data. In TDM
mode, the slot position of a powered down channel is retained. When a channel is re-enabled, the conversions
reset at the time of SPI register write. Resynchronize the ADC if required. If activating channels from all-channel
power down, wait 300µs before synchronizing the channels.

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7.4.4 Speed Modes

Four programmable speed modes allow tradeoffs between data rate, noise performance and power
consumption. Table 7-8 shows the maximum data rates (OSR at minimum value) and nominal clock frequencies.
Operation in the reduced speed modes lowers the device power consumption at reduced bandwidth for
applications not requiring large signal bandwidths.
Table 7-8. Data Rates and Clock Frequencies
MODE CLOCK FREQUENCY (fCLK) fDATA WIDEBAND FILTER fDATA LOW-LATENCY FILTER
Max speed 32.768MHz 512kSPS 1365.3kSPS
High speed 25.6MHz 400kSPS 1066.6kSPS
Mid speed 12.8MHz 200kSPS 533.3kSPS
Low speed 3.2MHz 50kSPS 133.3kSPS

The speed mode is programmed by the SPEED_MODE[1:0] bits of the GEN_CFG2 register. The speed mode
selection is universal, applying to all channels. See the Recommended Operating Conditions for clock frequency
tolerances.
7.4.5 Synchronization
The ADC channels are synchronized by the START pin or by writing the START bit of the SPI CONTROL
register. Synchronization aligns the conversion times of all ADC channels together. If controlling conversions
through SPI (using the start/stop control mode), keep the START pin low to avoid contention with the pin. In SPI
programing mode, writing to registers in the address range of 08h through 50h results in simultaneous restart of
all channels. The restart causes loss of synchronization to the original START signal. Resynchronize the ADC
channels if necessary.
When using the internal clock divider with values > 1, ADC synchronization has uncertainty as to when the ADC
channels are converting due to the unknown phase of the divided clock signal. However, the ADC channels
remain synchronized together. To avoid synchronization uncertainty, use the divide by 1 option.
After synchronization, the ADC waits for the digital filter to settle before providing output data. The wait time is
equal to the filter latency (see the Digital Filter section for filter latency data). When OSR values of the channels
are different, the device waits for the slowest data channel to settle before the frame-sync output signals start. In
this case, the RPT_DATA bit of the slower channel DP_STATUS byte is set when the data are repeated during
faster channel updates.
The ADC has two modes for synchronization and control: synchronized and start/stop control modes, each with
specific functionalities. In SPI programming mode, the mode is programmed by the START_MODE[1:0] bits of
the GEN_CFG2 register. In hardware programming mode, the synchronized control mode is forced when the
wideband filter mode is selected. The start/stop control mode is the forced when the low-latency filter mode is
selected. The synchronized control mode is not available through SPI operation.
7.4.5.1 Synchronized Control Mode
Synchronized control mode synchronizes the ADC channels on the rising edge of the START pin. Conversions
continue whether START is high or low. Apply a single synchronizing pulse input or a continuous clock input to
the START pin.
As shown in Figure 7-26, synchronization occurs on the first START rising edge. If the time to the next START
rising edge is an n multiple of the conversion period within a ±1 / fCLK window, the ADC does not resynchronize
(n = 1, 2, 3, and so on). Resynchronization does not occur because the ADC conversion period is equal to the
period of the START signal. Conversely, if the START signal period is not an n multiple of the conversion period
within ± one fCLK cycle, the ADC channels resynchronize. There is no limit to the time period of the START
signal.
Figure 7-26 shows the ADC resynchronizing when the period of START input is not equal to a single or multiples
of the conversion period. As a result of the digital filter processing time, a time difference exists between the

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START signal that caused synchronization and the resulting FSYNC output signal. The time difference varies
with the OSR value of the filter.
START period not equal to n x fDATA within ± 1 / fCLK window

START pin
Re-synchronization is forced
Filter Latency 1/fDATA

FSYNC output

Figure 7-26. Synchronized Control Mode

7.4.5.2 Start/Stop Control Mode

Start/stop control mode enables and disables conversions. All channels are synchronized (started) by taking the
START pin high or by writing 1b to the START bit of the CONTROL register. The START bit is acknowledged
when CS is taken high following the register write operation. The ADC continue conversions until stopped by
taking the START pin low, or by writing 1b to the STOP bit. When stopped, conversions in progress complete
and additional conversions are stopped. The final rising edge of the FSYNC clock signal is the last conversion
data. To restart an ongoing conversion, pulse START low to high, or write 1b to the START bit a second time.
To perform a one-shot conversion, briefly pulse START high, or write to the STOP bit soon after writing to the
START bit. Figure 7-27 shows the START control and the FSYNC output signal.
START pin
or START bit write 1b STOP bit write 1b
START/STOP bits
Filter Latency 1/fDATA

FSYNC output

Last conversion output

Figure 7-27. Start/Stop Control Mode

7.4.6 Conversion-Start Delay Time

A programmable delay time delays the start of the first conversion after synchronization. After the delay is used
for the first conversion, following conversions are not delayed until synchronized again. The delay time allows for
settling of external components. For example, providing time for signal switching through an external multiplexer.
The delay is global to all ADC channels and adds to the conversion latency time. See the DELAY[2:0] bits of the
GEN_CFG1 register.
7.4.7 Calibration
Offset and gain registers for each channel correct offset and gain errors. As shown in Figure 7-28, the 24-bit
offset register value is subtracted from the conversion data before multiplication by the 24-bit gain register value.
Data are rounded to the final resolution (16- or 24-bit) and clipped to +FS and –FS code values for the final
output.

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DATA bit 6 of GEN_CFG3 register

(register address = 0Ah)
0b = 24 bit
1b = 16 bit

AINPn +
AINNn
ADC
ADCn Digital
Filter n Σ Data clipped and
rounded to width
Final
Output
-

CHn_OFS registers 1/400000h

(register address MSB = Channel n x 08h + 13h )
(register address MID = Channel n x 08h + 14h )
(register address LSB = Channel n x 08h + 15h ) CHn_GAN registers
(register address MSB = Channel n x 08h + 16h )
(register address MID = Channel n x 08h + 17h )
(register address LSB = Channel n x 08h + 18h )

Figure 7-28. Calibration Block Diagram

Equation 20 shows how conversion data are calibrated:

Final Output Data = (Data – CHn_OFS) × CHn_GAN / 400000h (20)

7.4.7.1 Offset Calibration Registers
The offset calibration value is a 24-bit word consisting of three registers coded in two's-complement format. The
offset value is subtracted from the conversion data. The most-significant byte of the three registers is the low
address. See the CHn Offset register for the register addresses of each channel. If the ADC is programmed
for 16-bit data mode, the data are left-justified to the most-significant offset byte. The left-justification allows
sub-LSB offset correction in 16-bit data mode. Table 7-9 shows example offset calibration values.
Table 7-9. OFFSET Register Values
OFFSET REGISTER VALUE OFFSET APPLIED
000010h –16LSB
000001h –1LSB
FFFFFFh 1LSB
FFFFF0h 16LSB

7.4.7.2 Gain Calibration Registers

The gain calibration value is a 24-bit word consisting of three registers coded in straight-binary format and
normalized to unity gain at 400000h. For example, to correct a gain error > 1, the gain calibration value is <
400000h. Table 7-10 shows example gain calibration values. The most-significant byte of the three registers is
the low address. See the CHn_Gain register for the gain register addresses of each channel.
Table 7-10. GAIN Register Values
GAIN REGISTER VALUE GAIN CORRECTION APPLIED
433333h 1.05
400000h 1
3CCCCCh 0.95

7.4.7.3 Calibration Procedure

The recommended calibration procedure is as follows:
1. Preset the offset and gain calibration registers to 000000h and 400000h, respectively.
2. Perform offset calibration by shorting the inputs using the input multiplexer. To include the offset error of the
external amplifier stages, short the inputs of the system. Acquire conversion data from the channel and write
the average value of the data to the offset calibration registers. Averaging the data reduces conversion noise
to improve calibration accuracy.

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3. Perform gain calibration by applying a calibration signal to the inputs. To include the gain error of the external
amplifier stage, apply the signal to the system inputs. For standard input range mode, choose the calibration
voltage to be less than the full-scale input range to avoid clipping the output code. Clipped output codes
result in inaccurate calibration. For example, use a 3.9V calibration signal with VREF = 4.096V. If operating
in extended input range mode, a calibration signal equal to VREF can be used. Acquire conversion data from
the channel and average the results. Use Equation 21 to calculate the gain calibration value.
Gain Calibration Value = (expected output code / actual output code) · 400000h (21)

For example, the expected output code of a 3.9V calibration voltage using a 4.096V reference voltage is:
(3.9V / 4.096V) · 7FFFFFh = 79E000h.
7.4.8 Data Averaging
The ADC supports channel-to-channel averaging to create higher resolution data from the original channel data.
Averaging occurs across channels in groups of two, four, or eight, as programmed by the AVG_MODE[1:0] bits
of the GEN_CFG2 register. In typical use, the signal is applied in parallel to the channels to be averaged. When
the noise between channels is uncorrelated, the dynamic range improvement in dB is 20 × log(√n), where n =
number of channels averaged. Program the channels to the same data rate (OSR) in averaging mode.
Averaging is performed after the offset, gain, and output code clip operations. Therefore, averaging is based on
the final output data from each channel. If clipped data occurs for a channel, the clipped data also reflects in
the averaged result. The MOD_FLAG of the DP_STATUS header is an OR of the original channel MOD_FLAG
status bits. Table 7-11 shows how the averaged data is assigned to the ADC channel number. The original
channel data are not available. The averaged data is compatible in TDM and daisy-chain operation.
Table 7-11. Data Averaging Modes
ASSIGNED CHANNEL TWO-CHANNEL AVERAGING FOUR-CHANNEL AVERAGING EIGHT-CHANNEL AVERAGING
CH0 Average of CH0, CH1 Average of CH0−CH3 Average of CH0−CH7 (ADS127L18)
CH1 Average of CH2, CH3 Average of CH4−CH7 (ADS127L18) —
CH2 Average of CH4, CH5 (ADS127L18) — —
CH3 Average of CH6, CH7 (ADS127L18) — —

7.4.9 Diagnostics
The device has several diagnostics to detect errors during ADC operation.
7.4.9.1 ERROR Pin and ERR_FLAG Bit
The ERROR pin is an open-drain digital output with an internal 100kΩ pull-up resistor that drives low to indicate
an error. Figure 7-29 shows the ERROR pin block diagram. Use a stronger value pullup resistor if leakage
current from the controller input causes an output-high voltage error. The ERROR pins from several devices can
be tied together. Read the STATUS registers to determine the device that asserted the error.

IOVDD

100k
ERROR
Controller

Error logic

Figure 7-29. ERROR pin

An error is the logical OR of the seven SPI STATUS register bits. Table 7-12 shows the STATUS register bits that
cause an error.

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Table 7-12. ERROR BITS

STATUS REGISTER BITS BIT LOCATION FUNCTION
ALV_FLAG STATUS[6] Analog low-voltage flag
POR_FLAG STATUS[5] Power-on reset flag
SPI_ERR STATUS[4] SPI input CRC error
REG_ERR STATUS[3] Register map CRC error
ADC_ERR STATUS[2] Internal ADC error
ADDR_ERR STATUS[1] SPI register address error
SCLK_ERR STATUS[0] SCLK count error

ERROR is driven low at power-up due to automatic assertion of the ALV_FLAG and POR_FLAG flags. Although
not required for device operation, write 1b to the SPI STATUS register to clear the power flags to allow indication
of other errors. Other error bits are cleared by writing 1b after the error condition causing the error is removed.
The ERR_FLAG of the data port STATUS byte is the inversion of the ERROR pin. In hardware control mode,
there is no access to the STATUS register, therefore an error is caused only by the ADC_ERR bit.
7.4.9.2 SPI CRC
The SPI CRC is an SPI error check code that detects transmission errors to and from the SPI port. A CRC byte
is transmitted with the ADC input data from the host. A CRC byte is transmitted with the register data from the
ADC. The SPI CRC error check is enabled by the SPI_CRC_EN bit of the GEN_CFG3 register.
The SPI CRC argument is two bytes. The CRC-In code is calculated over the two input command bytes. Any
input bytes padded to the start of the frame are not included in the CRC calculation. The ADC checks the input
command CRC code against an internal code calculated over the two received bytes. If the CRC codes do not
match, the command is not executed and the SPI_ERR bit is set in the STATUS byte. Further register write
operations are blocked except to the STATUS register to allow clearing the SPI CRC error by writing 1b to the
SPI_ERR bit. Register read operations are not blocked unless an SPI_CRC error is detected in the immediately
preceding register read command frame.
The CRC-Out code is calculated over the output register data byte and the STATUS byte. If STATUS is disabled,
the byte is treated as zero for CRC-Out calculation purposes.
The CRC value is the 8-bit remainder of a bitwise exclusive-OR (XOR) operation of the variable-length argument
with the CRC polynomial. The 8-bit CRC is based on the CRC-8-ATM (HEC) polynomial: X8 + X2 + X1 + 1. The
nine coefficients of the polynomial are: 1 00000111.
The following procedure computes the CRC value:
1. Left shift the initial data value by eight bits by appending 0s in the LSB, creating a new data value.
2. Perform an initial XOR to the MSB of the new data value from step 1 with FFh.
3. Align the MSB of the CRC polynomial to the left-most, logic 1 of the data.
4. The bits of the data value not in alignment with the CRC polynomial drop down and append to the right of the
new XOR result. XOR the data value with the aligned CRC polynomial. The XOR operation creates a new,
shorter-length value.
5. If the XOR result is less than or equal to the 8-bit CRC length, the procedure ends, yielding an 8-bit CRC
code result. Otherwise, continue with the XOR operation at step 3 using the current XOR result. The number
of loop iterations depend on the value of the initial data.
7.4.9.3 Register Map CRC
The register map CRC detects changes to the register values. The CRC is a 16-bit value stored at register 05h
(high byte) and register 06h (low byte). Calculate the CRC over the register address range 08h to 50h (for both
ADS127L14 and ADS127L18) and write the value to the CRC registers. The ADC compares the CRC register
value to an internal calculation. The REG_ERR flag of the STATUS byte is set if the CRC register value is
incorrect. Correct the CRC value, then write 1b to the REG_ERR bit to clear the error. The REG_CRC_EN bit of
the GEN_CFG3 register enables the register CRC.

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The register map CRC uses a 16-bit polynomial based on the CRC-16-IBM polynomial: X16 + X15 + X2 + 1. The
17 coefficients are 1 10000000 00000101.
7.4.9.4 ADC Error
The ADC performs continuous checks of the internal non-volatile memory. The ADC_ERR flag of the STATUS
register is set if an error is detected. Reset or power-cycle the ADC to clear the ADC_ERR.
7.4.9.5 SPI Address Range
Register access by the read and write commands is checked for valid address range. The valid address
range is 00h to 50h for both ADS127L14 and ADS127L18 devices. The ADDR_ERR bit is set in the STATUS
register when the register address range is exceeded. Clear the error by writing 1b. Except for the STATUS
register, register write operations are blocked if the flag is set. Address range checking is enabled by setting
SPI_ADDR_EN = 1b in the GEN_CFG3 register.
7.4.9.6 SCLK Counter
An SCLK counter monitors the number of SCLKs in an SPI frame to be multiples of 8. The SCLK_ERR flag of
the STATUS register is set if the number of SCLKs is not a multiple of 8. Except for the STATUS register, register
write operations are blocked until the flag is cleared by writing 1b to the bit. The SCLK counter is enabled by
setting SCLK_CNT_EN = 1b of the GEN_CFG3 register.
7.4.9.7 Clock Counter
The ADC provides a clock counter to verify the internal clock frequency. CLK_CNT is an 8-bit register operating
in continuous rollover mode at a frequency = fCLK/32. To verify the clock frequency, read the register at known
intervals and compare the difference of values to the expected value. The ADC must be in active conversion
mode with a minimum SCLK frequency of fCLK/32 to read the counter value.
The counter is enabled by the CLK_CNT_EN bit of the GEN_CFG3 register. When enabled, the counter value
initializes to 00h. When disabled, the counter value is 00h.
7.4.9.8 Frame-Sync CRC
The frame-sync CRC is an optional byte appended to the conversion data. The CRC is eight bits and is
calculated over the data bytes and, if enabled, including the STATUS_DP byte. The argument for the CRC
calculation is 16 bits, 24 bits, or 32 bits. The number of bits to be used for the CRC depend on the mode. For
the 16-bit data mode, the CRC covers two bytes. For the 24-bit data mode or the STATUS_DP byte plus 16
bits of data, the CRC covers three bytes. For the STATUS_DP byte plus 24 bits of data, the CRC covers three
bytes. The CRC uses the same CRC-8 ATM polynomial as the SPI CRC. The DP_CRC_EN bit of the DP_CFG1
register enables the CRC byte.
7.4.9.9 Self Test
Each channel of the device provides offset error, gain error, noise, and CMRR test capability. The tests are
accomplished by using the test modes of the input multiplexer and by external processing of the resulting data.
See Table 7-1 for the test options.
7.4.10 Frame-Sync Data Port
The frame-sync data port outputs conversion data. The port is a synchronous, read-only interface with FSYNC
and DCLK output clock signals with a programmable number of data lanes for the DOUTx pins. The frame-sync
signals are continuously operated except when stopped in the start/stop control mode.
Figure 7-30 shows the frame-sync pins. Pins 8 through 13 of the frame-sync port are multiplexed with GPIO
pins. When enabled, the GPIO function takes priority over the frame-sync pins. Default operation is GPIO
disabled.

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15 FSYNC

6 7 8 9 10 11 12 13 14

DOUT0

DOUT1

DOUT2/GPIO2

DOUT3/GPIO3

DOUT4/DIN3/GPIO4

DOUT5/DIN2/GPIO5

DOUT6/DIN1/GPIO6

DOUT7/DIN0/GPIO7

DCLK
Frame-Sync Port

Figure 7-30. ADS127L18 Frame-Sync Port Pins

Figure 7-31 shows the FSYNC, DCLK and DOUTx signals. (DIN and GPIO functions are subsequently removed
from the pin names). New conversion data are synchronized on the FSYNC rising edges, where the data bits
update on the DCLK falling edges. The data are shifted out continuously with no breaks between packets. The
dependent fields shown in the figure are dependent on the time division multiplexing and the input bits from
daisy-chain operation.
1/fDATA

FSYNC

DCLK

DOUTx Data Packet n Dependent Dependent Data Packet n+1

Figure 7-31. Frame-Sync Port Operation

7.4.10.1 Data Packet

The data port provides the conversion data in the form of data packets. A data packet consists of a STATUS_DP
header byte, the channel data, and a CRC byte. The STATUS_DP and CRC bytes are optional and correspond
to the conversion data of each channel. Figure 7-32 shows the full length, five-byte data packet, but is
configurable to the minimum size, two-byte packet consisting of minimum 16-bit data. The STATUS_DP header
and CRC bytes of the packet are enabled by bits 7 and 6 of the DP_CFG1 register.

STATUS_DP (A) MSB DATA MID DATA(B) LSB DATA CRC (A)

Data Packet

A. STATUS_DP and CRC bytes are optional.

B. The data field is two bytes (16-bit resolution) or three bytes (24-bit resolution).

Figure 7-32. Data Packet

7.4.10.2 Data Format

Conversion data are coded in two's-complement format, MSB sign bit first, 16- or 24-bit resolution. The data
resolution is selected by the DATA bit of the GEN_CFG3 register. Table 7-13 lists the data scaling for the 24-bit
data mode. Conversion data clips to positive and negative full-scale code values when the input signal exceeds
the positive and negative full-scale range. 16-bit resolution mode rounds the data to the nearest 16-bit value.

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Table 7-13. Data Format

24-BIT OUTPUT DATA(2)
INPUT VOLTAGE, VIN (V)(1)
STANDARD RANGE EXTENDED RANGE
1.25 · k · VREF · (223 – 1) / 223 7FFFFFh
7FFFFFh
k · VREF · (223 – 1) / 223 666666h
k · VREF / 223 000001h 000001h
0 000000h 000000h
–k · VREF / 223 FFFFFFh FFFFFFh
–k · VREF 99999Ah
800000h
–1.25 · k · VREF 800000h

(1) k = 1 or 2 depending on the 1x or 2x input range option.

(2) Ideal output data, excluding offset, gain, linearity, and noise errors. Reduced data resolution occurs
with 12, 16, and 24 OSR values.
7.4.10.3 STATUS_DP Header Byte
STATUS_DP is an optional header byte prefixed to the conversion data. STATUS_DP indicates the channel
number of the data as well as status indicators. Figure 7-33 and Table 7-14 show the field descriptions. The
STATUS_DP header is enabled by setting the DP_STAT_EN bit of the DP_CFG1 register.
Figure 7-33. STATUS_DP Header
7 6 5 4 3 2 1 0
PWR_FLAG ERR_FLAG MOD_FLAG RPT_DATA PWDN CH_ID[2:0]

Table 7-14. STATUS_DP Header Field Descriptions

Bit Field Description
7 PWR_FLAG Power flag.
This flag is the OR of the ALV_FLAG and POR_FLAG from the SPI STATUS
register, which indicates device power-up. If desired, clear the PWR_FLAG by clearing
ALV_FLAG and POR_FLAG. Clearing the PWR_FLAG is not necessary for device
operation. This bit is always 0b in hardware programming mode.
0b = No power supply event from flag last cleared
1b = Power-supply event
6 ERR_FLAG Error flag.
This bit is the inversion of the ERROR pin output. This bit is always 0b in hardware
programming mode. See the Error Pin section for more details.
0b = No error
1b = Error
5 MOD_FLAG Modulator saturation flag.
This bit indicates modulator saturation during the conversion cycle. The flag is updated
at the completion of each conversion.
0b = No modulator saturation
1b = Modulator saturation
4 RPT_DATA Repeat data flag.
This bit indicates whether data are new or repeated. Repeated data are caused by
different data rates between channels with slower channels repeating the original
data between updates of faster channels. Repeated data are also caused by the
repeat-data mode, programmed by the DP_DAISY bit of the DP_CFG1 register. This
bit is always 0b in hardware programming mode.
0b = Data are new
1b = Data are repeated
3 PWDN Power down flag.
This bit indicates power down or standby mode.
0b = Channel in power down or standby mode
1b = Normal operation

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Table 7-14. STATUS_DP Header Field Descriptions (continued)

Bit Field Description
2:0 CH_ID[2:0] Channel identification number.
These bits show the channel number corresponding to the data.
000b = Channel 0
001b = Channel 1
010b = Channel 2
011b = Channel 3
100b = Channel 4 (ADS127L18 only)
101b = Channel 5 (ADS127L18 only)
110b = Channel 6 (ADS127L18 only)
111b = Channel 7 (ADS127L18 only)

7.4.10.4 FSYNC Pin

The FSYNC pin is the word clock signal of the frame-sync port. FSYNC transitions high to indicate the beginning
of new channel data. The FSYNC clock frequency is fDATA. If the channels are programmed to different data
rates, the FSYNC frequency is the fastest data channel.
7.4.10.5 DCLK Pin
The DCLK pin is the frame-sync port bit-clock output signal that shifts out conversion data from the DOUTx pins.
Data are updated on the falling DCLK edge and are read on the rising DCLK edge.
The DCLK frequency is derived from the clock input signal by a programmable divider. See the Clock Operation
section for details of the CLK and DCLK dividers. The DCLK signal frequency must be sufficient to transmit the
data in one conversion period, otherwise data are lost. Equation 22 shows how to calculate the minimum DCLK
frequency.

fDCLK ≥ fDATA · TDM ratio · Data Packet Size (22)

where:
• fDATA = Data rate (Hz).
• TDM ratio = 1: eight data lanes, 2: four data lanes, 4: two data lanes, 8: one data lane.
• Data packet = Number of bits in a channel data packet (16, 24, 32 or 40 bits).
For example, with fDATA = 200kSPS, TDM ratio = 2 (four data lanes), and 40-bit data packet, the minimum DCLK
frequency = 200kHz · 2 · 40 = 16MHz. DCLK can be higher than the required minimum in which case the extra
bits occurring after the data packet bits are ignored.
When operating devices in daisy-chain mode, the TDM ratio in the fDCLK equation is multiplied by the number of
devices in the chain.
Table 7-15 shows additional examples of CLK and DCLK frequencies. Use the DCLK and CLK dividers to
provide the required ADC and DCLK clock frequencies based on the speed mode, data rate, TDM factor and
packet size.
Table 7-15. DCLK Frequency Examples
DATA DCLK CLKIN DCLK
SPEED PACKET CLK ADC CLOCK DCLK
RATE TDM RATIO MIN INPUT (1) (1) ACTUAL
MODE SIZE DIVIDER (MHz) DIVIDER
(kSPS) (MHz) (MHZ) (MHz)
Max 1365.3 2 24 65.536 65.536 2 32.768 1 65.536
Max 512 1 24 12.288 32.768 1 32.768 2 16.384
Max 512 4 24 49.152 65.536 2 32.768 1 65.536
High 400 4 24 38.400 51.200 2 25.600 1 51.200
Mid 200 4 40 32.000 38.400 3 12.800 1 38.400
Low 50 8 40 16.000 25.600 8 3.200 1 25.600

(1) Daisy chain operation requires the CLK and DCLK dividers are programmed to the divide by 1 option.

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7.4.10.6 DOUTx Pins

DOUTx are the data output pins of the frame-sync port. Output data are updated on the DCLK falling edges and
latched by the host on the rising edges. The number of DOUTx pins providing channel data is programmed by
the DP_TDM[1:0] bits of the DP_CFG1 register. Inactive DOUTx pins are available as GPIO or as daisy-chain
input pins (DIN) to input data from another device.
7.4.10.7 DINx Pins
The DINx pins are the frame-sync port digital inputs that receive data from another device for daisy-chain
operation. The number of DOUTx pins (or data lanes) is programmed by the DP_TDM[1:0] bits of the DP_CFG1
register. Depending on the level of DP_TDM[1:0] programming, unused DOUTx pins automatically change state
to DINx input pins. The exception is the DOUT1 pin which remains as an output. If daisy-chain mode is not used,
tie the DINx pins to ground or use pull-down resistors. Do not let the DINx pins float.
7.4.10.8 Time Division Multiplexing
Time division multiplexing (TDM) mode serializes channel data into the data lanes. The number of data lanes
are programmable to 1, 2, 4 or 8 for ADS127L18 and 1, 2 or 4 for the ADS127L14. When the number of data
lanes is less than the number of channels, the device packs data in TDM mode. The DP_TDM[1:0] bits of the
DP_CFG1 register programs the number of data lanes.
The general characteristics of the data lanes are listed below.
• If the number data lanes are less than eight (ADS127L18) or less than four (ADS127L18), the unused DOUT
pins become data inputs to support daisy chaining. The exception is DOUT1 which remains a driven output.
• The DINx pin numbers correlate to the DOUTx pin numbers for daisy chaining. The data inputs must either
be tied low (or high as desired), or driven by a daisy chain device.
• When a channel is powered down, the data slot occupies the same position with frozen data. The channel ID
bits of the STATUS byte remain active.
• When channels are powered down, the DOUTx pins of the data lanes remain as outputs.
Figure 7-34 shows the one data-lane option for the ADS127L18. DOUT2 through DOUT7 become unused inputs
which must not be allowed to float. Apply daisy-chain data to the DIN0 pin. If unused, tie the pin to ground.
FSYNC

Repeated data or daisy-chain DINn data.

DOUT0 Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch0

Figure 7-34. DP_TDM[1:0] = 00b, One Data Lane (ADS127L18)

Figure 7-35 shows the two data-lane option for the ADS127L18 and the one data-lane option for the
ADS127L14. DOUT2 through DOUT7 (ADS127L18) and DOUT2, DOUT3 (ADS127L14) become unused inputs
which must not be allowed to float. Apply daisy-chain data to the DIN0 pin (ADS127L14) and to DIN0, DIN1
(ADS127L18). If unused, tie the pins to ground.
FSYNC

Repeated data or daisy-chain DINn data.

DOUT0 Ch0 Ch1 Ch2 Ch3 Ch0

DOUT1 Ch4 Ch5 Ch6 Ch7 Ch4

Figure 7-35. DP_TDM[1:0] = 01b, Two Data Lanes (ADS127L18) or One Data Lane (ADS127L14 )

Figure 7-36 shows the four data-lane option for the ADS127L18 and the two data-lane option for the
ADS127L14. DOUT4 through DOUT7 (ADS127L18) become unused inputs which must not be allowed to float.
Apply daisy-chain data to DIN0, DIN1 (ADS127L14) and DIN0 through DIN3 (ADS127L18). If unused, tie to
ground.

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FSYNC

Repeated data or daisy-chain DINn data.

DOUT0 Ch0 Ch1 Ch0

DOUT1 Ch2 Ch3 Ch2

DOUT2 Ch4 Ch5 Ch4

DOUT3 Ch6 Ch7 Ch6

Figure 7-36. DP_TDM[1:0] = 10b, Four Data Lanes (ADS127L18) or Two Data Lanes (ADS127L14 )

Figure 7-37 shows the eight data-lane option for the ADS127L18 and four data-lane option for the ADS127L14.
DOUT4 through DOUT7 are not available for the ADS127L14. Daisy chaining is not possible for this mode.
FSYNC

All data lanes repeat original data. Daisy-chain not supported.

DOUT0 Ch0 Ch0

DOUT1 Ch1 Ch1

DOUT2 Ch2 Ch2

DOUT3 Ch3 Ch3

DOUT4 Ch4 Ch4

DOUT5 Ch5 Ch5

DOUT6 Ch6 Ch6

DOUT7 Ch7 Ch7

Figure 7-37. DP_TDM[1:0] = 11b, Eight Data Lanes (ADS127L18) or Four Data Lanes (ADS127L14 )

7.4.10.9 Daisy Chain

The device supports daisy-chaining of the frame-sync ports to reduce the number of data lanes when multiple
devices are used. For daisy-chaining, connect the DOUTx pins to the DINx pins of the following devices. Data
appearing on the following devices DINx pins are shifted in and append to the data on DOUTx. The DP_DAISY
bit of the DP_CFG1 register programs the DINx pins to receive data for daisy-chaining. If disabled, daisy-chain
input data are ignored and original data of each device are repeated.
There is no limit to the number of daisy-chained devices, provided the OSR and packet size are considered so
all data are output within a conversion period, otherwise data are lost. See the DCLK Pin section for details of
DCLK.
The general requirements for devices in daisy-chain operation are as follows:
• The ADC clock and DCLK frequencies are the same.
• DCLK_DIV[1:0] and CLK_DIV[2:0] are programmed to the divide-by-1 values.
• External clock operation.
• DP_TDM[1:0] (TDM mode) is programmed the same for all devices in the chain.
• Devices are synchronized together.

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Figure 7-38 shows a daisy-chain connection of two ADS127L18 devices using one data lane for 16 channels
of data (DP_TDM[1:0] = 00b). In this TDM mode, the DOUT[7:4] pins default to DIN[3:0] data inputs. Because
DOUT2 and DOUT3 also become unused inputs, external pull-down resistors are used to prevent the inputs
from floating. DOUT1 is an unconnected output. Because of the amount of data required to be shifted out within
a data period, the minimum value OSR is 256 to operate with 32-bit data packets.
ADC Clock

Frame-Sync Receiver
ADS127L18 ADS127L18
(ADC2) (ADC1) SYNC Output
START FSYNC X START FSYNC Word Clock Input
CLKIN DCLK X CLKIN DCLK Bit Clock Input
DIN0 DOUT0 DIN0 DOUT0 Data Input
DIN1 DOUT1 X DIN1 DOUT1 X
DIN2 DOUT2 DIN2 DOUT2
DIN3 DOUT3 DIN3 DOUT3

Figure 7-38. One-Lane Daisy Chain

Figure 7-39 shows the data format of the one data-lane connection.
FSYNC

ADC1 DOUT0 ADC1-Ch0 ADC1-Ch1 ADC1-Ch7 ADC2-Ch0 ADC2-Ch1 ADC2-Ch7 ADC1-Ch0 + 1

Figure 7-39. One-Lane Daisy Chain Data

Figure 7-40 shows a daisy-chain connection of two ADS127L18 devices using four data lanes for 16 channels of
data (DP_TDM[1:0] = 10b). An alternative approach is to operate the devices in parallel in two data-lane mode
yielding the same number of data lanes, but with a different data format.
ADC Clock

Frame-Sync Receiver
ADS127L18 ADS127L18
(ADC2) (ADC1) SYNC Output
START FSYNC X START FSYNC Word Clock Input
CLKIN DCLK X CLKIN DCLK Bit Clock Input
DIN0 DOUT0 DIN0 DOUT0 Data Input 0
DIN1 DOUT1 DIN1 DOUT1 Data Input 1
DIN2 DOUT2 DIN2 DOUT2 Data Input 2
DIN3 DOUT3 DIN3 DOUT3 Data Input 3

Figure 7-40. Four-Lane Daisy Chain

Figure 7-41 shows the data format of the four data-lane connection.
FSYNC

ADC1 DOUT0 ADC1-Ch0 ADC1-Ch1 ADC2-Ch0 ADC2-Ch1 ADC1-Ch0 +1

ADC1 DOUT1 ADC1-Ch2 ADC1-Ch3 ADC2-Ch2 ADC2-Ch3 ADC1-Ch2 +1

ADC1 DOUT2 ADC1-Ch4 ADC1-Ch5 ADC2-Ch4 ADC2-Ch5 ADC1-Ch4 +1

ADC1 DOUT3 ADC1-Ch6 ADC1-Ch7 ADC2-Ch6 Ch7 (ADC2) ADC1-Ch6 +1

Figure 7-41. Four-Lane Daisy Chain Data

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7.4.10.10 DOUTx Timing

The timing of the DOUTx pins is programmable to help meet external requirements. DOUTx is delayed or
advanced relative to the FSYNC and DCLK signals over a ±6ns range with an approximate bit weight = 0.3ns, as
shown in the Figure 7-42. The timing between the FSYNC and DCLK signals is fixed. The DOUT_DLY[4:0] bits
of the DP_CFG2 register programs the DOUTx timing.

FSYNC

DCLK

DOUT delay
(DOUT_DLY[4:0] < 0)

DOUT

DOUT advance
(DOUT_DLY[4:0] > 0)

DOUT

Figure 7-42. DOUT Timing Adjustment

7.5 Programming
The device has two interfaces: frame-sync and SPI. The frame-sync interface provides the conversion data and
the SPI interface is used to configure the device. The device is also programmed by hardware device pins to
replace SPI programming. The MODE pin selects between hardware programming or SPI programming mode.
The MODE pin is read at power-up and after reset to determine the programming mode. See the Hardware
Programming section for details. See the SPI Programming section for SPI programming details.
7.5.1 Hardware Programming
In the hardware programming mode, the device is programmed by strapping the pins to IOVDD, DGND or
floated, but also can be tied to a controller I/O to change ADC configuration as needed. Hardware programming
is selected by floating or grounding the MODE pin, in which SPI programing is disabled. Figure 7-43 and Table
7-16 show the hardware pins and the pin functionality. Not all device options are available in hardware mode.
See the SPI Programming section for details of SPI programming.
Hardware
Programming Pins
SCLK/FLTR

CS/SPEED

DGND or Float
MODE
56

SDI/OSR0 1

SDO/OSR1 2
Hardware
Programming Pins
GPIO0/TDM 3

GPIO1/HDR 4

Figure 7-43. Hardware Programming Mode

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Table 7-16. Hardware Programming Pins

PIN NO. DESCRIPTION STATE(1) FUNCTION
0 Hardware programming, all buffers ON
SPI or hardware
MODE 54 1 SPI programming
programming mode
F Hardware programming, all buffers OFF
0 Low-speed mode
CS/SPEED 55 Speed mode 1 Max-speed mode
F Mid-speed mode
0 Wideband filter
SCLK/FLTR 56 Filter type 1 Low-latency sinc4 filter
F Low-latency sinc4 + sinc1 filter
OSR1/ SINC4 + SINC1
WIDEBAND FILTER SINC4 FILTER
OSR0 FILTER
00 32 12 64
01 64 16 128
0F 128 24 320
SDO/OSR1 10 256 32 640
2,1 Filter OSR
SDI/OSR0
11 512 64 1280
1F 1024 128 3200
F0 2048 256 6400
F1 4096 1024 12800
FF 4096 4096 32000
0 No TDM, four or eight data lanes (all DOUTx pins are used)
1 ADS127L18: one data lane (DOUT0 pin)
GPIO0/TDM 3 Data port TDM
ADS127L14: one data lane (DOUT0 pin)
F
ADS127L18: two data lanes (DOUT0 and DOUT1 pins)
0 24 data bits (only)
GPIO1/HDR 4 Data-port header 1 STATUS header byte + 24 data bits
F STATUS header byte + 24 data bits + CRC byte

1. F = float state.
The device reads the pins at power-up and at device reset by applying pulses through a weak driver (ZOUT =
25kΩ). Make sure the pin levels are established prior to power-up or reset. If a floating condition is detected,
the device drives the pin low to prevent the pin from floating during normal operation. After the pins are read,
changes to the pins are not acknowledged until the next power up or reset cycle.
Because the device applies pulses to read the pins, the float-state condition limits the external pin capacitance
and external leakage current. The logic 1 and 0 input conditions also limits the maximum pull-up and pull-down
resistors. Figure 7-44 shows the electrical limits for each state. For proper pin mode detection, do not tie
together floating inputs of other devices.
OE
ILEAKAGE <5A IOVDD Pin
Pin
R <3k R <3k
CLOAD <50pF
Pin

Float Logic high Logic low

Figure 7-44. Hardware Programming Pin Conditions

Programming options not available in the hardware mode assume the SPI register default values. See the
Register Map section for the default values. Table 7-17 shows the exceptions to the SPI defaults.

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Table 7-17. Hardware Programming Default

FUNCTION HARDWARE MODE DEFAULT
Clock mode External clock
Reference range High reference range
VCM output Enabled

7.5.2 SPI Programming

SPI Programming is selected by tying the MODE pin to IOVDD. In SPI mode, the hardware mode is disabled
and the device is programmed by writing to the SPI registers. Figure 7-45 shows the SPI pins.
SPI Pins

SCLK/FLTR
IOVDD

CS/SPEED

MODE
56

54
SDI/OSR0 1
SPI Pins
SDO/OSR1 2

Figure 7-45. SPI Pins

The SPI consists of four signals: CS, SCLK, SDI, and SDO (hardware pin functions are subsequently removed
from the pin names). The interface operates in a passive mode where SCLK is an input to the device, driven by
the host. The interface is compatible to SPI mode 1 (CPOL = 0 and CPHA = 1). In SPI mode 1, SCLK idles low,
and data are updated on SCLK rising edges and read on SCLK falling edges. The interface supports full-duplex
operation, meaning input data and output data are transmitted simultaneously.
An optional 8-bit CRC value validates data transmission between the host and the device. A 16-bit CRC register
value detects register map changes after the initial register data are loaded.
7.5.2.1 Chip Select (CS)
CS is an active-low input that enables the SPI for communication. Communication is started by taking CS low
and is ended by taking CS high. When CS is taken high, the device ends communication by interpreting the
last 16 bits of input data (24 bits in CRC mode). The device interprets the last bits regardless of the number of
bits shifted in. When CS is high, the SPI interface resets, commands are blocked, and the SDO pin enters a
high-impedance state.
7.5.2.2 Serial Clock (SCLK)
SCLK is the serial clock input that shifts register data into and out of the ADC. Output data update on the SCLK
rising edge and input data are latched on the SCLK falling edge. SCLK is a Schmitt-triggered input designed to
increase noise immunity. Even though SCLK is noise resistant, keep SCLK as noise-free as possible to avoid
unintentional SCLK transitions. Avoid ringing and overshoot on the SCLK input. A series termination resistor
placed at the SCLK driver often reduces ringing.
7.5.2.3 Serial Data Input (SDI)
SDI is the SPI data input. SDI is used to input data to the device. Data are latched on the SCLK falling edge. Idle
SDI high or low when not active.
7.5.2.4 Serial Data Output (SDO)
SDO is the SPI data output. Output data from the ADC are updated on the SCLK rising edge. The SDO pin is
tri-state when CS is high.

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7.5.3 SPI Frame

Communication through the SPI is based on the concept of frames. A frame is started by taking CS low and is
ended by taking CS high. When CS is taken high, the device interprets the last 16 or 24 bits of data (depending
on configuration), regardless of the amount of data shifted in.
7.5.4 Commands
Commands are used to read and write register data to configure and control the device. Commands are two
bytes long (plus an optional CRC byte). The Register Map is a series of 8-bit registers, accessible by read and
write operations, one register access at a time. When SPI CRC is enabled, the device computes the CRC input
value of the two bytes preceding the CRC byte to verify the command. Table 7-18 shows the command format.
Table 7-18. Commands
COMMAND BYTE1 BYTE2 BYTE 3 (Optional CRC Mode)
Read register 00h + register address [6:0] Don't care CRC of byte 1 and byte 2
Write register 80h + register address [6:0] Register data CRC of byte 1 and byte 2

There is a special input bit pattern that directly resets the ADC. See the Reset by SPI Input Pattern section for
details.
Table 7-19 summarizes the input and output byte sequence for read and write commands corresponding to the
STATUS and CRC options. STATUS and CRC are enabled by setting the respective bits in the GEN_CFG3
register. The communication frame size is 2 or 3 bytes depending if CRC is enabled.
Table 7-19. SPI Frame Size
(1)
FRAME SIZE STATUS CRC INPUT BYTE SEQUENCE OUTPUT BYTE SEQUENCE
no no Write Command: ECHO + 0
Write Command: Command + Data Read Command: Data + 0
2 bytes
yes no Read Command: Command + 0 Write Command: ECHO + STATUS
Read Command: Data + STATUS
no yes Write Command: ECHO+ 0 + CRC
Write Command: Command + Data + CRC Read Command: Data + 0 + CRC
3 bytes
yes yes Read Command: Command + 0 + CRC Write Command: ECHO + STATUS + CRC
Read Command: Data + STATUS + CRC

(1) ECHO is the previous frame register-data byte of the write command echoed to the next frame
7.5.4.1 Write Register Command
The write register command writes register data. The write register operation is performed in one frame. The
first byte of the command is the base value (80h) added to the 7-bit register address. The second byte of the
command is the register data. When the address verification is enabled when out of range address occurs, the
write operation is rejected and the ADDR_ERR flag is set in the STATUS byte. The register data format is MSB
first.
Figure 7-46 shows an example of writing register data with STATUS and CRC disabled, resulting in a two-byte
command operation. If the previous operation was a write register command, the first output byte is the echo
of the previously written register data. Otherwise, the first output byte is the register data from the register read
operation.

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8 16

SCLK

SDI 80h + Address[6:0] Register data

Previous command
SDO 00h
dependent

Figure 7-46. Write Register Data (STATUS and CRC Disabled)

Figure 7-47 shows an example of a write register operation with STATUS and CRC enabled. The frame is three
bytes long because CRC is enabled. If the previous operation was a write register command, the first output
byte is the echo of the previously written register data. If a CRC or out-of-range address error occurred in the
previous frame, the write operation is rejected. The echo byte is then inverted, and the SPI_FLAG bit is set in the
STATUS byte. Further register write operations are blocked until the SPI_FLAG is reset by writing 1b to clear. If
the previous operation is a register read, the first output byte is the register data.

8 16 24

SCLK

SDI 80h + Address[6:0] Register data CRC In

Previous command
SDO STATUS CRC Out
dependent

Figure 7-47. Write Register Data (STATUS and CRC Enabled)

7.5.4.2 Read Register Command

The read register command reads register data. The command follows an off-frame protocol where the read
command is sent in one frame and the ADC responds with register data in the next frame. The first byte of the
command is 00h plus the 7-bit register address. The second byte is unused. The response to a register address
outside the valid range is 00h and if the SPI address range verification is enabled, the ADDR_ERR flag is set in
the STATUS byte. The register data format is MSB first. Full duplex operation is possible by shifting in the next
command while reading the current register data.
Figure 7-48 shows an example of reading register data with the STATUS and CRC bytes disabled. Frame 1 is
the command frame and frame 2 is the data response frame. The frames are delimited by taking CS high. In this
example, the length of the response frame is two bytes long because CRC is disabled. Optionally, short-cycle
the response frame after the register data is read by taking CS high. A read from an invalid register returns zero
for register data.

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Frame 1 Frame 2
CS

8 16 8 16

SCLK

SDI 00h + Address[6:0] Arbitrary Next operation Dependent

Previous command
SDO 00h Reg data 00h
dependent

Figure 7-48. Read Register Data (STATUS and CRC Disabled)

Figure 7-49 shows an example of reading register data with STATUS and CRC enabled. The length of the
frames are three bytes because CRC is enabled. The value of the second command byte is arbitrary, but is
used with the first command byte to determine the CRC In value. The register data byte and the STATUS byte
determine the CRC Out value.
If a CRC error occurred during the register read command, the SPI_ERR flag is set in STATUS. If an out-of-
range address error occurred during the register read command, the register response data (Reg data) is zero
and the ADDR_ERR flag is set in STATUS. In both cases, future reads are processed regardless whether error
flags set or cleared.
Frame 1 Frame 2
CS

8 16 24 8 16 24

SCLK

SDI 00h + Address[6:0] Arbitrary CRC In Next operation Dependent CRC In

Previous command
SDO STATUS CRC Out Reg data STATUS CRC Out
dependent

Figure 7-49. Read Register Data (STATUS and CRC Enabled)

7.5.5 SPI Daisy-Chain

The SPI supports daisy-chaining to connect multiple devices. For daisy-chain operation, connect the SDO pins
to the SDI pins of the following devices. There is no special programming required, simply apply additional shift
clocks to extend the frame length to access all devices in the chain. To input data, first shift in the data intended
for the last device in the chain. The devices interpret the last two or three bytes of data prior to taking CS high
(three bytes if CRC is enabled). Data is shifted out from the last device in the chain followed by data from the
first device in the chain.
Figure 7-50 shows a two-device, daisy-chain connection and Figure 7-51 shows the data format for a register
write commands for each device. The Data Out line of the controller connects to ADC (1) SDI and ADC (2) SDO
connects to the Data In line of the controller. ADC (1) input data is shifted out on SDO to drive the ADC (2) SDI.
The shift operation continues until the last device in the chain is reached. The SPI frame ends when CS is taken
high, at which time the data shifted in to each device are interpreted. The second frame shifts out the register
data from both devices through the ADC (2) SDO pin.

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IOVDD IOVDD

ADC (2) ADC (1) SPI Controller

SDO SDI SDO SDI Data Out

CS CS Chip Select

SCLK SCLK SCLK

Data In

Figure 7-50. SPI Daisy-Chain

ADC (2) ADC (1)

ADC (1) SDI Write Reg Cmd. Write Reg Cmd.

ADC (2) ADC (1)

ADC (2) SD0 Don’t Care Don’t Care
Reg Data Reg Data

SCLK

32 total SCLK (16-bit frames with CRC disabled) 32 total SCLK (16-frames with CRC disabled)

Figure 7-51. SPI Daisy-Chain Register Write Data Format

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8 Register Map
Table 8-1 lists the register memory map of the ADS127L14 and ADS127L18. Memory addresses 02h to 10h are
common programming to all device channels. Addresses 11h through 30h apply to device channels 0 through
3. Addresses 31h through 50h apply to device channels 4 through 7. Unlisted register addresses are not to be
written to.
Table 8-1. Register Map Summary
Address Register Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00h DEV_ID xxh DEV_ID[7:0]
01h REV_ID xxh REV_ID[7:0]
02h STATUS 60h RESERVED ALV_FLAG POR_FLAG SPI_ERR REG_ERR ADC_ERR ADDR_ERR SCLK_ERR
03h CLK_CNT 00h CLK_CNT[7:0]
04h GPIO_RD 00h GPIO_RD[7:0]
05h CRC_MSB 00h CRC_MSB[7:0]
06h CRC_LSB 00h CRC_LSB[7:0]
07h CONTROL 00h RESET[5:0] START STOP
08h GEN_CFG1 00h RESERVED DELAY[2:0] VCM REFP_BUF REF_RNG
09h GEN_CFG2 04h AVG_MODE[1:0] RESERVED START_MODE[1:0] SPEED_MODE[1:0] STBY_MODE
0Ah GEN_CFG3 80h OUT_DRV DATA CLK_CNT_EN SPI_STAT_EN SPI_ADDR_EN SCLK_CNT_EN SPI_CRC_EN REG_CRC_EN
0Bh DP_CFG1 20h DP_CRC_EN DP_STAT_EN DP_TDM[1:0] RESERVED DP_DAISY RESERVED
0Ch DP_CFG2 00h RESERVED DCLK_DIV[1:0] DOUT_DLY[4:0]
0Dh CLK_CFG 00h RESERVED CLK_SEL CLK_DIV[2:0]
0Eh GPIO_WR 00h GPIO_WR[7:0]
0Fh GPIO_DIR 00h GPIO_DIR[7:0]
10h GPIO_EN 00h GPIO_EN[7:0]
11h CH0_CFG1 00h RESERVED CH0_MUX[2:0] CH0_INP_RNG CH0_EX_RNG CH0_BUFN CH0_BUFP
12h CH0_CFG2 00h RESERVED CH0_PWDN CH0_FLTR[4:0]
13h CH0_OFS_MSB 00h CH0_OFFSET_MSB[7:0]
14h CH0_OFS_MID 00h CH0_OFFSET_MID[7:0]
15h CH0_OFS_LSB 00h CH0_OFFSET_LSB[7:0]
16h CH0_GAN_MSB 40h CH0_GAIN_MSB[7:0]
17h CH0_GAN_MID 00h CH0_GAIN_MID[7:0]
18h CH0_GAN_LSB 00h CH0_GAIN_LSB[7:0]
19h CH1_CFG1 00h RESERVED CH1_MUX[2:0] CH1_INP_RNG CH1_EX_RNG CH1_BUFN CH1_BUFP
1Ah CH1_CFG2 00h RESERVED CH1_PWDN CH1_FLTR[4:0]
1Bh CH1_OFS_MSB 00h CH1_OFFSET_MSB[7:0]
1Ch CH1_OFS_MID 00h CH1_OFFSET_MID[7:0]
1Dh CH1_OFS_LSB 00h CH1_OFFSET_LSB[7:0]
1Eh CH1_GAN_MSB 40h CH1_GAIN_MSB[7:0]
1Fh CH1_GAN_MID 00h CH1_GAIN_MID[7:0]
20h CH1_GAN_LSB 00h CH1_GAIN_LSB[7:0]
21h CH2_CFG1 00h RESERVED CH2_MUX[2:0] CH2_INP_RNG CH2_EX_RNG CH2_BUFN CH2_BUFP
22h CH2_CFG2 00h RESERVED CH2_PWDN CH2_FLTR[4:0]
23h CH2_OFS_MSB 00h CH2_OFFSET_MSB[7:0]
24h CH0_OFS_MID 00h CH2_OFFSET_MID[7:0]
25h CH2_OFS_LSB 00h CH2_OFFSET_LSB[7:0]
26h CH2_GAN_MSB 40h CH2_GAIN_MSB[7:0]
27h CH2_GAN_MID 00h CH2_GAIN_MID[7:0]
28h CH2_GAN_LSB 00h CH2_GAIN_LSB[7:0]
29h CH3_CFG1 00h RESERVED CH3_MUX[2:0] CH3_INP_RNG CH3_EX_RNG CH3_BUFN CH3_BUFP
2Ah CH3_CFG2 00h RESERVED CH3_PWDN CH3_FLTR[4:0]
2Bh CH3_OFS_MSB 00h CH3_OFFSET_MSB[7:0]
2Ch CH3_OFS_MID 00h CH3_OFFSET_MID[7:0]
2Dh CH3_OFS_LSB 00h CH3_OFFSET_LSB[7:0]
2Eh CH3_GAN_MSB 40h CH3_GAIN_MSB[7:0]
2Fh CH3_GAN_MID 00h CH3_GAIN_MID[7:0]

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Table 8-1. Register Map Summary (continued)

Address Register Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
30h CH3_GAN_LSB 00h CH3_GAIN_LSB[7:0]
31h CH4_CFG1 00h RESERVED CH4_MUX[2:0] CH4_INP_RNG CH4_EX_RNG CH4_BUFN CH4_BUFP
32h CH4_CFG2 00h RESERVED CH4_PWDN CH4_FLTR[4:0]
33h CH4_OFS_MSB 00h CH4_OFFSET_MSB[7:0]
34h CH4_OFS_MID 00h CH4_OFFSET_MID[7:0]
35h CH4_OFS_LSB 00h CH4_OFFSET_LSB[7:0]
36h CH4_GAN_MSB 40h CH4_GAIN_MSB[7:0]
37h CH4_GAN_MID 00h CH4_GAIN_MID[7:0]
38h CH4_GAN_LSB 00h CH4_GAIN_LSB[7:0]
39h CH5_CFG1 00h RESERVED CH5_MUX[2:0] CH5_INP_RNG CH5_EX_RNG CH5_BUFN CH5_BUFP
3Ah CH5_CFG2 00h RESERVED CH5_PWDN CH5_FLTR[4:0]
3Bh CH5_OFS_MSB 00h CH5_OFFSET_MSB[7:0]
3Ch CH5_OFS_MID 00h CH5_OFFSET_MID[7:0]
3Dh CH5_OFS_LSB 00h CH5_OFFSET_LSB[7:0]
3Eh CH5_GAN_MSB 40h CH5_GAIN_MSB[7:0]
3Fh CH5_GAN_MID 00h CH5_GAIN_MID[7:0]
40h CH5_GAN_LSB 00h CH5_GAIN_LSB[7:0]
41h CH6_CFG1 00h RESERVED CH6_MUX[2:0] CH6_INP_RNG CH6_EX_RNG CH6_BUFN CH6_BUFP
42h CH6_CFG2 00h RESERVED CH6_PWDN CH6_FLTR[4:0]
43h CH6_OFS_MSB 00h CH6_OFFSET_MSB[7:0]
44h CH6_OFS_MID 00h CH6_OFFSET_MID[7:0]
45h CH6_OFS_LSB 00h CH6_OFFSET_LSB[7:0]
46h CH6_GAN_MSB 40h CH6_GAIN_MSB[7:0]
47h CH6_GAN_MID 00h CH6_GAIN_MID[7:0]
48h CH6_GAN_LSB 00h CH6_GAIN_LSB[7:0]
49h CH7_CFG1 00h RESERVED CH7_MUX[2:0] CH7_INP_RNG CH7_EX_RNG CH7_BUFN CH7_BUFP
4Ah CH7_CFG2 00h RESERVED CH7_PWDN CH7_FLTR[4:0]
4Bh CH7_OFS_MSB 00h CH7_OFFSET_MSB[7:0]
4Ch CH7_OFS_MID 00h CH7_OFFSET_MID[7:0]
4Dh CH7_OFS_LSB 00h CH7_OFFSET_LSB[7:0]
4Eh CH7_GAN_MSB 40h CH7_GAIN_MSB[7:0]
4Fh CH7_GAN_MID 00h CH7_GAIN_MID[7:0]
50h CH7_GAN_LSB 00h CH7_GAIN_LSB[7:0]

Table 8-2 shows the access-type codes in this section.

Table 8-2. Register Access-Type Codes
Access Type Code Description
R R Read only
W W Write only
W1C W1C Write 1 to clear
R/W R/W Read or write

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8.1 DEV_ID Register (Address = 00h) [Reset = 04h or 06h]

DEV_ID is described in Table 8-3.
Table 8-3. DEV_ID Register Description
Bit Field Type Reset Description
7-0 DEV_ID[7:0] R 00000xx0b Device identification number.
00000100b = ADS127L14
00000110b = ADS127L18

8.2 REV_ID Register (Address = 01h) [Reset = xxh]

REV_ID is described in Table 8-4.
Table 8-4. REV_ID Register Description
Bit Field Type Reset Description
7-0 REV_ID[7:0] R xxxxxxxxb Die revision number.
The die revision number is subject to change during device
production without prior notice.

8.3 STATUS Register (Address = 02h) [Reset = 60h]

STATUS is shown in Figure 8-1 and described in Table 8-5.
Figure 8-1. STATUS Register
7 6 5 4 3 2 1 0
RESERVED ALV_FLAG POR_FLAG SPI_ERR REG_ERR ADC_ERR ADDR_ERR SCLK_ERR
R-0b R/W1C-1b R/W1C-1b R/W1C-0b R/W1C-0b R-0b R/W1C-0b R/W1C-0b

Table 8-5. STATUS Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R 0b Reserved
6 ALV_FLAG R/W1C 1b Analog supply low-voltage flag.
This bit indicates a low-voltage condition of the analog power
supplies. Write 1b to reset the flag to detect the next occurrence
of a low-voltage condition.
0b = No event from when flag last cleared
1b = Analog power supply low-voltage detected
5 POR_FLAG R/W1C 1b Power-on reset flag.
This bit indicates the device was reset at power-on or brownout of
the IOVDD power supply or by a user reset operation. Write 1b to
reset the flag to detect the next occurrence of a device reset.
0b = No reset from when flag last cleared
1b = Reset occurred
4 SPI_ERR R/W1C 0b SPI CRC error.
This bit indicates an SPI CRC error was detected. Except for
this register, register write operations are blocked when the bit is
set. Clear the bit by writing 1b. CRC validation is enabled by the
SPI_CRC_EN bit.
0b = No error
1b = SPI CRC error
3 REG_ERR R/W1C 0b Register map CRC error.
This bit indicates a register map CRC error. The user writes a 16-bit
CRC value to the CRC_MSB and CRC_LSB registers, calculated
over addresses 08h to 50h for both devices. Clear the error by
correcting the CRC value, then write 1b to clear the bit. The register
map CRC validation is enabled by the REG_CRC_EN register bit.
0b = No error
1b = Register map CRC error

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Table 8-5. STATUS Register Field Descriptions (continued)

Bit Field Type Reset Description
2 ADC_ERR R 0b ADC error.
This bit indicates an internal ADC error. Reset the device or perform
a power cycle to clear the error.
0b = No error
1b = ADC error
1 ADDR_ERR R/W1C 0b SPI register address error.
This bit indicates an invalid register read or write address. The valid
address range is 00h to 50h for both devices. Except for the STATUS
register, register write operations are blocked when the error is set.
Clear the error by writing 1b. Address error check is enabled by
setting SPI_ADDR_EN = 1b.
0b = No error
1b = Invalid register read/write address
0 SCLK_ERR R/W1C 0b SPI SCLK count error.
This bit indicates the number of SCLK cycles was not a multiple of
eight. Except for the STATUS register, register write operations are
blocked when the flag is set. Clear the error by writing 1b. SCLK
count error check is enabled by setting SCLK_CNT_EN = 1b.
0b = No error
1b = Number of SCLK clock cycles is not a multiple of eight

8.4 CLK_CNT Register (Address = 03h) [Reset = 00h]

CLK_CNT is described in Table 8-6.
Table 8-6. CLK_CNT Register Description
Bit Field Type Reset Description
7-0 CLK_CNT[7:0] R 00000000b Clock count value register.
This register is a counter of the ADC clock. The counter increments
at a rate of fCLK / 32, divided by the CLK_DIV[2:0] setting. Read
the register at known intervals to verify the ADC clock frequency.
The clock count is enabled by the CLK_CNT_EN register bit. When
enabled, the counter value resets to 00h. When disabled, the count
value is 00h.

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8.5 GPIO_RD Register (Address = 04h) [Reset = 00h]

GPIO_RD is shown in Figure 8-2 and described in Table 8-7.
Figure 8-2. GPIO_RD Register
7 6 5 4 3 2 1 0
GPIO_RD7 GPIO_RD6 GPIO_RD5 GPIO_RD4 GPIO_RD3 GPIO_RD2 GPIO_RD1 GPIO_RD0
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b

Table 8-7. GPIO_RD Register Field Descriptions

Bit Field Type Reset Description
7-0 GPIO_RD[7:0] R 00000000b GPIO read data register.
These bits are the read values of GPIO. If the GPIO is programmed
as an output, the value returned is from the GPIO pin.

8.6 CRC_MSB, CRC_LSB Registers (Addresses = 05h, 06h) [Reset = 00h]

CRC registers described in Table 8-8.
Table 8-8. CRC Registers Description
Name Address Type Reset Description
CRC_MSB 5h R/W 00h Two-byte register map CRC value.
CRC_LSB 6h R/W 00h Write a 16-bit CRC value, computed over the register range 08h to
50h. The register map CRC check is enabled by the REG_CRC_EN
bit. The CRC error is reported to the REG_ERR bit of the STATUS
register.

8.7 CONTROL Register (Address = 07h) [Reset = 00h]

CONTROL is shown in Figure 8-3 and described in Table 8-9.
Figure 8-3. CONTROL Register
7 6 5 4 3 2 1 0
RESET[5:0] START STOP
R/W-000000b R/W-0b R/W-0b

Table 8-9. CONTROL Register Field Descriptions

Bit Field Type Reset Description
7-2 RESET[5:0] R/W 000000b Software reset.
Write the value of 010110b to reset the ADC. Make sure the START
or STOP bits are also 0b in the same write operation. These bits
self-clear and always read 000000b.
1 START R/W 0b START conversions.
Start channel conversions by writing 1b. This bit also restarts an
ongoing conversion. Conversions continue until 1b is written to the
STOP bit. This bit self-clears after written, therefore always reads 0b.
This bit is not functional in synchronized control mode.
0b = No operation
1b = Start or restart conversions
0 STOP R/W 0b Stop conversions.
Stop channel conversions by writing 1b. This bit self-clears after
written, therefore always reads 0b. This bit is not functional in
synchronized control mode.
0b = No operation
1b = Stop conversions on all channels

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8.8 GEN_CFG1 Register (Address = 08h) [Reset = 00h]

GEN_CFG1 is shown in Figure 8-4 and described in Table 8-10.
Figure 8-4. GEN_CFG1 Register
7 6 5 4 3 2 1
RESERVED DELAY[2:0] VCM REFP_BUF REF_RNG
R-00b R/W-000b R/W-0b R/W-0b R/W-0b

Table 8-10. GEN_CFG1 Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 00b Reserved.
5-3 DELAY[2:0] R/W 000b Conversion start delay time selection.
Select the conversion start delay time in number of fMOD cycles after
taking START high (or setting the START bit).
000b = 0
001b = 4
010b = 8
011b = 16
100b = 32
101b = 128
110b = 512
111b = 1024
2 VCM R/W 0b Common-mode voltage output enable.
This bit enables the common-mode voltage output of the VCM pin.
The VCM output voltage is equal to (AVDD1 + AVSS) / 2.
0b = Disabled
1b = Enabled
1 REFP_BUF R/W 0b Reference positive buffer enable.
This bit enables the REFP pin precharge buffer.
0b = Disabled
1b = Enabled
0 REF_RNG R/W 0b Voltage reference range selection.
This bit selects the low or high voltage operating range of the
reference input. Program the range to match the actual reference
voltage.
0b = Low-voltage reference range
1b = High-voltage reference range

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8.9 GEN_CFG2 Register (Address = 09h) [Reset = 04h]

GEN_CFG2 is shown in Figure 8-5 and described in Table 8-11.
Figure 8-5. GEN_CFG2 Register
7 6 5 4 3 2 1 0
AVG_MODE[1:0] RESERVED START_MODE[1:0] SPEED_MODE[1:0] STBY_MODE
R/W-00b R-0b R/W-00b R/W-10b R/W-0b

Table 8-11. GEN_CFG2 Register Field Descriptions

Bit Field Type Reset Description
7-6 AVG_MODE[1:0] R/W 00b Channel averaging mode.
Select the number of channels to average. See the Data Averaging
section for more details.
00b = Disabled
01b = Average in groups of two
10b = Average in groups of four
11b = Average in a group of eight (ADS127L18)
5 RESERVED R 0b Reserved
4-3 START_MODE[1:0] R/W 00b START mode selection.
These bits program the functional mode of the START pin. See the
Synchronization section for more details.
00b = Start/stop control mode
01b = Reserved
10b = Synchronized control mode
11b = Reserved
2-1 SPEED_MODE[1:0] R/W 10b Speed mode selection.
These bits program the device speed mode.
00b = Low-speed mode (fCLK = 3.2MHz)
01b = Mid-speed mode (fCLK = 12.8MHz)
10b = High-speed mode (fCLK = 25.6MHz)
11b = Max-speed mode (fCLK = 32.768MHz)
0 STBY_MODE R/W 0b Standby mode selection.
This bit enables the standby mode when conversions are stopped.
Standby mode reduces power consumption compared to the idle
mode.
0b = Idle mode, device fully powered
1b = Standby mode, analog section of channels powered down

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8.10 GEN_CFG3 Register (Address = 0Ah) [Reset = 80h]

GEN_CFG3 is shown in Figure 8-6 and described in Table 8-12.
Figure 8-6. GEN_CFG3 Register
7 6 5 4 3 2 1 0
OUT_DRV DATA CLK_CNT_EN SPI_STAT_EN SPI_ADDR_EN SCLK_CNT_EN SPI_CRC_EN REG_CRC_EN
R/W-1b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 8-12. GEN_CFG3 Register Field Descriptions

Bit Field Type Reset Description
7 OUT_DRV R/W 1b Digital output drive selection.
Select the digital output driver strength. Full drive strength increases
the slew rate of the output signal.
0b = Full-power driver strength
1b = Half-power driver strength
6 DATA R/W 0b Data resolution selection.
This bit selects the output data resolution.
0b = 24-bit resolution
1b = 16-bit resolution
5 CLK_CNT_EN R/W 0b Clock counter enable.
This bit enables the ADC clock counter register.
0b = Disabled
1b = Enabled
4 SPI_STAT_EN R/W 0b SPI status byte output enable.
This bit enables the STATUS register value in the SPI output.
0b = Disabled
1b = Enabled
3 SPI_ADDR_EN R/W 0b SPI register address enable.
This bit enables the SPI address verification. The ADDR_ERR bit
of the STATUS register sets if the register read or write address is
invalid.
0b = Disabled
1b = Enabled
2 SCLK_CNT_EN R/W 0b SCLK count enable.
This bit enables the SPI SCLK count verification. The SCLK_ERR bit
of the STATUS register sets if the number of SCLK cycles in a frame
are not multiples of 8.
0b = Disabled
1b = Enabled
1 SPI_CRC_EN R/W 0b SPI CRC enable.
This bit enables the SPI CRC output byte and the input data CRC
check. The SPI_ERR bit of the STATUS byte sets if the input CRC is
in error. Write 1b to the SPI_ERR bit to clear the error.
0b = Disabled
1b = Enabled
0 REG_CRC_EN R/W 0b Register map CRC enable.
This bit enables the register map CRC error verification. The
REG_ERR bit of the STATUS byte sets if the CRC value is not
correct.
0b = Disabled
1b = Enabled

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8.11 DP_CFG1 Register (Address = 0Bh) [Reset = 20h]

DP_CFG1 is shown in Figure 8-7 and described in Table 8-13.
Figure 8-7. DP_CFG1 Register
7 6 5 4 3 2 1 0
DP_CRC_EN DP_STAT_EN DP_TDM[1:0] RESERVED DP_DAISY RESERVED
R/W-0b R/W-0b R/W-10b R-00b R/W-0b R-0b

Table 8-13. DP_CFG1 Register Field Descriptions

Bit Field Type Reset Description
7 DP_CRC_EN R/W 0b Data port CRC byte enable.
This bit enables the data port CRC byte. A CRC byte is appended to
the end of the channel data.
0b = Disabled
1b = Enabled
6 DP_STAT_EN R/W 0b Data port status byte enable.
This bit enables the data port status byte. The status byte is prefixed
to the beginning of the channel data.
0b = Disabled
1b = Enabled
5-4 DP_TDM[1:0] R/W 10b Data port time division multiplexing (TDM) configuration.
These bits select the number of data lanes. See the Time Division
Multiplexing section for details.
00b = One data lane
01b = One (ADS127L14) / two data lanes (ADS127L18)
10b = Two (ADS127L14) / four data lanes (ADS127L18)
11b = Four (ADS127L14) / eight data lanes (ADS127L18)
3-2 RESERVED R 00b Reserved.
1 DP_DAISY R/W 0b Data port daisy-chain mode.
This bit selects daisy-chain or repeat data modes.
0b = TDM data mode. DINx data are shifted-in and appended to the
original channel data.
1b = Repeat data mode. Original channel data are repeated and
DINx data are ignored.
0 RESERVED R 0b Reserved.

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8.12 DP_CFG2 Register (Address = 0Ch) [Reset = 00h]

DP_CFG2 is shown in Figure 8-8 and described in Table 8-14.
Figure 8-8. DP_CFG2 Register
7 6 5 4 3 2 1 0
RESERVED DCLK_DIV[1:0] DOUT_DLY[4:0]
R-0b R/W-00b R/W-00000b

Table 8-14. DP_CFG2 Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R 0b Reserved
6-5 DCLK_DIV[1:0] R/W 00b Data port DCLK frequency divider.
These bits select the frame-sync DCLK frequency.
00b = Divide by 1
01b = Divide by 2
10b = Divide by 4
11b = Divide by 8
4-0 DOUT_DLY[4:0] R/W 00000b Data port DOUTx delay.
These bits select the delay or advance of the DOUTx signals
relative to the DCLK and FSYNC signals. Positive values advance
the DOUTx signals; negative values delay the DOUTx signals. The
bit weight is approximately 0.3ns. See the Data Port Offset Timing
section for details.

8.13 CLK_CFG Register (Address = 0Dh) [Reset = 00h]

CLK_CFG is shown in Figure 8-9 and described in Table 8-15.
Figure 8-9. CLK_CFG Register
7 6 5 4 3 2 1 0
RESERVED CLK_SEL CLK_DIV[2:0]
R-0000b R/W-0b R/W-000b

Table 8-15. CLK_CFG Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R 0000b Reserved.
3 CLK_SEL R/W 0b ADC clock selection.
This bit selects the internal oscillator or external clock operation.
0b = Internal oscillator
1b = External clock
2-0 CLK_DIV[2:0] R/W 000b ADC clock divider.
These bits select the clock signal divider for both external clock and
internal oscillator.
000b = Divide by 1
001b = Divide by 2
010b = Divide by 3
011b = Divide by 4
100b - 111b = Divide by 8

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8.14 GPIO_WR Register (Address = 0Eh) [Reset = 00h]

GPIO_WR is shown in Figure 8-10 and described in Table 8-16.
Figure 8-10. GPIO_WR Register
7 6 5 4 3 2 1 0
GPIO_WR7 GPIO_WR6 GPIO_WR5 GPIO_WR4 GPIO_WR3 GPIO_WR2 GPIO_WR1 GPIO_WR0
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 8-16. GPIO_WR Register Field Descriptions

Bit Field Type Reset Description
7-0 GPIO_WR[7:0] R/W 00000000b GPIO write data.
This register is the GPIO write data register. Set the direction of the
GPIO pins to output mode to write the value. See the GPIO_RD
register to read GPIO data.
0b = GPIO pin is driven low
1b = GPIO pin is driven high

8.15 GPIO_DIR Register (Address = 0Fh) [Reset = 00h]

GPIO_DIR is shown in Figure 8-11 and described in Table 8-17.
Figure 8-11. GPIO_DIR Register
7 6 5 4 3 2 1 0
GPIO_DIR7 GPIO_DIR6 GPIO_DRI5 GPIO_DIR4 GPIO_DIR3 GPIO_DIR2 GPIO_DIR1 GPIO_DIR0
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 8-17. GPIO_DIR Register Field Descriptions

Bit Field Type Reset Description
7-0 GPIO_DIR[7:0] R/W 00000000b GPIO direction.
This register programs the GPIO direction as inputs or outputs.
0b = The GPIO pin is an output
1b = The GPIO pin is an input

8.16 GPIO_EN Register (Address = 10h) [Reset = 00h]

GPIO_EN is shown in Figure 8-12 and described in Table 8-18.
Figure 8-12. GPIO_EN Register
7 6 5 4 3 2 1 0
GPIO_EN7 GPIO_EN6 GPIO_EN5 GPIO_EN4 GPIO_EN3 GPIO_EN2 GPIO_EN1 GPIO_EN0
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 8-18. GPIO_EN Register Field Descriptions

Bit Field Type Reset Description
7-0 GPIO_EN[7:0] R/W 00000000b GPIO enable.
This register enables the GPIO function for each pin. When enabled,
the GPIO pin function has priority over other pin functions.
0b = GPIO pin is disabled
1b = GPIO pin is enabled

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8.17 CHn_CFG1 Registers (Address = Channel Number × 08h + 11h) [Reset = 00h]
Channel n configuration 1 register addresses are shown in Table 8-19. The register bit map is shown in Figure
8-13 and described in Table 8-20.
Table 8-19. CHn_CFG1 Register Addresses
NAME DESCRIPTION ADDRESS
CH0_CFG1 Channel 0 configuration 1 11h
CH1_CFG1 Channel 1 configuration 1 19h
CH2_CFG1 Channel 2 configuration 1 21h
CH3_CFG1 Channel 3 configuration 1 29h
CH4_CFG1 Channel 4 configuration 1 31h
CH5_CFG1 Channel 5 configuration 1 39h
CH6_CFG1 Channel 6 configuration 1 41h
CH7_CFG1 Channel 7 configuration 1 49h

Figure 8-13. CHn_CFG1 Register

7 6 5 4 3 2 1 0
RESERVED CHn_MUX[2:0] CHn_INP_RNG CHn_EX_RNG CHn_BUFN CHn_BUFP
R-0b R/W-000b R/W-0b R/W-0b R/W-0b R/W-0b

Table 8-20. CHn_CFG1 Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R 0b Reserved
6-4 CHn_MUX[2:0] R/W 000b Channel input multiplexer selection.
These bits select between the signal input or input test modes. See
the Analog Inputs (AINP, AINN) section for details.
000b = Normal input polarity
001b = Reverse input polarity
010b = Offset and noise test: Internal short to mid supply
011b = CMRR test to AINP
100b = CMRR test to AINN
101b = –FS test
110b = +FS test
111b = +FS test
3 CHn_INP_RNG R/W 0b Channel input range selection.
This bit selects the 1x or 2x input range. See the Input Range section
for more details.
0b = 1x input range
1b = 2x input range
2 CHn_EX_RNG R/W 0b Channel extended input range selection.
This bit extends the input range by 25%. See the Input Range
section for more details.
0b = Disabled
1b = Enabled: The FS range is extended by 25%
1 CHn_BUFN R/W 0b Channel analog input negative buffer enable.
This bit enables the channel AINN precharge buffer.
0b = Disabled
1b = Enabled
0 CHn_BUFP R/W 0b Channel analog input positive buffer enable.
This bit enables the channel AINP precharge buffer.
0b = Disabled
1b = Enabled

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8.18 CHn_CFG2 Registers (Address = Channel Number × 08h + 12h) [Reset = 00h]
Channel n configuration 2 register addresses are shown in Table 8-21. The register bit map is shown in Figure
8-14 and described in Table 8-22.
Table 8-21. CHn_CFG2 Register Addresses
NAME REGISTER DESCRIPTION ADDRESS
CH0_CFG2 Channel 0 configuration 2 12h
CH1_CFG2 Channel 1 configuration 2 1Ah
CH2_CFG2 Channel 2 configuration 2 22h
CH3_CFG2 Channel 3 configuration 2 2Ah
CH4_CFG2 Channel 4 configuration 2 32h
CH5_CFG2 Channel 5 configuration 2 3Ah
CH6_CFG2 Channel 6 configuration 2 42h
CH7_CFG2 Channel 7 configuration 2 4Ah

Figure 8-14. CHn_CFG2 Register

7 6 5 4 3 2 1 0
RESERVED CHn_PWDN CHn_FLTR[4:0]
R-00b R/W-0b R/W-00000b

Table 8-22. CHn_CFG2 Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 00b Reserved.
5 CHn_PWDN R/W 0b Channel power-down mode selection.
When set, the ADC channel is powered down. When powered down,
channel data are the last remaining data.
0b = Active
1b = Powered down

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Table 8-22. CHn_CFG2 Register Field Descriptions (continued)

Bit Field Type Reset Description
4-0 CHn_FLTR[4:0] R/W 00000b Channel digital filter and data rate selection.
These bits configure the digital filter and data rate for each channel.
The data rate between channels must be related by power of 2. The
device has five filter configurations: wideband, sinc4, sinc4 + sinc1,
sinc3, and sinc3 + sinc1. See the Digital Filter section for the data
rate corresponding to the OSR.
00000b = Wideband: OSR = 32
00001b = Wideband: OSR = 64
00010b = Wideband: OSR = 128
00011b = Wideband: OSR = 256
00100b = Wideband: OSR = 512
00101b = Wideband: OSR = 1024
00110b = Wideband: OSR = 2048
00111b = Wideband: OSR = 4096
01000b = Sinc4: OSR = 12
01001b = Sinc4: OSR = 16
01010b = Sinc4: OSR = 24
01011b = Sinc4: OSR = 32
01100b = Sinc4: OSR = 64
01101b = Sinc4: OSR = 128
01110b = Sinc4: OSR = 256
01111b = Sinc4: OSR = 512
10000b = Sinc4: OSR = 1024
10001b = Sinc4: OSR = 2048
10010b = Sinc4: OSR = 4096
10011b = Sinc4: OSR = 32 + sinc1: OSR = 2
10100b = Sinc4: OSR = 32 + sinc1: OSR = 4
10101b = Sinc4: OSR = 32 + sinc1: OSR = 10
10110b = Sinc4: OSR = 32 + sinc1: OSR = 20
10111b = Sinc4: OSR = 32 + sinc1: OSR = 40
11000b = Sinc4: OSR = 32 + sinc1: OSR = 100
11001b = Sinc4: OSR = 32 + sinc1: OSR = 200
11010b = Sinc4: OSR = 32 + sinc1: OSR = 400
11011b = Sinc4: OSR = 32 + sinc1: OSR = 1000
11100b = Sinc3: OSR = 26667
11101b = Sinc3: OSR = 32000
11110b = Sinc3: OSR = 32000 + sinc1: OSR = 3
11111b = Sinc3: OSR = 32000 + sinc1: OSR = 5

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8.19 CHn Offset Registers [Reset = 000000h]

Channel n offset registers are described in Table 8-23.
Table 8-23. CHn Offset Registers Description
ADDRESS
NAME TYPE RESET DESCRIPTION
MSB MID LSB
Channel 0 offset 13h 14h 15h
Channel 1 offset 1Bh 1Ch 1Dh
These registers are three-byte offset registers.
Channel 2 offset 23h 24h 25h Three registers form the 24-bit offset calibration word of
Channel 3 offset 2Bh 2Ch 2Dh each channel. The offset value is in two's-complement
R/W 000000h representation and is subtracted from the conversion
Channel 4 offset 33h 34h 35h result. The offset operation precedes the gain operation.
Channel 5 offset 3Bh 3Ch 3Dh In 16-bit mode, conversion data are left-justified to the
24-bit offset value.
Channel 6 offset 43h 44h 45h
Channel 7 offset 4Bh 4Ch 4Dh

8.20 CHn Gain Registers [Reset = 400000h]

Channel n gain registers are described in Table 8-24.
Table 8-24. CHn Gain Registers Description
ADDRESS
NAME TYPE RESET DESCRIPTION
MSB MID LSB
Channel 0 gain 16h 17h 18h
Channel 1 gain 1Eh 1Fh 20h
Channel 2 gain 26h 27h 28h These registers are three-byte gain registers.
Three registers form the 24-bit gain calibration word
Channel 3 gain 2Eh 2Fh 30h of each channel. The gain value is in straight-binary
R/W 400000h
Channel 4 gain 36h 37h 38h representation and is normalized to 400000h for gain
= 1. The conversion data are multiplied by GAIN[23:0] /
Channel 5 gain 3Eh 3Fh 40h 400000h after the offset operation.
Channel 6 gain 46h 47h 48h
Channel 7 gain 4Eh 4Fh 50h

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The performance capability of the ADS127L1x devices is achievable when familiar with the requirements of the
input driver, antialias filter, reference voltage, bypass capacitors, and PCB layout. The following sections provide
design guidelines.
9.1.1 Input Driver
The input precharge buffers reduce the kick-back voltage caused by the ADC sampling capacitor. Reducing the
kick-back improves linearity performance and relaxes the bandwidth requirements of the signal driver. Generally,
the buffers provides the greatest benefit for input driver bandwidths of 10MHz or less. For higher bandwidth
drivers, disabling the precharge buffers is optional to reduce power consumption. However, full-rated THD and
SNR data sheet performance is realized when the buffers are used for most input drivers up to 150MHz.
Slower ADC speed modes operate the modulator at slower clock rates, thus the driver has more time to settle
between modulator input samples. See the related single-channel ADC THP210 and ADS127L11 Performance
application note for details of the THP210 driver performance.
9.1.2 Antialias Filter
Input signals occurring near the modulator sampling rate (fMOD) alias to the pass band resulting in data errors.
When aliased, the errors cannot be removed by post processing. If these signals are present, an analog low-
pass filter at the ADC input removes the out-of-band frequencies to reduce aliasing. The order of the anti-alias
filter depends on the OSR value and the desired level of attenuation. Large values of OSR provide large
frequency ranges between the Nyquist frequency and fMOD for the filter to attenuate the signal. For example, for
OSR = 128, more than two decades of frequency separate fDATA and fMOD. With a corner frequency = fDATA, a
third-order, 60dB per decade filter provides a 120dB alias rejection at fMOD.
9.1.3 Reference Voltage
To meet data sheet performance, a reference voltage with low noise and sufficient drive strength that settles the
sampled reference input is required. Incomplete settling of the reference voltage appears as a gain error to the
system. In extreme cases of poor reference settling, device linearity is affected. The reference precharge buffer
for the positive input significantly reduces the reference input charge leading to low gain error. See the Power
Supply Recommendations section for the reference input bypass capacitor.

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9.2 Typical Application

0.1 F 1 F

R3 THS4551
1k

ADS127L14
C3 220
180pF
ADS127L18
pF
R1 R2 R4 R5 R6
499 499 499 FB- 5 22
PD AINPn
VIN (-) IN+
OUT- One of 4/8
C1 C2 C4 VOCM 2.2nF
OUT+
channels
220pF 330pF 470pF IN- AINNn
VIN (+) FB+ 5 22 220
499 499 499 180pF pF

VCM
0.1 F

5V REF6041
VIN
OUT_F
EN REFP
1µF SS OUT_S REFP
FILT
GND_S GND_F 2.2µF
22µF
120k
REFN
1µF REFN

Figure 9-1. Input Signal Antialias Filter and Reference Voltage

9.2.1 Design Requirements

Figure 9-1 shows an input antialias filter using the THS4551 fully-differential input signal driver. The goal of this
design is an antialias filter at the ADC input to attenuate out-of-band signals at the modulator sample rate (fMOD).
The filter requirement is 90dB attenuation at the fMOD frequency (12.8MHz in high-speed mode) using OSR = 32
(fDATA = 400kHz) in wideband filter mode. The other filter design goals are flat amplitude response and low group
delay error within the pass band of the signal.
Table 9-1 lists the target design values and the actual values achieved in this design.
Table 9-1. Antialias Filter Design Requirements
FILTER PARAMETER TARGET VALUE ACTUAL VALUE
Voltage gain 0dB 0dB
Alias rejection at 12.8MHz 90dB 90dB
–0.1dB frequency 250kHz 260kHz
–3dB frequency 500kHz 550kHz
Pass-band amplitude peaking 20mdB 12mdB
Group delay linearity 0.1μs 0.017μs
Total noise of the filter and ADC (165kHz bandwidth) 12μV 11.8μV

9.2.2 Detailed Design Procedure

The antialias filter consists of a passive first-order input filter, an active second-order filter, and a passive
first-order output filter. The filter is fourth-order overall. The filter design accommodates the worst-case wideband
filter OSR value (32). This worst-case value results in less than two decades of frequency range between
the Nyquist frequency at fDATA and the fMOD frequency. The fourth-order filter provides 90dB roll-off over this
frequency range. The roll-off at fMOD is the key requirement of the filter.

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The THS4551 amplifier is selected for the active filter stage because of the 135MHz gain-bandwidth product and
50ns settling time. The amplifier GBP is sufficient to maintain flat passband response and stable filter roll-off at
12.8MHz. A 10MHz amplifier used with gain has marginal GBP to fully support the required roll-off at the fMOD
frequency.
The design of the active filter section begins with an equal-R assumption to reduce the number of component
values to select. The dc gain of the filter is R3 / (R1 + R2). The 1kΩ resistors are low enough in value to keep
resistor noise and amplifier input current noise from affecting the noise of the ADC.
The 1kΩ input resistor is divided into two 499Ω resistors (R1 and R2) to implement the first-order filter using C1.
The first-order filter is decoupled from the second-order active filter, but shares R1 and R2 to determine each
filter stage corner frequency. The corner frequency is given by C1 and the Thevenin resistance at the terminals
of C1 (RTH = 2 × 250Ω).
Assuming an arbitrary selection for R4 (2 × 499Ω) is used for this design. Calculate the values of the 2 × 180pF
(C3) feedback capacitors and the single 330pF differential capacitor (C2). These values are calculated by the
filter design equations given in the Design Methodology for MFB Filters in ADC Interface Applications application
note. The design inputs are filter fO and filter Q for the multiple-feedback active-filter topology. The differential
capacitor (C4) is not part of the filter design but improves filter phase margin. The 5Ω resistors (R5) isolate the
amplifier outputs from stray capacitance to further improve filter phase margin.
The final RC filter at the ADC inputs serves two purposes. First, the filter provides a fourth pole to the overall
filter response, thereby increasing roll-off. The other purpose of the RC filter at the inputs is a charge reservoir
to filter the sampled input of the ADC. The charge reservoir reduces the instantaneous charge demand of
the amplifier, maintaining low distortion and low gain error that otherwise degrades from incomplete amplifier
settling. The input filter values are 2 × 22Ω and 2.2nF. The 22Ω resistors are outside the THS4551 filter loop to
isolate the amplifier outputs from the 2.2nF capacitor to maintain phase margin.
Low voltage-coefficient C0G capacitors are used everywhere in the signal path for the low distortion properties.
The amplifier gain resistors are 0.1% tolerance to provide best possible THD performance. The ADC VCM
output connection to the amplifier VOCM input pin is optional because the same function is provided by the
amplifier.
See the THS4551 data sheet for additional examples of active filter design and applications.

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9.2.3 Application Curves

The following figures are produced by the TINA-TI™, SPICE-based analog simulation program. Download the
THS4551 SPICE model at the THS4551 product folder.
Figure 9-2 shows the frequency response of the antialias filter and the total response of the antialias filter and
ADC. As shown in this image, the filter provides 90dB stop-band attenuation from the Nyquist frequency to the
12.8MHz fMOD frequency.
Figure 9-3 shows the analog filter group delay. The 0.575μs group delay is small in comparison to the 85μs
group delay of the ADC digital filter (34 / fDATA). The analog filter group delay linearity is 0.017μs, peaking at the
edge of the 165kHz pass band.

0
Antialias filter
To tal response
-25
Amplitude (dB)

-50

-75

-100

-125
1 10 100 1000 10000 100000
Frequency (kHz)

Figure 9-2. Antialias Filter Frequency Response Figure 9-3. Antialias Filter Group Delay

Figure 9-4 shows the noise density of the antialias filter circuit, the noise density of the ADC, and the combined
noise density of the filter and ADC. Noise density is the noise voltage per √Hz of bandwidth plotted versus
frequency.
Figure 9-5 shows the total noise from the 1Hz start frequency up to the ADC final bandwidth. Below 200Hz,
noise is dominated by 1 / f voltage and current noise of the THS4551 amplifier. Above 200Hz, noise is dominated
by ADC noise. The integrated noise of the filter and ADC over the 165kHz bandwidth is 11.8μV, meeting the
12μV target value.

150 20
ADC noise density ADC noise
10
AA filter noise density AA filter noise
125 Combined noise density Combined noise
Noise Density (nV /Hz)

100
To tal Noise (V)

50
0.1

0 0.01
1 10 100 1000 10000 100000 1000000 1 10 100 1000 10000 100000 1000000
Frequency (Hz) Frequency (Hz)

Figure 9-4. Noise Density Figure 9-5. Total Noise

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9.3 Power Supply Recommendations

The ADCs have three analog power supplies and one digital power supply. Power-supply voltages AVDD1 and
AVSS configure the channels for unipolar or bipolar signal types. Example configurations are AVDD1 = 5V and
AVSS = DGND for unipolar signals, and AVDD1 = 2.5V and AVSS = –2.5V for bipolar signals. The AVDD2
power-supply voltage is with respect to AVSS and the IOVDD power-supply voltage is with respect to DGND.
The specified range of the power supplies are listed in the Recommended Operating Conditions.
Table 9-2 shows power-supply configuration options. The power-supply voltage values shown are nominal.
Table 9-2. Power-Supply Configurations (Nominal)
SPEED MODE CONFIGURATION AVDD1 – DGND AVSS – DGND AVDD2 – DGND IOVDD – DGND
Unipolar 5V 0V 1.8V to 5V 1.8V
Max speed
Bipolar 2.5V –2.5V 0V to 2.5V 1.8V
Unipolar 5V 0V 1.8V to 5V 1.8V
High speed
Bipolar 2.5V –2.5V 0V to 2.5V 1.8V
Unipolar 3.3V to 5V 0V 1.8V to 5V 1.8V
Mid speed
Bipolar 1.65V to 2.5V –1.65V to –2.5V 0.15V to 2.5V 1.8V
Unipolar 3V to 5V 0V 1.8V to 5V 1.8V
Low speed
Bipolar 1.5V to 2.5V –1.5V to –2.5V 0.3V to 2.5V 1.8V

The power supplies do not require special sequencing and are able to be powered up in any order and are
tolerant to slow or fast ramp rates. However, make sure no analog or digital input exceeds the respective AVDD1
and AVSS (analog) or IOVDD (digital) power-supply voltages. An internal reset is performed after the IOVDD
power-supply voltage is applied.
Table 9-3 shows the recommended bypass capacitors for the devices. All capacitors are minimum 6.3V, X7R
ceramic dielectric. In addition to using a single ground plane for DGND, best performance is achieved with power
planes for IOVDD, AVDD1, AVDD2, and AVSS. If AVSS = 0V for unipolar supply operation, use one ground
plane for AVSS and DGND. If AVSS = -2.5V for bipolar supply operation, bypass AVSS and AVDD1 to the
DGND plane.
For both the ADS127L14 and the ADS127L18, AVSS pin numbers 45 and 51 do not require bypass capacitors.
In addition, the ADS127L14 AVSS pin numbers 29 through 36 do not require bypass capacitors. Tie these pins
to the AVSS plane.
Table 9-3. Bypass Capacitors
POSITIVE PINS NEGATIVE PINS CAPACITOR (X7R)
IOVDD (pins 18, 19 tied together) DGND (pin17) 2.2uF
CAPD (pin 20) DGND (pin 21) 2.2uF
AVDD1 (pins 23, 24 tied together) AVSS (pin 22) 2.2uF
AVDD2 (pin 25) AVSS (pin 22) 2.2uF
CAPA (pins 26, 27 tied together) AVSS (pin 28) 10uF
REFP (pins 49, 50 tied together) REFN (pins 47, 48 tied together) 2.2µF (REFP buffer on), 10uF (REFP buffer off)
REFN (pins 47, 48 tied together) AVSS (pins 45, 51 tied together) 2.2µF (only required if REFN is not tied to ground)

9.3.1 AVDD1 and AVSS

AVDD1 and AVSS are analog supply voltages that power the precharge buffers and the modulator sampling
switches. Configure the ADC for bipolar operation (such as ±2.5V power supplies), or for unipolar operation
(such as AVDD1 = 5V and AVSS = DGND). The mid- and low-speed operating modes offer the option of
reducing AVDD1. See the Recommended Operating Conditions section for details.

Product Folder Links: ADS127L14 ADS127L18

ADS127L14, ADS127L18
www.ti.com SBASAM0B – MARCH 2024 – REVISED NOVEMBER 2024

9.3.2 AVDD2
AVDD2 is an analog supply voltage that powers the modulator core. To simplify the number of power supplies,
connect AVDD2 to AVDD1, or operate AVDD2 at a reduced voltage to lower power consumption.
9.3.3 IOVDD
IOVDD is the digital power-supply voltage for the device I/O pins. IOVDD is also internally regulated to power the
digital core. The voltage level of IOVDD is independent of the analog supply configuration.
9.3.4 CAPA and CAPD
CAPA and CAPD are the output voltages of the internal voltage regulators. These voltages are for internal
operation and are not designed to drive external loads. These pins require external bypass capacitors as shown
in Table 9-3.
9.4 Layout
9.4.1 Layout Guidelines
To achieve data sheet performance, use a minimum four-layer PCB board with the inner layers dedicated
to ground and power planes. Use one or more power planes to route the power supplies to the ADC. Best
performance is achieved by combining the analog and digital grounds in a single, unbroken ground plane. In
some layout geometries, however, separate analog and digital grounds are necessary to direct digital currents
away from the analog ground. Noisy digital currents include pulsing LED indicators, relays, and so on. In
this case, consider separate ground return paths for these digital currents. When separate analog and digital
grounds are used, join the grounds at the ADC.
The top and bottom layers route the analog and digital signals. Route the input signal as a matched differential
pair throughout the signal chain to reduce differential noise coupling. Avoid crossing or adjacent placement of
digital signals with the analog signals. Separate the ADC clock input signal from SPI, frame-sync signals and
other clock signals to avoid coupling which can cause jitter.
Place the voltage reference close to the ADC. Orient the reference such that the reference ground pin is close
to the ADC REFN pins with a direct connection from the ADC REFN to the reference ground pin. Place the
reference input capacitor close to the ADC reference input pins. Place the signal input bypass capacitors close
to the ADC inputs. Optimize the location of the differential input capacitor over the location of the capacitors from
each input to ground.
Figure 9-6 shows an ADS127L18 layout example with SPI connections. The analog input differential capacitors
are 2.2nF C0G dielectric. The analog input common-mode capacitors are 220pF C0G dielectric. The differential
input capacitors are placed close to the analog input pins. The input drivers are shown on the top and bottom
sides of the PCB to conserve space.
10Ω resistors are used in series with the digital outputs to augment the 40Ω driver output impedance to reduce
the potential for ringing in the PCB trace. Pull-down resistors are used for the DOUTx/DINx/GPIOx pins (pins 10
through 13) to prevent the pins from floating in the event they are programmed for inputs.

Product Folder Links: ADS127L14 ADS127L18
ADS127L14, ADS127L18
SBASAM0B – MARCH 2024 – REVISED NOVEMBER 2024 www.ti.com

9.4.2 Layout Example

AVDD1
AVDD2 IOVDD
AIN7
+

– CLKIN

AIN6
+
FSYNC
–
DCLK
AIN5 DOUT7/DIN0/GPIO7
+
DOUT6/DIN1/GPIO6
–
DOUT5/DIN2/GPIO5
AIN4 DOUT4/DIN3/GPIO4
+ DOUT3/GPIO3
– DOUT2/GPIO2
AIN3 DOUT1
+ DOUT0
–

ERROR
AIN2
+ SDO
– SDI

AIN1 SCLK
+ CS
– MODE pin = IOVDD for SPI mode
START
AIN0 RESET
+
- +
– Reference
Inputs
VCM output

Figure 9-6. ADS127L18 PCB Layout Example

See the QFN and SON PCB Attachment application note for details of attaching the VQFN package to the
printed circuit board.

Product Folder Links: ADS127L14 ADS127L18

ADS127L14, ADS127L18
www.ti.com SBASAM0B – MARCH 2024 – REVISED NOVEMBER 2024

10 Device and Documentation Support

10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, THP210 and ADS127L11 Performance application note
• Texas Instruments, ADS127L11 CRC Calculator
• Texas Instruments, IEPE Vibration Sensor Interface Reference Design for PLC Analog Input design guide
• Texas Instruments, THS4551 Low-Noise, Precision, 150-MHz, Fully Differential Amplifier data sheet
• Texas Instruments, REF60xx High-Precision Voltage Reference with Integrated ADC Drive Buffer data sheet
• Texas Instruments, Design Methodology for MFB Filters in ADC Interface Applications application note
• Texas Instruments, QFN and SON PCB Attachment application note
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2024) to Revision B (November 2024) Page
• Changed document status from Advance Information to Production Data.........................................................1

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: ADS127L14 ADS127L18
PACKAGE OPTION ADDENDUM

www.ti.com 28-Nov-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ADS127L18IRSHR ACTIVE VQFN RSH 56 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS127L18 Samples

ADS127L18IRSHT ACTIVE VQFN RSH 56 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS127L18 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 28-Nov-2024

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 29-Nov-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS127L18IRSHR VQFN RSH 56 2500 330.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2
ADS127L18IRSHT VQFN RSH 56 250 180.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 29-Nov-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS127L18IRSHR VQFN RSH 56 2500 367.0 367.0 35.0
ADS127L18IRSHT VQFN RSH 56 250 210.0 185.0 35.0

Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

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SBASAM0B – MARCH 2024 – REVISED NOVEMBER 2024

ADS127L1x 512kSPS, Quad and Octal, Simultaneous-Sampling, 24-Bit ADCs

Functional Block Diagrams

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS127L14 ADS127L18

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

4 Pin Configuration and Functions

Figure 4-1. ADS127L14 RSH Package, 56-Pin VQFN (Top View)

4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS127L14 ADS127L18

Figure 4-2. ADS127L18 RSH Package, 56-Pin VQFN (Top View)

Table 4-1. Pin Functions

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5

Table 4-1. Pin Functions (continued)

6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS127L14 ADS127L18

Table 4-1. Pin Functions (continued)

(1) I = input, O = output, I/O = bidirectional input-output, P = power, GND = ground.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7

5.2 ESD Ratings

8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS127L14 ADS127L18

5.3 Recommended Operating Conditions

VAINPn, Input buffer off AVSS – 0.05 AVDD1 + 0.05

Differential input voltage 1x input range –VREF VREF

Differential reference voltage Low-reference range 0.5 2.5 2.75

5.4 Thermal Information

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9

5.5 Electrical Characteristics

10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

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5.5 Electrical Characteristics (continued)

fIN = 9.7kHz and 10.3kHz, Second-order terms –120

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11

5.5 Electrical Characteristics (continued)

fIN = 9.7kHz and 10.3kHz, Second-order terms –125 dB

12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: ADS127L14 ADS127L18

5.5 Electrical Characteristics (continued)

fIN = 9.7kHz and 10.3kHz, Second-order terms –125

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13

5.5 Electrical Characteristics (continued)

fIN = 9.7kHz and 10.3kHz, Second-order terms –125 dB

14 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

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5.5 Electrical Characteristics (continued)

REFP and REFN High-speed mode 20

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15

5.5 Electrical Characteristics (continued)

AVDD1, AVSS current One channel 0.9 1.0 mA

Wideband filter High-speed mode 1.6 2.0

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5.5 Electrical Characteristics (continued)

(1) Best-fit method.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17

5.6 Timing Requirements

(1) fCLK is the main ADC clock.

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

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5.7 Switching Characteristics

5.8 Timing Diagrams

Figure 5-1. Clock Timing Requirements

tp(FSDC) tw(DCLKH) tw(DCLKL)

DOUT MSB MSB

Figure 5-2. Frame-Sync Port Switching Characteristics

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19

td(CSSC) tc(SCLK) td(SCCS)

Figure 5-3. SPI Timing Requirements

tp(CSDO) tp(SCDO) tp(CSDOZ)

Figure 5-4. SPI Switching Characteristics

Figure 5-5. START Pin Timing Requirements

Figure 5-6. START Pin Switching Characteristics

20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

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