ADS131M04

SBAS890D – MARCH 2019 – REVISED MAY 2021

ADS131M04 4-Channel, Simultaneously-Sampling, 24-Bit, Delta-Sigma ADC

1 Features 3 Description
• 4 simultaneously sampling differential inputs The ADS131M04 is a four-channel, simultaneously-
• Programmable data rate up to 64 kSPS sampling, 24-bit, delta-sigma (ΔΣ), analog-to-digital
• Programmable gain up to 128 converter (ADC) that offers wide dynamic range, low
• Noise performance: power, and energy-measurement-specific features,
– 102-dB dynamic range at gain = 1, 4 kSPS making the device an excellent fit for energy metering,
– 80-dB dynamic range at gain = 64, 4 kSPS power metrology, and circuit breaker applications. The
• Total harmonic distortion: –100 dB ADC inputs can be directly interfaced to a resistor-
• High-impedance inputs for direct sensor divider network or a power transformer to measure
connection: voltage or to a current transformer, shunt, or a
– Input impedance 330-kΩ for gains of Rogowski coil to measure current.
1, 2, and 4 The individual ADC channels can be independently
– Input impedance ≥ 1-MΩ for gains of configured depending on the sensor input. A low-
8, 16, 32, 64, and 128 noise, programmable gain amplifier (PGA) provides
• Programmable channel-to-channel phase delay gains ranging from 1 to 128 to amplify low-level
calibration: signals. Additionally, this device integrates channel-
– 244-ns resolution, 8.192-MHz fCLKIN to-channel phase calibration and offset and gain
• Current-detect mode allows for extremely low calibration registers to help remove signal-chain
power tamper detection errors.
• Fast startup: first data within 0.5 ms of supply
ramp A low-drift, 1.2-V reference is integrated into the
• Integrated negative charge pump allows input device reducing printed circuit board (PCB) area.
signals below ground Optional cyclic redundancy checks (CRCs) on the
• Crosstalk between channels: –120 dB data input, data output, and register map maintain
• Low-drift internal voltage reference communication integrity.
• Cyclic redundancy check (CRC) on The complete analog front-end (AFE) is offered
communications and register map in a 20-pin TSSOP package or a leadless 20-pin
• 2.7-V to 3.6-V analog and digital supplies WQFN package and is specified over the industrial
• Low power consumption: 3.3 mW at 3-V AVDD temperature range of –40°C to +125°C.
and DVDD
• Packages: 20-pin TSSOP or 20-pin WQFN Device Information(1)
• Operating temperature range: –40°C to +125°C PART NUMBER PACKAGE BODY SIZE (NOM)
TSSOP (20) 6.50 mm × 4.40 mm
2 Applications ADS131M04
WQFN (20) 3.00 mm × 3.00 mm
• Electricity meters: commercial and residential
(1) For all available packages, see the orderable addendum at
• Circuit breakers the end of the data sheet.
• Protection relays
• Power quality meters
AVDD DVDD

• Battery test equipment 1.2-V

Reference

• Battery management systems

AIN0P +
Phase Shift & Gain & Offset
'6 ADC
Digital Filters Calibration
AIN0N ±

SYNC / RESET

AIN1P +
Phase Shift & Gain & Offset
'6 ADC
Digital Filters Calibration CS
AIN1N ±
SCLK
Control &
Serial Interface DIN
DOUT
AIN2P +
Phase Shift & Gain & Offset DRDY
'6 ADC
Digital Filters Calibration
AIN2N ±

Clock
AIN3P + CLKIN
Phase Shift & Gain & Offset Generation
'6 ADC
Digital Filters Calibration
AIN3N ±

AGND DGND

Simplified Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.5 Programming............................................................ 35
2 Applications..................................................................... 1 8.6 ADS131M04 Registers............................................. 45
3 Description.......................................................................1 9 Application and Implementation.................................. 75
4 Revision History.............................................................. 2 9.1 Application Information............................................. 75
5 Pin Configuration and Functions...................................4 9.2 Typical Application.................................................... 83
6 Specifications.................................................................. 5 10 Power Supply Recommendations..............................90
6.1 Absolute Maximum Ratings ....................................... 5 10.1 CAP Pin Behavior................................................... 90
6.2 ESD Ratings .............................................................. 5 10.2 Power-Supply Sequencing......................................90
6.3 Recommended Operating Conditions ........................6 10.3 Power-Supply Decoupling.......................................90
6.4 Thermal Information ...................................................6 11 Layout........................................................................... 91
6.5 Electrical Characteristics ............................................7 11.1 Layout Guidelines................................................... 91
6.6 Timing Requirements ................................................. 9 11.2 Layout Example...................................................... 92
6.7 Switching Characteristics ...........................................9 12 Device and Documentation Support..........................93
6.8 Timing Diagrams....................................................... 10 12.1 Documentation Support.......................................... 93
6.9 Typical Characteristics.............................................. 11 12.2 Receiving Notification of Documentation Updates..93
7 Parameter Measurement Information.......................... 16 12.3 Support Resources................................................. 93
7.1 Noise Measurements................................................ 16 12.4 Trademarks............................................................. 93
8 Detailed Description......................................................17 12.5 Electrostatic Discharge Caution..............................93
8.1 Overview................................................................... 17 12.6 Glossary..................................................................93
8.2 Functional Block Diagram......................................... 17 13 Mechanical, Packaging, and Orderable
8.3 Feature Description...................................................18 Information.................................................................... 93
8.4 Device Functional Modes..........................................29

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (January 2021) to Revision D (May 2021) Page

• Changed maximum data rate from 32 kSPS to 64 kSPS in Features section....................................................1
• Corrected analog input pin numbering in Pin Functions table ........................................................................... 4
• Added footnote for Absolute Maximum Ratings table ........................................................................................5
• Updated maximum data rate for all power modes.............................................................................................. 7
• Changed noise during startup to 1.5mVrms....................................................................................................... 7
• Updated typcial characteristics plots DC CMRR vs AVDD, DC CMRR vs Temperature, Dynamic Range vs
Gain and Input Bias Current vs Gain ............................................................................................................... 11
• Added OSR of 64 to Noise Measurements section ......................................................................................... 16
• Added OSR of 64 to Digital Filter section......................................................................................................... 20
• Added OSR of 64 to SINC3 and SINC3 + SINC1 Filter section.........................................................................22
• Updated description of the test signal derived from the internal reference ......................................................24
• Added OSR of 64 to Channel Phase Calibration section................................................................................. 25
• Added OSR of 64 to Data Ready section......................................................................................................... 35
• Added TBM (Turbo-mode) bit in CLOCK register in Register Map ..................................................................45
• Changed Register Map table............................................................................................................................ 45
• Changed root cause description in Troubleshooting section ........................................................................... 82

Changes from Revision B (June 2020) to Revision C (January 2021) Page

• Added gain of 128 to High impedance inputs bullet........................................................................................... 1
• Changed RUK (WQFN) package from preview to production data.................................................................... 1
• Added thermal pad to RUK pinout and Pin Functions table .............................................................................. 4
• Added Offset Error time drift and Gain Error time drift........................................................................................7
• Changed SPI Timing Diagram and SYNC/RESET Timing Requirements figures............................................ 10
• Added typical characteristics plots and corrected test condition of Typical Characteristics section ................ 11
• Added fMOD equation in the ΔΣ Modulator section............................................................................................20

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• Changed description in SINC3 and SINC3 + SINC1 Filter section.................................................................... 22

• Changed captions for figures in the Digital Filter Characteristic section...........................................................23
• Changed communication cyclic redundancy check (CRC) seed value............................................................ 28
• Added DRDY transitions in Power-Up and Reset section................................................................................ 29
• Moved Fast Startup Behavior section to Device Functional Modes section, and changed values for wait time
delays in text and figures.................................................................................................................................. 30
• Added global-chop mode block diagram, global-chop mode conversion timing diagram, and Equation 9 ......31
• Deleted comments about MOSI, MISO, slave, and master.............................................................................. 35
• Added description for new conversions when reading data in the Data Ready (DRDY) section......................35
• Changed description sentence for each register section..................................................................................45
• Changed Register Map table............................................................................................................................ 45
• Added pullup resistor option for DRDY in the Unused Inputs and Outputs section..........................................75
• Changed Number of phases row in Key System Specifications table.............................................................. 84
• Changed layout example image....................................................................................................................... 92

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5 Pin Configuration and Functions

DGND
AGND

DVDD
AVDD

CAP
AVDD 1 20 DVDD

AGND 2 19 DGND

20

19

18

17

16
AIN0P 3 18 CAP
AIN0P 1 15 CLKIN
AIN0N 4 17 CLKIN
AIN0N 2 14 DIN

Thermal AIN1N 5 16 DIN

AIN1N 3 13 DOUT
Pad
AIN1P 6 15 DOUT
AIN1P 4 12 SCLK

AIN2P 7 14 SCLK
AIN2P 5 11 DRDY
10

AIN2N 8 13 DRDY
6

AIN3N 9 12 CS
AIN2N

AIN3N

AIN3P

SYNC/RESET

CS

AIN3P 10 11 SYNC/RESET
Not to scale

Not to scale

Figure 5-1. RUK Package), 20-Pin WQFN, Top View Figure 5-2. PW Package, 20-Pin TSSOP, Top View

Table 5-1. Pin Functions

PIN
NO. I/O DESCRIPTION(1)
NAME
WQFN TSSOP
AGND 20 2 Supply Analog ground
AIN0N 2 4 Analog input Negative analog input 0
AIN0P 1 3 Analog input Positive analog input 0
AIN1N 3 5 Analog input Negative analog input 1
AIN1P 4 6 Analog input Positive analog input 1
AIN2N 6 8 Analog input Negative analog input 2
AIN2P 5 7 Analog input Positive analog input 2
AIN3N 7 9 Analog input Negative analog input 3
AIN3P 8 10 Analog input Positive analog input 3
AVDD 19 1 Supply Analog supply. Connect a 1-µF capacitor to AGND.
Digital low-dropout (LDO) regulator output.
CAP 16 18 Analog output
Connect a 220-nF capacitor to DGND.
CLKIN 15 17 Digital input Master clock input
CS 10 12 Digital input Chip select; active low
DGND 17 19 Supply Digital ground
DIN 14 16 Digital input Serial data input
DOUT 13 15 Digital output Serial data output
DRDY 11 13 Digital output Data ready; active low
DVDD 18 20 Supply Digital I/O supply. Connect a 1-µF capacitor to DGND.
SCLK 12 14 Digital input Serial data clock
SYNC/RESET 9 11 Digital input Conversion synchronization or system reset; active low
Thermal pad — — Thermal pad; connect to AGND

(1) See the Unused Inputs and Outputs section for details on how to connect unused pins.

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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN MAX UNIT
AVDD to AGND –0.3 3.9 V
AGND to DGND –0.3 0.3 V
Power-supply voltage DVDD to DGND –0.3 3.9 V
DVDD to DGND, CAP tied to DVDD –0.3 2.2 V
CAP to DGND –0.3 2.2 V
Analog input voltage AINxP, AINxN AGND – 1.6 AVDD + 0.3 V
Digital input voltage CS, CLKIN, DIN, SCLK, SYNC/RESET DGND – 0.3 DVDD + 0.3 V
Input current Continuous, all pins except power-supply pins –10 10 mA
Junction, TJ 150
Temperature °C
Storage, Tstg –60 150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
AVDD to AGND, normal operating modes 2.7 3.0 3.6
Analog power supply AVDD to AGND, standby and current-detect modes 2.4 3.0 3.6 V
AGND to DGND –0.3 0 0.3
DVDD to DGND 2.7 3.0 3.6
Digital power supply DVDD to DGND, DVDD shorted to CAP (digital LDO V
1.65 1.8 2
bypassed)
ANALOG INPUTS(1)

VAINxP, Gain = 1, 2, or 4 AGND – 1.3 AVDD

Absolute input voltage V
VAINxN Gain = 8, 16, 32, 64 or 128 AGND – 1.3 AVDD – 1.8
VIN Differential input voltage VIN = VAINxP - VAINxN –VREF / Gain VREF / Gain V
EXTERNAL CLOCK SOURCE
High-resolution mode 0.3 8.192 8.4
fCLKIN External clock frequency Low-power mode 0.3 4.096 4.15 MHz
Very-low-power mode 0.3 2.048 2.08
Duty cycle 40% 50% 60%
DIGITAL INPUTS
Input voltage DGND DVDD V
TEMPERATURE RANGE
TA Operating ambient temperature –40 125 °C

(1) The subscript "x" signifies the channel. For example, the positive analog input to channel 0 is named AIN0P. See the Pin
Configurations and Functions section for the pin names.

6.4 Thermal Information

ADS131M04
THERMAL METRIC(1) RUK (WQFN) PW (TSSOP) UNIT
20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 94.1 94.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 58.1 34.9 °C/W
RθJB Junction-to-board thermal resistance 64.3 46.4 °C/W
ΨJT Junction-to-top characterization parameter 31.8 2.7 °C/W
ΨJB Junction-to-board characterization parameter 58.0 46.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9 N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, all channels enabled, global-chop
mode disabled and gain = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Gain = 1, 2, or 4, VINP = VINN = 0 V,
Input bias current 0.6
IB = (IBP + IBN) / 2
IB µA
Gain = 8, 16, 32, 64 or 128, VINP = VINN =
Input bias current 0.2
0 V, IB = (IBP + IBN) / 2
Gain = 1, 2, or 4 300 kΩ
Zin Differential input impedance
Gain = 8, 16, 32, 64, or 128 ±1 (1) µA/V
ADC CHARACTERISTICS
Resolution 24 Bits
Gain settings 1, 2, 4, 8, 16, 32, 64, 128
High-resolution mode, fCLKIN = 8.192 MHz 250 64k
fDATA Data rate Low-power mode, fCLKIN = 4.096 MHz 125 32k SPS
Very-low-power mode, fCLKIN = 2.048 MHz 62.5 16k
Measured from supplies at 90% to first DRDY
Startup time 0.5 ms
falling edge
ADC PERFORMANCE
ppm of
INL Integral nonlinearity (best fit) 6
FSR
±175
Offset error (input referred) Global-chop mode, channel 0 ±35 µV
Global-chop mode, channels 1-3 ±15
300
Offset drift nV/°C
Global-chop mode 200
1000 hours at 85°C, TSSOP package 4
Offset error time drift μV
1000 hours at 85°C, QFN package 4
Gain error ±0.1%
1
Gain drift ppm/°C
Including internal reference 8.5
1000 hours at 85°C, TSSOP package 400
Gain error time drift ppm
1000 hours at 85°C, QFN package 120
At dc 100
CMRR Common-mode rejection ratio dB
fCM = 50 Hz or 60 Hz 94
AVDD at dc 75
DVDD at dc 88
PSRR Power-supply rejection ratio dB
AVDD supply, fPS = 50 Hz or 60 Hz 78
DVDD supply, fPS = 50 Hz or 60 Hz 85
5.35 µVRMS
Input-referred noise
During fast-startup 1.5 mVRMS
Gain = 1 99 102
dB
Dynamic range Gain = 64 80
All other gain settings See Table 7-1
Crosstalk fIN = 50 Hz or 60 Hz –120 dB
fIN = 50 Hz or 60 Hz, gain = 1, VIN = –0.5 dBFS,
100
normalized
SNR Signal-to-noise ratio dB
fIN = 50 Hz or 60 Hz, gain = 64, VIN = –0.5 dBFS,
79
normalized
fIN = 50 Hz or 60 Hz (up to 50 harmonics),
THD Total harmonic distortion –100 dB
VIN = –0.5 dBFS

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6.5 Electrical Characteristics (continued)

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, all channels enabled, global-chop
mode disabled and gain = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN = 50 Hz or 60 Hz (up to 50 harmonics),
SFDR Spurious-free dynamic range 105 dB
VIN = –0.5 dBFS
INTERNAL VOLTAGE REFERENCE
VREF Internal reference voltage 1.2 V
Accuracy TA = 25°C ±0.1%
Temperature drift 7.5 20 ppm/°C
DIGITAL INPUTS/OUTPUTS
VIL Logic input level, low DGND 0.2 DVDD V
VIH Logic input level, high 0.8 DVDD DVDD V
VOL Logic output level, low IOL = –1 mA 0.2 DVDD V
VOH Logic output level, high IOH = 1 mA 0.8 DVDD V
IIN Input current DGND < VDigital Input < DVDD –1 1 µA
POWER SUPPLY
High-resolution mode 3.5 4.0
Low-power mode 2.0 2.2 mA
IAVDD Analog supply current Very-low-power mode 1.0 1.2
Current-detect mode 0.9 mA
Standby mode 0.3 µA
High-resolution mode 0.4 0.5
Low-power mode 0.2 0.3 mA
IDVDD Digital supply current(2) Very-low-power mode 0.1 0.2
Current-detect mode 0.065 mA
Standby mode 1 µA
High-resolution mode 12
Low-power mode 6.6
mW
PD Power dissipation Very-low-power mode 3.3
Current-detect mode 2.9
Standby mode 3.9 µW

(1) Specified in µA/V because current can flow either into or out of the input pin.
(2) Currents measured with SPI idle.

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6.6 Timing Requirements

over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)
MIN MAX UNIT
1.65 V ≤ DVDD ≤ 2.0 V
tw(CLH) Pulse duration, CLKIN high 49 ns
tw(CLL) Pulse duration, CLKIN low 49 ns
tc(SC) SCLK period 64 ns
tw(SCL) Pulse duration, SCLK low 32 ns
tw(SCH) Pulse duration, SCLK high 32 ns
td(CSSC) Delay time, first SCLK rising edge after CS falling edge 16 ns
td(SCCS) Delay time, CS rising edge after final SCLK falling edge 10 ns
tw(CSH) Pulse duration, CS high 20 ns
tsu(DI) Setup time, DIN valid before SCLK falling egde 5 ns
th(DI) Hold time, DIN valid after SCLK falling edge 8 ns
tw(RSL) Pulse duration, SYNC/RESET low to generate device reset 2048 tCLKIN
tw(SYL) Pulse duration, SYNC/RESET low for synchronization 1 2047 tCLKIN
tsu(SY) Setup time, SYNC/RESET valid before CLKIN rising edge 10 ns
2.7 V ≤ DVDD ≤ 3.6 V
tw(CLL) Pulse duration, CLKIN low 49 ns
tw(CLH) Pulse duration, CLKIN high 49 ns
tc(SC) SCLK period 40 ns
tw(SCL) Pulse duration, SCLK low 20 ns
tw(SCH) Pulse duration, SCLK high 20 ns
td(CSSC) Delay time, first SCLK rising edge after CS falling edge 16 ns
td(SCCS) Delay time, CS rising edge after final SCLK falling edge 10 ns
tw(CSH) Pulse duration, CS high 15 ns
tsu(DI) Setup time, DIN valid before SCLK falling egde 5 ns
th(DI) Hold time, DIN valid after SCLK falling edge 8 ns
tw(RSL) Pulse duration, SYNC/RESET low to generate device reset 2048 tCLKIN
tw(SYL) Pulse duration, SYNC/RESET low for synchronization 1 2047 tCLKIN
tsu(SY) Setup time, SYNC/RESET valid before CLKIN rising edge 10 ns

6.7 Switching Characteristics

over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1.65 V ≤ DVDD ≤ 2.0 V
tp(CSDO) Propagation delay time, CS falling edge to DOUT driven 50 ns
Progapation delay time, SCLK rising edge to valid new
tp(SCDO) 32 ns
DOUT
Propagation delay time, CS rising edge to DOUT high
tp(CSDOZ) 75 ns
impedance
tw(DRH) Pulse duration, DRDY high 4 tCLKIN
tw(DRL) Pulse duration, DRDY low 4 tCLKIN
SPI timeout 32768 tCLKIN
Measured from supplies at 90%
tPOR Power-on-reset time 250 µs
to first DRDY rising edge
tREGACQ Register default acquisition time 5 µs

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6.7 Switching Characteristics (continued)

over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
2.7 V ≤ DVDD ≤ 3.6 V
tp(CSDO) Propagation delay time, CS falling edge to DOUT driven 50 ns
Progapation delay time, SCLK rising edge to valid new
tp(SCDO) 20 ns
DOUT
Propagation delay time, CS rising edge to DOUT high
tp(CSDOZ) 75 ns
impedance
tw(DRH) Pulse duration, DRDY high 4 tCLKIN
tw(DRL) Pulse duration, DRDY low 4 tCLKIN
SPI timeout 32768 tCLKIN
Measured from supplies at 90%
tPOR Power-on-reset time 250 µs
to first DRDY rising edge
tREGACQ Register default acquisition time 5 µs

6.8 Timing Diagrams

tw(CLH) tw(CLL)

CLKIN

tw(DRL)
DRDY
tw(DRH)

CS
§

td(CSSC) tw(SCL) tc(SC) td(SCCS)

tw(CSH)
tw(SCH)
§

SCLK
tsu(DI)
th(DI)
§ §

DIN

tp(CSDO) tp(SCDO) tw(CSDOZ)

§ §

DOUT MSB MSB - 1 LSB + 1 LSB

SPI settings are CPOL = 0 and CPHA = 1. CS transitions must take place when SCLK is low.

Figure 6-1. SPI Timing Diagram

§

CLKIN
tsu(SY)
tw(SYL) tw(RSL)
SYNC/RESET
§

Figure 6-2. SYNC/RESET Timing Requirements

Supplies 90%

tPOR

DRDY

Figure 6-3. Power-On-Reset Timing

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6.9 Typical Characteristics

at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global-chop mode
disabled (unless otherwise noted)

350
HR Mode
LP Mode
300
VLP Mode
Input Bias Current (nA)

250

200

150

100

50

0
8 16 32 64 128
Gain
Gains of 8, 16, 32, 64, and 128 only
Figure 6-4. Input Bias Current vs Gain Figure 6-5. Input Impedance vs Gain
350

Input Offset Voltage (PV) 300

250

200

150

100

50

0
1 2 4 8 16 32 64 128
Gain
30 units, channel 1

Figure 6-6. Startup Time Histogram Figure 6-7. Input Offset Voltage vs Gain

200

180
Input Offset Voltage (PV)

160

140

120

100
-40 -20 0 20 40 60 80 100 120 140
Temperature (qC) ADS1

Includes internal reference error

Figure 6-8. Input Offset Voltage vs Temperature Figure 6-9. Gain Error vs Temperature

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6.9 Typical Characteristics (continued)

at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global-chop mode
disabled (unless otherwise noted)

0 0

-100 -25

-200 -50
Gain Error (ppm)

Gain Error (ppm)

-300 -75

-400 -100

-500 -125

-600 -150
0 200 400 600 800 1000 0 200 400 600 800 1000
Time (Hours) Time (Hours)

18 units, all channels 18 units, all channels

Figure 6-10. Gain Error vs Time (TSSOP Package) Figure 6-11. Gain Error vs Time (WQFN Package)
0 100 300 100

Humidity (%) Humidity (%)

-300 80 150 80
Relative Humidity (%)

Relative Humidity (%)

Gain Error (ppm)

Gain Error (ppm)

-600 60 0 60

-900 40 -150 40

-1200 20 -300 20

-1500 0 -450 0
0 20 40 60 80 0 20 40 60 80
Time (Hours) Time (Hours)

18 units, all channels 18 units, all channels

Figure 6-12. Gain Error vs Humidity (TSSOP Package) Figure 6-13. Gain Error vs Humidity (WQFN Package)
115 114
Gain Gain
1 16 1 4 16 64
110 2 32 110 2 8 32 128
4 64
8 128
105 106
DC CMRR (dB)

DC CMRR (dB)

100 102

95 98

90 94

85 90
-40 -20 0 20 40 60 80 100 120 140 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Temperature AVDD Voltage (V)

Figure 6-14. DC CMRR vs Temperature Figure 6-15. DC CMRR vs AVDD

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6.9 Typical Characteristics (continued)

at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global-chop mode
disabled (unless otherwise noted)

110 110
109 109
108 108

AC AVDD CMRR (dB)

107 107
AVDD CMRR (dB)

106 106
105 105
104 104
103 103
102 102
101 101
100 100
10 20 30 50 70100 200 500 1000 2000 5000 10000 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Frequency (Hz) ADS1
AVDD Voltage (V) ADS1

Figure 6-16. AVDD CMRR vs Frequency Figure 6-17. AC CMRR vs AVDD

120 110

110 105
DC DVDD PSRR (dB)
AVDD DC PSRR (dB)

100 100

90 95

80 90

70 85

60 80
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (qC) Temperature (qC) ADS1

Figure 6-18. DC AVDD PSRR vs Temperature Figure 6-19. DC DVDD PSRR vs Temperature

Gain = 1, inputs shorted Gain = 1, inputs shorted

Figure 6-20. Single Device Noise Histogram at 4 kSPS Figure 6-21. Single Device Noise Histogram at 32 kSPS

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6.9 Typical Characteristics (continued)

at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global-chop mode
disabled (unless otherwise noted)

6.2 110
Channel 0 HR Mode
6 Channel 1 LP Mode
Channel 2 100 VLP Mode
Channel 3

Dynamic Range (dB)

5.8
Noise (PVrms)

90
5.6

5.4 80

5.2
70
5

4.8 60
-40 -20 0 20 40 60 80 100 120 140 1 2 4 8 16 32 64 128
Temperature (qC) Gain ADS1

Figure 6-22. Noise vs Temperature Figure 6-23. Dynamic Range at 4 kSPS vs Gain
110 120
Channel 110
0
1 100
100
2 90
Dynamic Range (dB)

Dynamic Range (dB)

3
80
90 70
OSR
60 128
80 50 256
40 512
1024
30 2048
70 4096
20
8192
10 16384
60 0
1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128
Gain ADS1
Gain ADS1

Figure 6-24. Dynamic Range vs Gain Figure 6-25. Dynamic Range vs Gain
-100 -80
OSR
-105 -85 16384
8192
-110 4096
-90 2048
1024
Crosstalk (dB)

-115
THD (dB)

-95 512
265
-120 128
-100
-125
-105
-130
-110
-135

-140 -115
0 1 2 3 1 2 4 8 16 32 64 128
Channel Gain ADS1

Figure 6-26. Crosstalk vs Channel Figure 6-27. THD vs Gain

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6.9 Typical Characteristics (continued)

at TA = 25°C, AVDD = 3 V, DVDD = 3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global-chop mode
disabled (unless otherwise noted)
-100 5
Channel HR Mode
0 4.5 LP Mode
-102.5 1 VLP Mode
4
2
3

AVDD Current (mA)

-105 3.5
3
THD (dB)

-107.5 2.5
2
-110
1.5

-112.5 1
0.5
-115 0
2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 1 2 4 8 16 32 64 128
AVDD Voltage (V) Gain ADS1

Figure 6-28. THD vs AVDD

Figure 6-29. AVDD Current vs Gain
3.5 400

350
3
300
AVDD Current (mA)

DVDD Current (PA)

2.5
250

2 200

150
1.5
100
1 HR Mode HR Mode
LP Mode 50 LP Mode
VLP Mode VLP Mode
0.5 0
0 1 2 3 4 5 6 7 8 8.5 0 1 2 3 4 5 6 7 8 8.5
Frequency (MHz) Frequency (MHz) ADS1
ADS1

Figure 6-30. AVDD Current vs CLKIN Frequency Figure 6-31. DVDD Current vs CLKIN Frequency

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7 Parameter Measurement Information

7.1 Noise Measurements
Adjust the data rate and gain to optimize the ADS131M04 noise performance. When averaging is increased by
reducing the data rate, noise drops correspondingly. Table 7-1 summarizes the ADS131M04 noise performance
using the 1.2-V internal reference and a 3.0-V analog power supply. The data are representative of typical noise
performance at TA = 25°C when fCLKIN = 8.192 MHz. The modulator clock frequency fMOD = fCLKIN / 2. The data
shown are typical input-referred noise results with the analog inputs shorted together and taking an average of
multiple readings across all channels. A minimum 1 second of consecutive readings are used to calculate the
RMS noise for each reading. Table 7-2 shows the dynamic range and effective resolution calculated from the
noise data. Equation 1 calculates dynamic range. Equation 2 calculates effective resolution. In each case, VREF
corresponds to the internal 1.2-V reference. In global-chop mode, noise is improved by a factor of √ 2.
The noise performance scales with the OSR and gain settings, but is independent from the configured power
mode. Thus, the device exhibits the same noise performance in different power modes when selecting the same
OSR and gain settings. However, the data rate at the OSR settings scales based on the applied clock frequency
for the different power modes.

§ VREF ·
Dynamic Range = 20 u log ¨ ¸¸
¨ 2 u Gain u V
© RMS ¹ (1)

§ 2 u VREF ·
Effective Resolution = log2 ¨ ¸
© Gain u VRMS ¹ (2)
Table 7-1. Noise (µVRMS) at TA = 25°C
DATA RATE (kSPS), GAIN
OSR
fCLKIN = 8.192 MHz 1 2 4 8 16 32 64 128
16384 0.25 1.90 1.69 1.56 0.95 0.64 0.42 0.42 0.42
8192 0.5 2.39 2.13 2.13 1.29 0.86 0.57 0.57 0.57
4096 1 3.38 2.99 2.88 1.74 1.17 0.77 0.77 0.77
2048 2 4.25 3.91 3.79 2.27 1.52 1.00 1.00 1.00
1024 4 5.35 4.68 4.52 2.70 1.82 1.20 1.20 1.20
512 8 7.56 6.62 6.37 3.82 2.55 1.69 1.69 1.69
256 16 10.68 9.56 9.09 5.42 3.63 2.39 2.39 2.40
128 32 21.31 15.26 13.52 7.89 5.21 3.41 3.42 3.42
64 64 75.34 41.63 26.84 14.59 8.9 5.57 5.58 5.58

Table 7-2. Dynamic Range (Effective Resolution) at TA = 25°C

DATA RATE (kSPS), GAIN
OSR
fCLKIN = 8.192 MHz 1 2 4 8 16 32 64 128
16384 0.25 113 (20.3) 108 (19.4) 103 (18.6) 101 (18.3) 98 (17.8) 96 (17.5) 90 (16.5) 84 (15.4)
8192 0.5 111 (19.9) 106 (19.1) 100 (18.1) 98 (17.8) 96 (17.4) 93 (17.0) 87 (16.0) 81 (15.0)
4096 1 108 (19.4) 103 (18.6) 97 (17.7) 96 (17.4) 93 (17.0) 91 (16.6) 85 (15.6) 79 (14.6)
2048 2 106 (19.1) 101 (18.2) 95 (17.3) 93 (17.0) 91 (16.6) 88 (16.2) 82 (15.2) 76 (14.2)
1024 4 104 (18.8) 99 (18.0) 93 (17.0) 92 (16.8) 89 (16.3) 87 (15.9) 81 (14.9) 75 (13.9)
512 8 101 (18.3) 96 (17.5) 90 (16.5) 89 (16.3) 86 (15.8) 84 (15.4) 78 (14.4) 72 (13.4)
256 16 98 (17.8) 93 (16.9) 87 (16.0) 86 (15.8) 83 (15.3) 81 (14.9) 75 (13.9) 69 (12.9)
128 32 92 (16.8) 89 (16.3) 84 (15.4) 83 (15.2) 80 (14.8) 78 (14.4) 72 (13.4) 65 (12.4)
64 64 81 (15.0) 80 (14.8) 78 (14.4) 77 (14.3) 75 (14.0) 74 (13.7) 68 (12.7) 62 (11.7)

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8 Detailed Description
8.1 Overview
The ADS131M04 is a low-power, four-channel, simultaneously sampling, 24-bit, delta-sigma (ΔΣ) analog-to-
digital converter (ADC) with a low-drift internal reference voltage. The dynamic range, size, feature set, and
power consumption are optimized for cost-sensitive applications requiring simultaneous sampling.
The ADS131M04 requires both analog and digital supplies. The analog power supply (AVDD – AGND) can
operate between 2.7 V and 3.6 V. An integrated negative charge pump allows absolute input voltages as low as
1.3 V below AGND, which enables measurements of input signals varying around ground with a single-ended
power supply. The digital power supply (DVDD – DGND) accepts both 1.8-V and 3.3-V supplies. The device
features a programmable gain amplifier (PGA) with gains up to 128. An integrated input precharge buffer
enabled at gains greater than 4 ensures high input impedance at high PGA gain settings. The ADC receives its
reference voltage from an integrated 1.2-V reference. The device allows differential input voltages as large as
the reference. Three power-scaling modes allow designers to trade power consumption for ADC dynamic range.
Each channel on the ADS131M04 contains a digital decimation filter that demodulates the output of the ΔΣ
modulators. The filter enables data rates as high as 32 kSPS per channel in high-resolution mode. The relative
phase of the samples can be configured between channels, thus enabling an accurate compensation for the
sensor phase response. Offset and gain calibration registers can be programmed to automatically adjust output
samples for measured offset and gain errors. The Functional Block Diagram provides a detailed diagram of the
ADS131M04.
The device communicates via a serial programming interface (SPI)-compatible interface. Several SPI commands
and internal registers control the operation of the ADS131M04. Other devices can be added to the same SPI bus
by adding discrete CS control lines. The SYNC/RESET pin can be used to synchronize conversions between
multiple ADS131M04 devices as well as to maintain synchronization with external events.
8.2 Functional Block Diagram
AVDD DVDD

1.2-V
Reference

AIN0P +
Phase Shift & Gain & Offset
'6 ADC
Digital Filters Calibration
AIN0N ±

SYNC / RESET

AIN1P +
Phase Shift & Gain & Offset
'6 ADC
Digital Filters Calibration CS
AIN1N ±
SCLK
Control &
Serial Interface DIN
DOUT
AIN2P +
Phase Shift & Gain & Offset DRDY
'6 ADC
Digital Filters Calibration
AIN2N ±

Clock
AIN3P + CLKIN
Phase Shift & Gain & Offset Generation
'6 ADC
Digital Filters Calibration
AIN3N ±

AGND DGND

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8.3 Feature Description

8.3.1 Input ESD Protection Circuitry
Basic electrostatic discharge (ESD) circuitry protects the ADS131M04 inputs from ESD and overvoltage events
in conjunction with external circuits and assemblies. Figure 8-1 depicts a simplified representation of the ESD
circuit. The protection for input voltages exceeding AVDD can be modeled as a simple diode.

AVDD

AINnP

To analog inputs

AINnN

AVDD

Figure 8-1. Input ESD Protection Circuitry

The ADS131M04 has an integrated negative charge pump that allows for input voltages below AGND with a
unipolar supply. Consequently, shunt diodes between the inputs and AGND cannot be used to clamp excessive
negative input voltages. Instead, the same diode that clamps overvoltage is used to clamp undervoltage at its
reverse breakdown voltage. Take care to prevent input voltages or currents from exceeding the limits provided in
the Absolute Maximum Ratings table.
8.3.2 Input Multiplexer
Each channel of the ADS131M04 has a dedicated input multiplexer. The multiplexer controls which signals are
routed to the ADC channels. Configure the input multiplexer using the MUXn[1:0] bits in the CHn_CFG register.
The input multiplexer allows the following inputs to be connected to the ADC channel:
• The analog input pins corresponding to the given channel
• AGND, which is helpful for offset calibration
• Positive DC test signal
• Negative DC test signal
See the Internal Test Signals section for more information about the test signals. Figure 8-2 shows a diagram of
the input multiplexer on the ADS131M04.
MUXn[1:0] = 00
SW
To Positive
AINnP
PGA Input
SW

SW

MUXn[1:0] = 01 MUXn[1:0] = 10

+
DC Test
SW
SW

AGND MUXn[1:0] = 11
Signal
±
SW

SW

MUXn[1:0] = 01 MUXn[1:0] = 10
SW
To Negative
AINnN
PGA Input
MUXn[1:0] = 00

Figure 8-2. Input Multiplexer

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8.3.3 Programmable Gain Amplifier (PGA)

Each channel of the ADS131M04 features an integrated programmable gain amplifier (PGA) that provides gains
of 1, 2, 4, 8, 16, 32, 64, and 128. The gains for all channels are individually controlled by the PGAGAINn bits for
each channel in the GAIN1 register.
Varying the PGA gain scales the differential full-scale input voltage range (FSR) of the ADC. Equation 3
describes the relationship between FSR and gain. Equation 3 uses the internal reference voltage, 1.2 V, as the
scaling factor without accounting for gain error caused by tolerance in the reference voltage.

FSR = ±1.2 V / Gain (3)

Table 8-1 shows the corresponding full-scale ranges for each gain setting.
Table 8-1. Full-Scale Range
GAIN SETTING FSR
1 ±1.2 V
2 ±600 mV
4 ±300 mV
8 ±150 mV
16 ±75 mV
32 ±37.5 mV
64 ±18.75 mV
128 ±9.375 mV

The input impedance of the PGA dominates the input impedance characteristics of the ADS131M04. The
PGA input impedance for gain settings up to 4 behaves according to Equation 4 without accounting for
device tolerance and change over temperature. Minimize the output impedance of the circuit that drives the
ADS131M04 inputs to obtain the best possible gain error, INL, and distortion performance.

330 kΩ × 4.096 MHz / fMOD (4)

where:
• fMOD is the ΔΣ modulator frequency, fCLKIN / 2
The device uses an input precharge buffer for PGA gain settings of 8 and higher. The input impedance at these
gain settings is very high. Specifying the input bias current for these gain settings is therefore more useful. A plot
of input bias current for the high gain settings is provided in Figure 6-5.
8.3.4 Voltage Reference
The ADS131M04 uses an internally-generated, low-drift, band-gap voltage to supply the reference for the ADC.
The reference has a nominal voltage of 1.2 V, allowing the differential input voltage to swing from –1.2 V to 1.2 V.
The reference circuitry starts up very quickly to accommodate the fast-startup feature of this device. The device
waits until after the reference circuitry is fully settled before generating conversion data.
8.3.5 Clocking and Power Modes
An LVCMOS clock must be provided at the CLKIN pin continuously when the ADS131M04 is running in normal
operation. The frequency of the clock can be scaled in conjunction with the power mode to provide a tradeoff
between power consumption and dynamic range.
The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of three power modes:
high-resolution (HR) mode, low-power (LP) mode, and very low-power (VLP) mode. Changing the PWR[1:0] bits
scales the internal bias currents to achieve the expected power levels. The external clock frequency must follow
the guidance provided in the Recommended Operating Conditions table corresponding to the intended power
mode in order for the device to perform according to the specification.

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8.3.6 ΔΣ Modulator
The ADS131M04 uses a delta-sigma (ΔΣ) modulator to convert the analog input voltage to a one's density
modulated digital bit-stream. The ΔΣ modulator oversamples the input voltage at a frequency many times greater
than the output data rate. The modulator frequency, fMOD, of the ADS131M04 is equal to half the master clock
frequency, that is, fMOD = fCLKIN / 2.
The output of the modulator is fed back to the modulator input through a digital-to-analog converter (DAC) as a
means of error correction. This feedback mechanism shapes the modulator quantization noise in the frequency
domain to make the noise more dense at higher frequencies and less dense in the band of interest. The digital
decimation filter following the ΔΣ modulator significantly attenuates the out-of-band modulator quantization
noise, allowing the device to provide excellent dynamic range.
8.3.7 Digital Filter
The ΔΣ modulator bitstream feeds into a digital filter. The digital filter is a linear phase, finite impulse response
(FIR), low-pass sinc-type filter that attenuates the out-of-band quantization noise of the ΔΣ modulator. The digital
filter demodulates the output of the ΔΣ modulator by averaging. The data passing through the filter is decimated
and downsampled, to reduce the rate at which data come out of the modulator (fMOD) to the output data rate
(fDATA). The decimation factor is defined as per Equation 5 and is called the oversampling ratio (OSR).

OSR = fMOD / fDATA (5)

The OSR is configurable and set by the OSR[2:0] bits in the CLOCK register. There are eight OSR settings in
the ADS131M04, allowing eight different data rate settings for any given master clock frequency. Table 8-2 lists
the OSR settings and their corresponding output data rates for the nominal CLKIN frequencies mentioned.
The OSR determines the amount of averaging of the modulator output in the digital filter and therefore also
the filter bandwidth. The filter bandwidth directly affects the noise performance of the ADC because lower
bandwidth results in lower noise whereas higher bandwidth results in higher noise. See Table 7-1 for the noise
specifications for various OSR settings.

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Table 8-2. OSR Settings and Data Rates for Nominal Master Clock Frequencies
NOMINAL MASTER CLOCK
POWER MODE fMOD OSR OUTPUT DATA RATE
FREQUENCY
64 64 kSPS
128 32 kSPS
256 16 kSPS
512 8 kSPS
HR 8.192 MHz 4.096 MHz 1024 4 kSPS
2048 2 kSPS
4096 1 kSPS
8192 500 SPS
16384 250 SPS
64 32 kSPS
128 16 kSPS
256 8 kSPS
512 4 kSPS
LP 4.096 MHz 2.048 MHz 1024 2 kSPS
2048 1 kSPS
4096 500 SPS
8192 250 SPS
16384 125 SPS
64 16 kSPS
128 8 kSPS
256 4 kSPS
512 2 kSPS
VLP 2.048 MHz 1.024 MHz 1024 1 kSPS
2048 500 SPS
4096 250 SPS
8192 125 SPS
16384 62.5 SPS

8.3.7.1 Digital Filter Implementation

Figure 8-3 shows the digital filter implementation of the ADS131M04. The modulator bit-stream feeds two
parallel filter paths, a sinc3 filter, and a fast-settling filter path.
Power-up
or
PHASEx[9:0] OSR[2:0] Reset 265 ” 1024

Sinc3
Phase Regular 0 Sinc1 Averager 0
Delay Filter (OSR>1024)

Modulator Global Calibration

Bitstream MUX OSR[2:0] MUX Chop Logic,
Logic Gain scaling

Fast-Settling Filter 1 1

PGA_GAINx[2:0]
OSR = 1024

Figure 8-3. Digital Filter Implementation

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8.3.7.1.1 Fast-Settling Filter

At power-up or after a device reset, the ADS131M04 selects the fast-settling filter to allow for settled output data
generation with minimal latency. The fast-settling filter has the characteristic of a first-order sinc filter (sinc1).
After two conversions, the device switches to and remains in the sinc3 filter path until the next time the device is
reset or powered cycled.
The fast-settling filter exhibits wider bandwidth and less stop-band attenuation than the sinc3 filter. Consequently,
the noise performance when using the fast-settling filter is not as high as with the sinc3 filter. The first two
samples available from the ADS131M04 after a supply ramp or reset have the noise performance and frequency
response corresponding to the fast-settling filter as specified in the Electrical Characteristics table, whereas
subsequent samples have the noise performance and frequency response consistent with the sinc3 filter. See
the Fast Startup Behavior section for more details regarding the fast startup capabilities of the ADS131M04.
8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter
The ADS131M04 selects the sinc3 filter path two conversion after power-up or device reset. For OSR settings
of 64 to 1024 the sinc3 filter output directly feeds into the global-chop and calibration logic. For OSR settings of
2048 and higher the sinc3 filter is followed by a sinc1 filter. As shown in Table 8-3, the sinc3 filter operates at a
fixed OSR of 1024 in this case while the sinc1 filter implements the additional OSRs of 2 to 16. That means when
an OSR of 4096 (for example) is selected, the sinc3 filter operates at an OSR of 1024 and the sinc1 filter at an
OSR of 4.
The filter has infinite attenuation at integer multiples of the data rate except for integer multiples of fMOD. Like
all digital filters, the digital filter response of the ADS131M04 repeats at integer multiples of the modulator
frequency, fMOD. The data rate and filter notch frequencies scale with fMOD.
When possible, plan frequencies for unrelated periodic processes in the application for integer multiples of the
data rate such that any parasitic effect they have on data acquisition is effectively cancelled by the notches
of the digital filter. Avoid frequencies near integer multiples of fMOD whenever possible because tones in these
bands can alias to the band of interest.
The sinc3 and sinc3 + sinc1 filters for a given channel require time to settle after a channel is enabled, the
channel multiplexer or gain setting is changed, or a resynchronization event occurs. See the Synchronization
section for more details on resynchronization. Table 8-3 lists the settling times of the sinc3 and sinc3 + sinc1
filters for each OSR setting. The ADS131M04 does not gate unsettled data. Therefore, the host must account for
the filter settling time and disregard unsettled data if any are read. The data at the next DRDY falling edge after
the filter settling time listed in Table 8-3 has expired can be considered fully settled.
Table 8-3. Digital Filter Startup Times After Power-Up or Resynchronization
OSR (OVERALL) OSR (SINC3) OSR (SINC1) SETTLING TIME (tCLKIN)
64 64 N/A 728
128 128 N/A 856
256 256 N/A 1112
512 512 N/A 1624
1024 1024 N/A 2648
2048 1024 2 4696
4096 1024 4 8792
8192 1024 8 16984
16384 1024 16 33368

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8.3.7.2 Digital Filter Characteristic

Equation 6 calculates the z-domain transfer function of a sinc3 filter that is used for OSRs of 1024 and lower.
3
N
1 Z
H z 1
N1 Z
(6)

where N is the OSR.

Equation 7 calculates the transfer function of a sinc3 filter in terms of the continuous-time frequency parameter f.

3
Npf
sin
fMOD
½H(f)½ =
pf
N ´ sin
fMOD
(7)

where N is the OSR.

Figure 8-4 through Figure 8-7 show the digital filter response of the fast-settling filter and the sinc3 filter for OSRs
of 1024 and lower. Figure 8-6 and Figure 8-7 show the digital filter response of the sinc3 + sinc1 filter for an OSR
of 4096.

0 0

-20 -1.5

-3
-40
Magnitude (dB)
Magnitude (dB)

-4.5
-60
-6
-80
-7.5

-100 -9

-120 -10.5 Fast-settling filter

Fast-settling filter
Sinc3 filter Sinc3 filter
-140 -12
0 0.1 0.2 0.3 0.4 0.5
0 1 2 3 4 5
Frequency (fIN/fDATA)
Frequency (fIN/fDATA)

Figure 8-4. Fast-Settling and Sinc3 Digital Filter Figure 8-5. Fast-Settling and Sinc3 Digital Filter
Response Response, Pass-Band Detail
0 0
Sinc3 filter (1024)
-20 Sinc3 + Sinc1 filter
-2

-40
-4
Magnitude (dB)

Magnitude (dB)

-60
-6
-80

-8
-100

-120 -10
Sinc3 filter (1024)
Sinc3 + Sinc1 filter
-140 -12
0 1 2 3 4 5 6 7 8 9 10 11 12 0 0.1 0.2 0.3 0.4 0.5
Frequency (fIN/fDATA) Frequency (fIN/fDATA)
Figure 8-6. Digital Filter Response for OSR = 1024 Figure 8-7. Digital Filter Response for OSR = 1024
and OSR = 4096 and OSR = 4096, Pass-Band Detail

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8.3.8 DC Block Filter

The ADS131M04 includes an optional high-pass filter to eliminate any systematic offset or low-frequency noise.
The filter is enabled by writing any value in the DCBLOCK[3:0] bits in the CD_TH_LSB register besides 0h.
The DC block filter can be enabled and disabled on a channel-by-channel basis by the DCBLKn_DIS bit in the
CHn_CFG register for each respective channel.
Figure 8-8 shows the topology of the DC block filter. Coefficient a represents a register configurable value that
configures the cutoff frequency of the filter. The cutoff frequency is configured using the DCBLOCK[3:0] bits in
the CD_TH_LSB register. Table 8-4 describes the characteristics of the filter for various DCBLOCK[3:0] settings.
The data provided in Table 8-4 is provided for an 8.192-MHz CLKIN frequency and a 4-kSPS data rate. The
frequency response of the filter response scales directly with the frequency of CLKIN and the data rate.

a
Input 1Å
2 Output

z-1
ÅD
1-z-1

Figure 8-8. DC Block Filter Topology

Table 8-4. DC Block Filter Characteristics

–3-dB PASS-BAND ATTENUATION(1) SETTLING TIME (Samples)
DCBLOCK[3:0] a COEFFICIENT
CORNER(1) 50 Hz 60 Hz SETTLED >99% FULLY SETTLED
0h DC block filter disabled
1h 1/4 181 Hz 11.5 dB 10.1 dB 17 88
2h 1/8 84.8 Hz 5.89 dB 4.77 dB 36 187
3h 1/16 41.1 Hz 2.24 dB 1.67 dB 72 387
4h 1/32 20.2 Hz 657 mdB 466 mdB 146 786
5h 1/64 10.0 Hz 171 mdB 119 mdB 293 1585
6h 1/128 4.99 Hz 43.1 mdB 29.9 mdB 588 3182
7h 1/256 2.49 Hz 10.8 mdB 7.47 mdB 1178 6376
8h 1/512 1.24 Hz 2.69 mdB 1.87 mdB 2357 12764
9h 1/1024 622 mHz 671 µdB 466 µdB 4714 25540
Ah 1/2048 311 mHz 168 µdB 116 µdB 9430 51093
Bh 1/4096 155 mHz 41.9 µdB 29.1 µdB 18861 102202
Ch 1/8192 77.7 mHz 10.5 µdB 7.27 µdB 37724 204447
Dh 1/16384 38.9 mHz 2.63 µdB 1.82 µdB 75450 409156
Eh 1/32768 19.4 mHz 655 ndB 455 ndB 150901 820188
Fh 1/65536 9.70 mHz 164 ndB 114 ndB 301803 1627730

(1) Values given are for a 4-kSPS data rate with a 8.192-MHz CLKIN frequency.

8.3.9 Internal Test Signals

The ADS131M04 features an internal analog test signal that is useful for troubleshooting and diagnosis. A
positive or negative DC test signal can be applied to the channel inputs through the input multiplexer. The
multiplexer is controlled through the MUXn[1:0] bits in the CHn_CFG register. The test signals are created by
internally dividing the internal reference voltage. The same signal is shared by all channels.
The test signal is nominally 2 / 15 × VREF. The test signal automatically adjusts its voltage level with the gain
setting such that the ADC always measures a signal that is 2 / 15 × VDiff Max. For example, at a gain of 1, this
voltage equates to 160 mV. At a gain of 2, this voltage is 80 mV.

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8.3.10 Channel Phase Calibration

The ADS131M04 allows fine adjustment of the sample phase between channels through the use of channel
phase calibration. This feature is helpful when different channels are measuring the outputs of different types
of sensors that have different phase responses. For example, in power metrology applications, voltage can
be measured by a voltage divider, whereas current is measured using a current transformer that exhibits a
phase difference between its input and output signals. The differences in phase between the voltage and current
measurement must be compensated to measure the power and related parameters accurately.
The phase setting of the different channels is configured by the PHASEn[9:0] bits in the CHn_CFG register
corresponding to the channel whose phase adjustment is desired. The register value is a 10-bit two's
complement value corresponding to the number of modulator clock cycles of phase offset compared to a
reference phase of 0 degrees.
The mechanism for achieving phase adjustment derives from the ΔΣ architecture. The ΔΣ modulator produces
samples continuously at the modulator frequency, fMOD. These samples are filtered and decimated to the output
data rate by the digital filter. The ratio between fMOD and the data rate is the oversampling ratio (OSR). Each
conversion result corresponds to an OSR number of modulator samples provided to the digital filter. When the
different channels of the ADS131M04 have no programmed phase offset between them, the modulator clock
cycles corresponding to the conversion results of the different channels are aligned in the time domain. Figure
8-9 depicts an example scenario where the voltage input to channel 1 has no phase offset from channel 0.

Sample
Period
CH0 Input

CH1 Input

Figure 8-9. Two Channel Outputs With Equal Phase Settings

However, the sample period of one channel can be shifted with respect to another. If the inputs to both channels
are sinusoids of the same frequency and the samples for these channels are retrieved by the host at the same
time, the effect is that the phase of the channel with the modified sample period appears shifted. Figure 8-10
depicts how the period corresponding to the samples are shifted between channels. Figure 8-11 illustrates how
the samples appear as having generated a phase shift when they are retrieved by the host.

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Sample
Period
CH0 Input

CH1 Input

Sample Period
Offset

Figure 8-10. Channel 1 With a Positive Sample Phase Shift With Respect to Channel 0

CH0 Output
CH1 Output

Figure 8-11. Channels 1 and 0 From the Perspective of the Host

The valid setting range is from –OSR / 2 to (OSR / 2) – 1, except for OSRs greater than 1024, where the phase
calibration setting is limited to –512 to 511. If a value outside of –OSR / 2 and (OSR / 2) – 1 is programmed,
the device internally clips the value to the nearest limit. For example, if the OSR setting is programmed to 128
and the PHASEn[9:0] bits are programmed to 0001100100b corresponding to 100 modulator clock cycles, the
device sets the phase of the channel to 63 because that value is the upper limit of phase calibration for that OSR
setting. Table 8-5 gives the range of phase calibration settings for various OSR settings.
Table 8-5. Phase Calibration Setting Limits for Different OSR Settings
OSR SETTING PHASE OFFSET RANGE (tMOD) PHASEn[9:0] BITS RANGE
64 –32 to 31 11 1110 0000b to 00 0001 1111b
128 –64 to 63 11 1100 0000b to 00 0011 1111b
256 –128 to 127 11 1000 0000b to 00 0111 1111b
512 –256 to 255 11 0000 0000b to 00 1111 1111b
1024 –512 to 511 10 0000 0000b to 01 1111 1111b
2048 –512 to 511 10 0000 0000b to 01 1111 1111b
4096 –512 to 511 10 0000 0000b to 01 1111 1111b
8192 –512 to 511 10 0000 0000b to 01 1111 1111b
16384 –512 to 511 10 0000 0000b to 01 1111 1111b

Follow these steps to create a phase shift larger than half the sample period for OSRs less than 2048:
• Create a phase shift corresponding to an integer number of sample periods by modifying the indices between
channel data in software
• Use the phase calibration function of the ADS131M04 to create the remaining fractional sample period phase
shift
For example, to create a phase shift of 2.25 samples between channels 0 and 1, create a phase shift of two
samples by aligning sample N in the channel 0 output data stream with sample N+2 in the channel 1 output

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data stream in the host software. Make the remaining 0.25 sample adjustment using the ADS131M04 phase
calibration function.
The phase calibration settings of the channels affect the timing of the data-ready interrupt signal, DRDY. See the
Data Ready (DRDY) section for more details regarding how phase calibration affects the DRDY signal.
8.3.11 Calibration Registers
The calibration registers allow for the automatic computation of calibrated ADC conversion results from pre-
programmed values. The host can rely on the device to automatically correct for system gain and offset after
the error correction terms are programmed into the corresponding device registers. The measured calibration
coefficients must be store in external non-volatile memory and programmed into the registers each time the
ADS131M04 powers up because the ADS131M04 registers are volatile.
The offset calibration registers are used to correct for system offset error, otherwise known as zero error.
Offset error corresponds to the ADC output when the input to the system is zero. The ADS131M04 corrects
for offset errors by subtracting the contents of the OCALn[23:0] register bits in the CHn_OCAL_MSB and
CHn_OCAL_LSB registers from the conversion result for that channel before being output. There are separate
CHn_OCAL_MSB and CHnOCAL_LSB registers for each channel, which allows separate offset calibration
coefficients to be programmed for each channel. The contents of the OCALn[23:0] bits are interpreted by the
device as 24-bit two's complement values, which is the same format as the ADC data.
The gain calibration registers are used to correct for system gain error. Gain error corresponds to the
deviation of gain of the system from its ideal value. The ADS131M04 corrects for gain errors by multiplying
the ADC conversion result by the value given by the contents of the GCALn[23:0] register bits in the
CHn_GCAL_MSB and CHn_GCAL_LSB registers before being output. There are separate CHn_GCAL_MSB
and CHn_GCAL_LSB registers for each channel, which allows separate gain calibration coefficients to be
programmed for each channel. The contents of the GCALn[23:0] bits are interpreted by the device as 24-bit
unsigned values corresponding to linear steps ranging from gains of 0 to 2 – (1 / 223). Table 8-6 describes the
relationship between the GCALn[23:0] bit values and the gain calibration factor.
Table 8-6. GCALn[23:0] Bit Mapping
GCALn[23:0] VALUE GAIN CALIBRATION FACTOR
000000h 0
000001h 1.19 × 10–7
800000h 1
FFFFFEh 2 – 2.38 × 10–7
FFFFFFh 2 – 1.19 × 10–7

The calibration registers do not need to be enabled because they are always in use. The OCALn[23:0] bits have
a default value of 000000h resulting in no offset correction. Similarly, the GCALn[23:0] bits default to 800000h
resulting in a gain calibration factor of 1.
Figure 8-12 depicts a block diagram illustrating the mechanics of the calibration registers on one channel of the
ADS131M04.

û Digital
To Interface
Modulator Filter
Å

OCALn[23:0] 1
223

GCALn[23:0]

Figure 8-12. Calibration Block Diagram

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8.3.12 Communication Cyclic Redundancy Check (CRC)

The ADS131M04 features a cyclic redundancy check (CRC) engine on both input and output data to mitigate
SPI communication errors. The CRC word is 16 bits wide for either input or output CRC. Coverage includes all
words in the SPI frame where the CRC is enabled, including padded bits in a 32-bit word size.
CRC on the SPI input is optional and can be enabled and disabled by writing the RX_CRC_EN bit in the MODE
register. Input CRC is disabled by default. When the input CRC is enabled, the device checks the provided
input CRC against the CRC generated based on the input data. A CRC error occurs if the CRC words do not
match. The device does not execute any commands, except for the WREG command, if the input CRC check
fails. A WREG command always executes even when the CRC check fails. The device sets the CRC_ERR bit
in the STATUS register for all cases of a CRC error. The response on the output in the SPI frame following the
frame where the CRC error occurred is that of a NULL command, which means the STATUS register plus the
conversion data are output in the following SPI frame. The CRC_ERR bit is cleared when the STATUS register is
output.
The output CRC cannot be disabled and always appears at the end of the output frame. The host can ignore the
data if the output CRC is not used.
There are two types of CRC polynomials available: CCITT CRC and ANSI CRC (CRC-16). The CRC setting
determines the algorithm for both the input and output CRC. The CRC type is programmed by the CRC_TYPE
bit in the MODE register. Table 8-7 lists the details of the two CRC types.
The seed value of the CRC calculation is FFFFh.
Table 8-7. CRC Types
CRC TYPE POLYNOMIAL BINARY POLYNOMIAL
CCITT CRC x16 + x12 + x5 + 1 0001 0000 0010 0001
ANSI CRC x16 + x15 + x2 +1 1000 0000 0000 0101

8.3.13 Register Map CRC

The ADS131M04 performs a CRC on its own register map as a means to check for unintended changes to the
registers. Enable the register map CRC by setting the REG_CRC_EN bit in the MODE register. When enabled,
the device constantly calculates the register map CRC using each bit in the writable register space. The register
addresses covered by the register map CRC on the ADS131M04 are 02h through 1Ch. The CRC is calculated
beginning with the MSB of register 02h and ending with the LSB of register 1Ch using the polynomial selected in
the CRC_TYPE bit in the MODE register.
The calculated CRC is a 16-bit value and is stored in the REGMAP_CRC register. The calculation is done using
one register map bit per CLKIN period and constantly checks the result against the previous calculation. The
REG_MAP bit in the STATUS register is set to flag the host if the register map CRC changes, including changes
resulting from register writes. The bit is cleared by reading the STATUS register, or by the STATUS register being
output as a response to the NULL command.

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8.4 Device Functional Modes

Figure 8-13 shows a state diagram depicting the major functional modes of the ADS131M04 and the transitions
between them.
POR, pin reset, or
RESET command

Reset
Reset complete

STANDBY
Standby WAKEUP && GC_EN Continuous
Mode Conversion Mode

STANDBY

Current detection WAKEUP GC_EN

complete && GC_EN
GC_EN

SYNC Current Global-Chop

Detect Mode Mode

Figure 8-13. State Diagram Depicting Device Functional Modes

8.4.1 Power-Up and Reset

The ADS131M04 is reset in one of three ways: by a power-on reset (POR), by the SYNC/RESET pin, or by
a RESET command. After a reset occurs, the configuration registers are reset to the default values and the
device begins generating conversion data as soon as a valid MCLK is provided. In all three cases a low to high
transition on the DRDY pin indicates that the SPI interface is ready for communication. The device ignores any
SPI communication before this point.
8.4.1.1 Power-On Reset
Power-on reset (POR) is the reset that occurs when a valid supply voltage is first applied. The POR process
requires tPOR from when the supply voltages reach 90% of their nominal value. Internal circuitry powers up and
the registers are set to their default state during this time. The DRDY pin transitions from low to high immediately
after tPOR indicating the SPI interface is ready for communication. The device ignores any SPI communication
before this point.
8.4.1.2 SYNC/RESET Pin
The SYNC/RESET pin is an active low, dual-function pin that generates a reset if the pin is held low longer than
tw(RSL). The device maintains a reset state until SYNC/RESET is returned high. The host must wait for at least
tREGACQ after SYNC/RESET is brought high or for the DRDY rising edge before communicating with the device.
Conversion data are generated immediately after the registers are reset to their default values, as described in
the Fast Startup Behavior section.
8.4.1.3 RESET Command
The ADS131M04 can be reset via the SPI RESET command (0011h). The device communicates in frames
of a fixed length. See the SPI Communication Frames section for details regarding SPI data framing on the
ADS131M04. The RESET command occurs in the first word of the data frame, but the command is not latched
by the device until the entire frame is complete. After the response completes channel data and CRC words are

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clocked out. Terminating the frame early causes the RESET command to be ignored. Six words are required to
complete a frame on the ADS131M04.
A reset occurs immediately after the command is latched. The host must wait for tREGACQ before communicating
with the device to ensure the registers have assumed their default settings. Conversion data are generated
immediately after the registers are reset to their default values, as described in the Fast Startup Behavior
section.
8.4.2 Fast Startup Behavior
The ADS131M04 begins generating conversion data shortly after startup as soon as a valid CLKIN signal
is provided to the ΔΣ modulators. The fast startup feature is useful for applications such as circuit breakers
powered from the mains that require a fast determination of the input voltage soon after power is applied to
the device. Fast startup is accomplished via two mechanisms. First, the device internal power-supply circuitry
is designed specifically to enable fast startup. Second, the digital decimation filter dynamically switches from a
fast-settling filter to a sinc3 filter when the sinc3 filter has had time to settle.
After the supplies are ramped to 90% of their final values, the device requires tPOR for the internal circuitry to
settle. The end of tPOR is indicated by a transition of DRDY from low to high. The transition of DRDY from low to
high also indicates the SPI interface is ready to accept commands.
The ΔΣ modulators of the ADS131M04 require CLKIN to toggle after tPOR to begin working. The modulators
begin sampling the input signal after an initial wait time delay of (256 + 44) × tMOD when CLKIN begins toggling.
Therefore, provide a valid clock signal on CLKIN as soon as possible after the supply ramp to achieve the fastest
possible startup time.
The data generated by the ΔΣ modulators are fed to the digital filter blocks. The data are provided to both the
fast-settling filter and the sinc3 filter paths. The fast-settling filter requires only one data rate period to provide
settled data. Meanwhile, the sinc3 filter requires three data rate periods to settle. The fast-settling filter generates
the output data for the two interim ADC output samples indicated by DRDY transitioning from high to low while
the sinc3 filter is settling. The device disables the fast-settling filter and provides conversion data from the sinc3
filter path for the third and following samples. Figure 8-14 shows the behavior of the fast-startup feature when
using an external clock that is provided to the device right after the supplies have ramped. Table 8-8 shows the
values for the various startup and settling times relevant to the device startup.
Supplies 90% tSETTLE3

tPOR tSETTLE1 tDATA tDATA

DRDY

Fast-settling Fast-settling Sinc3 Sinc3

filter data filter data filter data filter data

CLKIN ... ... ... ...

Figure 8-14. Fast Startup Behavior and Settling Times

Table 8-8. Fast Startup Settling Times for Default OSR = 1024
VALUE (DETAILS) VALUE VALUE AT
PARAMETER
(tMOD) (tMOD) fCLKIN = 8.192 MHz (ms)
tDATA = 1/fDATA 1024 1024 0.250
tSETTLE1 256 + 44 + 1024 1324 0.323
tSETTLE3 256 + 44 + 3 x 1024 3372 0.823

The fast-settling filter provides conversion data that are significantly noisier than the data that comes from the
sinc3 filter path, but allows the device to provide settled conversion data during the longer settling time of the
more accurate sinc3 digital filter. If the level of precision provided by the fast-settling filter is insufficient even for

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the first samples immediately following startup, ignore the first two instances of DRDY toggling from high to low
and begin collecting data on the third instance.
The startup process following a RESET command or a pin reset using the SYNC/RESET pin is similar to what
occurs after power up. However there is no tPOR in the case of a command or pin reset because the supplies are
already ramped. After reset, the device waits for the initial wait time delay of (256 + 44) × tMOD before providing
modulator samples to the two digital filters. The fast-settling filter is enabled for the first two output samples.
8.4.3 Conversion Modes
There are two ADC conversion modes on the ADS131M04: continuous-conversion and global-chop mode.
Continuous-conversion mode is a mode where ADC conversions are generated constantly by the ADC at a
rate defined by fMOD / OSR. Global-chop mode differs from continuous-conversion mode because global-chop
periodically chops (or swaps) the inputs, which reduces system offset errors at the cost of settling time between
the points when the inputs are swapped. In either continuous-conversion or global-chop mode, there are three
power modes that provide flexible options to scale power consumption with bandwidth and dynamic range. The
Power Modes section discusses these power modes in further detail.
8.4.3.1 Continuous-Conversion Mode
Continuous-conversion mode is the mode in which ADC data are generated constantly at the rate of fMOD /
OSR. New data are indicated by a DRDY falling edge at this rate. Continuous-conversion mode is intended for
measuring AC signals because this mode allows for higher output data rates than global-chop mode.
8.4.3.2 Global-Chop Mode
The ADS131M04 incorporates a global-chop mode option to reduce offset error and offset drift inherent to
the device due to mismatch in the internal circuitry to very low levels. When global-chop mode is enabled
by setting the GC_EN bit in the GLOBAL_CHOP_CFG register, the device uses the conversion results from
two consecutive internal conversions taken with opposite input polarity to cancel the device offset voltage.
Conversion n is taken with normal input polarity. The device then reverses the internal input polarity for
conversion n + 1. The average of two consecutive conversions (n and n + 1, n + 1 and n + 2 and so on)
yields the final offset compensated result.
Figure 8-15 shows a block diagram of the global-chop mode implementation. The combined PGA and ADC
internal offset voltage is modeled as VOFS. Only this device inherent offset voltage is reduced by global-chop
mode. Offset in the external circuitry connected to the analog inputs is not affected by global-chop mode.
Chop Switch GC_EN
VOFS

AINnP + -
ADC Digital Global-Chop
PGA ADC Conversion Output
Filter Mode Control
AINnN

Figure 8-15. Global-Chop Mode Implementation

The conversion period in global-chop mode differs from the conversion time when global-chop mode is disabled
(tDATA = OSR x tMOD). Figure 8-16 shows the conversion timing for an ADC channel using global-chop mode.
Global-chop delay

Modulator sampling
st nd
Conversion Data not Data not Swap inputs, Data not Data not 1 global-chop 2 global-chop x

ADC overhead

xx xx
start settled settled digital filter reset settled settled conversion result conversion result

Sampling Sampling Sampling Sampling Sampling Sampling Sampling Sampling Sampling Sampling Sampling Sampling
n n n n+1 n+1 n+1 n+2 n+2 n+2 n+3 n+3 n+3

x x

tGC_FIRST CONVERSION tGC_CONVERSION tDATA

Figure 8-16. Conversion Timing With Global-Chop Mode Enabled

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Every time the device swaps the input polarity, the digital filter is reset. The ADC then always takes three internal
conversions to produce one settled global-chop conversion result.
The ADS131M04 provides a programmable delay (tGC_DLY) between the end of the previous conversion period
and the beginning of the subsequent conversion period after the input polarity is swapped. This delay is to
allow for external input circuitry to settle because the chopping switches interface directly with the analog inputs.
The GC_DLY[3:0] bits in the GLOBAL_CHOP_CFG register configure the delay after chopping the inputs. The
global-chop delay is selected in terms of modulator clock periods from 2 to 65,536 x tMOD.
The effective conversion period in global-chop mode follows Equation 8. A DRDY falling edge is generated each
time a new global-chop conversion becomes available to the host.
The conversion process of all ADC channels in global-chop mode is restarted in the following two conditions so
that all channels start sampling at the same time:
• Falling edge of SYNC/RESET pin
• Change of OSR setting
The conversion period of the first conversion after the ADC channels have been reset is considerably longer
than the conversion period of all subsequent conversions mentioned in Equation 8, because the device first
needs to perform two fully settled internal conversions with the input polarity swapped. The conversion period for
the first conversion in global-chop mode follows Equation 9.

tGC_CONVERSION = tGC_DLY + 3 × OSR x tMOD (8)

tGC_FIRST_CONVERSION = tGC_DLY + 3 × OSR x tMOD + tGC_DLY + 3 × OSR x tMOD + 44 x tMOD (9)

Using global-chop mode reduces the ADC noise shown in Table 7-1 at a given OSR by a factor of √2 because
two consecutive internal conversions are averaged to yield one global-chop conversion result. The DC test
signal cannot be measured in global-chop mode.
Phase calibration is automatically disabled in global-chop mode.
8.4.4 Power Modes
In both continuous-conversion and global-chop mode, there are three selectable power modes that allow scaling
of power with bandwidth and performance: high-resolution (HR) mode, low-power (LP) mode, and very-low-
power (VLP) mode. The mode is selected by the PWR[1:0] bits in the CLOCK register. See the Recommended
Operating Conditions table for restrictions on the CLKIN frequency for each power mode.
8.4.5 Standby Mode
Standby mode is a low-power state in which all channels are disabled, and the reference and other non-essential
circuitry are powered down. This mode differs from completely powering down the device because the device
retains its register settings. Enter standby mode by sending the STANDBY command (0022h). Stop toggling
CLKIN when the device is in standby mode to minimize device power consumption. Exit standby mode by
sending the WAKEUP command (0033h). After exiting standby mode, the modulators begin sampling the input
signal after a modulator settling time of 8 × tMOD when CLKIN begins toggling.
8.4.6 Current-Detect Mode
Current-detect mode is a special mode that is helpful for applications requiring tamper detection when the
equipment is in a low-power state. In this mode, the ADS131M04 collects a configurable number of samples at a
nominal data rate of 2.7 kSPS and compares the absolute value of the results to a programmable threshold. If a
configurable number of results exceed the threshold, the host is notified via a DRDY falling edge and the device
returns to standby mode. Enter current-detect mode by providing a negative pulse on SYNC/RESET with a pulse
duration less than tw(RSL) when in standby mode. Current-detect mode can only be entered from standby mode.
The device uses a limited power operating mode to generate conversions in current-detect mode. The
conversion results are only used for comparison by the internal digital threshold comparator and are not
accessible by the host. The device uses an internal oscillator that enables the device to capture the data without

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the use of the external clock input. Do not toggle CLKIN when in current-detect mode to minimize device power
consumption.
Current-detect mode is configured in the CFG, THRSHLD_MSB, and THRSHLD_LSB registers. Enable and
disable current-detect mode by toggling the CD_EN bit in the CFG register. The THRSHLD_MSB and
THRSHLD_LSB registers contain the CD_THRSH[23:0] bits that represent the digital comparator threshold
value during current detection.
The number of samples used for current detection are programmed by the CD_LEN[2:0] bits in the CFG register.
The number of samples used for current detection range from 128 to 3584.
The programmable values in CD_NUM[2:0] configure the number of samples that must exceed the threshold
for a detection to occur. The purpose of requiring multiple samples for detection is to control noisy values that
may exceed the threshold, but do not represent a high enough power level to warrant action by the host. In
summary, the conversion result must exceed the value programmed in CD_THRSH[23:0] a number of times as
represented by the value stored in CD_NUM[2:0].
The device can be configured to notify the host based on any of the results from either individual channels ,
all channels, or any combination of channels. The CD_ALLCH bit in the CFG register determines how many
channels are required to exceed the programmed thresholds to trigger a current detection. When the bit is 1, all
enabled channels are required to meet the current detection requirements in order for the host to be notified. If
the bit is 0, any enabled channel triggers a current detection notification if the requirements are met. Enable and
disable channels using the CHn_EN bits in the CLK register to control which combination of channels must meet
the requirements to trigger a current-detection notification.
Figure 8-17 illustrates a flow chart depicting the current-detection process on the ADS131M04.

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Continuous-Conversion
Mode
WAKEUP Command

No
STANDBY
Command?

Yes

Standby Mode

No
SYNC
Asserted?

Yes

Current-Detect Mode

Yes
Samples Collected =
CD_LEN?

No

No
Measurement >
CD_THRSHLD?

Yes

Increment threshold
counter

No
Threshold counter >
CD_NUM?

Yes

No
Assert DRDY CD_ALLCH?

Yes

Yes No
Current detected on all
enabled channels?

Figure 8-17. Current-Detect Mode Flow Chart

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8.5 Programming
8.5.1 Interface
The ADS131M04 uses an SPI-compatible interface to configure the device and retrieve conversion data. The
device always acts as an SPI slave; SCLK and CS are inputs to the interface. The interface operates in
SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, the SCLK idles low and data are launched
or changed only on SCLK rising edges; data are latched or read by the master and slave on SCLK falling
edges. The interface is full-duplex, meaning data can be sent and received simultaneously by the interface. The
device includes the typical SPI signals: SCLK, CS, DIN (MOSI), and DOUT (MISO). In addition, there are two
other digital pins that provide additional functionality. The DRDY pin serves as a flag to the host to indicate
new conversion data are available. The SYNC/RESET pin is a dual-function pin that allows synchronization of
conversions to an external event and allows for a hardware device reset.
8.5.1.1 Chip Select (CS)
The CS pin is an active low input signal that selects the device for communication. The device ignores any
communication and DOUT is high impedance when CS is held high. Hold CS low for the duration of a
communication frame to ensure proper communication. The interface is reset each time CS is taken high.
8.5.1.2 Serial Data Clock (SCLK)
The SCLK pin is an input that serves as the serial clock for the interface. Output data on the DOUT pin transition
on the rising edge of SCLK and input data on DIN are latched on the falling edge of SCLK.
8.5.1.3 Serial Data Input (DIN)
The DIN pin is the serial data input pin for the device. Serial commands are shifted in through the DIN pin by the
device with each SCLK falling edge when the CS pin is low.
8.5.1.4 Serial Data Output (DOUT)
The DOUT pin is the serial data output pin for the device. The device shifts out command responses and
ADC conversion data serially with each rising SCLK edge when the CS pin is low. This pin assumes a high-
impedance state when CS is high.
8.5.1.5 Data Ready (DRDY)
The DRDY pin is an active low output that indicates when new conversion data are ready in conversion mode
or that the requirements are met for current detection when in current-detect mode. Connect the DRDY pin to a
digital input on the host to trigger periodic data retrieval in conversion mode.
The timing of DRDY with respect to the sampling of a given channel on the ADS131M04 depends on the
phase calibration setting of the channel and the state of the DRDY_SEL[1:0] bits in the MODE register. Setting
the DRDY_SEL[1:0] bits to 00b configures DRDY to assert when the channel with the largest positive phase
calibration setting, or the most lagging, has a new conversion result. When the bits are 01b, the device asserts
DRDY each time any channel data are ready. Finally, setting the bits to either 10b or 11b configures the device
to assert DRDY when the channel with the most negative phase calibration setting, or the most leading, has
new conversion data. Changing the DRDY_SEL[1:0] bits has no effect on DRDY behavior in global-chop mode
because phase calibration is automatically disabled in global-chop mode.
The timing of the first DRDY assertion after channels are enabled or after a synchronization pulse is provided
depends on the phase calibration setting. If the channel that causes DRDY to assert has a phase calibration
setting less than zero, the first DRDY assertion can be less than one sample period from the channel being
enabled or the occurrence of the synchronization pulse. However, DRDY asserts in the next sample period if the
phase setting puts the output timing too close to the beginning of the sample period.
Table 8-9 lists the phase calibration setting boundary at which DRDY either first asserts within a sample period,
or in the next sample period. If the setting for the channel configured to control DRDY assertion is greater than
the value listed in Table 8-9 for each OSR, DRDY asserts for the first time within a sample period of the channel
being enabled or the synchronization pulse. If the phase setting value is equal to or more negative than the value

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in Table 8-9, DRDY asserts in the following sample period. See the Synchronization section for more information
about synchronization.
Table 8-9. Phase Setting First DRDY Assertion Boundary
OSR PHASE SETTING BOUNDARY PHASEn[9:0] BIT SETTING BOUNDARY
64 +13 00Dh
128 –19 3EDh
256 –83 3ADh
512 –211 32Dh
1024 –467 22Dh
>1024 None N/A

The DRDY_HIZ bit in the MODE register configures the state of the DRDY pin when deasserted. By default
the bit is 0b, meaning the pin is actively driven high using a push-pull output stage. When the bit is 1b, DRDY
behaves like an open-drain digital output. Use a 100-kΩ pullup resistor to pull the pin high when DRDY is not
asserted.
The DRDY_FMT bit in the MODE register determines the format of the DRDY signal. When the bit is 0b, new
data are indicated by DRDY changing from high to low and remaining low until either all of the conversion data
are shifted out of the device, or remaining low and going high briefly before the next time DRDY transitions
low. When the DRDY_FMT bit is 1b, new data are indicated by a short negative pulse on the DRDY pin. If
the host does not read conversion data after the DRDY pulse when DRDY_FMT is 1b, the device skips a
conversion result and does not provide another DRDY pulse until the second following instance when data are
ready because of how the pulse is generated. See the Collecting Data for the First Time or After a Pause in Data
Collection section for more information about the behavior of DRDY when data are not consistently read.
The DRDY pulse is blocked when new conversions complete while conversion data are read. Therefore, avoid
reading ADC data during the time where new conversions complete in order to achieve consistent DRDY
behavior.
8.5.1.6 Conversion Synchronization or System Reset (SYNC/RESET)
The SYNC/RESET pin is a multi-function digital input pin that serves primarily to allow the host to synchronize
conversions to an external process or to reset the device. See the Synchronization section for more details
regarding the synchronization function. See the SYNC/RESET Pin section for more details regarding how the
device is reset.
8.5.1.7 SPI Communication Frames
SPI communication on the ADS131M04 is performed in frames. Each SPI communication frame consists
of several words. The word size is configurable as either 16 bits, 24 bits, or 32 bits by programming the
WLENGTH[1:0] bits in the MODE register.
The ADS131M04 implements a timeout feature for the SPI communication. Enable or disable the timeout using
the TIMEOUT bit in the MODE register. When enabled, the entire SPI frame (first SCLK to last SCLK) must
complete within 215 CLKIN cycles otherwise the SPI will reset. This feature is provided as a means to recover
SPI synchronization for cases where CS is tied low.
The interface is full duplex, meaning that the interface is capable of transmitting data on DOUT while
simultaneously receiving data on DIN. The input frame that the host sends on DIN always begins with a
command. The first word on the output frame that the device transmits on DOUT always begins with the
response to the command that was written on the previous input frame. The number of words in a command
depends on the command provided. For most commands, there are six words in a frame. On DIN, the host
provides the command, the command CRC if input CRC is enabled or a word of zeros if input CRC is disabled,
and four additional words of zeros. Simultaneously on DOUT, the device outputs the response from the previous
frame command, four words of ADC data representing the four ADC channels, and a CRC word. Figure 8-18
illustrates a typical command frame structure.

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DRDY

CS

SCLK

DIN Command CRC Command CRC

DOUT Hi-Z Response Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data CRC Hi-Z Response Channel 0 Data

Figure 8-18. Typical Communication Frame

There are some commands that require more than six words. In the case of a read register (RREG) command
where more than a single register is read, the response to the command contains the acknowledgment of
the command followed by the register contents requested, which may require a larger frame depending on
how many registers are read. See the RREG (101a aaaa annn nnnn) section for more details on the RREG
command.
In the case of a write register (WREG) command where more than a single register is written, the frame extends
to accommodate the additional data. See the WREG (011a aaaa annn nnnn) section for more details on the
WREG command.
See the Commands section for a list of all valid commands and their corresponding responses on the
ADS131M04.
Under special circumstances, a data frame can be shortened by the host. See the Short SPI Frames section for
more information about artificially shortening communication frames.
8.5.1.8 SPI Communication Words
An SPI communication frame with the ADS131M04 is made of words. Words on DIN can contain commands,
register settings during a register write, or a CRC of the input data. Words on DOUT can contain command
responses, register settings during a register read, ADC conversion data, or CRC of the output data.
Words can be 16, 24, or 32 bits. The word size is configured by the WLENGTH[1:0] bits in the MODE register.
The device defaults to a 24-bit word size. Commands, responses, CRC, and registers always contain 16 bits of
actual data. These words are always most significant bit (MSB) aligned, and therefore the least significant bits
(LSBs) are zero-padded to accommodate 24- or 32-bit word sizes. ADC conversion data are nominally 24 bits.
The ADC truncates its eight LSBs when the device is configured for 16-bit communication. There are two options
for 32-bit communication available for ADC data that are configured by the WLENGTH[1:0] bits in the MODE
register. Either the ADC data can be LSB padded with zeros or the data can be MSB sign extended.
8.5.1.9 ADC Conversion Data
The device provides conversion data for each channel at the data rate. The time when data are available
relative to DRDY asserting is determined by the channel phase calibration setting and the DRDY_SEL[1:0] bits
in the MODE register when in continuous-conversion mode. All data are available immediately following DRDY
assertion in global-chop mode. The conversion status of all channels is available as the DRDY[3:0] bits in the
STATUS register. The STATUS register content is automatically output as the response to the NULL command.

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Conversion data are 24 bits. The data LSBs are truncated when the device operates with a 16-bit word size.
The LSBs are zero padded or the MSBs sign extended when operating with a 32-bit word size depending on the
setting of the WLENGTH[1:0] bits in the MODE register.
Data are given in binary two's complement format. Use Equation 10 to calculate the size of one code (LSB).

1 LSB = (2.4 / Gain) / 224 = +FSR / 223 (10)

A positive full-scale input VIN ≥ +FSR – 1 LSB = 1.2 / Gain – 1 LSB produces an output code of 7FFFFFh and
a negative full-scale input (VIN ≤ –FSR = –1.2 / Gain) produces an output code of 800000h. The output clips at
these codes for signals that exceed full-scale.
Table 8-10 summarizes the ideal output codes for different input signals.
Table 8-10. Ideal Output Code versus Input Signal
INPUT SIGNAL,
IDEAL OUTPUT CODE
VIN = VAINP – VAINN
≥ FSR (223 – 1) / 223 7FFFFFh
FSR / 223 000001h
0 000000h
–FSR / 223 FFFFFFh
≤ –FSR 800000h

Figure 8-19 shows the mapping of the analog input signal to the output codes.

7FFFFFh
7FFFFEh
¼
Output Code

000001h
000000h
FFFFFFh
¼

800001h
800000h

-FS ¼ 0 ¼ FS
Input Voltage VIN
23 23
2 -1 2 -1
-FS FS
23 23
2 2

Figure 8-19. Code Transition Diagram

8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
Take special precaution when collecting data for the first time or when beginning to collect data again after a
pause. The internal mechanism that outputs data contains a first-in-first-out (FIFO) buffer that can store two
samples of data per channel at a time. The DRDY flag for each channel in the STATUS register remains set
until both samples for each channel are read from the device. This condition is not obvious under normal
circumstances when the host is reading each consecutive sample from the device. In that case, the samples are
cleared from the device each time new data are generated so the DRDY flag for each channel in the STATUS
register is cleared with each read. However, both slots of the FIFO are full if a sample is missed or if data are
not read for a period of time. Either strobe the SYNC/RESET pin to re-synchronize conversions and clear the
FIFOs, or quickly read two data packets when data are read for the first time or after a gap in reading data.
This process ensures predictable DRDY pin behavior. See the Synchronization section for information about the
synchronization feature. These methods do not need to be employed if each channel data was read for each
output data period from when the ADC was enabled.

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Figure 8-20 depicts an example of how to collect data after a period of the ADC running, but where no data
are being retrieved. In this instance, the SYNC/RESET pin is used to clear the internal FIFOs and realign the
ADS131M04 output data with the host.
Time where data is
not being read

DRDY

SYNC / RESET

SYNC Pulse

CS

SCLK

Hi-Z
DOUT Data Data CRC Status Data CRC

Figure 8-20. Collecting Data After a Pause in Data Collection Using the SYNC/RESET Pin

Another functionally equivalent method for clearing the FIFO after a pause in collecting data is to begin by
reading two samples in quick succession. Figure 8-21 depicts this method. This example shows when the
DRDY_FMT bit in the MODE register is set to 0b indicating DRDY is a level output. There is a very narrow pulse
on DRDY immediately after the first set of data are shifted out of the device. This pulse may be too narrow
for some microcontrollers to detect. Therefore, do not rely upon this pulse but instead immediately read out the
second data set after the first data set. The host operates synchronous to the device after the second word is
read from the device.
Time where data is
not being read
Narrow DRDY Pulse

DRDY

CS

SCLK

Hi-Z
DOUT Data Data CRC Status Data CRC Status Data CRC

Data is read a
second time

Figure 8-21. Collecting Data After a Pause in Data Collection by Reading Data Twice

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8.5.1.10 Commands
Table 8-11 contains a list of all valid commands, a short description of their functionality, their binary command
word, and the expected response that appears in the following frame.
Table 8-11. Command Definitions
COMMAND DESCRIPTION COMMAND WORD RESPONSE
NULL No operation 0000 0000 0000 0000 STATUS register
RESET Reset the device 0000 0000 0001 0001 1111 1111 0010 0100
STANDBY Place the device into standby mode 0000 0000 0010 0010 0000 0000 0010 0010
Wake the device from standby mode to conversion
WAKEUP 0000 0000 0011 0011 0000 0000 0011 0011
mode
Lock the interface such that only the NULL, UNLOCK,
LOCK 0000 0101 0101 0101 0000 0101 0101 0101
and RREG commands are valid
UNLOCK Unlock the interface after the interface is locked 0000 0110 0101 0101 0000 0110 0101 0101
dddd dddd dddd dddd
Read nnn nnnn plus 1 registers beginning at address a
RREG 101a aaaa annn nnnn or
aaaa a
111a aaa annn nnnn (1)
Write nnn nnnn plus 1 registers beginning at address a 010a aaaa ammm mmmm
WREG 011a aaaa annn nnnn (2)
aaaa a

(1) When nnn nnnn is 0, the response is the requested register data dddd dddd dddd dddd. When nnn nnnn is greater than 0, the
response begins with 111a aaaa annn nnnn, followed by the register data.
(2) In this case mmm mmmm represents the number of registers that are actually written minus one. This value may be less than nnn
nnnn in some cases.

8.5.1.10.1 NULL (0000 0000 0000 0000)

The NULL command is the no-operation command that results in no registers read or written, and the state of
the device remains unchanged. The intended use case for the NULL command is during ADC data capture. The
command response for the NULL command is the contents of the STATUS register. Any invalid command also
gives the NULL response.
8.5.1.10.2 RESET (0000 0000 0001 0001)
The RESET command resets the ADC to its register defaults. The command is latched by the device at the
end of the frame. A reset occurs immediately after the command is latched. The host must wait for tREGACQ
after reset before communicating with the device to ensure the registers have assumed their default settings.
The device sends an acknowledgment of FF24h when the ADC is properly RESET. The device responds with
0011h if the command word is sent but the frame is not completed and therefore the device is not reset. See
the RESET Command section for more information regarding the operation of the reset command. Figure 8-22
illustrates a properly sent RESET command frame.

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CS

SCLK

DIN RESET CRC

RESET command
latched here

DOUT Hi-Z Response 'RQ¶W &DUH 'RQ¶W &DUH 'RQ¶W &DUH 'RQ¶W &DUH 'RQ¶W &DUH Hi-Z

Figure 8-22. RESET Command Frame

8.5.1.10.3 STANDBY (0000 0000 0010 0010)

The STANDBY command places the device in a low-power standby mode. The command is latched by the
device at the end of the frame. The device enters standby mode immediately after the command is latched. See
the Standby Mode section for more information. This command has no effect if the device is already in standby
mode.
8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
The WAKEUP command returns the device to conversion mode from standby mode. This command has no
effect if the device is already in conversion mode.
8.5.1.10.5 LOCK (0000 0101 0101 0101)
The LOCK command locks the interface, preventing the device from accidentally latching unwanted commands
that can change the state of the device. When the interface is locked, the device only responds to the NULL,
RREG, and UNLOCK commands. The device continues to output conversion data even when locked.
8.5.1.10.6 UNLOCK (0000 0110 0110 0110)
The UNLOCK command unlocks the interface if previously locked by the LOCK command.
8.5.1.10.7 RREG (101a aaaa annn nnnn)
The RREG is used to read the device registers. The binary format of the command word is 101a aaaa annn
nnnn, where a aaaa a is the binary address of the register to begin reading and nnn nnnn is the unsigned
binary number of consecutive registers to read minus one. There are two cases for reading registers on the
ADS131M04. When reading a single register (nnn nnnn = 000 0000b), the device outputs the register contents in
the command response word of the following frame. If multiple registers are read using a single command (nnn
nnnn > 000 0000b), the device outputs the requested register data sequentially in order of addresses.

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8.5.1.10.7.1 Reading a Single Register

Read a single register from the device by specifying nnn nnnn as zero in the RREG command word. As with
all SPI commands on the ADS131M04, the response occurs on the output in the frame following the command.
Instead of a unique acknowledgment word, the response word is the contents of the register whose address is
specified in the command word. Figure 8-23 shows an example of reading a single register.

DRDY

CS

SCLK

DIN RREG CRC Command CRC

Register
DOUT Hi-Z Response Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data CRC Hi-Z Channel 0 Data
Data

Figure 8-23. Reading a Single Register

8.5.1.10.7.2 Reading Multiple Registers

Multiple registers are read from the device when nnn nnnn is specified as a number greater than zero in the
RREG command word. Like all SPI commands on the ADS131M04, the response occurs on the output in the
frame following the command. Instead of a single acknowledgment word, the response spans multiple words
in order to shift out all requested registers. Continue toggling SCLK to accommodate outputting the entire
data stream. ADC conversion data are not output in the frame following an RREG command to read multiple
registers. Figure 8-24 shows an example of reading multiple registers.
CS

SCLK

DIN RREG CRC Command CRC

RREG 1st UHJLVWHU¶V 2nd UHJLVWHU¶V N-1th UHJLVWHU¶V Nth UHJLVWHU¶V

DOUT Hi-Z Response Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data CRC Hi-Z CRC Hi-Z
ack data data data data

Figure 8-24. Reading Multiple Registers

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8.5.1.10.8 WREG (011a aaaa annn nnnn)

The WREG command allows writing an arbitrary number of contiguous device registers. The binary format of the
command word is 011a aaaa annn nnnn, where a aaaa a is the binary address of the register to begin writing
and nnn nnnn is the unsigned binary number of consecutive registers to write minus one. Send the data to be
written immediately following the command word. Write the intended contents of each register into individual
words, MSB aligned.
If the input CRC is enabled, write this CRC after the register data. The registers are written to the device as
they are shifted into DIN. Therefore, a CRC error does not prevent an erroneous value from being written to a
register. An input CRC error during a WREG command sets the CRC_ERR bit in the STATUS register.
The device ignores writes to read-only registers or to out-of-bounds addresses. Gaps in the register map
address space are still included in the parameter nnn nnnn, but are not writeable so no change is made to them.
The response to the WREG command that occurs in the following frame appears as 010a aaaa ammm mmmm
where mmm mmmm is the number of registers actually written minus one. This number can be checked by the
host against nnn nnnn to ensure the expected number of registers are written.
Figure 8-25 shows a typical WREG sequence. In this example, the number of registers to write is larger than
the number of ADC channels and, therefore, the frame is extended beyond the ADC channels and output CRC
word. Ensure all of the ADC data and output CRC are shifted out during each transaction where new data are
available. Therefore, the frame must be extended beyond the number of words required to send the register data
in some cases.
DRDY

CS

SCLK

1st UHJLVWHU¶V 2nd UHJLVWHU¶V 3rd UHJLVWHU¶V 4th UHJLVWHU¶V 5th UHJLVWHU¶V 6th UHJLVWHU¶V N-1th UHJLVWHU¶V Nth UHJLVWHU¶V
DIN WREG CRC Command CRC
data data data data data data data data

DOUT Hi-Z Response Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data CRC 'RQ¶W &DUH Hi-Z Response Channel 0 Data

Figure 8-25. Writing Registers

8.5.1.11 Short SPI Frames

The SPI frame can be shortened to only send commands and receive responses if the ADCs are disabled and
no ADC data are being output by the device. Read out all of the expected output data words from each sample
period if the ADCs are enabled. Reading all of the data output with each frame ensures predictable DRDY pin
behavior. If reading out all the data on each output data period is not feasible, see the Collecting Data for the
First Time or After a Pause in Data Collection section on how to begin reading data again after a pause from
when the ADCs were last enabled.
A short frame is not possible when using the RESET command. A full frame must be provided for a device reset
to take place when providing the RESET command.

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8.5.2 Synchronization
Synchronization can be performed by the host to ensure the ADC conversions are synchronized to an external
event. For example, synchronization can realign the data capture to the expected timing of the host if a glitch on
the clock causes the host and device to become out of synchronization.
Provide a negative pulse on the SYNC/RESET pin with a duration less than tw(RSL) but greater than a CLKIN
period to trigger synchronization. The device internally compares the leading negative edge of the pulse to its
internal clock that tracks the data rate. The internal data rate clock has timing equivalent to the DRDY pin if
configured to assert with a phase calibration setting of 0b. If the negative edge on SYNC/RESET aligns with
the internal data rate clock, the device is determined to be synchronized and therefore no action is taken. If
there is misalignment, the digital filters on the device are reset to be synchronized with the SYNC/RESET pulse.
Conversions are immediately restarted when the SYNC/RESET pin is toggled in global-chop mode.
The phase calibration settings on all channels are retained during synchronization. Thus, channels with non-zero
phase calibration settings generate conversion results less than a data rate period after the synchronization
event occurs. However, the results can be corrupted and are not settled until the respective channels have at
least three conversion cycles for the sinc3 filter to settle.

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8.6 ADS131M04 Registers

Table 8-12 lists the ADS131M04 registers. All register offset addresses not listed in Table 8-12 should be
considered as reserved locations and the register contents should not be modified.
Table 8-12. Register Map
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
RESET
ADDRESS REGISTER VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DEVICE SETTINGS AND INDICATORS (Read-Only Registers)
RESERVED CHANCNT[3:0]
00h ID 24xxh
RESERVED
LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET WLENGTH[1:0]
01h STATUS 0500h
RESERVED DRDY3 DRDY2 DRDY1 DRDY0
GLOBAL SETTINGS ACROSS CHANNELS
RESERVED REGCRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0]
02h MODE 0510h
RESERVED TIMEOUT DRDY_SEL[1:0] DRDY_HiZ DRDY_FMT
RESERVED CH3_EN CH2_EN CH1_EN CH0_EN
03h CLOCK 0F0Eh
RESERVED TBM OSR[2:0] PWR[1:0]
RESERVED PGAGAIN3[2:0] RESERVED PGAGAIN2[2:0]
04h GAIN 0000h
RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0]
RESERVED GC_DLY[3:0] GC_EN
06h CFG 0600h
CD_ALLCH CD_NUM[2:0] CD_LEN[2:0] CD_EN
CD_TH_MSB[15:8]
07h THRSHLD_MSB 0000h
CD_TH_MSB[7:0]
CD_TH_LSB[7:0]
08h THRSHLD_LSB 0000h
RESERVED DCBLOCK[3:0]
CHANNEL-SPECIFIC SETTINGS
PHASE0[9:2]
09h CH0_CFG 0000h
PHASE0[1:0] RESERVED DCBLK0_DIS0 MUX0[1:0]
OCAL0_MSB[15:8]
0Ah CH0_OCAL_MSB 0000h
OCAL0_MSB[7:0]
OCAL0_LSB[7:0]
0Bh CH0_OCAL_LSB 0000h
RESERVED
GCAL0_MSB[15:8]
0Ch CH0_GCAL_MSB 8000h
GCAL0_MSB[7:0]
GCAL0_LSB[7:0]
0Dh CH0_GCAL_LSB 0000h
RESERVED
PHASE1[9:2]
0Eh CH1_CFG 0000h
PHASE1[1:0] RESERVED DCBLK1_DIS0 MUX1[1:0]
OCAL1_MSB[15:8]
0Fh CH1_OCAL_MSB 0000h
OCAL1_MSB[7:0]
OCAL1_LSB[7:0]
10h CH1_OCAL_LSB 0000h
RESERVED
GCAL1_MSB[15:8]
11h CH1_GCAL_MSB 8000h
GCAL1_MSB[7:0]
GCAL1_LSB[7:0]
12h CH1_GCAL_LSB 0000h
RESERVED
PHASE2[9:2]
13h CH2_CFG 0000h
PHASE2[1:0] RESERVED DCBLK2_DIS0 MUX2[1:0]
OCAL2_MSB[15:8]
14h CH2_OCAL_MSB 0000h
OCAL2_MSB[7:0]
OCAL2_LSB[7:0]
15h CH2_OCAL_LSB 0000h
RESERVED
GCAL2_MSB[15:8]
16h CH2_GCAL_MSB 8000h
GCAL2_MSB[7:0]
GCAL2_LSB[7:0]
17h CH2_GCAL_LSB 0000h
RESERVED

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Table 8-12. Register Map (continued)

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
RESET
ADDRESS REGISTER VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
PHASE3[9:2]
18h CH3_CFG 0000h
PHASE3[1:0] RESERVED DCBLK3_DIS0 MUX3[1:0]
OCAL3_MSB[15:8]
19h CH3_OCAL_MSB 0000h
OCAL3_MSB[7:0]
OCAL3_LSB[7:0]
1Ah CH3_OCAL_LSB 0000h
RESERVED
GCAL3_MSB[15:8]
1Bh CH3_GCAL_MSB 8000h
GCAL3_MSB[7:0]
GCAL3_LSB[7:0]
1Ch CH3_GCAL_LSB 0000h
RESERVED
REGISTER MAP CRC AND RESERVED REGISTERS
REG_CRC[15:8]
3Eh REGMAP_CRC 0000h
REG_CRC[7:0]
RESERVED
3Fh RESERVED 0000h
RESERVED

Complex bit access types are encoded to fit into small table cells. Table 8-13 shows the codes that are used for
access types in this section.
Table 8-13. Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

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8.6.1 ID Register (Address = 0h) [reset = 24xxh]

The ID register is shown in Figure 8-26 and described in Table 8-14.
Return to the Summary Table.
Figure 8-26. ID Register
15 14 13 12 11 10 9 8
RESERVED CHANCNT[3:0]
R-0010b R-0100b

7 6 5 4 3 2 1 0
RESERVED
R-xxxxxxxxb

Table 8-14. ID Register Field Descriptions

Bit Field Type Reset Description
15:12 RESERVED R 0010b Reserved
Always reads 0010b
11:8 CHANCNT[3:0] R 0100b Channel count Always reads 0100b
7:0 RESERVED R xxxxxxxxb Reserved
Values are subject to change without notice.

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8.6.2 STATUS Register (Address = 1h) [reset = 0500h]

The STATUS register is shown in Figure 8-27 and described in Table 8-15.
Return to the Summary Table.
Figure 8-27. STATUS Register
15 14 13 12 11 10 9 8
LOCK F_RESYNC REG_MAP CRC_ERR CRC_TYPE RESET WLENGTH[1:0]
R-0b R-0b R-0b R-0b R-0b R-1b R-01b

7 6 5 4 3 2 1 0
RESERVED DRDY3 DRDY2 DRDY1 DRDY0
R-0000b R-0b R-0b R-0b R-0b

Table 8-15. STATUS Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R 0b SPI interface lock indicator

0b = Unlocked (default)

1b = Locked

14 F_RESYNC R 0b ADC resynchronization indicator.

This bit is set each time the ADC resynchronizes.

0b = No resynchronization (default)

1b = Resynchronization occurred

13 REG_MAP R 0b Register map CRC fault indicator

0b = No change in the register map CRC (default)

1b = Register map CRC changed

12 CRC_ERR R 0b SPI input CRC error indicator

0b = No CRC error (default)

1b = Input CRC error occured

11 CRC_TYPE R 0b CRC type

0b = 16 bit CCITT (default)

1b = 16 bit ANSI

10 RESET R 1b Reset status

0b = Not reset

1b = Reset occurred (default)

9:8 WLENGTH[1:0] R 01b Data word length

00b = 16 bit

01b = 24 bits (default)

10b = 32 bits; zero padding

11b = 32 bits; sign extension for 24-bit ADC data

7:4 RESERVED R 0000b Reserved

Always reads 0000b

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Table 8-15. STATUS Register Field Descriptions (continued)

Bit Field Type Reset Description
3 DRDY3 R 0b Channel 3 ADC data available indicator

0b = No new data available

1b = New data are available

2 DRDY2 R 0b Channel 2 ADC data available indicator

0b = No new data available

1b = New data are available

1 DRDY1 R 0b Channel 1 ADC data available indicator

0b = No new data available

1b = New data are available

0 DRDY0 R 0b Channel 0 ADC data available indicator

0b = No new data available

1b = New data are available

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8.6.3 MODE Register (Address = 2h) [reset = 0510h]

The MODE register is shown in Figure 8-28 and described in Table 8-16.
Return to the Summary Table.
Figure 8-28. MODE Register
15 14 13 12 11 10 9 8
RESERVED REG_CRC_EN RX_CRC_EN CRC_TYPE RESET WLENGTH[1:0]
R/W-00b R/W-0b R/W-0b R/W-0b R/W-1b R/W-01b

7 6 5 4 3 2 1 0
RESERVED TIMEOUT DRDY_SEL[1:0] DRDY_HiZ DRDY_FMT
R/W-000b R/W-1b R/W-00b R/W-0b R/W-0b

Table 8-16. MODE Register Field Descriptions

Bit Field Type Reset Description
15:14 RESERVED R/W 00b Reserved
Always write 00b
13 REG_CRC_EN R/W 0b Register map CRC enable

0b = Register CRC disabled (default)

1b = Register CRC enabled

12 RX_CRC_EN R/W 0b SPI input CRC enable

0b = Disabled (default)

1b = Enabled

11 CRC_TYPE R/W 0b SPI input and output, register map CRC type

0b = 16-bit CCITT (default)

1b = 16-bit ANSI

10 RESET R/W 1b Reset

Write 0b to clear this bit in the STATUS register

0b = No reset

1b = Reset occurred (default by definition)

9:8 WLENGTH[1:0] R/W 01b Data word length selection

00b = 16 bits

01b = 24 bits (default)

10b = 32 bits; LSB zero padding

11b = 32 bits; MSB sign extension

7:5 RESERVED R/W 000b Reserved

Always write 000b
4 TIMEOUT R/W 1b SPI Timeout enable

0b = Disabled

1b = Enabled (default)

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Table 8-16. MODE Register Field Descriptions (continued)

Bit Field Type Reset Description
3:2 DRDY_SEL[1:0] R/W 00b DRDY pin signal source selection

00b = Most lagging enabled channel (default)

01b = Logic OR of all the enabled channels

10b = Most leading enabled channel

11b = Most leading enabled channel

1 DRDY_HiZ R/W 0b DRDY pin state when conversion data are not available

0b = Logic high (default)

1b = High impedance

0 DRDY_FMT R/W 0b DRDY signal format when conversion data are available

0b = Logic low (default)

1b = Low pulse with a fixed duration

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8.6.4 CLOCK Register (Address = 3h) [reset = 0F0Eh]

The CLOCK register is shown in Figure 8-29 and described in Table 8-17.
Return to the Summary Table.
Figure 8-29. CLOCK Register
15 14 13 12 11 10 9 8
RESERVED CH3_EN CH2_EN CH1_EN CH0_EN
R-0000b R/W-1b R/W-1b R/W-1b R/W-1b
7 6 5 4 3 2 1 0
RESERVED TBM OSR[2:0] PWR[1:0]
R/W-00b R/W-0b R/W-011b R/W-10b

Table 8-17. CLOCK Register Field Descriptions

Bit Field Type Reset Description
15:12 RESERVED R 0000b Reserved
Always reads 0000b
11 CH3_EN R/W 1b Channel 3 ADC enable

0b = Disabled

1b = Enabled (default)

10 CH2_EN R/W 1b Channel 2 ADC enable

0b = Disabled

1b = Enabled (default)

9 CH1_EN R/W 1b Channel 1 ADC enable

0b = Disabled

1b = Enabled (default)

8 CH0_EN R/W 1b Channel 0 ADC enable

0b = Disabled

1b = Enabled (default)

7:6 RESERVED R/W 00b Reserved

Always write 00b
5 TBM R/W 0b Modulator oversampling ratio 64 selection (TurboMode)

0b = OSR set by Bit 4:2 , i.e. OSR[2:0]

1b = OSR of 64 is selected

4:2 OSR[2:0] R/W 011b Modulator oversampling ratio selection

000b = 128

001b = 256

010b = 512

011b = 1024 (default)

100b = 2048

101b = 4096

110b = 8192

111b = 16256

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Table 8-17. CLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
1:0 PWR[1:0] R/W 10b Power mode selection

00b = Very-low-power

01b = Low-power

10b = High-resolution (default)

11b = High-resolution

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8.6.5 GAIN1 Register (Address = 4h) [reset = 0000h]

The GAIN1 register is shown in Figure 8-30 and described in Table 8-18.
Return to the Summary Table.
Figure 8-30. GAIN1 Register
15 14 13 12 11 10 9 8
RESERVED PGAGAIN3[2:0] RESERVED PGAGAIN2[2:0]
R/W-0b R/W-000b R/W-0b R/W-000b
7 6 5 4 3 2 1 0
RESERVED PGAGAIN1[2:0] RESERVED PGAGAIN0[2:0]
R/W-0b R/W-000b R/W-0b R/W-000b

Table 8-18. GAIN1 Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R/W 0b Reserved
Always write 0b
14:12 PGAGAIN3[2:0] R/W 000b PGA gain selection for channel 3

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

11 RESERVED R/W 0b Reserved

Always write 0b
10:8 PGAGAIN2[2:0] R/W 000b PGA gain selection for channel 2

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

7 RESERVED R/W 0b Reserved

Always write 0b

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Table 8-18. GAIN1 Register Field Descriptions (continued)

Bit Field Type Reset Description
6:4 PGAGAIN1[2:0] R/W 000b PGA gain selection for channel 1

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

3 RESERVED R/W 0b Reserved

Always write 0b
2:0 PGAGAIN0[2:0] R/W 000b PGA gain selection for channel 0

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = G64

111b = 128

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8.6.6 RESERVED Register (Address = 5h) [reset = 0000h]

The RESERVED register is shown in Figure 8-31 and described in Table 8-19.
Return to the Summary Table.
Figure 8-31. RESERVED Register
15 14 13 12 11 10 9 8
RESERVED
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED
R/W-00000000b

Table 8-19. RESERVED Register Field Descriptions

Bit Field Type Reset Description
15:0 RESERVED R/W 00000000 Reserved
00000000b Always write 0000000000000000b

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8.6.7 CFG Register (Address = 6h) [reset = 0600h]

The CFG register is shown in Figure 8-32 and described in Table 8-20.
Return to the Summary Table.
Figure 8-32. CFG Register
15 14 13 12 11 10 9 8
RESERVED GC_DLY[3:0] GC_EN
R/W-000b R/W-0011b R/W-0b

7 6 5 4 3 2 1 0
CD_ALLCH CD_NUM[2:0] CD_LEN[2:0] CD_EN
R/W-0b R/W-000b R/W-000b R/W-0b

Table 8-20. CFG Register Field Descriptions

Bit Field Type Reset Description
15:13 RESERVED R/W 000b Reserved
Always write 000b
12:9 GC_DLY[3:0] R/W 0011b Global-chop delay selection
Delay in modulator clock periods before measurement begins

0000b = 2

0001b = 4

0010b = 8

0011b = 16 (default)

0100b = 32

0101b = 64

0110b = 128

0111b = 256

1000b = 512

1001b = 1024

1010b = 2048

1011b = 4096

1100b = 8192

1101b = 16384

1110b = 32768

1111b = 65536

8 GC_EN R/W 0b Global-chop enable

0b = Disabled (default)

1b = Enabled

7 CD_ALLCH R/W 0b Current-detect channel selection

Channels required to trigger current-detect

0b = Any channel (default)

1b = All channels

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Table 8-20. CFG Register Field Descriptions (continued)

Bit Field Type Reset Description
6:4 CD_NUM[2:0] R/W 000b Number of current-detect exceeded thresholds selection
Number of current-detect exceeded thresholds to trigger a detection

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

3:1 CD_LEN[2:0] R/W 000b Current-detect measurement length selection

Current-detect measurement length in conversion periods

000b = 128 (default)

001b = 256

010b = 512

011b = 768

100b = 1280

101b = 1792

110b = 2560

111b = 3584

0 CD_EN R/W 0b Current-detect mode enable

0b = Disabled (default)

1b = Enabled

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8.6.8 THRSHLD_MSB Register (Address = 7h) [reset = 0000h]

The THRSHLD_MSB register is shown in Figure 8-33 and described in Table 8-21.
Return to the Summary Table.
Figure 8-33. THRSHLD_MSB Register
15 14 13 12 11 10 9 8
CD_TH_MSB[15:8]
R/W-00000000b

7 6 5 4 3 2 1 0
CD_TH_MSB[7:0]
R/W-00000000b

Table 8-21. THRSHLD_MSB Register Field Descriptions

Bit Field Type Reset Description
15:0 CD_TH_MSB[15:0] R/W 00000000 Current-detect mode threshold MSB
00000000b

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8.6.9 THRSHLD_LSB Register (Address = 8h) [reset = 0000h]

The THRSHLD_LSB register is shown in Figure 8-34 and described in Table 8-22.
Return to the Summary Table.
Figure 8-34. THRSHLD_LSB Register
15 14 13 12 11 10 9 8
CD_TH_LSB[7:0]
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED DCBLOCK
R-0000b R/W-0000b

Table 8-22. THRSHLD_LSB Register Field Descriptions

Bit Field Type Reset Description
15:8 CD_TH_LSB[7:0] R/W 00000000b Current-detect mode threshold LSB
7:4 RESERVED R 0000b Reserved
Always write 0000b
3:0 DCBLOCK[3:0] R/W 0000b DC block filter setting, see Table 8-4for details.
Value of coefficient a

0000b = DC block filter disabled

0001b = 1/4

0010b = 1/8

0011b = 1/16

0100b = 1/32

0101b = 1/64

0110b = 1/128

0111b = 1/256

1000b = 1/512

1001b = 1/1024

1010b = 1/2048

1011b = 1/4096

1100b = 1/8192

1101b = 1/16384

1110b = 1/32768

1111b = 1/65536

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8.6.10 CH0_CFG Register (Address = 9h) [reset = 0000h]

The CH0_CFG register is shown in Figure 8-35 and described in Table 8-23.
Return to the Summary Table.
Figure 8-35. CH0_CFG Register
15 14 13 12 11 10 9 8
PHASE0[9:2]
R/W-0000000000b

7 6 5 4 3 2 1 0
PHASE0[1:0] RESERVED DCBLK0_DIS0 MUX0[1:0]
R/W-0000000000b R-000b R/W-0b R/W-00b

Table 8-23. CH0_CFG Register Field Descriptions

Bit Field Type Reset Description
15:6 PHASE0[9:0] R/W 0000000000 Channel 0 phase delay
b Phase delay in modulator clock cycles provided in two's complement
format. See Table 8-5 for details.
5:3 RESERVED R 000b Reserved
Always write 000b
2 DCBLK0_DIS0 R/W 0b DC block filter for channel 0 disable

0b = Controlled by DCBLOCK[3:0] (detault)

1b = Disabled for this channel

1:0 MUX0[1:0] R/W 00b Channel 0 input selection

00b = AIN0P and AIN0N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

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8.6.11 CH0_OCAL_MSB Register (Address = Ah) [reset = 0000h]

The CH0_OCAL_MSB register is shown in Figure 8-36 and described in Table 8-24.
Return to the Summary Table.
Figure 8-36. CH0_OCAL_MSB Register
15 14 13 12 11 10 9 8
OCAL0_MSB[15:8]
R/W-00000000b

7 6 5 4 3 2 1 0
OCAL0_MSB[7:0]
R/W-00000000b

Table 8-24. CH0_OCAL_MSB Register Field Descriptions

Bit Field Type Reset Description
15:0 OCAL0_MSB[15:0] R/W 00000000 Channel 0 offset calibration register bits [23:8]
00000000b

8.6.12 CH0_OCAL_LSB Register (Address = Bh) [reset = 0000h]

The CH0_OCAL_LSB register is shown in Figure 8-37 and described in Table 8-25.
Return to the Summary Table.
Figure 8-37. CH0_OCAL_LSB Register
15 14 13 12 11 10 9 8
OCAL0_LSB[7:0]
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED
R-00000000b

Table 8-25. CH0_OCAL_LSB Register Field Descriptions

Bit Field Type Reset Description
15:8 OCAL0_LSB[7:0] R/W 00000000b Channel 0 offset calibration register bits [7:0]
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

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8.6.13 CH0_GCAL_MSB Register (Address = Ch) [reset = 8000h]

The CH0_GCAL_MSB register is shown in Figure 8-38 and described in Table 8-26.
Return to the Summary Table.
Figure 8-38. CH0_GCAL_MSB Register
15 14 13 12 11 10 9 8
GCAL0_MSB[15:8]
R/W-10000000b

7 6 5 4 3 2 1 0
GCAL0_MSB[7:0]
R/W-00000000b

Table 8-26. CH0_GCAL_MSB Register Field Descriptions

Bit Field Type Reset Description
15:0 GCAL0_MSB[15:0] R/W 1000000000 Channel 0 gain calibration register bits [23:8]
000000b

8.6.14 CH0_GCAL_LSB Register (Address = Dh) [reset = 0000h]

The CH0_GCAL_LSB register is shown in Figure 8-39 and described in Table 8-27.
Return to the Summary Table.
Figure 8-39. CH0_GCAL_LSB Register
15 14 13 12 11 10 9 8
GCAL0_LSB[7:0]
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED
R-00000000b

Table 8-27. CH0_GCAL_LSB Register Field Descriptions

Bit Field Type Reset Description
15:8 GCAL0_LSB[7:0] R/W 00000000b Channel 0 gain calibration register bits [7:0]
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

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8.6.15 CH1_CFG Register (Address = Eh) [reset = 0000h]

The CH1_CFG register is shown in Figure 8-40 and described in Table 8-28.
Return to the Summary Table.
Figure 8-40. CH1_CFG Register
15 14 13 12 11 10 9 8
PHASE1[9:2]
R/W-0000000000b

7 6 5 4 3 2 1 0
PHASE1[1:0] RESERVED DCBLK1_DIS0 MUX1[1:0]
R/W-0000000000b R-000b R/W-0b R/W-00b

Table 8-28. CH1_CFG Register Field Descriptions

Bit Field Type Reset Description
15:6 PHASE1[9:0] R/W 0000000000 Channel 1 phase delay
b Phase delay in modulator clock cycles provided in two's complement
format. See Table 8-5 for details.
5:3 RESERVED R 000b Reserved
Always reads 000b
2 DCBLK1_DIS0 R/W 0b DC block filter for channel 1 disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0 MUX1[1:0] R/W 00b Channel 1 input selection

00b = AIN1P and AIN1N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

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8.6.16 CH1_OCAL_MSB Register (Address = Fh) [reset = 0000h]

The CH1_OCAL_MSB register is shown in Figure 8-41 and described in Table 8-29.
Return to the Summary Table.
Figure 8-41. CH1_OCAL_MSB Register
15 14 13 12 11 10 9 8
OCAL1_MSB[15:8]
R/W-00000000b

7 6 5 4 3 2 1 0
OCAL1_MSB[7:0]
R/W-00000000b

Table 8-29. CH1_OCAL_MSB Register Field Descriptions

Bit Field Type Reset Description
15:0 OCAL1_MSB[15:0] R/W 00000000 Channel 1 offset calibration register bits [23:8]
00000000b

8.6.17 CH1_OCAL_LSB Register (Address = 10h) [reset = 0000h]

The CH1_OCAL_LSB register is shown in Figure 8-42 and described in Table 8-30.
Return to the Summary Table.
Figure 8-42. CH1_OCAL_LSB Register
15 14 13 12 11 10 9 8
OCAL1_LSB[7:0]
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED
R-00000000b

Table 8-30. CH1_OCAL_LSB Register Field Descriptions

Bit Field Type Reset Description
15:8 OCAL1_LSB[7:0] R/W 00000000b Channel 1 offset calibration register bits [7:0]
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

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8.6.18 CH1_GCAL_MSB Register (Address = 11h) [reset = 8000h]

The CH1_GCAL_MSB register is shown in Figure 8-43 and described in Table 8-31.
Return to the Summary Table.
Figure 8-43. CH1_GCAL_MSB Register
15 14 13 12 11 10 9 8
GCAL1_MSB[15:8]
R/W-10000000b

7 6 5 4 3 2 1 0
GCAL1_MSB[7:0]
R/W-00000000b

Table 8-31. CH1_GCAL_MSB Register Field Descriptions

Bit Field Type Reset Description
15:0 GCAL1_MSB[15:0] R/W 1000000000 Channel 1 gain calibration register bits [23:8]
000000b

8.6.19 CH1_GCAL_LSB Register (Address = 12h) [reset = 0000h]

The CH1_GCAL_LSB register is shown in Figure 8-44 and described in Table 8-32.
Return to the Summary Table.
Figure 8-44. CH1_GCAL_LSB Register
15 14 13 12 11 10 9 8
GCAL1_LSB[7:0]
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED
R-00000000b

Table 8-32. CH1_GCAL_LSB Register Field Descriptions

Bit Field Type Reset Description
15:8 GCAL1_LSB[7:0] R/W 00000000b Channel 1 gain calibration register bits [7:0]
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

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8.6.20 CH2_CFG Register (Address = 13h) [reset = 0000h]

The CH2_CFG register is shown in Figure 8-45 and described in Table 8-33.
Return to the Summary Table.
Figure 8-45. CH2_CFG Register
15 14 13 12 11 10 9 8
PHASE2[9:2]
R/W-0000000000b

7 6 5 4 3 2 1 0
PHASE2[2:0] RESERVED DCBLK2_DIS0 MUX2[1:0]
R/W-0000000000b R-000b R/W-0b R/W-00b

Table 8-33. CH2_CFG Register Field Descriptions

Bit Field Type Reset Description
15:6 PHASE2[9:0] R/W 0000000000 Channel 2 phase delay
b Phase delay in modulator clock cycles provided in two's complement
format. See Table 8-5 for details.
5:3 RESERVED R 000b Reserved
Always reads 000b
2 DCBLK2_DIS0 R/W 0b DC block filter for channel 2 disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0 MUX2[1:0] R/W 00b Channel 2 input selection

00b = AIN2P and AIN2N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

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8.6.21 CH2_OCAL_MSB Register (Address = 14h) [reset = 0000h]

The CH2_OCAL_MSB register is shown in Figure 8-46 and described in Table 8-34.
Return to the Summary Table.
Figure 8-46. CH2_OCAL_MSB Register
15 14 13 12 11 10 9 8
OCAL2_MSB[15:8]
R/W-00000000b

7 6 5 4 3 2 1 0
OCAL2_MSB[7:0]
R/W-00000000b

Table 8-34. CH2_OCAL_MSB Register Field Descriptions

Bit Field Type Reset Description
15:0 OCAL2_MSB[15:0] R/W 00000000 Channel 2 offset calibration register bits [23:8]
00000000b

8.6.22 CH2_OCAL_LSB Register (Address = 15h) [reset = 0000h]

The CH2_OCAL_LSB register is shown in Figure 8-47 and described in Table 8-35.
Return to the Summary Table.
Figure 8-47. CH2_OCAL_LSB Register
15 14 13 12 11 10 9 8
OCAL2_LSB[7:0]
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED
R-00000000b

Table 8-35. CH2_OCAL_LSB Register Field Descriptions

Bit Field Type Reset Description
15:8 OCAL2_LSB[7:0] R/W 00000000b Channel 2 offset calibration register bits [7:0]
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

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8.6.23 CH2_GCAL_MSB Register (Address = 16h) [reset = 8000h]

The CH2_GCAL_MSB register is shown in Figure 8-48 and described in Table 8-36.
Return to the Summary Table.
Figure 8-48. CH2_GCAL_MSB Register
15 14 13 12 11 10 9 8
GCAL2_MSB[15:8]
R/W-10000000b

7 6 5 4 3 2 1 0
GCAL2_MSB[7:0]
R/W-00000000b

Table 8-36. CH2_GCAL_MSB Register Field Descriptions

Bit Field Type Reset Description
15:0 GCAL2_MSB[15:0] R/W 1000000000 Channel 2 gain calibration register bits [23:8]
000000b

8.6.24 CH2_GCAL_LSB Register (Address = 17h) [reset = 0000h]

The CH2_GCAL_LSB register is shown in Figure 8-49 and described in Table 8-37.
Return to the Summary Table.
Figure 8-49. CH2_GCAL_LSB Register
15 14 13 12 11 10 9 8
GCAL2_LSB[7:0]
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED
R-00000000b

Table 8-37. CH2_GCAL_LSB Register Field Descriptions

Bit Field Type Reset Description
15:8 GCAL2_LSB[7:0] R/W 00000000b Channel 2 gain calibration register bits [7:0]
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

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8.6.25 CH3_CFG Register (Address = 18h) [reset = 0000h]

The CH3_CFG register is shown in Figure 8-50 and described in Table 8-38.
Return to the Summary Table.
Figure 8-50. CH3_CFG Register
15 14 13 12 11 10 9 8
PHASE3[9:2]
R/W-0000000000b

7 6 5 4 3 2 1 0
PHASE3[1:0] RESERVED DCBLK3_DIS0 MUX3[1:0]
R/W-0000000000b R-000b R/W-0b R/W-00b

Table 8-38. CH3_CFG Register Field Descriptions

Bit Field Type Reset Description
15:6 PHASE3[9:0] R/W 0000000000 Channel 3 phase delay
b Phase delay in modulator clock cycles provided in two's complement
format. See Table 8-5 for details.
5:3 RESERVED R 000b Reserved
Always reads 000b
2 DCBLK3_DIS0 R/W 0b DC block filter for channel 3 disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0 MUX3[1:0] R/W 00b Channel 3 input selection

00b = AIN3P and AIN3N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

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8.6.26 CH3_OCAL_MSB Register (Address = 19h) [reset = 0000h]

The CH3_OCAL_MSB register is shown in Figure 8-51 and described in Table 8-39.
Return to the Summary Table.
Figure 8-51. CH3_OCAL_MSB Register
15 14 13 12 11 10 9 8
OCAL3_MSB[15:8]
R/W-00000000b

7 6 5 4 3 2 1 0
OCAL3_MSB[7:0]
R/W-00000000b

Table 8-39. CH3_OCAL_MSB Register Field Descriptions

Bit Field Type Reset Description
15:0 OCAL3_MSB[15:0] R/W 00000000 Channel 3 offset calibration register bits [23:8]
00000000b

8.6.27 CH3_OCAL_LSB Register (Address = 1Ah) [reset = 0000h]

The CH3_OCAL_LSB register is shown in Figure 8-52 and described in Table 8-40.
Return to the Summary Table.
Figure 8-52. CH3_OCAL_LSB Register
15 14 13 12 11 10 9 8
OCAL3_LSB[7:0]
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED
R-00000000b

Table 8-40. CH3_OCAL_LSB Register Field Descriptions

Bit Field Type Reset Description
15:8 OCAL3_LSB[7:0] R/W 00000000b Channel 3 offset calibration register bits [7:0]
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

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8.6.28 CH3_GCAL_MSB Register (Address = 1Bh) [reset = 8000h]

The CH3_GCAL_MSB register is shown in Figure 8-53 and described in Table 8-41.
Return to the Summary Table.
Figure 8-53. CH3_GCAL_MSB Register
15 14 13 12 11 10 9 8
GCAL3_MSB[15:8]
R/W-10000000b

7 6 5 4 3 2 1 0
GCAL3_MSB[7:0]
R/W-00000000b

Table 8-41. CH3_GCAL_MSB Register Field Descriptions

Bit Field Type Reset Description
15:0 GCAL3_MSB[15:0] R/W 1000000000 Channel 3 gain calibration register bits [23:8]
000000b

8.6.29 CH3_GCAL_LSB Register (Address = 1Ch) [reset = 0000h]

The CH3_GCAL_LSB register is shown in Figure 8-54 and described in Table 8-42.
Return to the Summary Table.
Figure 8-54. CH3_GCAL_LSB Register
15 14 13 12 11 10 9 8
GCAL3_LSB[7:0]
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED
R-00000000b

Table 8-42. CH3_GCAL_LSB Register Field Descriptions

Bit Field Type Reset Description
15:8 GCAL3_LSB[7:0] R/W 00000000b Channel 3 gain calibration register bits [7:0]
7:0 RESERVED R 00000000b Reserved
Always reads 00000000b

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8.6.30 REGMAP_CRC Register (Address = 3Eh) [reset = 0000h]

The REGMAP_CRC register is shown in Figure 8-55 and described in Table 8-43.
Return to the Summary Table.
Figure 8-55. REGMAP_CRC Register
15 14 13 12 11 10 9 8
REG_CRC[15:8]
R-0000000000000000b

7 6 5 4 3 2 1 0
REG_CRC[7:0]
R-0000000000000000b

Table 8-43. REGMAP_CRC Register Field Descriptions

Bit Field Type Reset Description
15:0 REG_CRC[15:0] R 00000000 Register map CRC
00000000b

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8.6.31 RESERVED Register (Address = 3Fh) [reset = 0000h]

The RESERVED register is shown in Figure 8-56 and described in Table 8-44.
Return to the Summary Table.
Figure 8-56. RESERVED Register
15 14 13 12 11 10 9 8
RESERVED
R/W-00000000b

7 6 5 4 3 2 1 0
RESERVED
R/W-00000000b

Table 8-44. RESERVED Register Field Descriptions

Bit Field Type Reset Description
15:0 RESERVED R/W 00000000 Reserved,
00000000b Always write 0000000000000000b

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

9.1.1 Unused Inputs and Outputs
Leave any unused analog inputs floating or connect them to AGND.
Do not float unused digital inputs because excessive power-supply leakage current can result. Tie all unused
digital inputs to the appropriate levels, DVDD or DGND. Leave the DRDY pin unconnected or connect it to
DVDD using a weak pullup resistor if unused.
9.1.2 Antialiasing
An analog low-pass filter is required in front of each of the channel inputs to prevent out-of-band noise
and interferers from coupling into the band of interest. Because the ADS131M04 is a delta-sigma ADC, the
integrated digital filter provides substantial attenuation for frequencies outside of the band of interest up to the
frequencies adjacent to fMOD. Therefore, a single-order RC filter provides sufficient antialiasing protection in the
vast majority of applications.
Choosing the values of the resistor and capacitor depends on the desired cutoff frequency, limiting source
impedance for the ADC inputs, and providing enough instantaneous charge to the ADC input sampling
circuit through the filter capacitor. Figure 9-1 shows the recommended filter component values. These
recommendations are sufficient for CLKIN frequencies between 2 MHz and 8.2 MHz.
1k

To ADC
10 nF Inputs

1k

Figure 9-1. Recommended Antialiasing Circuitry

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9.1.3 Minimum Interface Connections

Figure 9-2 depicts how the ADS131M04 can be configured for the minimum number of interface pins. This
configuration is useful when using data isolation to minimize the number of isolation channels required or when
the microcontroller (MCU) pins are limited.
The CLKIN pin requires an LVCMOS clock that can be either generated by the MCU or created using a
local LVCMOS output device. Tie the SYNC/RESET pin to DVDD in hardware if unused. The DRDY pin
can be left floating if unused. Connect either SYNC/RESET or DRDY to the MCU to ensure the MCU stays
synchronized to ADC conversions. If the MCU provides CLKIN, the CLKIN periods can be counted to determine
the sample period rather than forcing synchronization using the SYNC/RESET pin or monitoring the DRDY
pin. Synchronization cannot be regained if a bit error occurs on the clock and samples can be missed if the
SYNC/RESET or DRDY pins are not used. CS can be tied low in hardware if the ADS131M04 is the only device
on the SPI bus. Ensure the data input and output CRC are enabled and are used to guard against faulty register
reads and writes if CS is tied low permanently.
Local
Oscillator
DVDD
OR

CLKIN CLKOUT

SYNC/RESET GPIO
OR
DRDY GPIO

Device CS CS MCU

OR
SCLK SCLK

DIN MOSI

DOUT MISO

DGND

Figure 9-2. Minimum Connections Required to Operate the ADS131M04

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9.1.4 Multiple Device Configuration

Multiple ADS131M04 devices can be arranged to capture all signals simultaneously. The same clock must be
provided to all devices and the SYNC/RESET pins must be strobed simultaneously at least one time to align the
sample periods internally between devices. The phase settings of each device can be changed uniquely, but the
host must take care to record which channel in the group of devices represents the zero phase.
The devices can also share the SPI bus where only the CS pins for each device are unique. Each device can
be addressed sequentially by asserting CS for the device that the host wishes to communicate with. The DOUT
pin remains high impedance when the CS pin is high, allowing the DOUT lines to be shared between devices
as long as no two devices sharing the bus simultaneously have their CS pins low. Figure 9-3 shows multiple
devices configured for simultaneous data acquisition while sharing the SPI bus.
Monitoring the DRDY output of only one of the devices is sufficient because all devices convert simultaneously.

Device 1
SYNC/RESET GPIO
CLKIN CLKOUT
DRDY IRQ
SCLK SCLK
MCU
DIN MOSI
DOUT MISO
CS CS1
CS2

...
Device 2 CSn

SYNC/RESET
CLKIN
DRDY
SCLK
DIN
DOUT
CS

Device n
SYNC/RESET
CLKIN
DRDY
SCLK
DIN
DOUT
CS

Figure 9-3. Multiple Device Configuration

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9.1.5 Power Metrology Applications

Each channel of the ADS131M04 is identical, giving designers the flexibility to sense voltage or current with any
channel. Simultaneous sampling allows the application to calculate instantaneous power for any simultaneous
voltage and current measurement. This section provides several diagrams depicting the common energy
metrology configurations that can be used with the ADS131M04. A Rogowski coil can alternatively be used
to sense current in the following examples wherever a CT is used. The integration to determine the current
flowing through the Rogowski coil is done digitally if that modification is made. RC antialiasing filters are not
shown in the following diagrams for simplicity, but are recommended for all channels.
Figure 9-4 shows a two-phase (or split phase) metrology front-end that uses current transformers (CTs) to
measure the current on two live phases and two resistor voltage dividers to measure the voltage between the
live phases and neutral. Figure 9-5 shows a configuration similar to Figure 9-4, but with the voltage measured
between the phases and the neutral current measured directly with a CT.

Load Load Load Load

VDD VDD

AVDD AVDD

AIN0N AIN0N

AIN0P AIN0P

AIN1P AIN1P

AIN1N AIN1N
ADS131M04 ADS131M04
AIN2N AIN2N

AIN2P AIN2P

AIN3P AIN3P

AIN3N AIN3N

AGND AGND

Phase Neutral Phase Phase Neutral Phase

Figure 9-4. Two-Phase CTs for Live Currents, With Figure 9-5. Two-Phase CTs for Live and Neutral
Voltages Measured to Neutral Currents, With Voltages Measured Between
Phases

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Figure 9-6 shows a single phase configuration where live and neutral currents are monitored using CTs, the live
phase voltage is measured using a voltage divider, and the final channel is used for an auxiliary measurement.
This auxiliary measurement can be temperature if connected to an external thermistor or other voltage output
temperature sensor. Otherwise this measurement can sense any other signal that requires monitoring on the
board. Figure 9-7 is similar to Figure 9-6 but shows a configuration where the live current is measured using a
CT and the neutral current is measured using a shunt. The reverse configuration, where the shunt is used for live
and the CT for neutral, is also valid.

Load Load

VDD VDD

AVDD AVDD

AIN0N AIN0N

AIN0P AIN0P

AIN1P AIN1P

AIN1N AIN1N
ADS131M04 ADS131M04
AIN2N AIN2N

AIN2P AIN2P

AIN3P AIN3P
Aux Aux
AIN3N AIN3N

AGND AGND

Phase Neutral Phase Neutral

Figure 9-6. Single-Phase CT for Live and Neutral Figure 9-7. Single-Phase, Shunt for Live Current,
Currents, With Phase and Auxiliary Voltages CT for Neutral Current, With Phase and Auxiliary
Measured Voltages Measured

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9.1.6 Code Example

This section contains example pseudocode for a simple program that configures and streams data from the
ADS131M04. The pseudocode is written to resemble C code. The code uses several descriptive precompiler-
defined constants that are indicated in upper case. The definitions are not included for brevity. The program
works in three sections: MCU initialization, ADC configuration, and data streaming. This code is not optimized for
using the fast startup feature of the ADS131M04.
The MCU is initialized by enabling the necessary peripherals for this example. These peripherals include an
SPI port, a GPIO configured as an input for the ADS131M04 DRDY output, a clock output to connect to the
ADS131M04 CLKIN input, and a direct memory access (DMA) module that streams data from the SPI port into
memory without significant processor intervention. The SPI port is configured to a 24-bit word size because the
ADC default SPI word size is 24 bits. The CS pin is configured to remain low as long as the SPI port is busy so
that it does not de-assert in the middle of a frame.
The ADC is configured through register writes. A function referred to as adcRegisterWrite writes an ADC register
using the SPI peripheral. No CRC data integrity is used in this example for simplicity, but is recommended. The
ADC outputs are initially disabled so short frames can be written during initialization consistent with the guidance
provided in the Short SPI Frames section. The ADC is configured to output DRDY as pulses, the gain is changed
to 32 for channels 1 and 3, and the DC block filter is used with a corner frequency of 622 mHz. Finally, the ADC
word size is changed to 32 bits with an MSB sign extension to accommodate the MCU memory length and to
allow for 32-bit DMA transfers. All other settings are left as defaults.
Data streaming is performed by using an interrupt that is configured to trigger on a negative edge received on
the GPIO connected to the DRDY pin. The interrupt service routine, referred to as DRDYinterrupt, sends six
32-bit dummy words to assert CS and to toggle SCLK for the length of the entire ADC output frame. The ADC
output frame consists of one 32-bit status word, four 32-bit ADC conversion data words, and an optional 32-bit
CRC word. The frame is long enough for output CRC even though the CRC word is disabled in this example.
The DMA module is configured to trigger upon receiving data on the SPI input. The DMA automatically sends
the ADC data to a predetermined memory location as soon as the data are shifted into the MCU through the SPI
input.

numFrameWords = 6; // Number of words in a full ADS131M04 SPI frame

unsigned long spiDummyWord[numFrameWords] =
{ 0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000}; // Dummy word frame to write ADC during ADC data reads

bool firstRead = true; // Flag to tell us if we are reading ADC data for the// first time
signed long adcData; // Location where DMA will store ADC data in memory,
// length defined elsewhere/*
Interrupt the MCU each time DRDY asserts when collecting data
*/
DRDYinterupt(){
if(firstRead){ // Clear the ADC's 2-deep FIFO on the first read
for(i=0; i<numFrameWords; i++){
SPI.write(spiDummyWord + i);
}
for(i=0; i<numFrameWords; i++){
SPI.read();
}
firstRead = false; // Clear the flag
DMA.enable(); // Let the DMA start sending ADC data to memory
}
for (i=0; i<numFrameWords; i++){// Send the dummy data to the ADC to get// the ADC data
SPI.write(spiDummyWord + i);
}
}
/*
adcRegisterWrite

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Short function that writes one ADC register at a time. Blocks return until SPI
is idle. Returns false if the word length is wrong.
param
addrMask: 16-bit register address mask
data: data to write
adcWordLength: word length which ADC expects. Either 16, 24 or 32.
return
true if word length was valid
false if not
*/
bool adcRegisterWrite(unsigned short addrMask, unsigned short data,
unsigned char adcWordLength){
unsigned char shiftValue; // Stores the amount of bit shift based on
// ADC word length
if(adcWordLength==16){
shiftValue = 0; // If length is 16, no shift
}else if(adcWordLength==24){
shiftValue = 8; // If length is 24, shift left by 8
}else if(adcWordLength==32){
shiftValue = 16; // If length is 32, shift left by 16
}else{
return false; // If not, invalid length
}
SPI.write((WREG_OPCODE | // Write address and opcode
addrMask) << shiftValue);// Shift to accommodate ADC word length

SPI.write(data << shiftValue);// Write register data

while(SPI.isBusy()); // Wait for data to complete sending
return true;
}
/*
main routine
*/
main(){
enableSupplies();
GPIO.inputEnable('input'); // Enable GPIO connected to DRDY
clkout.enable(8192000); // Enable 8.192 MHz clock to CLKIN
SPI.enable(); // Enable SPI port
SPI.wordLengthSet(24); // ADC default word length is 24 bits
SPI.configCS(STAY_ASSERTED);// Configure CS to remain asserted until frame// is complete
while(!GPIO.read()){} // Wait for DRDY to go high indicating it is ok// to talk to ADC
adcRegisterWrite(CLOCK_ADDR, // Write CLOCK register
ALL_CH_DISABLE_MASK | // Turn off all channels so short// frames can be written
during// config
OSR_1024_MASK | PWR_HR_MASK, 24); // Re-write defaults for other bits// in CLOCK register
adcRegisterWrite(MODE_ADDR, // Write MODE register
RESET_MASK | DRDY_FMT_PULSE_MASK | // Clear the RESET flag, make DRDY// active low pulse
WLENGTH_24_MASK | // Re-write defaults for other bits
SPI_TIMEOUT_MASK, 24; // in MODE register
adcRegisterWrite(GAIN1_ADDR, // Write GAIN1 register
PGAGAIN3_32_MASK | // Set channels 1 and 3 PGA gain to
PGAGAIN1_32_MASK, 24); // 32 in this example// Leave channels 0 and 2 at default//
gain of 1
adcRegisterWrite(THRSHLD_LSB_ADDR, // Write THRSHLD_LSB register
0x09, 24); // Set DCBLOCK filter to have a// corner frequency of 622 mHz
DMA.triggerSet(SPI);// Configure DMA to trigger when data comes in// on the MCU SPI port
DMA.txAddrSet(SPI.rxAddr());// Set the DMA to take from the incoming SPI
// port
DMA.rxAddrSet(&adcData);// Set the DMA to send ADC data to a predefined
// memory location
adcRegisterWrite(MODE_ADDR, // Write MODE register
WLENGTH_32_SIGN_EXTEND_MASK | // Make ADC word size 32 bits to// accommodate DMA
DRDY_FMT_PULSE_MASK | // Re-write other set bits in MODE
SPI_TIMEOUT_MASK, 24); // register
SPI.wordLengthSet(32); // Set SPI word size to 32 bits to// accomodate DMA
adcRegisterWrite(CLOCK_ADDR, // Write CLOCK register
ALL_CH_ENABLE_MASK | // Turn on all ADC channels
OSR_1024_MASK | PWR_HR_MASK, 32); // Re-write defaults for other bits// in CLOCK register
GPIO.interuptEnable();// Enable DRDY interrupt and begin streaming data
}

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9.1.7 Troubleshooting
Table 9-1 lists common issues faced when designing with the ADS131M04 and the corresponding solutions. This
list is not comprehensive.
Table 9-1. Troubleshooting Common Issues Using the ADS131M04
ISSUE POSSIBLE ROOT CAUSE POSSIBLE SOLUTION
ADC conversion data are not being read. Read data after each DRDY falling edge after
The DRDY pin is toggling at half the expected The two-deep ADC data FIFO overflows and following the recommendations given in the
frequency. triggers DRDY one time every two ADC data Collecting Data for the First Time or After a
periods. Pause in Data Collection section.
The SYNC/RESET pin functions as a
The F_RESYNC bit is set in the STATUS constant synchronization check, rather than
The SYNC/RESET pin is being toggled
word even though this bit was already a convert start pin. See the Synchronization
asynchronously to CLKIN.
cleared. section for more details on the intended
usage of the SYNC/RESET pin.
The entire frame is not being sent to the Read all data words in the output data
The same ADC conversion data are output
ADC. The ADC does not recognize data as frame, including those for channels that are
twice before changing.
being read. disabled.

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9.2 Typical Application

This section describes a class 0.1 split-phase energy measurement front-end using the ADS131M04. The ADC
samples the outputs of the CTs and voltage dividers to measure the current and voltage (respectively) of each
leg of the AC mains. The design can achieve high accuracy across a wide input current range (0.05 A – 100
A) and supports high sampling frequencies necessary for advanced power quality features such as individual
harmonic analysis. Using the ADS131M04 to sample the CT output provides designers greater flexibility in the
choice of metrology microcontrollers when compared to an integrated system-on-a-chip (SoC) and dedicated
application-specific products.
The design and results shown in this section are discussed in much greater detail as part of the TIDA-010037:
High accuracy split-phase CT electricity meter reference design using standalone ADCs design guide.
Figure 9-8 shows the front-end for the split-phase energy measurement design.
Load Load

VDD ADS131M04

AVDD

AIN0N VDD MCU

DVDD VDD
AIN0P
CLKIN CLKOUT
AIN1P
DRDY Interruptible GPIO

SCLK SPI CLK

AIN1N
CS SPI CS
AIN2N
DIN SPI MOSI

AIN2P DOUT SPI MISO

AIN3P DGND GND

AIN3N

AGND

Phase Neutral Phase

Figure 9-8. Split-Phase Metrology Design Front-End

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9.2.1 Design Requirements

Table 9-2. Key System Specifications
FEATURES DESCRIPTION
Number of phases 1 phase (split-phase with two voltages measured)
E-meter accuracy class Class 0.1
Current sensor Current transformer
Current range 0.05 A to 100 A
System nominal frequency 50 Hz or 60 Hz
• Active, reactive, apparent power, and energy
• Root mean square (RMS) current and voltage
Measured parameters • Power factor
• Line frequency

9.2.2 Detailed Design Procedure

A current sensor connects to the current channels and a simple voltage divider is used for the corresponding
voltage measurement. The CT has an associated burden resistor that must be connected at all times to protect
the measuring device. The selection of the CT and the burden resistor is made based on the manufacturer
and current range required for energy measurements. The voltage divider resistors for the voltage channel
are selected to ensure the mains voltage is divided down to adhere to the normal input voltage ranges of the
ADS131M04.
In this design, the ADS131M04 interacts with a microcontroller (MCU) in the following manner:
• The CLKIN clock used by the ADS131M04 device is provided by the MCU
• When new ADC samples are ready, the ADS131M04 device asserts its DRDY pin, which alerts the MCU that
new samples are available
• After being alerted of new samples, the MCU uses one of its SPI interfaces to retrieve the voltage and current
samples from the ADS131M04
9.2.2.1 Voltage Measurement Front-End
The nominal voltage from the mains is from 100 V – 240 V so this voltage must be scaled down to be sensed by
an ADC. Figure 9-9 shows the analog front-end used for this voltage scaling.
RHI RHI RHI RFILT
Live AINxP
CFILT
RV RLO
RFILT
Neutral AINxN

Figure 9-9. Voltage Measurement Front-End

The analog front-end for voltage consists of a spike protection varistor (RV), a voltage divider network (RHI and
RLO), and an RC low-pass filter (RFILT and CFILT).
Equation 11 shows how to calculate the range of differential voltages fed to the voltage ADC channel for a given
mains voltage and the selected voltage divider resistor values.

R LO
V ADC r V RMS u 2 u
3R HI R LO (11)

RHI is 300 kΩ and RLO is 750 Ω in this design. For a mains voltage of 120 V (as measured between the line and
neutral), the input signal to the voltage ADC has a voltage swing of ±128 mV (91 mVRMS) based on Equation 11

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and the selected resistor values. This voltage is well within the ±1.2-V input voltage range that can be sensed by
the ADS131M04 for the selected PGA gain value of 1 that is used for the voltage channels.
9.2.2.2 Current Measurement Front-End
The analog front-end for current inputs is different from the analog front-end for the voltage inputs. Figure 9-10
shows the analog front-end used for a current channel.
RFILT
AINxP
RB CFILT

RB RFILT
AINxN

Live

Figure 9-10. Current Measurement Front-End

The analog front-end for current consists of burden resistors for the current transformers (RB) and an RC
low-pass filter (RFILT and CFILT) that functions as an antialias filter.
Two identical burden resistors in series are used with the common point being connected to GND instead of
using one burden resistor for best THD performance. This split-burden resistor configuration ensures that the
waveforms fed to the positive and negative terminals of the ADC are 180 degrees out-of-phase with each other,
which provides the best THD results with this ADC. The total burden resistance is selected based on the current
range used and the turns ratio specification of the CT (this design uses CTs with a turns ratio of 2000). The total
value of the effective burden resistor (2RB) for this design is 12.98 Ω.
Equation 12 shows how to calculate the range of differential voltages fed to the current ADC channel for a given
maximum current, CT turns ratio, and burden resistor value.

V ADC r I RMS u 2R B u 2 N CT (12)

Based on the maximum RMS current of 100 A, a CT turns ratio NCT of 2000, and an effective burden resistor
2RB between AINxP and AINxN of 12.98 Ω for this design, the input signal to the current ADC has a voltage
swing of ±918 mV maximum (649 mVRMS) when the maximum current rating of the meter (100 A) is applied. This
±918-mV maximum input voltage is well within the ±1.2-V input range of the device for the selected PGA gain of
1 that is used for the current channels.
9.2.2.3 ADC Setup
The ADS131M04 receives its clock from the MCU in this design. The ADS131M04 is configured in HR mode and
the MCU provides an 8.192-MHz master clock, which is within the allowable clock frequency range for HR mode.
The MCU SPI port that is used to communicate with the ADS131M04 is configured to CPOL = 0 and CPHA =
1. The SPI clock frequency is configured to be 8.192 MHz so that all conversion data can be shifted out of the
device successfully within the sample period. When powered on, the MCU configures the ADS131M04 registers
with the following settings using SPI register writes.
• GAIN1 register settings: PGA gain of 1 is used for all ADC channels.
• CHx_CNG register settings (where x is the channel number): All ADC channel inputs are connected to
the external ADC pins and the channel phase delay set to 0 for each channel. The channel phase setting
can also be configured in this register. This design uses an integer number of output samples for phase
calibration so the processing is done in software completely.
• CLOCK register settings: OSR = 512, all channels enabled, and HR mode.
After the ADS131M04 registers are properly initialized, the MCU is configured to generate a GPIO interrupt
whenever a falling edge occurs on the DRDY pin, which indicates that the ADS131M04 has new samples
available.

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The clock fed to the CLKIN pin of the ADS131M04 is internally divided by two to generate the modulator clock.
The output data rate of the ADS131M04 is therefore fMOD / OSR = fCLKIN / (2 × OSR) = 8 kSPS.
9.2.2.4 Calibration
Certain signal chain errors can be corrected through a single room temperature calibration. The ADS131M04
has the capability to store calibration values and use the values to correct the results in real time. Among those
errors that can be corrected in real time with the ADS131M04 are offset error, gain error, and phase error.
Offset calibration is performed by determining the measured output of the signal chain when the input is zero
voltage for a voltage channel or zero current for a current channel. The value can be measured and recorded
in external non-volatile memory for each channel. When the system is deployed, these values can be provided
to the CHn_OCAL_MSB and CHn_OCAL_LSB registers for the corresponding channels. The ADS131M04 then
subtracts these values from its conversion results prior to providing them to the host. Alternatively, the integrated
DC block filter can be used to implement offset correction.
Similar to offset error correction, system gain error can be determined prior to deployment and can be used to
correct the gain error on each channel in real time. Gain error is defined as the percentage difference in the
ADC transfer function from its PGA gain corrected ideal value of 1. This error can be determined by measuring
the results from both a maximum and minimum input signal, finding the difference between these results, and
dividing by the difference between the ideal difference. Equation 13 describes how to calculate gain error.

V,I Max,Measured V,I Min,Measured

Gain Error 1
V,I Max V,I Min (13)

To correct for gain error, divide each offset-corrected conversion result by the measured gain. The ADS131M04
multiplies each conversion result by the calibration factor stored in the CHn_GCAL_MSB and CHn_GCAL_LSB
registers according to the method described in the Calibration Registers section. The host can program the
measured inverted gain values for each channel into these registers to have them automatically corrected for
each sample.
The ADS131M04 can also correct for system phase error introduced by sensors. For this design, the CT
introduces some phase error into the system. This design uses a software method for phase correction, but
the ADS131M04 can perform this function in real time. The system must first measure the phase relationships
between the various channels. Then, define one channel as phase 0. Subsequently, the PHASEn bits in the
CHn_CFG registers corresponding to the various other channels can be edited to correct their phase relationship
relative to the phase 0 channels.
9.2.2.5 Formulae
This section describes the formulas used for the power and energy calculations. Voltage and current samples
are obtained at a sampling rate of 8000 Hz. All samples that are taken in approximately one-second (1 sec)
frames are kept and used to obtain the RMS values for voltage and current for each phase.
Power and energy are calculated for active and reactive energy samples of one frame. These samples are
phase-corrected. Then phase active and reactive powers are calculated through the following formulas:

N samples 1
1
P Actual.ph
N samples ¦ v > n @ u i >n @
n 0 (14)

N samples 1
1
PRe active.ph
N samples ¦ v ª¬n n 90°º¼ u i >n@
n 0 (15)

2 2 2
PApparent.ph PActual.ph PRe active.ph (16)

where:

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• v[n] = Voltage sample

• i[n] = Current sample
• Nsamples = Number of samples in the approximately 1-second frame
• v[n-n90°] = Voltage sample with a 90° phase shift
• PACTUAL,ph = Instantaneous actual power for the measured phase
• PREACTIVE = Instantaneous reactive power for the measured phase
• PAPPARENT,ph = Instantaneous apparent power for the measured phase
The 90° phase shift approach is used for two reasons:
1. This approach allows accurate measurement of the reactive power for very small currents
2. This approach conforms to the measurement method specified by IEC and ANSI standards
The calculated mains frequency is used to calculate the 90° shifted voltage sample. Because the frequency
of the mains varies, the mains frequency is first measured accurately to phase shift the voltage samples
accordingly.
To get an exact 90° phase shift, interpolation is used between two samples. For these two samples, a voltage
sample slightly more than 90 degrees before the current sample and a voltage sample slightly less than 90°
before the current sample are used. The phase shift implementation of the application consists of an integer part
and a fractional part. The integer part is realized by providing an N samples delay. The fractional part is realized
by a one-tap FIR filter.
The cumulative power values can be calculated by summing the per phase power results. The cumulative
energy can be calculated by multiplying the cumulative power by the number of samples in the packet.
The host calculates the frequency in terms of samples-per-mains cycle by counting zero crossings of the sine
wave. Equation 17 converts this result from a samples-per-mains cycle to Hertz.

Frequency (Hz) = Data rate (samples / second) / Frequency (samples / cycle) (17)

After the active power and apparent power are calculated, the absolute value of the power factor is calculated.
In the internal representation of power factor of the system, a positive power factor corresponds to a capacitive
load and a negative power factor corresponds to an inductive load. The sign of the internal representation of
power factor is determined by whether the current leads or lags voltage, which is determined in the background
process. Therefore, Equation 18 and Equation 19 calculate the internal representation of the power factor:

PF = PACTUAL / PAPPARENT, if capacitive load (18)

PF = -PACTUAL / PAPPARENT, if inductive load (19)

9.2.3 Application Curves

A source generator was used to provide the voltages and currents to the system. In this design, a nominal
voltage of 240 V between the line and neutral, a calibration current of 10 A, and a nominal frequency of 60 Hz
were used for each phase.
When the voltages and currents are applied to the system, the design outputs the cumulative active energy
pulses and cumulative reactive energy pulses at a rate of 6400 pulses per kilowatt hour. This pulse output was
fed into a reference meter that determined the energy percentage error based on the actual energy provided
to the system and the measured energy as determined by the active and reactive energy output pulse of the
system.
The current was varied from 50 mA to 100 A for the cumulative active energy error and cumulative reactive
energy error testing. A phase shift of 0°, 60°, and −60° was applied between the voltage and current waveforms
fed to the design for cumulative active energy testing. Based on the error from the active energy output pulse,
several plots of active energy percentage error versus current were created for 0°, 60°, and –60° phase shifts.
For the cumulative reactive energy error testing, a similar process was followed except that 30°, 60°, –30°, and
–60° phase shifts were used, and the cumulative reactive energy error was plotted instead of the cumulative
active energy error. In the cumulative active and reactive energy testing, the sum of the energy reading of each
phase was tested for accuracy.
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In addition to testing active energy by varying current, active energy was also tested by varying the RMS voltage
from 240 V to 15 V and measuring the active energy percentage error.
The front-end was calibrated before obtaining the following results. The active energy results are within 0.1%
at 0° phase shift. At 60° and –60° phase shift, which is allowed to have relaxed accuracy in electricity meter
standards, the trend where the results deviate at higher currents is from the CT phase shift varying across
current.
This design and results are discussed in much greater detail in the TIDA-010037: High accuracy split-phase CT
electricity meter reference design using standalone ADCs design guide.
Table 9-3 shows the cumulative active energy accuracy results with changing voltage. Table 9-4 shows the
cumulative active energy results with varying current. Figure 9-11 depicts a plot of the values in Table 9-4.
Table 9-3. Cumulative Phase Active Energy % Error
Versus Voltage, Two-Voltage Mode
VOLTAGE (V) % ERROR
240 0.0353
120 0.022
60 0.016
30 0.014
15 0.013

Table 9-4. Cumulative Phase Active Energy % Error

Versus Current
CURRENT (A) 0° 60° –60°
0.05 0.019 0.045 –0.032
0.10 0.006 0.058 –0.032
0.25 0.0125 0.045 –0.0385
0.50 0.006 0.032 –0.032
1.00 0.015 0.045 –0.019
2.00 0.003 0.045 –0.039
5.00 0.006 0.024 –0.012
10.00 0.01 0.0165 0
20.00 –0.007 0.002 –0.013
30.00 0.002 –0.007 0.0085
40.00 0 –0.016 0.019
50.00 –0.003 –0.035 0.042
60.00 0.002 –0.047 0.053
70.00 0.009 –0.047 0.063
80.00. 0.007 –0.05 0.067
90.00 0.013 –0.045 0.08
100.00 0.0223 –0.04 0.092

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0.5
0°
0.4 60°
0.3 -60°

Active Energy Error (%)

0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0 10 20 30 40 50 60 70 80 90 100
Current (A) D003

Figure 9-11. Cumulative Phase Active Energy % Error Versus Current

Table 9-5 shows the cumulative reactive energy accuracy results with changing current. Figure 9-12 illustrates a
plot of the values in Table 9-4.
Table 9-5. Cumulative Reactive Energy % Error Versus Current
CURRENT (A) 30° 60° –30° –60°
0.05 –0.003 0.004 –0.023 –0.027
0.10 –0.037 –0.013 0.011 –0.008
0.25 –0.067 –0.027 0.043 0.002
1.00 –0.044 –0.021 0.0415 0.011
5.00 –0.036 –0.0183 0.022 0.001
10.00 –0.03 –0.012 0.014 –0.003
20.00 –0.041 –0.026 –0.0035 –0.013
40.00 –0.01 –0.016 –0.021 –0.016
60.00 0.025 –0.0007 –0.047 –0.0247
80.00 0.041 0.0085 –0.048 –0.021
100.00 0.054 0.02 –0.044 –0.012

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0.5
30°
0.4 60°
0.3 -30°

Reactive Energy Error (%)

-60°
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0 10 20 30 40 50 60 70 80 90 100
Current (A) D005

Figure 9-12. Cumulative Reactive Energy % Error Versus Current

10 Power Supply Recommendations

10.1 CAP Pin Behavior
The ADS131M04 core digital voltage of 1.8 V is created from an internal LDO from DVDD. The CAP pin outputs
the LDO voltage created from the DVDD supply and requires an external bypass capacitor. When operating from
DVDD > 2.7 V, place a 220-nF capacitor on the CAP pin to DGND. If DVDD ≤ 2 V, tie the CAP pin directly to the
DVDD pin and decouple the star-connected pins using a 100-nF capacitor to DGND.
10.2 Power-Supply Sequencing
The power supplies can be sequenced in any order but the analog and digital inputs must never exceed the
respective analog or digital power-supply voltage limits.
10.3 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. AVDD and DVDD must each be
decoupled with a 1-µF capacitor. Place the bypass capacitors as close to the power-supply pins of the device
as possible with low-impedance connections. Using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics are recommended for power-supply
decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use
of vias for connecting the capacitors to the device pins can offer superior noise immunity. The use of multiple
vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. The analog and
digital ground are recommended to be connected together as close to the device as possible.

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11 Layout
11.1 Layout Guidelines
For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces
on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane
may not be practical. If ground plane separation is necessary, make a direct connection of the planes at the
ADC. Do not connect individual ground planes at multiple locations because this configuration creates ground
loops.
Route digital traces away from all analog inputs and associated components in order to minimize interference.
Use C0G capacitors on the analog inputs. Use ceramic capacitors (for example, X7R grade) for the power-
supply decoupling capacitors. High-K capacitors (Y5V) are not recommended. Place the required capacitors as
close as possible to the device pins using short, direct traces. For optimum performance, use low-impedance
connections on the ground-side connections of the bypass capacitors.
When applying an external clock, be sure the clock is free of overshoot and glitches. A source-termination
resistor placed at the clock buffer often helps reduce overshoot. Glitches present on the clock input can lead to
noise within the conversion data.

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11.2 Layout Example

Figure 11-1 shows an example layout of the ADS131M04 requiring a minimum of two PCB layers. In general,
analog signals and planes are partitioned to the left and digital signals and planes to the right.

+3.3 V Via to corresponding

voltage plane or pour
Via to ground plane +3.3 V +3.3 V

or pour
Place CAP and power supply
decoupling capacitors close to pins

Channel 0

1: AVDD 20: DVDD

2: AGND 19: DGND

3: AIN0P 18: CAP

Channel 1
4: AIN0N 17: CLKIN

5: AIN1N 16: DIN

Device
6: AIN1P 15: DOUT

7: AIN2P 14: SCLK

Channel 2
8: AIN2N 13: DRDY

9: AIN3N 12: CS

10: AIN3P 11: SYNC/RST

Terminate long digital

Channel 3 input lines with resistors to
prevent reflection

Differential RC-filter
per channel

Figure 11-1. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, One-phase shunt electricity meter reference design using standalone ADCs design guide
• Texas Instruments, High accuracy split-phase CT electricity meter reference design using standalone ADCs
design guide
• Texas Instruments, ADC energy metrology library software
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ADS131M04IPWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A131M04 Samples

ADS131M04IPWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 A131M04 Samples

ADS131M04IRUKR ACTIVE WQFN RUK 20 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A31M04 Samples

ADS131M04IRUKT ACTIVE WQFN RUK 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A31M04 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jan-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS131M04 :

• Automotive : ADS131M04-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS131M04IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
ADS131M04IPWT TSSOP PW 20 250 180.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
ADS131M04IRUKR WQFN RUK 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
ADS131M04IRUKT WQFN RUK 20 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS131M04IPWR TSSOP PW 20 2000 356.0 356.0 35.0
ADS131M04IPWT TSSOP PW 20 250 210.0 185.0 35.0
ADS131M04IRUKR WQFN RUK 20 3000 367.0 367.0 35.0
ADS131M04IRUKT WQFN RUK 20 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

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 EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OUTLINE
RUK0020B SCALE 4.000
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.1 B
A
2.9

0.5
0.3

PIN 1 INDEX AREA

3.1 0.25
2.9 0.15

DETAIL
OPTIONAL TERMINAL
TYPICAL

DIMENSION A
OPTION 01 (0.1)
OPTION 02 (0.2)

0.8 MAX C

SEATING PLANE
0.05
0.00 0.08 C

1.7 0.05 (DIM A) TYP

OPT 02 SHOWN
6 10
EXPOSED
THERMAL PAD
16X 0.4
5
11

4X 21 SYMM
1.6

1
SEE TERMINAL 15
0.25
DETAIL 20X
0.15
0.1 C A B
20 16
PIN 1 ID SYMM 0.05
(OPTIONAL) 0.5
20X
0.3
4222676/A 02/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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 EXAMPLE BOARD LAYOUT
RUK0020B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.7)
SYMM

20 16

20X (0.6)

1
15

20X (0.2)
(0.6)
21 TYP SYMM

16X (0.4) (2.8)

5 11
(R0.05)
TYP

( 0.2) TYP
VIA
6 10
(2.8)

LAND PATTERN EXAMPLE

SCALE:20X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL
OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4222676/A 02/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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 EXAMPLE STENCIL DESIGN
RUK0020B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.47) TYP
(R0.05) TYP
20 16

20X (0.6)

1
15
21
20X (0.2)
(0.47)
TYP SYMM

16X (0.4) (2.8)

5 11

METAL
TYP

6 10
4X ( 0.75)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 21:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4222676/A 02/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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