CS5516

CS5520
16-Bit/20-Bit Bridge Transducer A/D Converter
Features Description
l On-chip Instrumentation Amplifier The CS5516 and CS5520 are complete solutions for dig-
l On-chip Programmable Gain Amplifier itizing low level signals from strain gauges, load cells,
and pressure transducers. Any family of mV output
l On-Chip 4-Bit D/A For Offset Removal transducers, including those requiring bridge excitation,
l Dynamic Excitation Options can be interfaced directly to the CS5516 or CS5520. The
l Linearity Error: ±0.0015% FS devices offer an on-chip software programmable instru-
mentation amplifier block, choice of DC or AC bridge
- 20-Bit No Missing Codes
excitation, and software selectable reference and signal
l CMRR at 50/60 Hz > 200 dB demodulation.
l System Calibration Capability with calibration
The CS5516 uses delta-sigma modulation to achieve
read/write option 16-bit resolution at output word rates up to 60 Hz. The
l 3, 4 or 5 wire Serial Communications Port CS5520 achieves 20-bit resolution at word rates up to
l Low Power Consumption: 40 mW 60 Hz.
- 10 µW Standby Mode for Portable applications The CS5516 and CS5520 sample at a rate set by the
user in the form of either an external CMOS clock or a
crystal. On-chip digital filtering provides rejection of all
frequencies above 12 Hz for a 4.096 MHz clock.
The CS5516 and CS5520 include system calibration to
null offset and gain errors in the input channel. The digi-
tal values associated with the system calibration can be
written to, or read from, the calibration RAM locations at
any time via the serial communications port. The 4-bit
DC offset D/A converter, in conjunction with digital cor-
rection, is initially used to zero the input offset value.

ORDERING INFORMATION
See page 29.
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Cirrus Logic, Inc.

Crystal Semiconductor Products Division Copyright  Cirrus Logic, Inc. 1997 MAR ‘95
P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
DS74F1
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com 1
 CS5516

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+, MDRV+ = 5V; VA-, VD- = -5V;
VREF= 2.5V(external differential voltage across VREF+ and VREF-); fCLK = 4.9152 MHz;
AC Excitation 300 Hz; Gain = 25; Bipolar Mode; Rsource = 300Ω with a 4.7nF to AGND at AIN (see Note 1);
unless otherwise specified.)

Parameter* Min Typ Max Units

Specified Temperature Range -40 to +85 °C
Accuracy
Linearity Error - 0.0015 0.003 ±%FS
Differential Nonlinearity - ±0.25 ±0.5 LSB16
Unipolar Gain Error (Note 2) - ±8 ±31 ppm
Bipolar Gain Error (Note 2) - ±8 ±31 ppm
Unipolar/Bipolar Gain Drift - ±1 - ppm/°C
Unipolar Offset (Note 2) - ±1 ±2 LSB16
Bipolar Offset (Note 2) - ±1 ±2 LSB16
Offset Drift - ±0.005 - µV/°C
Noise (Referred to Input) Gain = 25 (25 x 1) - 250 - nVrms
Gain = 50 (25 x 2) - 200 - nVrms
Gain = 100 (25 x 4) - 150 - nVrms
Gain = 200 (25 x 8) - 150 - nVrms
Notes: 1. The AIN and VREF pins present a very high input resistance at dc and a minor dynamic load which
scales to the master clock frequency. Both source resistance and shunt capacitance are therefore
critical in determining the source impedance requirements of the CS5516 and CS5520 at these pins.
2. Applies after system calibration at the temperature of interest.

Unipolar Mode Bipolar Mode

µV LSB’s % FS ppm FS LSB’s % FS ppm FS
0.4 0.26 0.0004 4 0.13 0.0002 2
0.76 0.50 0.0008 8 0.26 0.0004 4
1.52 1.00 0.0015 15 0.50 0.0008 8
3.04 2.00 0.0030 30 1.00 0.0015 15
6.08 4.00 0.0061 61 2.00 0.0030 30
VREF = 2.5V PGA gain = 1

CS5516; 16-Bit Unit Conversion Factors

* Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.

2 DS74F1
 CS5520

ANALOG CHARACTERISTICS (continued)

Parameter* Min Typ Max Units
Specified Temperature Range -40 to +85 °C
Accuracy
Linearity Error - 0.0007 0.0015 ±%FS
Differential Nonlinearity (No Missing Codes) 20 - - Bits
Unipolar Gain Error (Note 2) - ±4 ±24 ppm
Bipolar Gain Error (Note 2) - ±4 ±24 ppm
Unipolar/Bipolar Gain Drift - ±1 - ppm/°C
Unipolar Offset (Note 2) - ±4 ±8 LSB20
Bipolar Offset (Note 2) - ±4 ±8 LSB20
Offset Drift - ±0.005 - µV/°C
Noise (Referred to Input) Gain = 25 (25 x 1) - 250 - nVrms
Gain = 50 (25 x 2) - 200 - nVrms
Gain = 100 (25 x 4) - 150 - nVrms
Gain = 200 (25 x 8) - 150 - nVrms

Unipolar Mode Bipolar Mode

µV LSB’s % FS ppm FS LSB’s % FS ppm FS
0.025 0.26 0.0000238 0.25 0.13 0.0000119 0.125
0.047 0.50 0.0000477 0.50 0.26 0.0000238 0.25
0.095 1.00 0.0000954 1.0 0.50 0.0000477 0.50
0.190 2.00 0.0001907 2.0 1.00 0.0000954 1.0
0.380 4.00 0.0003814 4.0 2.00 0.0001907 2.0
VREF = 2.5V PGA gain = 1

CS5520; 20-Bit Unit Conversion Factors

* Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.

DS74F1 3
 CS5516, CS5520

ANALOG CHARACTERISTICS (continued)

Parameter Min Typ Max Units
Specified Temperature Range -40 to +85 °C
Analog Input
Analog Input Range Unipolar 12.5, 25, 50, 100 mV
Bipolar ±12.5, ±25, ±50, ±100 mV
Common Mode Rejection dc - 165 - dB
50, 60 Hz - 200 - dB
Input Capacitance - 5 - pF
Input Bias Current (Note 1) - 100 - pA
Instrumentation Amplifier
Gain - 25 -
Bandwidth - 200 - kHz
Unity Gain Bandwidth - 5 - MHz
Output Slew Rate - 1.5 - V/µsec
Noise @ 10 Hz BW - 100 - nVrms
Power Supply Rejection @ 50/60 Hz (Note 3) - 120 - dB
Common Mode Range (Note 4) - ±3 - V
Chopping Frequency - XIN/128 - Hz
Programmable Gain Amplifier
Gain Tracking (Note 5) - ±1 - %
4-Bit Offset Trim DAC
Accuracy - ±5 - %
Voltage Reference Input
Range (Note 6) 2.0 2.5 3.8 V
Common Mode Rejection: dc - 60 - dB
50, 60 Hz - 200 -
Input Capacitance - 15 - pF
Input Bias Current (Note 1) - 10 - nA
Notes: 3. This includes the on-chip digital filtering.
4. The maximum magnitude of the differential input voltage, Vdiff(in) is determined by the following:
Vdiff(in) < 300 mV - |Vcm/12.5 | and should never exceed 300mV.
Vcm is the common mode voltage which is applied to the instrumentation amplifier inputs.
The above equation should be used to calculate the allowable common mode voltage for a given
differential voltage applied to the first gain stage inputs. This limit ensures
that the instrumentation amplifier does not saturate.
5. Gain tracking accuracy can be significantly improved by uploading a calibrated gain word to the
gain register for each PGA gain selection.
6. The common mode voltage on the Voltage Reference Input, plus the reference range,
[(VREF+) - (VREF-)]/2, must not exceed ±3 volts.

4 DS74F1
 CS5516, CS5520

ANALOG CHARACTERISTICS (continued)

Parameter Min Typ Max Units
Modulator Differential Voltage Reference
Nominal Output Voltage - 3.75 - V
Initial Output Voltage Tolerance - ±100 - mV
Temperature Coefficient - 100 - ppm/°C
Line Regulation (4.75V < VA < 5.25V) - 0.5 - mV/V
Output Voltage Noise 0.1 to 15 Hz - 10 - µVp-p
Output Current Drive: Source Current - - 20 µA
Sink Current - - 20 µA
Power Supplies
DC Power Supply Currents IA+ - 2.7 3.5 mA
IA- - -2.7 -3.5 mA
ID+ - 1.5 2.2 mA
ID- - -0.6 -0.8 mA
Power Dissipation: (Note 7)
Normal Operation - 37.5 - mW
Standby Mode - 10 - µW
Power Supply Rejection: dc Positive Supplies - 100 - dB
dc Negative Supplies - 95 - dB
System Calibration Specifications
Positive Full Scale Calibration Range (Note 8)
Unipolar Mode 0.8T - 1.2T V
Bipolar Mode 0.8T - 1.2T V
Maximum Ratiometric Offset Calibration Range (Note 8)
Unipolar Mode -2T - +2T V
Bipolar Mode -2T - +2T V
Differential Input Voltage Range (Notes 4, 8, 9, 10)
Unipolar Mode Voffset + (1.2T) V
Bipolar Voffset ± (1.2T) V
Notes: 7. All outputs unloaded. All inputs CMOS levels.
8. T=VREF/(Gx25), where T is the full scale span, where VREF is the differential voltage across
VREF+ and VREF- in volts, and G is the gain setting of the second gain block. G can be set
to 1, 2, 4, 8. This sets the overall gain to 25, 50, 100, 200. The gain can then be fine tuned by
using the calibration of the full scale point.
9. When calibrated.
10. Voffset is the offset corrected by the offset calibration routine. V offset may be as large as 2T.

DS74F1 5
 CS5516, CS5520

DYNAMIC CHARACTERISTICS
Parameter Symbol Ratio Units
AIN and VREF Input Sampling Frequency fis fclk/128 Hz
Modulator Sampling Frequency fs fclk/256 Hz
Output Update Rate fout fclk/81,920 Hz
Filter Corner Frequency f-3dB fclk/341,334 Hz
Settling Time to ±0.0007% (FS Step) ts 6/fout s

DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 5%; VA-, VD- = -5V ± 5%;
DGND = 0) All measurements below are performed under static conditions.

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN VIH 4.5 - - V
All Pins Except XIN VIH 2.0 - - V
Low-Level Input Voltage XIN VIL - - 0.5 V
All Pins Except XIN VIL - - 0.8 V
High-Level Output Voltage (Note 11) VOH (VD+)-1.0 - - V
Low-Level Output Voltage lout = 1.6mA VOL - - 0.4 V
Input Leakage Current lin - 1 10 µA
3-State Leakage Current lOZ - - ±10 µA
Digital Output Pin Capacitance Cout - 9 - pF
Notes: 11. Iout = -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ Iout = -40 µA).

6 DS74F1
 CS5516, CS5520

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 12.)

Parameter Symbol Min Typ Max Units
DC Power Supplies: Positive Digital VD+ 4.5 5.0 5.5 V
Negative Digital VD- -4.5 -5.0 -5.5 V
Positive Analog VA+ 4.5 5.0 5.5 V
Negative Analog VA- -4.5 -5.0 -5.5 V
Differential Analog Reference Voltage (VREF+) - (VREF-) 2.0 2.5 3.8 V
Analog Input Voltage: (Note 13)
Unipolar VAIN 0 - +T V
Bipolar VAIN -T - +T V
Notes: 12. All voltages with respect to ground.
13. The CS5516 and CS5520 can accept input voltages up to +T in unipolar mode and -T to +T in bipolar
mode where T=VREF/(Gx25). G is the gain setting at the second gain block. When the inputs exceed
these values, the CS5516 and CS5520 will output positive full scale for any input above T, and
negative full scale for inputs below AGND in unipolar and -T in bipolar mode. This applies when the
analog input does not exceed ±2T overrange.

ABSOLUTE MAXIMUM RATINGS* (AGND, DGND = 0V, all voltages with respect to ground.)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Positive Digital (Note 14) VD+ -0.3 - (VA+)+0.3 V
Negative Digital VD- -0.3 - -5.5 V
Positive Analog VA+ -0.3 - 5.5 V
Negative Analog VA- +0.3 - -5.5 V
Input Current, Any Pin Except Supplies (Notes 15, 16) lin - - ±10 mA
Analog Input Voltage AIN and VREF pins VINA (VA-)-0.3 - (VA+)+0.3 V
Digital Input Voltage VIND -0.3 - (VD+)+0.3 V
Ambient Operating Temperature TA -55 - 125 °C
Storage Temperature Tstg -65 - 150 °C
Notes: 14. No pin should go more positive than (VA+)+0.3V. VD+ must always be less than (VA+)+0.3 V,and
can never exceed 6.0V.
15. Applies to all pins including continuous overvoltage conditions at the analog input pins.
16. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 mA.
* WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

DS74F1 7
 CS5516, CS5520

CS
t3 t6
SID MSB MSB-1
t4 t5 t
1
SCLK
t2

SID Write Timing (Not to Scale)

DRDY

CS
t7
SOD MSB MSB-1 LSB
t8 t1 t9
SCLK
t2

SOD Read Timing (Not to Scale)

DRDY
t 10
SOD MSB MSB-1 LSB
t8 t1 t9
SCLK
t2

SOD Read Timing with CS = 0 (Not to Scale)

t 12 t 14
CS
t 13 t 15
SCLK

CS with Continuous SCLK (Not to Scale)

8 DS74F1
 CS5516, CS5520

SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 5%;

VA-, VD- = -5V±5%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF)

Parameter Symbol Min Typ Max Units

Master Clock Frequency: Internal Oscillator / External Clock XIN 1.0 4.096 5.0 MHz
Master Clock Duty Cycle 40 - 60 %
Rise Times Any Digital Input (Note 18) trise - - 1.0 µs
Any Digital Output - 50 - ns
Fall Times Any Digital Input (Note 18) tfall - - 1.0 µs
Any Digital Output - 50 - ns
Startup
Power-on Reset Period tpor - 100 - ms
Oscillator Start-up Time XTAL = 4.9152 MHz(Note 19) tost - 60 - ms
RST Pulse Width tres 1/XIN - - ns
Serial Port Timing
Serial Clock Frequency SCLK - - 2.4 MHz
Serial Clock Pulse Width High t1 200 - - ns
Pulse Width Low t2 200 - - ns
SID Write Timing
CS Enable to Valid Latch Clock t3 150 - - ns
Data Set-up Time prior to SCLK rising t4 50 - - ns
Data Hold Time After SCLK Rising t5 50 - - ns
SCLK Falling Prior to CS Disable t6 50 - - ns
SOD Read Timing
CS to Data Valid t7 - - 150 ns
SCLK Falling to New Data Bit t8 - - 170 ns
SCLK Falling to SOD Hi-Z t9 - - 200 ns
DRDY Falling to Valid Data (CS = 0) t10 - - 150 ns
CS Rising to SOD Hi-Z t11 - - 150 ns
CS Disable Hold Time t12 50 - - ns
CS Enable Set-up Time t13 150 - - ns
CS Enable Hold Time t14 50 - - ns
CS Disable Set-up Time t15 150 - - ns
Notes: 18. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
19. Oscillator start-up time varies with crystal parameters. This specification does not apply when using
an external clock source.

DS74F1 9
 CS5516, CS5520

GENERAL DESCRIPTION
The CS5516 and CS5520 are monolithic CMOS coarse offset trimming, circuitry for generation
A/D converters which include an instrumentation and demodulation of AC (actually switched DC)
amplifier input, an on-chip programmable gain bridge excitation, and a serial port. The CS5516
amplifier, and a DAC for offset trimming. outputs 16-bit words; the CS5520 outputs 20-bit
While the devices are optimized for ratiometric words.
measurement of Wheatstone bridge applications,
they can be used for general purpose low-level The CS5516/20 devices can measure either
signal measurement. unipolar or bipolar signals. Self-calibration is
utilized to maximize performance of the meas-
Each of the devices includes a two-channel dif- urement system. To better understand the
ferential delta-sigma modulator (the signal capabilities of the CS5516/20, it is helpful to ex-
measurement input and the reference input are amine some of the error sources in bridge
digitized independently before a digital output measurement systems.
word is computed), a calibration microcontroller,
a two-channel digital filter, a programmable in-
strumentation amplifier block, a 4-bit DAC for

+5V 10 Ω
Analog
Supply 1 µF 0.1 µF 0.1 µF 1 µF
3 20
1 µF VA+ VD+
2 23
MDRV- XOUT
1
MDRV+
Optional
12 22
Bridge BX1 XIN Clock
Excitation Excitation Supply Source
Synch. Signals CS5516
Supply 11
BX2 CS5520
16
SCLK
18 Serial
9 SOD
VREF+ Data
17
SID Interface
- +
10 24
VREF- SMODE
15
6 DRDY
AIN+ Control
7 13
AIN- RST
Logic
5 14
AGND1 CS
Unused logic inputs 8 19
AGND2 DGND
must be connected
to DGND or VD+ VA- VD-
0.1 µF 1 µF 4 21 1 µF 0.1 µF
-5V 10 Ω
Analog
Supply

Figure 1. System Connection Diagram: AC Excitation Mode Using External Excitation

10 DS74F1
 CS5516, CS5520

THEORY OF OPERATION
The front page of this data sheet illustrates the After the programmable gain block, the output
block diagram of the CS5516 and CS5520 A/D of a 4-bit DAC is combined with the input sig-
converter. The device includes an instrumenta- nal. The DAC can be used to add or subtract
tion amplifier with a fixed gain of 25. This offset from the analog input signal. Offsets as
chopper-stabilized instrumentation amplifier is large as ±200 % of full scale can be trimmed
followed by a programmable gain stage with from the input signal.
gain settings of 1, 2, 4, and 8. The sensitivity of
the input is a function of the programmable gain The CS5516 and CS5520 are optimized to per-
setting and of the reference voltage connected form ratiometric measurement of bridge-type
between the VREF+ and VREF- pins of the de- transducers. The devices support dc bridge exci-
vice. The full scale of the converter is VREF/( G tation or two modes of ac (switched dc) bridge
x 25) in unipolar, or ±VREF/(G x 25) in bipolar, excitation. In the switched-dc modes of opera-
where VREF is the reference voltage between tion the converter fully demodulates both the
the VREF+ and VREF- pins, G is the gain set- reference voltage and the analog input signal
ting of the programmable gain amplifier, and 25 from the bridge.
is the gain of the instrumentation amplifier.

+5V 10 Ω
Analog
Supply 1 µF 0.1 µF 0.1 µF 1 µF
3 20
1 µF VA+ VD+
2 23
MDRV- XOUT
1
MDRV+
Optional
22
XIN Clock
Source
CS5516
CS5520
16
SCLK
18 Serial
9 SOD
VREF+ Data
17
SID Interface
- +
10 24
VREF- SMODE
15
6 DRDY
AIN+ Control
7 13
AIN- RST
Logic
5 14
AGND1 CS
Unused logic inputs 8 19
AGND2 DGND
must be connected
to DGND or VD+ VA- VD-
0.1 µF 1 µF 4 21 1 µF 0.1 µF
-5V 10 Ω
Analog
Supply

Figure 2. System Connection Diagram: DC Excitation Mode (EXC bit = 0), F1 = F0 = 0.

DS74F1 11
 CS5516, CS5520

Command Register
D7 D6 D5 D4 D3 D2 D1 D0
1 RSB2 RSB1 RSB0 R/W 0 0 0

BIT NAME VALUE FUNCTION

D7 D7 1 Must always be logic 1
RSB2-0 Register Select Bit Selects Register to be Read or Written per R/W bit
000 CONVERSION DATA (read only)
001 CONFIGURATION
010 GAIN
011 DAC
100 RATIOMETRIC OFFSET
101 NON-RATIOMETRIC OFFSET - AIN
110 NON-RATIOMETRIC OFFSET - VREF
111 NOT USED
R/W Read/Write 0 Write to the register selected by the RSB2-0 bits
1 Read from the register selected by the RSB2-0 bits
D2 D2 0 Not Used
D1 D1 0 Not Used
D0 D0 0 Not Used

Table 1. CS5516 and CS5520 Commands

The CS5516/20 includes a microcontroller which ter to be read, and present its 24-bit word to the
manages operation of the chip. Included in the port. The microcontroller will signal when the
microcontroller are eight different registers asso- 24-bit read data is available by causing the
ciated with the operation of the device. An 8-bit DRDY pin to go low.
command register is used to interpret instruc-
tions received via the serial port. When power The user must write or read the full 24-bit word
is applied, and the device has been reset, the se- except in the case of reading conversion data. In
rial port is initialized into the command mode. read data conversion mode, the user may read
In this mode it is waiting to receive an 8-bit less than 24 bits if CS is then made inactive
command via its serial port. The first 8 bits into (CS = 1). CS going inactive releases user control
the serial port are placed into the command reg- over the port and allows new data updates to the
ister. Table 1 lists all the valid command words port.
for reading from or writing to internal registers
of the converter. Once a valid 8-bit command The user can instruct the on-chip microcontroller
word has been received and decoded, the serial to perform certain operations via the configura-
port goes into data mode. In data mode the next tion register. Whenever a new word is written
24 serial clock pulses shift data either into or out to the 24-bit configuration register, the micro-
of the serial port. When writing data to the port, controller then decodes the word and executes
the data may immediately follow the command the configuration register instructions. Table 2
word. When reading data from the port, the user illustrates the bits of the configuration register.
must pause after clocking in the 8-bit command The bits in the configuration register will be dis-
word to allow the microcontroller time to decode cussed in various sections of this data sheet.
the command word, access the appropriate regis-
12 DS74F1
 CS5516, CS5520

Configuration Register
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
Register DAC3 DAC2 DAC1 DAC0 EXC F1 F0 D16 G1 G0 U/B D12
Reset (R) 0 0 0 0 0 0 0 0 0 0 0 0

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register A/S EC D9 D8 CC3 CC2 CC1 CC0 D3 D2 D1 RF
Reset (R) 0 0 0 0 0 0 0 0 0 0 0 0

BIT NAME VALUE FUNCTION

DAC3 DAC Sign Bit 0 R1 Add Offset
1 Subtract Offset This bit is read only2
DAC2-0 DAC Bits 000 R
001 25% Offset
010 50% Offset
011 75% Offset
100 100% Offset These bits are read only2
101 125% Offset
110 150% Offset
111 175% Offset
EXC Excitation: Internal 0 R BX1 and BX2 outputs are determined by bits F1 and F0
External 1 BX1 is an input which determines the phase of the
demodulation clock and the BX2 output
F1-F0 Select Frequency 00 R Excitation on BX1 & BX2 is dc. BX1=0 V, BX2=+5 V
01 Excitation Frequency on BX1 & BX2 is XIN/8192 Hz
10 Excitation Frequency on BX1 & BX2 is XIN/16384 Hz
11 Excitation Frequency on BX1 & BX2 is XIN/4096 Hz
D16 D16 0 R Must always be logic 0
G1-G0 Select PGA Gain 00 R Gain = 1 (X25)
10 Gain = 2 (X25)
01 Gain = 4 (X25)
11 Gain = 8 (X25)
U/B Select Unipolar/Bipo- 0 R Bipolar Measurement Mode
lar Mode 1 Unipolar Measurement Mode
D12 D12 0 R Must always be logic 0
A/S Awake/Sleep 0 R Awake Mode
1 Sleep Mode
EC Execute Calibration 0 R Calibration not active
1 Perform calibration selected by CC3-CC0 bits. EC bit
must be written back to "0" after calibration is completed
D9 D9 0 R Must always be logic 0
D8 D8 0 R Must always be logic 0
CC3-CC0 Calibration Control Bits 0000 R No calibration to be performed
1000 Calibrate non-ratiometric offset, VREF
0100 Calibrate non-ratiometric offset, AIN
0010 Calibrate ratiometric offset, AIN
0001 Calibrate gain, AIN
D3 D3 0 R Must always be logic 0
D2 D2 0 R Must always be logic 0
D1 D2 0 R Must always be logic 0
RF Reset Filter 0 R Normal operation
1 Reset Filter

Notes: 1.Reset State

2.A write to these bits does not change the register bit values. These bits are just a mirror of the DAC register contents.
Table 2. Configuration Register

DS74F1 13
 CS5516, CS5520

System Initialization CALIBRATION

Whenever power is applied to the After the CS5516/20 is reset, the device is func-
CS5516/CS5520 A/D converters, the devices tional and can perform measurements without
must be reset to a known condition before being calibrated. The converter will utilize the
proper operation can occur. The internal reset is initialized values of the calibration registers to
applied after power is established and lasts for calculate output words.
approximately 100 ms. The RST pin can also be
used to establish a reset condition. The reset sig- The converter uses the two outputs (AIN &
nal should remain low for at least one XIN clock VREF) of the dual channel converter along with
cycle to ensure adequate reset time. It is recom- the contents of the calibration registers to com-
mended that the RST pin be used to reset the pute the conversion data word. The following
converter if the power supplies rise very slowly equation indicates the computation.
or with poor startup characteristics. The RST AIN − R1
signal can be generated by a microcontroller out- R0 = R4 [[DDVREF − R2
]
− R3 ]
put, or by use of an R-C circuit.
Where R0 is the output data, DAIN and DVREF
The reset function initializes the configuration are the digital output words from the AIN and
register and all five of the calibration registers; VREF digital filter channels, and R1, R2, R3
and places the microcontroller in command and R4 are the contents of the following calibra-
mode ready to accept a command from the serial tion registers:
port. Whenever the device is reset the DRDY
pin will be set to a logic 1 and the on-chip regis- R1 = AIN non-ratiometric offset
ters are initialized to the following states: R2 = VREF non-ratiometric offset
R3 = AIN ratiometric offset
Configuration 000000(H)
R4 = Gain
Calibration registers:
DAC 000000(H)
Gain 800000(H)
The computed output word, R0, is a two’s com-
AIN Ratiometric Offset 000000(H) plement number.
AIN Non-ratiometric Offset 000000(H)
VREF Non-ratiometric Offset 000000(H) Calibration minimizes the errors in the converted
output data. If calibration has not been per-
formed, the measurements will include offset
and gain errors of the entire system.

The converter may be calibrated each time it is

powered up, or calibration words from a pre-
vious calibration may be uploaded into the
appropriate calibration registers from some type
of E2PROM by the system microcontroller.

The converter uses five different registers to

store specific calibration information. Each of
the calibration registers stores information perti-
nent to correcting a specific source of error
associated with either the converter or with the
input transducer and its wiring. The method by
14 DS74F1
 CS5516, CS5520

Configuration Register
EC CC3 CC2 CC1 CC0 CAL Type Calibration Time
1 1 0 0 0 VREF Non-ratiometric Offset 573,440/fclk
1 0 1 0 0 AIN Non-ratiometric Offset 573,440/fclk
1 0 0 1 0 AIN Ratiometric Offset 2,211,840/fclk
1 0 0 0 1 AIN System Gain 573,440/fclk
1 1 1 0 0 VREF & AIN Non-ratiometric Offset 573,440/fclk
0 X X X X End Calibration -

DRDY remains high through calibration sequence. In all modes, DRDY falls immediately upon completion of the calibration
sequence.
Table 3. CS5516/CS5520 Calibration Control
which calibration is initiated is common to each formed. The calibration steps should be per-
of the calibration registers. The configuration formed in the following sequence. If the user
register controls the execution of the calibration determines that non-ratiometric offset calibra-
process. Bits CC3--CC0 in the configuration tion is important, the non-ratiometric offset
register determine which type of calibration will errors of the VREF and AIN input channels
be performed and which of the five calibration should be calibrated first. Then the ratiometric
registers will be affected. On the falling edge of offset of the AIN channel should be calibrated.
the 24th SCLK, the configuration word will be And finally, the AIN channel gain should be
latched into the configuration register and the se- calibrated.
lected calibration will be executed. The time
required to perform a calibration is listed in Ta- Non-ratiometric Errors
ble 3. The DRDY pin will remain a logic 1
To calibrate out the VREF and AIN
during calibration, and will go low when the
non-ratiometric errors, the input channels to the
calibration step is completed.
VREF path into the converter and the AIN path
into the converter must be grounded (this may
The serial port should not be accessed while a
occur at the pins of the IC, or at the bridge exci-
calibration is in progress. The EC bit of the
tation as shown in Figure 3.). Then the EC,
configuration register remains a logic 1 until it is
CC2 and CC3 bits of the configuration register
overwritten by a new configuration word (EC =
must be set to logic 1. The converter will then
0). Consequently, if EC is left active, any write
perform a non-ratiometric calibration and place
(the falling edge of the 24th SCLK) to any regis-
BX1
ter inside the converter will cause a re-execution
BX2
of the calibration sequence. This occurs because
the internal microcontroller executes the contents CS5516 1B* 1A*
CS5520
of the configuration register every time the 24th
SCLK falls after writing a 24-bit word to any VREF+
internal register. To be certain that calibrations VREF-
AIN+
will not be re-executed each time a new word is
written or read via the serial port, the EC bit of + -
the configuration register must be written back
to a logic 0 after the final calibration step has AIN-
been completed. *Note: The bridge can be grounded with a
relay or with jumpers to perform
non-ratiometric calibration.
The CC3--CC0 bits of the configuration register
Figure 3. Non-ratiometric System Calibration using
determine the type of calibration to be per-
Internal Excitation

DS74F1 15
 CS5516, CS5520

the proper 24 bit calibration words in the VREF DRDY falls to signal the completion of this cali-
and AIN non-ratiometric registers. Note that the bration step, the EC bit of the configuration
two non-ratiometric offsets can be calibrated si- register must be set back to logic 0 to terminate
multaneously or independently, but they must be the calibration mode.
calibrated prior to the other calibration steps if
non-ratiometric offset calibration is to be used. If Limitations in Calibration Range
the effects of the non-ratiometric errors are not
There are five calibration registers in the con-
significant enough to affect the user application,
verter. There are two non-ratiometric offset
they can be left uncalibrated (after a reset, the
calibration registers, one for the AIN input and
non-ratiometric offset registers will contain
one for the VREF input; one 4-bit offset trim
000000(H)).
DAC; one ratiometric offset calibration register
for the AIN input; and one gain calibration reg-
Ratiometric Offset
ister. After the non-ratiometric offsets are
Once the non-ratiometric errors have been cali- calibrated, an LSB in either of the 24-bit non-ra-
brated, the ratiometric offset error of the AIN tiometric calibration registers represents 2-23
channel should be calibrated next. To perform proportion of an internally-scaled MDRV
this calibration step, a reference voltage must be (Modulator Differential Reference Voltage). At
applied to the VREF+ and VREF- pins. Then, the MDRV+ and MDRV- pins, the MDRV has a
place "zero" weight on the scale platform. This nominal value of 3.75 volts. This voltage is in-
will result in an offset voltage into the converter ternally scaled to a nominal 2.5 volts (never less
which will represent the offset of the bridge, the than 2.4 volts) for use with the non-ratiometric
wiring, and the AIN input of the converter itself. calibration. The two non-ratiometric calibration
A configuration word with the EC and CC1 bits words are stored in 2’s complement form with
set to logic 1 is then written into the configura- one count equal to slightly less than 300 nV at
tion register. During the ratiometric offset the input of the internal A/D converter. For the
calibration of AIN the microcontroller first uses AIN channel this will be scaled down by the
a successive approximation algorithm to com- gain of the instrumentation amplifier (X25) and
pute the correct values for the DAC3-DAC0 bits the PGA gain. For a PGA gain = 1, one count of
of the DAC register. This accommodates any a non-ratiometric register will represent slightly
large offsets on the AIN input signal. Once the less than 12 nV. Non-ratiometric offset at the
four DAC bits are computed, this amount of off- VREF input cannot exceed ± 2.4 volts to be
set is removed from the input signal. The within calibration range of the converter. Non-
microcontroller then computes the appropriate ratiometric offset to be calibrated by the AIN
24 bit number to place in the AIN ratiometric channel cannot exceed ± 2.4 volts divided by the
offset register to calibrate out the remaining off- channel gain. With a PGA gain = 1, the maxi-
set not removed by the DAC. mum non-ratiometric offset which can be
calibrated on the AIN channel cannot exceed
Gain ± 96 mV.
After the AIN ratiometric offset has been cali-
brated, the next step is to perform a gain When the ratiometric offset is calibrated, the 4-
calibration. Gain calibration is performed with bit DAC coarsely trims offset from the analog
"full scale" weight on the scale platform. The signal. The ratiometric offset which remains is
EC and CC0 bits of the configuration register finely trimmed after the signal has been con-
are set to logic 1. The gain calibration of the verted; using the contents of the ratiometric
AIN channel is the final calibration step. After offset register for digital correction. The DAC

16 DS74F1
 CS5516, CS5520

bits can be manipulated by the user to add or In a typical weigh scale application, the
subtract offset up to 200 percent of the nominal CS5516/CS5520 will be calibrated in combina-
input signal. The AIN ratiometric offset register tion with a load cell at the factory. Once
can be manipulated to add or subtract offset calibrated, the calibration words are off-loaded
equal to the maximum differential input signal from the converter and stored in E2PROM.
into the X25 amplifier. An LSB in the ratiomet- When powered-up in the field the calibration
ric offset register represents 2-23 proportion of words are up-loaded into the appropriate regis-
the voltage input across the VREF+ and VREF- ters. This is viable because the AIN and VREF
pins at the internal input to the AIN channel input to the converter are "chopper-stabilized"
A/D converter. This will be scaled down by the and maintain excellent stability when subjected
AIN channel gain when calculated relative to the to changes in temperature.
instrumentation amplifier input. For example,
with a VREF = 2.5 V, the PGA gain = 1, one Programmable Gain Amplifier
count of the ratiometric offset register would
The programmable gain amplifier inside the
represent about 12 nV at the instrumentation am-
CS5516/20 offers gains of 1, 2, 4, and 8. This is
plifier input. The proportion remains ratiometric
in addition to the fixed gain of × 25 in the input
even if the VREF voltage should change. The
instrumentation amplifier. The gain tracking of
24-bit register content is stored in 2’s comple-
the PGA is about one percent between ranges.
ment form.
The user can remove this error by performing a
gain calibration at the factory with a full scale
Manipulation of the DAC or ratiometric offset
signal on each range. The gain calibration word
register allows the user to shift the transfer func-
for each gain range can be off-loaded into
tion to allow for load cell creep or load cell zero
E2PROM and uploaded into the gain register
drift.
whenever a new gain setting is selected for the
PGA. Gain stability over temperature for the
The gain calibration is performed last. The con-
tents of the gain register spans from 2-23 to 2 as converter itself is approximately 1 ppm/°C when
shown in Table 4. After gain calibration has the device is used ratiometrically.
been performed, the numeric value in the gain
register should not exceed the range of 0.8 to Serial Interface Modes
1.2. The gain calibration range is ± 20 % of the The CS5516/20 support either 5, 4 or 3 pin se-
nominal value of 1.0. The nominal value of 1.0 rial interfacing. The SMODE pin sets the
is for an input span dictated by the VREF volt- operating mode of the serial interface. With
age, the PGA gain, and the X25 instrumentation SMODE = 0, the device assumes the user is op-
gain. The converter may operate with gain slope erating with either a 5 or 4 wire interface. The
factors from 0.5 to 2.0 (decimal), but when the five wire mode includes SOD, SID, SCLK,
slope exceeds 1.2 the converter output code DRDY, and CS. In the four wire mode, CS is
computation may lack adequate resolution and connected to DGND as a logic 0. The user
result in missing codes in the transfer function. would then interface to the SOD, SID, SCLK,
Internal circuitry may saturate for large signals and DRDY pins.
which would calibrate to a gain factor less than
0.8.

DS74F1 17
 CS5516, CS5520

AIN and VREF Non-Ratiometric Offset Registers

MSB LSB

≈
Register 20 2-1 2-2 2-3 2-4 2-5 2-18 2-19 2-20 2-21 2-22 2-23
Reset (R) 0 0 0 0 0 0 0 0 0 0 0 0

One LSB represents 2-23 proportion of the internal MDRV (≈2.5 Volts)

DAC Register
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
Register DAC3 DAC2 DAC1 DAC0 EXC F1 F0 D16 G1 G0 U/B D12
Reset (R) 0 0 0 0 0 0 0 0 0 0 0 0

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register A/S EC D9 D8 CC3 CC2 CC1 CC0 D3 D2 D1 RF
Reset (R) 0 0 0 0 0 0 0 0 0 0 0 0

BIT NAME VALUE FUNCTION

DAC3 DAC Sign Bit 0 R1 Add Offset
1 Subtract Offset
DAC2-0 DAC Bits 000 R
001 25% Offset
010 50% Offset
011 75% Offset
100 100% Offset
101 125% Offset
110 150% Offset
111 175% Offset
Bits 0 R These bits mirror the 2
read only
D19 to D0 Configuration Register

Note: 1. Reset State

2. A write to these bits does not change the register bit values.

AIN Ratiometric Offset Register

MSB LSB
≈

Register 20 2-1 2-2 2-3 2-4 2-5 2-18 2-19 2-20 2-21 2-22 2-23
Reset (R) 0 0 0 0 0 0 0 0 0 0 0 0

One LSB represents 2-23 proportion of the voltage [<(VREF+) - (VREF-)>/GAIN] where GAIN = 25 X PGA Gain

GAIN Register
MSB LSB
≈

Register 20 2-1 2-2 2-3 2-4 2-5 2-18 2-19 2-20 2-21 2-22 2-23
Reset (R) 1 0 0 0 0 0 0 0 0 0 0 0

The gain register span from 0 to (2-2-23). After Reset the MSB=1, all other bits are 0.

Table 4. Calibration Registers

18 DS74F1
 CS5516, CS5520

Reading a register in the converter requires a The CS5516/20 is designed such that it can out-
command word to be written to the SID pin. put conversion data words continuously, without
For example, to read the conversion data regis- issuing a new command word prior to each data
ter, the following command sequence should be read. Under the following circumstances, con-
performed. First, the command word 88(H) tinuous conversion data can be read from the
would be issued to the port. In the 5 wire inter- port after issuing only one 88(H) command
face mode, this would involve activating CS word. Once the command to read the conversion
low, followed by 8 SCLKs (note that SCLK data register is issued, DRDY must be allowed
must always start low and transition from low to to go low, after which 24 SCLKs are issued to
high to latch the transmit data, and then back read the data. This will cause DRDY to return
low again) to input the 8-bit command word. CS high.
must be low for the serial port to recognize
SCLKs during a write or a read, but it is actually The converter will continue to output conversion
the first rising SCLK during command time that words at the update rate as long as a different
gives the user control over the port. After writ- command word is not started prior to DRDY
ing the command word, the user must pause and falling again. The user is not required to read
wait until the CS5520 presents the selected reg- every output word to remain in the continuous
ister data to the serial port. The DRDY signal update mode. DRDY will toggle high, and then
will fall when the data is available. When read- low as each new output word becomes available.
ing the conversion data register, it may take up If a command word is issued immediately after a
to 112,000 XIN clock cycles for DRDY to fall data word is read, the converter will end the read
after the 88(H) command word is recognized. conversion mode. Figure 5 illustrates the con-
See Figure 4 for an illustration of command and tinuous data mode.
data word timing.
The user should perform all data reads and com-
The conversion data register is actually the accu- mand writes within 51,000 XIN clock cycles
mulator of the post-processor which computes after DRDY falls to avoid ambiguity as to who
the output data. At the end of each filter convo- controls the serial port.
lution cycle, the internal microcontroller checks
to see if a read conversion data register com- If SMODE = 1 (tied to VD+), the interface oper-
mand has been interpreted. If so, it transfers the ates as a 3 wire interface using only SOD, SID,
accumulator result to the serial port. and SCLK. In the 3 wire mode CS must be tied
to DGND. DRDY operates normally but is not
Whenever registers other than the conversion used. Instead, the DRDY signal modifies the
data register are read, the DRDY pin will fall behavior of the SOD signal, allowing it to signal
within 256 XIN clock cycles (62.5 µs with to the user when data is available. To read data
XIN = 4.096 MHz) after the command word is from the converter requires a command word to
recognized. When DRDY falls, 24 SCLKs are be written to the SID pin. The SOD output is
then issued to the port to read the 24-bit output normally high (never Hi-Z). When output data
data word. DRDY will return high after all 24 is available, the SOD signal will go low. The
bits have been clocked out. The SOD pin will be user would then issue 8 SCLKs to the SCLK pin
in a Hi-Z state whenever CS is high, or after all to clear this data ready signal. On the falling
24 output data bits have been clocked out of the edge of the 8th SCLK the SOD pin will present
port. the first bit of the 24-bit output word. 24 SCLKs
are then issued to read the data. Then SOD will
go high. SID should remain low whenever the
DS74F1 19
 CS5516, CS5520

CS

SCLK

SID MSB LSB

Command Time Data Time

8 SCLKs 24 SCLKs
SID Write

CS

SCLK

SID

Command Time td *
8 SCLKs

DRDY

SOD MSB LSB

Data Time
24 SCLKs
SOD Read (4 or 5 Wire)

SCLK

SID

Command Time td* 81,920 XIN

8 SCLKs Clock Cycles

SOD 8 SCLKs Clear DRDY MSB LSB

SOD falls if
Data Time Command
SOD Read (3 Wire) 24 SCLKs was 88(H)

Figure 4. Command and Data Word Timing

*See text for td time.

20 DS74F1
 CS5516, CS5520

SID pin is not being written. When reading Serial Port Initialization
SOD, SCLK cannot be continuous but must
If for any reason the off-chip microcontroller
burst one clock cycle per bit.
fails to know whether the serial port of the
CS5516/20 is in data mode or command mode,
The continuous read conversion data mode is
the following initialization procedure can be is-
also functional in the 3-wire interface mode. Is-
sued to the port to force the CS5516/20 into the
sue one 88(H) command word to the converter.
command mode. Write 128 or more 1’s to the
Then wait for SOD to go low. Issue 8 SCLKs to
SID pin. Then issue a single 0 to the SID pin.
clear the data ready function. The MSB data bit
The port will then be initialized into the com-
will then appear on the SOD pin. Issue 24
mand mode and will be waiting for an 8-bit
SCLKs to read the conversion word. At the fall-
command word.
ing edge of the 24th SCLK SOD will return
high. SOD will go low at the next DRDY falling
Bridge Excitation Options
time to indicate a new conversion word. Eight
SCLKs must again be issued to clear the data The CS5516/CS5520 A/D converters are opti-
ready function before clocking out the data con- mized for Wheatstone bridge applications. The
version word. The SOD pin will continue to converters support either dc or ac (switched dc)
toggle low each time a word is available even if bridge excitation.
the conversion data is not read. To terminate the
continuous conversion mode, input an 8-bit com- DC Bridge Excitation
man d word immediately after reading a The CS5516/CS5520 can be configured for dc
conversion word. bridge excitation in either of two ways. The
EXC bit of the configuration register can be set
The user should perform all data reads and com- for either internal or for external excitation. If
mand writes within 51,000 XIN clock cycles set to internally-controlled mode (EXC = 0), the
after SOD falls to avoid ambiguity as to who F1 and F0 bits must be set to logic 0s. In this
controls the serial port. condition, the bridge can be excited from a dc
supply with a resistor divider to develop the ap-
propriate reference voltage for the VREF+ and
VREF- pins. Note that the bridge excitation
Port Access Period
Valid 51,000
XIN Clock Cycles

CS

SCLK
8 SCLKs 24 SCLKs 24 SCLKs

SID

8 Data Bits 81,920 XIN

Clock Cycles

DRDY

SOD

24 Data Bits 24 Data Bits

Figure 5. Continuous Read Conversion Data Mode (4 or 5 Wire)

DS74F1 21
 CS5516, CS5520

s ho uld no t be ap plied prior to the from the BX1 and BX2 pins of the converter in
CS5516/CS5520 being powered-up. With EXC, the form of a two-phase non-overlapping clock.
F1, and F0 set to logic 0, the BX1 output will be The converter is capable of demodulating this
logic 0 (0 volts) and the BX2 output will be a clocked excitation. But only if the signals into
logic 1 (+5 volts). the AIN+ and VREF+ pins of the converter are
in phase with the demodulation clock inside the
A second method for configuring the converter converter (see Figure 7). The non-overlapping
for dc excitation is by setting EXC = 1, and clock signals from BX1 and BX2 are CMOS
pulling up BX1 (pin 12) to VD+ (pin 20) level outputs (0 to VD+ volts) and are capable
through a resistor. This sets the converter for of driving one TTL load. A buffer amplifier
use with external excitation which uses the MUST be used to drive the bridge.
BX1 pin as an input to set the excitation fre-
quency. With BX1 = VD+, the external
excitation frequency is zero, or dc. BX1 (Out)

td td
AC Bridge Excitation BX2 (Out)

AC bridge excitation involves using a clock sig-

Demod Clock
nal to generate a square wave which repetitively (Internal)
reverses the excitation polarity on the bridge. To Note: The signals from the bridge into AIN+ and
excite the bridge dynamically requires some type VREF+ of the converter must be in phase
with the demodulation clock.
of bridge driver external to the CS5516/CS5520 t d is 1 cycle of XIN clock.
converter. This driver is driven by a square wave Figure 7. Internal Excitation Clock Phasing
clock. The source of this clock depends upon
whether the converter is set for internal excita- Whenever the internal mode is used for dynamic
tion or for external excitation. Figure 6 bridge excitation the signals are non-overlap-
illustrates a sample bridge drive circuit when op- ping. The non-overlapping time is one XIN
erating in the internal AC excitation mode. clock cycle.
+5V
The converter can also be configured to provide
0.1 µF + 10 µF
+5V 100 k dynamic bridge excitation when operating in the
0V TP0610 6 external-controlled bridge excitation mode. With
BX2 -5V +5V
2 7
EXC+
the EXC bit of the configuration register set to
10 k
-5V logic 1, the BX1 pin becomes an input which
+5V
5
EXC- determines the bridge excitation frequency and
10 k 4
MICREL
-5V phase. BX1 should be near 50% duty cycle. The
3 MIC4428 or user can select the excitation frequency with the
MIC4425 following restrictions. The excitation frequency
-5V
Figure 6. Sample AC Bridge Driver must be synchronous with the XIN frequency of
the converter and must be chosen using the fol-
Using internal excitation involves setting the lowing equation:
EXC bit of the configuration register to 0, and Fexc = (N × XIN) ⁄ 81,920
setting the F1 and F0 bits to select the excitation where N is an integer and lies in the range in-
frequency for the bridge. In this mode the exci- cluding 1 to 160. Fexc is the desired bridge
tation frequency is a sub-multiple of the XIN excitation frequency. Other asynchronous fre-
clock frequency. The excitation clock is output
22 DS74F1
 CS5516, CS5520

quencies are possible but may introduce a jitter verter and the VREF+/VREF- leads to the con-
component in the BX output signals. It is de- verter are filtered, care should be exercised in
sirable not to choose an excitation frequency the choice of components. With either dc or ac
where interference components are present, excitation, one should limit any input filtering
such as 50 Hz or 60 Hz or their harmonics. The resistors on AIN to below 1 kΩ. Values greater
XIN frequency can be divided down using a than this will degrade noise performance of the
counter IC external to the A/D converter. Fexc converter. In ac excitation applications, any fil-
would be input to the BX1 pin of the converter tering must be broadband enough that the
to synchronize the internal operations of the am- switched dc excitation signal can settle within 10
plifiers and synchronous detection circuitry and µsecs. Failure to meet this settling requirement
to generate a clock output from the BX2 pin. will affect measurement accuracy. Figure 9 illus-
The BX2 output is then used to drive the bridge trates acceptable filter components for ac
amplifier with a signal of proper phase for detec- excitation. If only differential filtering is re-
tion by the converter. Figure 8 indicates the quired, a single capacitor can be placed between
necessary phase of the signals to ensure proper AIN+ and AIN- (and VREF+ and VREF-) in
demodulation. place of two capacitors to ground.
7.5k
EXC+ VREF+
BX1 (In) 470 pF
5k
t dd
7.5k 470 pF
BX2 (Out) EXC- VREF- CS5516
300 or
Demod Clock AIN+ AIN+ CS5520
0.0047 µF
(Internal)
Note: The signals from the bridge into AIN+ and
300 0.0047 µF
VREF+ of the converter must be in phase AIN- AIN-
with the demodulation clock.
t dd ≤ 64/XIN Figure 9. AIN and VREF Input Filter Components
Figure 8. External Excitation Clock Phasing

Whenever the dynamic excitation clock output Voltage Reference Considerations

from either the BX1 and BX2 pins (during inter-
nal excitation) or from the BX2 pin (during The CS5516/20 include an on-chip voltage refer-
external excitation) changes states, the converter ence which is output on the MDRV- and
waits 64 XIN cycles before sampling the AIN referenced from the MDRV+ pin. The converter
and VREF signal inputs. The delay allows some is designed to be operated as a ratiometric meas-
time for the signal to settle from the modulation urement device. The 2-channel delta-sigma
event. converter uses the internal MDVR (Modulator
Differential Voltage Reference) as its reference.
Input Filtering Since the MDVR is used for converting both the
AIN and VREF signals at the same time, the ab-
Some load cells are located a distance from the solute value of the MDVR and its tempco are
input to the converter. Under these conditions, not important when the CS5516/20 is used in the
separate twisted pair cabling is recommended for ratiometric measurement mode. The voltage ref-
the excitation drive to the bridge, the excitation erence output, MDVR-, should be decoupled
sense leads (if used), and for the AIN±/ΑΙΝ− using a 1 µF capacitor which is connected to the
signal leads. If the AIN+/AIN- leads to the con- MDRV+ supply line. Voltage reference decou-

DS74F1 23
 CS5516, CS5520

pling is shown on the system connection dia- The digital filter has a deep notch in its transfer
grams. function at 50 Hz (XIN = 4.096 MHz) or 60 Hz
(XIN = 4.9152 MHz) but other XIN frequencies
If absolute measurements are to be made by the can be used. The filter transfer function will
CS5516/20, then a precision reference should be scale proportionally. Figure 11 shows the trans-
input into the VREF+ and VREF- terminals. fer function of the filter when operated at three
different frequencies. With a 3.579 MHz XIN,
Clock Generator the filter offers greater than 90 dB rejection of
both 50 and 60 Hz.
The CS5516/20 includes a gate which can be
connected as a crystal oscillator to provide the 0
master clock to run the chip. Alternatively, an
-20
external (CMOS compatible) clock can be input (1) XIN = 3.579 MHz
-40 (2) XIN = 4.096 MHz
into the XIN pin. Figure 10 illustrates a simple (3) XIN = 4.915 MHz

Magnitude (dB)
model for the on-chip gate oscillator. The on- -60
chip oscillator is designed to typically operate -80
with crystal frequencies between 4.0 and 5.0
-100
MHz without additional loading capacitors. If
other crystal frequencies, or if ceramic resona- -120

tors are used, additional loading capacitance may -140

be necessary. -160
0 21.8 43.7 87.3 131.0 174.7 218.5
>1M 0 25 50 100 150 200 250
To Internal circuitry
XIN 0 30 60 120 180 240 300
400 400 XOUT Input Frequency (Hz)
22 23
Figure 11. Filter Magnitude Response
1pF 5pF 5pF 1pF
gm≅ 2000 umhos
180
150
XIN = 4.096 MHz
120
External XTAL
90
Figure 10. On-Chip Gate Oscillator Model
Phase (degrees)

60
30
The XOUT pin can be used to drive one CMOS 0
gate for system clock requirements. Be sure to -30
include the gate’s input capacitance and stray ca- -60

pacitance as part of the loading capacitance for -90

-120
the resonating element.
-150
-180
Digital Filter 0 5 10 15 20 25 30 35 40 45 50
Input Frequency (Hz)
The CS5516/20 is optimized to operate with clock
Figure 12. Filter Phase Response.
frequencies of 4.096 MHz or 4.9152 MHz. These
result in the filter having a 3dB bandwidth of 12
The output word rate of the converter scales
Hz or 15 Hz, with output word rates of 50 or
with the XIN clock rate and is set by the ratio of
60Hz. The rejection at 50Hz ± 3Hz is 70 dB mini- XIN/81,920; or 50 Hz for XIN = 4.096 MHz. If
mum with a 4.096 MHz clock. Similar rejection is very narrow signal bandwidths, such as 3 Hz,
obtained at 60 Hz with a 4.9152 MHz clock. are desired, averaging of the output words is rec-
ommended.
24 DS74F1
 CS5516, CS5520

The digital filter computes a new output data Under normal operating conditions, the flag bits
word every 81,920 XIN clock cycles. If the in- will be zeroes. The flag bits will be set to all
put experiences a large change in amplitude, the ones whenever an overrange condition exists.
PGA gain is changed, or the DAC calibration Under large overrange conditions where the in-
registers are changed, it may take up to six filter put signal exceeds the nominal full scale input
cycles (81,920 X 6 clock cycles) for the filter to by approximately two times (for example:
compute an output word which is fully settled to 50 mV input when the nominal full scale input
the input signal. is set-up for 25 mV), the converter may be un-
able to compute a proper output code. In this
Output Coding condition flag bits will be set to all 1s but the
conversion data may be a value other than full
The CS5516/20 converters output data in binary
scale plus or minus.
format when operating in unipolar mode and in
two’s complement when operating in bipolar
After the converter is first powered-up, a RST is
mode. Table 5 illustrates the output coding for
issued, or the device comes out of the SLEEP
the converters. Note that when reading conver-
mode, the first conversion data read may
sion data from the converter the data word is
erroneously have its error flag bits set to "1".
output MSB or sign bit first. Falling edges on
SCLK advance the data word to the next lower
Synchronizing Multiple Converters
bit.
Multiple converters can be made to output their
The output conversion words from both the conversion words at the same time if they are
CS5516 and the CS5520 are 24 bits long. The operated from the same clock signal at XIN. To
CS5516 has 16 data bits followed by 8 flag bits synchronize multiple converters requires that
(all identical). The CS5520 has 20 data bits fol- they all have their RF bit of the configuration
lowed by 4 flag bits (all identical). To read the register written to a logic 1 and then back to 0.
conversion data, including the error flag infor- The filters will be allowed to start convolutions
mation will require at least 17 SCLKs for the after the falling edge of the 24th SCLK used to
CS5516 and at least 21 SCLKs for the CS5520. write the RF bit to the configuration register.

Unipolar Input Offset Bipolar Input Two’s Unipolar Input Offset Bipolar Input Two’s
Voltage Binary Voltage Complement Voltage Binary Voltage Complement
>(VFS-1.5 LSB) FFFF >(VFS-1.5 LSB) 7FFF >(VFS-1.5 LSB) FFFFF >(VFS-1.5 LSB) 7FFFF
FFFF 7FFF FFFFF 7FFFF
VFS-1.5 LSB ----- VFS-1.5 LSB ----- VFS-1.5 LSB ----- VFS-1.5 LSB -----
FFFF 7FFE FFFFE 7FFFE
8000 0000 80000 00000
VFS/2-0.5 LSB ----- -0.5 LSB ----- VFS/2-0.5 LSB ----- -0.5 LSB -----
7FFF FFFF 7FFFF FFFFF
0001 8001 00001 80001
+0.5 LSB ----- -VFS+0.5 LSB ----- +0.5 LSB ----- -VFS+0.5 LSB -----
0000 8000 00000 80000
<(+0.5 LSB) 0000 <(-VFS+0.5 LSB) 8000 <(+0.5 LSB) 00000 <(-VFS+0.5 LSB) 80000
CS5516 Output Coding CS5520 Output Coding
Note: VFS in the table equals the full scale voltage between +VREF/(G x 25) and ground for unipolar mode; and
between ±VREF/(G x 25) for bipolar mode. The signal input to the A/D section of the converter has been
amplified by the instrumentation amplifier (x25) and the PGA gain, G (1, 2, 4, or 8). See text about error
flags under overrange conditions.
Table 5. Output Coding for the CS5516/20 Converters.

DS74F1 25
 CS5516, CS5520

The filter will start a new convolution on the

next rising edge of the XIN clock after the 24th 140

SCLK falls. 120

100
Sleep Mode
80
The CS5516/20 configuration register has an 60
A/S bit which allows the users to put the device
40
in a sleep condition to lower quiescent power.
Upon reset the A/S bit device is set to a logic 0 20
which places the device in the ’awake’ condi- 0
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
tion. Writing a 1 to the A/S bit will shutdown
Figure 13. CS5520 Noise Histogram.
most of the chip, including the oscillator. It is
desirable to use the following sequence when
coming out of sleep. Write a logic 0 to the A/S
bit of the configuration register. In the same
configuration word write a logic 1 to the RF bit
of the configuration register. Then wait until it is
certain that the oscillator has started. After the
oscillator has started or a clock present on the
XIN pin, set the RF bit back to 0. The user
should then wait at least 6 output word update
periods before expecting a valid output data
word.

Noise Performance
Typical noise performance for the converter is
listed in the specification tables for each PGA
gain. Figure 13 illustrates a noise histogram for
1000 output conversions from the CS5520. The
data for the histogram was collected using the
CDB5520 evaluation board; with VREF at 2.5
volts, PGA = 4, bipolar mode. The data shows
the standard deviation of the data set is 3.2
Schematic & Layout Review Service
LSBs. One LSB is equivalent to [VREF X 2(bi-
Confirm Optimum
polar)]/ [Inst amp gain X PGA gain X number
Schematic & Layout
of codes] or (2.5 X 2)/ (25 X 4 X 2E20) = 47.7
Before Building Your Board.
nV. One standard deviation is equivalent to rms
if the data is Normal or Gaussian. The rms noise For Our Free Review Service
presented by the plot is 153 nV, which is in Call Applications Engineering.
good agreement with the typical noise specifica-
tion of 150 nV for a PGA gain of 4. C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2

Applications
See the Application Notes section of the databook.

26 DS74F1
 CS5516, CS5520

PIN DESCRIPTIONS

Modulator Diff. Voltage Ref + MDRV+ 1 24 SMODE Serial Interface Mode

Modulator Diff. Voltage Ref - MDRV- 2 23 XOUT Crystal Out
Positive Analog Power VA+ 3 22 XIN Crystal In
Negative Analog Power VA- 4 21 VD- Negative Digital Power
Analog Ground One AGND1 5 20 VD+ Positive Digital Power
Analog In + AIN+ 6 19 DGND Digital Ground
Analog In - AIN- 7 18 SOD Serial Output Data
Analog Ground Two AGND2 8 17 SID Serial Input Data
Voltage Ref In + VREF+ 9 16 SCLK Serial Clock Input
Voltage Ref In - VREF- 10 15 DRDY Data Ready
Bridge Excite 2 BX2 11 14 CS Chip Select
Bridge Excite 1 BX1 12 13 RST Reset

Power Supply Connections

VD+ - Positive Digital Power, PIN 20.
Positive digital supply voltage. Nominally +5 volts.

VD- - Negative Digital Power, PIN 21.

Negative digital supply voltage. Nominally -5 volts.

DGND - Digital Ground, PIN 19.

Digital ground.

VA+ - Positive Analog Power, PIN 3.

Positive analog supply voltage. Nominally +5 volts.

VA- - Negative Analog Power, PIN 4.

Negative analog supply voltage. Nominally -5 volts.

AGND1, AGND2 - Analog Ground, PINS 5, 8.

Analog ground.

Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 22, 23
An internal gate is connected to these pins enabling the use of either a crystal or a ceramic
resonator to provide the master clock for the device. Alternatively, an external (CMOS
compatible) clock can be input to the XIN pin as the master clock for the device.

DS74F1 27
 CS5516, CS5520

Digital Inputs
RST - Reset, PIN 13.
Reset pin initializes all calibration registers to a known condition and places the serial port into
the command mode.

CS - Chip Select, PIN 14.

An input which can be enabled by an external device to gain control over the serial port. When
this pin is high, SOD is in a high impedance state if SMODE = 0.

SCLK - Serial Data Clock, PIN 16.

A clock signal at this pin determines the output rate of the data from the SOD pin and the input
data rate on the SID pin.

SID - Serial Input Data, PIN 17.

This pin is used for inputting command and configuration words or inputting calibration words.
Data is input at a rate determined by SCLK. SID is in a don’t care state when no data is being
clocked in.

SMODE - Serial Interface Mode, PIN 24.

Selects the operating mode of the serial port. When low the serial port operates in the 5 or 4
wire interface mode. When high the chip will enter the 3 wire interface mode.

Analog Inputs
AIN+ and AIN- - Analog Inputs, PINS 6, 7.
The analog input signals from the transducer. These are true differential inputs.

VREF+ and VREF- - Voltage Reference Inputs, PINS 9,10.

These are the differential analog reference voltage inputs.

MDRV+ - Modulator Differential Voltage Reference, PIN 1.

Positive terminal of the internal differential voltage reference which can be tied to the positive
supply (VA+) or ground (AGND).

MDRV- - Modulator Differential Voltage Reference, PIN 2.

This is the -3.75V modulator differential voltage reference output and can be used to generate
an analog reference. Note this is with reference to the MDRV+ pin.

28 DS74F1
 CS5516, CS5520

Digital Outputs
BX1 and BX2 - AC Bridge Excitation Signals, PINS 12, 11.
These can be buffered to drive the transducer or used as synchronizing signals for a transducer
drive circuit. BX1 and BX2 are 0 to +5V signals.

DRDY - Data Ready, PIN 15.

DRDY goes low every 81,920 cycles of XIN (when in read conversion data mode) to indicate
that new data has been placed in the output port. DRDY goes high when all the serial port data
is clocked out, when the serial port is being updated with new data, when a calibration is in
progress, or when the device is in SLEEP.

SOD - Serial Output Data, PIN 18.

Data from the serial port will be output from this pin at a rate determined by SCLK . The data
will either be conversion data, or, calibration values, dependent upon the command word that
has been previously input on the SID pin. The SOD pin furnishes a high impedance output
state when not transmitting data (SMODE = 0).

ORDERING GUIDE

Model Number Linearity Error (Max) Temperature Range Package

CS5516-AP 0.003% -40°C to +85°C 24-pin 0.3" Plastic DIP
CS5516-AS 0.003% -40°C to +85°C 24-pin 0.3" SOIC
CS5520-BP 0.0015% -40°C to +85°C 24-pin 0.3" Plastic DIP
CS5520-BS 0.0015% -40°C to +85°C 24-pin 0.3" SOIC

DS74F1 29
 CS5516, CS5520

SPECIFICATION DEFINITIONS

Linearity Error
The deviation of a code from a straight line which extends between two fixed points on the
A/D converter transfer function. In unipolar mode, the straight line extends from one point
located 1⁄2 LSB below the first code transition, one count above all zeros; to the second point
located 1⁄2 LSB beyond the code transition to all ones. In bipolar mode, the straight line extends
from one point located 1⁄2 LSB beyond the code transition to all ones, passing through a point
1⁄ LSB below code 8000(H) (16-bit); 80000(H) (20-bit); extending to beyond negative full
2
scale. Units are in percent of full-scale.

Differential Nonlinearity
The deviation of a code’s width from the ideal width. Units in LSBs.

Full Scale Error

The deviation of the last code transition form the ideal [{(VREF+)-(VREF-)}-3⁄2 LSB]. Units
are in LSBs.

Unipolar Offset
The deviation of the first code transition from the ideal (1⁄2 LSB above AGND) when in
unipolar mode (BP/UP low). Units are in LSBs.

Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1⁄2 LSB below
AGND) when in bipolar mode (BP/UP high). Units are in LSBs.

30 DS74F1
 CDB5516
CDB5520
CS5516 and CS5520 ADC Evaluation Board
Features Description
l On-board microcontroller The CDB5516 and CDB5520 provide quick and easy
l RS232 Serial Communicationswith host PC evaluation of the CS5516 and CS5520 bridge transducer
A/D converters. Direct connection of the bridge to the
l Supports either AC or DC bridge drive evaluation board is provided.
l On-board bridge driver
The board also contains a microcontroller, with firmware
l Supports ratiometric or absolute which allows the board to be controlled via simple serial
measurements commands, using the RS232 communications port of a
l Evaluation software included PC.

ORDERING INFORMATION
CDB5516 Evaluation Board
CDB5520 Evaluation Board
I

-5V 0V +5V 0V +5V

Load
Cell
AIN+ Clock
RS232
CS5516 Driver/
Receiver
CS5520
AIN- SCLK
SID Microcontroller
SOD
VREF+

VREF- RS232
Connector
Bridge
Excitation
BX1
BX2

Cirrus Logic, Inc.

Crystal Semiconductor Products Division Copyright  Cirrus Logic, Inc. 1998 MAR ‘95
P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
DS74DB#
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com 31
 CDB5516/CDB5520

Introduction Evaluation Board Overview

The CDB5516/20 evaluation board provides a Figure 1 illustrates the schematic of the bridge
means of testing the CS5516 and CS5520 bridge driver and A/D converter portion of the circuit
transducer A/D converters. The board is de- board. The converter operates from a 4 MHz
signed to be interfaced to a PC-compatible crystal. This results in the converter outputting
computer via an RS-232 port. Software is sup- conversion words at a 50 Hz rate. The board
plied with the board which provides control of comes configured to be interfaced to a bridge
all registers in the CS5516 or the CS5520. transducer via the 6-pin transducer terminal
block. The sense lines on the transducer termi-
The board is configured to be operated from +5 nal block provide the reference voltage for the
and -5 volt power supplies. A bridge transducer converter.
or a bridge transducer simulator is required if the
board is to be evaluated in the ratiometric oper- For absolute measurements, the user can connect
ating mode. either an external reference voltage (up to 3.8
volts) to the reference terminal block or connect
the on-board 2.5 volt LT1019 reference as the
voltage reference for the converter.
R1
MICREL 10
Q1 +5VA
+5VA MIC4428
TP0610 0.1µF C7 C9
0.1µF
3 1 1µF 2 20
6 C8 10k
100k VA+ MDRV+ MDRV- VD+ R17
7
2 R13
10k 11
BX2 12
EXC BX1
EXC GND R14 100k
U3 C20 C21
EXC 4 10k R16
+ R15 CS5516/20
5 22
3 0.1µF 10 µF XIN
P1
SIG+ -5VA 301 6 4.000
AIN+ MHz
R12 C18
SIG- 5
4.7nF AGND1
8 23
AGND2 XOUT OSCLK
SENSE+
4.7nF 24
301 C19 7 SMODE SMODE
SENSE- AIN- 18
R11 SOD SOD
EXC+ 7.5k 17 To
9 SID SID
VREF+ Figure 2
EXC- R7 470pF 16
5.0k SCLK SCLK
C16 1A
R6 15
1B DRDY DRDY
2A 14
7.5k C17 470pF 10 CS CS
R4 VREF- 13
P2 301 R5 RST RST
2B
REF+ 19
301 4.7nF C15 DGND
REF-
R3 VA- VD-
4 R2 21 0.1µF
+5VA
-5VA C10
U5 50
C14 10
LT1019- C11 J1
0.1µF 0.1µF
2.5V R8 0.1µF
RST
CS
DRDY
SCLK
SID
SOD
SMODE

C29 AGND DGND

Figure 1. Bridge Driver and A/D Converter

32 DS74DB3
 CDB5516/CDB5520

A bridge driver, composed of a Siliconix TP0610 PC-compatible computer via the RS-232 inter-
transistor and a Micrel MIC4428 dual CMOS face. The microcontroller derives its 4 MHz
driver, is provided which allows the BX2 output clock from the A/D converter clock. The micro-
from the CS5516 or CS5520 to provide either dc controller is configured to communicate over the
or ac excitation to the bridge. RS-232 link at 4800 baud, no parity, 8-bit data,
and 1 stop bit. A Motorola MC145407 RS-232
The digital interface pins of the A/D converter interface chip is used to send and recieve data to
connect to the microcontroller, or alternatively, the PC-compatible computer via the 25-pin Sub-
these connections can be cut, or the on-board D connector.
microcontroller can be removed, and the user’s
own microcontroller can be interfaced to J1 Table 1 lists the commands sent to the microcon-
header connector. troller to write to or to read from the registers in
the A/D converter. If software other than that
Figure 2 illustrates the Motorola 68HC705C8 provided with the evaluation board is used, the
microcontroller which reads or writes data into format of the data transmitted over the RS232
the A/D converter and communicates with the line is as follow: Write commands are com-

+5VD

+5VD
+ C23 0.1µF 10µF
C25
47µF C22 +
19 17
40 10k Vcc VDD R28
1 RESET 3 18 10k
10k 10k VDD RESET C2- C1- C27
R20 10µF RI
3 Vpp C28 + 1 20 + 10µF 22
1µF
2 U2 C24 RXD C2+ C1+
IRQ
29 16 5 TXD
68HC705C8 PD0 2
38 OSC2 TXD
30 15 6 RXD
39 PD1 3
OSCLK OSC1
+5VD
SMODE 10 PA1
34 14 7 RTS
PD5 35 4
31
SOD PD2 TCMP 37 470 470 470
From 32 TCAP 13 8 CTS
SID PD3 5
Figure 1 33 D1 D2
SCLK PD4 8
PA3
36 PD7 7 12 9 DTR
DRDY PA4 20
6
PA5
11 5
CS PA0 PA6
4 11 10 DSR
9 PA7 6
RST PA2

12 28 DCD
PB0 PC0 8
13 PC1 27
PB1 U4
14 PC2 26
PB2
15 PC3 25 MC145407 7
PB3
16 PC4 24
PB4 GND Vss
17 PC5 23
PB5
18 PC6 22 2 4
PB6
19 21 Sub-D
+

PB7 Vss PC7

25 Pin
20 10µF
C26
Figure 2. Microcontroller and RS-232 Interface

DS74DB3 33
 CDB5516/CDB5520

Register Read Write

Conversion Data Register 50(H)
Configuration Register 51(H) D1(H)
DAC Register 53(H) D3(H)
Gain Register 52(H) D2(H)
AIN Ratiometric Offset Register 54(H) D4(H)
AIN Nonratiometric Offset Register 55(H) D5(H)
VREF Nonratiometric Offset Register 56(H) D6(H)

Table 1. Microcontroller commands via RS-232

posed of one byte for command which is trans- One of the converters is used to convert the
mitted with its LSB first. The command is VREF voltage input, and the other is used to
followed by three data bytes which make up the convert the AIN signal input. Both converters
24-bit word to be written to the selected register utilize an on-chip voltage reference to perform
of the A/D converter. The three bytes are trans- conversions of their respective inputs. Since
mitted lowest order byte first (bits 7 - 0) with the both converters use the same reference they
LSB of the byte transmitted first. track one another. The digital processing logic
of the A/D converter depends on the presence of
Figure 3 illustrates the power supply connections both signals to properly compute a digital output
to the evaluation board. Voltages of +5 and -5 word. If the evaluation board is configured for
analog and +5 digital are required. bridge measurement, and no bridge (load cell or
simulator) is connected to the bridge transducer
Using the Evaluation Board terminal block, the converter will output a code
of zero because no reference voltage is present
Prior to using the board to evaluate the CS5516 between the VREF+ and VREF- pins.
or CS5520 A/D converter, a good understanding
of the full potential of the converter is necessary. The span of the AIN input signal is determined
It is recommended that the CS5516/CS5520 de- by a combination of the instrumentation ampli-
vice data sheet be thoroughly read prior to fier gain (X25), the programmable gain amplifier
attemp ting to u se the ev aluation board. (PGA) gain, the magnitude of the voltage be-
The CS5516 or CS5520 bridge transducer A/D tween the VREF+ and VREF- input pins, and
converter actually contains two A/D converters. the calibration words for gain and offset. For ex-
+5V +5VA +5 +5VD

+ +
C3 C4 Z3 C5 C6
Z1
47µF 0.1µF
47µF 0.1µF
DGND
AGND

+
Z2 C1 C2
47µF 0.1µF
-5V -5VA

Figure 3. Power Supplies

34 DS74DB3
 CDB5516/CDB5520

ample, the board comes with a set of precision ible in handling load cells with different output
resistors which divide the excitation supply levels. Whenever configured as a bridge
(nominally 10 volts total) down to 2.5 volts be- transducer device, the CS5516 or the CS5520
tween the VREF+ and VREF- input pins. This A/D converter operates in ratiometric measure-
sets the nominal full scale voltage into the A/D ment mode. Figures 4 and 5 illustrate how to
converter. The input span of the instrumentation connect 4-wire and 6-wire bridge transducers to
amplifier can be calculated to by knowing the the board.
PGA gain setting, and that the gain of the instru-
mentation amplifier is X25. If the PGA is set for Alternatively, the CS5516 or CS5520 can be
a gain of 8, then the input span to the instrumen- configured for absolute measurement if a preci-
tation amplifier will be 2.5 volts (VREF+ - sion reference voltage is supplied between the
VREF-) divided by 8 X 25, or 2.5/(200) = 12.5 VREF+ and VREF- pins of the A/D converter.
millivolt nominal in unipolar mode. The device The board can be modified to accept a reference
can be then calibrated with an input voltage into the voltage reference terminal block; or the
which is as low as 20% less than nominal or up on-board LT1019-2.5 volt reference can be used
to 20% greater than nominal. Therefore, with as the reference voltage for the A/D converter.
this VREF+ - VREF- voltage (2.5 volts) and a To use either of these inputs will require that
PGA gain of 8 the input span can be calibrated jumper wires be soldered in either 1A-1B to se-
to handle a span from a low of 10 mV to a high lect the external voltage reference input, or
of 15 mV. To modify the input span the user can 2A-2B to select the on-board LT1019-2.5. Fig-
either change the PGA gain or modify the resis- ure 6 illustrates the connection of an external
tor divider on the bridge sense voltage to yield voltage reference to the evaluation board for ab-
an appropriate value in the range of 2.0 to 3.8 solute voltage measurement applications. To
volts. This makes the A/D converter quite flex- achieve an accurate reference voltage resistor R6

SIG + SIG +

SIG - SIG -

SENSE + SENSE +
_ _
+ SENSE - + SENSE -

EXC + EXC +

EXC - EXC -

Figure 4. 4-Wire Bridge Connections Figure 5. 6-Wire Bridge Connections

DS74DB3 35
 CDB5516/CDB5520

must be removed from between the +VREF and MIC4428 driver should be returned to the EXC
-VREF pins. It may be desirable to also remove position.
R5, R7, C16, and C17 in some applications.
After the non-ratiometric calibration steps are
Calibrating the A/D Converter performed, the AIN ratiometric offset is then
calibrated. With "zero weight" on the load cell,
As explained in the CS5516/CS5520 data sheet, the converter is instructed via the configuration
the order in which the calibration steps are per- register to perform the AIN ratiometric offset
formed are important. If one chooses to use the calibration step. Finally, with "full scale weight"
non-ratiometric calibration capabilities of the on the load cell, the converter is instructed to
converter, the non-ratiometric errors of the perform the gain calibration step.
VREF and AIN channels should be calibrated
first. The non-ratiometric calibration steps can The converter is then ready to perform conver-
be performed at the same time. Before the non- sions.
ratiometric offset calibration is initiated, the
bridge should be grounded. This can be achieved Software
on the evaluation board by moving the two
jumpers at the output of the MIC4428 driver to The evaluation board comes with software and a
the GND position (see Figure 1). The converter RS-232 cable to interface the board to a RS-232
is then instructed via the configuration register port of a PC-compatible computer. The software
bits to perform the non-ratiometric calibration diskette contains a README.TXT file which
steps. Once the non-ratiometric calibrations are explains its operation.
completed, jumpers at the output of the

+5V +5VA +5 +5VD

+ +
C3 C4 Z3 C5 C6
Z1
47µF 0.1µF
47µF 0.1µF
DGND
AGND

+
Z2 C1 C2
47µF 0.1µF
-5V -5VA

Figure 6. Using Off-board Voltage Reference

36 DS74DB3
 CDB5516/CDB5520

Figure 7 illustrates the software supplied with

the CDB5516/CDB5520 evaluation board. The
software allows the user to manipulate the regis-
ters of the converter and perform calibrations
and conversions. It decodes the status of the con-
figuration register and indicates the gain register
scale factor. The software enables the user to
collect data to a file, average samples and com-
pute the average and standard deviation of the
samples which have been collected.

Figure 7. Screen for the CDB5516/CDB5520 Evaluation Board Software

DS74DB3 37
 CDB5516/CDB5520

Figure 8. CDB5520 Silkscreen

38 DS74DB3
 CDB5516/CDB5520

Figure 9. CDB5520 Top Ground Plane

DS74DB3 39
 CDB5516/CDB5520

Figure 10. CDB5520 Solder Side Trace Layer

40 DS74DB3
• Notes •