LTC2499

24-Bit 8-/16-Channel
DS ADC with Easy Drive Input Current
Cancellation and I2C Interface
Features Description
n Up to Eight Differential or 16 Single-Ended Inputs The LTC®2499 is a 16-channel (eight differential), 24-bit,
n Easy Drive™ Technology Enables Rail-to-Rail No Latency ∆S™ ADC with Easy Drive technology and a
Inputs with Zero Differential Input Current 2-wire, I2C interface. The patented sampling scheme elimi-
n Directly Digitizes High Impedance Sensors with nates dynamic input current errors and the shortcomings
Full Accuracy of on-chip buffering through automatic cancellation of
n 2-Wire I2C Interface with 27 Addresses Plus One differential input current. This allows large external source
Global Address for Synchronization impedances and rail-to-rail input signals to be directly
n 600nV RMS Noise digitized while maintaining exceptional DC accuracy.
n Integrated High Accuracy Temperature Sensor
The LTC2499 includes a high accuracy, temperature
n GND to V
CC Input/Reference Common Mode Range sensor and an integrated oscillator. This device can be
n Programmable 50Hz, 60Hz or Simultaneous
configured to measure an external signal (from combi-
50Hz/60Hz Rejection Mode nations of 16 analog input channels operating in single-
n 2ppm INL, No Missing Codes
ended or differential modes) or its internal temperature
n 1ppm Offset and 15ppm Full-Scale Error
sensor. The integrated temperature sensor offers 1/30th°C
n 2x Speed/Reduced Power Mode (15Hz Using Internal
resolution and 2°C absolute accuracy.
Oscillator and 80µA at 7.5Hz Output)
n No Latency: Digital Filter Settles in a Single Cycle, The LTC2499 allows a wide common mode input range
Even After a New Channel Is Selected (0V to VCC), independent of the reference voltage. Any
n Single Supply 2.7V to 5.5V Operation (0.8mW) combination of single-ended or differential inputs can
n Internal Oscillator be selected and the first conversion, after a new channel
n Tiny 5mm × 7mm QFN Package is selected, is valid. Access to the multiplexer output en-
ables optional external amplifiers to be shared between all
Applications analog inputs and auto calibration continuously removes
their associated offset and drift.
n Direct Sensor Digitizer L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
n Direct Temperature Measurement No Latency ∆∑ and Easy Drive are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
n Instrumentation
n Industrial Process Control

Typical Application Integrated High Performance Temperature Sensor

Data Acquisition System with Temperature Compensation 5
2.7V TO 5.5V 4
3
CH0 MUXOUT/ VCC 10µF 0.1µF
ABSOLUTE ERROR (°C)

CH1 ADCIN 2
• REF+
• 1
• IN+
CH7 16-CHANNEL 1.7k
24-BIT ∆Σ ADC 0
CH8 MUX WITH EASY DRIVE SDA
• 2-WIRE –1
• IN– SCL I2C INTERFACE
• –2
CH15 REF–
COM –3
fO
TEMPERATURE –4
MUXOUT/ OSC
SENSOR ADCIN –5
2499 TA01 –55 –30 –5 20 45 70 95 120
TEMPERATURE (°C) 2499 TA02
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LTC2499
Absolute Maximum Ratings Pin Configuration
(Notes 1, 2)
TOP VIEW
Supply Voltage (VCC).................................... –0.3V to 6V

GND
GND
GND
CA2
CA1
CA0
Analog Input Voltage

fO
38 37 36 35 34 33 32
(CH0-CH15, COM).....................–0.3V to (VCC + 0.3V)
GND 1 31 GND
REF +, REF –................................–0.3V to (VCC + 0.3V) SCL 2 30 REF–
ADCINN, ADCINP, MUXOUTP, SDA 3 29 REF+
MUXOUTN.................................–0.3V to (VCC + 0.3V) GND 4 28 VCC
Digital Input Voltage.......................–0.3V to (VCC + 0.3V) NC 5 27 MUXOUTN

Digital Output Voltage....................–0.3V to (VCC + 0.3V) GND 6

39
26 ADCINN

Operating Temperature Range COM 7 25 ADCINP

CH0 8 24 MUXOUTP
LTC2499C................................................. 0°C to 70°C
CH1 9 23 CH15
LTC2499I..............................................–40°C to 85°C CH2 10 22 CH14
Storage Temperature Range....................–65°C to 150°C CH3 11 21 CH13
CH4 12 20 CH12
13 14 15 16 17 18 19

CH5
CH6
CH7
CH8
CH9
CH10
CH11
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN #39) IS GND, MUST BE SOLDERED TO PCB

order information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2499CUHF#PBF LTC2499CUHF#TRPBF 2499 38-Lead (5mm × 7mm) Plastic QFN 0°C to 70°C
LTC2499IUHF#PBF LTC2499IUHF#TRPBF 2499 38-Lead (5mm × 7mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

electrical characteristics (normal speed)

The l denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 24 Bits
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) l 2 10 ppm of VREF
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) l 1 ppm of VREF
Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) l 0.5 2.5 µV
Offset Error Drift 2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN– ≤ V CC 10 nV/°C
Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF l 25 ppm of VREF
Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 0.1 ppm of VREF/°C
Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF l 25 ppm of VREF
Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF 0.1 ppm of VREF/°C
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Electrical
The Characteristics (Normal Speed) l denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 15 ppm of VREF
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V 15 ppm of VREF
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 15 ppm of VREF
Output Noise 2.7V < VCC < 5.5V, 2.5V ≤ VREF ≤ VCC, 0.6 µVRMS
GND ≤ IN+ = IN– ≤ VCC (Note 12)
Internal PTAT Signal TA = 27°C (Note 13) 27.8 28.0 28.2 mV
Internal PTAT Temperature Coefficient 93.5 µV/°C

Electrical
The Characteristics (2x Speed) l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 24 Bits
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) l 2 10 ppm of VREF
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 1 ppm of VREF
Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) l 0.2 2 mV
Offset Error Drift 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 100 nV/°C
Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF l 25 ppm of VREF
Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 0.1 ppm of VREF/°C
Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF l 25 ppm of VREF
Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF 0.1 ppm of VREF/°C
Output Noise 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN+ = IN– ≤ VCC 0.85 µVRMS

Converter
The Characteristics l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN– ≤ V CC (Note 5) l 140 dB
Input Common Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7) l 140 dB
Input Common Mode Rejection 60Hz ±2% 2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN– ≤ V CC (Notes 5, 8) l 140 dB
Input Normal Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7) l 110 120 dB
Input Normal Mode Rejection 60Hz ±2% 2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN– ≤ V CC (Notes 5, 8) l 110 120 dB
Input Normal Mode Rejection 50Hz/60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9) l 87 dB
Reference Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC , GND ≤ IN+ = IN– ≤ V CC (Note 5) l 120 140 dB
Power Supply Rejection DC VREF = 2.5V, IN+ = IN– = GND 120 dB
Power Supply Rejection, 50Hz ±2%, 60Hz ±2% VREF = 2.5V, IN+ = IN– = GND (Notes 7, 8, 9) 120 dB

Analog
The Input and Reference l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN+ Absolute/Common Mode IN+ Voltage GND – 0.3V VCC + 0.3V V
(IN+ Corresponds to the Selected Positive Input Channel)
IN– Absolute/Common Mode IN– Voltage GND – 0.3V VCC + 0.3V V
(IN– Corresponds to the Selected Negative Input Channel
or COM)
VIN Input Voltage Range (IN+ – IN–) Differential/Single-Ended l –FS +FS V
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Analog
The Input and Reference l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
FS Full Scale of the Input (IN+ – IN–) Differential/Single-Ended l 0.5VREF V
LSB Least Significant Bit of the Output Code l FS/224
REF+ Absolute/Common Mode REF+ Voltage l 0.1 VCC V
REF– Absolute/Common Mode REF– Voltage l GND REF+ – V
0.1V
VREF Reference Voltage Range (REF+ – REF–) l 0.1 VCC V
CS(IN+) IN+ Sampling Capacitance 11 pF
CS(IN–) IN– Sampling Capacitance 11 pF
CS(VREF) VREF Sampling Capacitance 11 pF
IDC_LEAK(IN+) IN+ DC Leakage Current Sleep Mode, IN+ = GND l –10 1 10 nA
IDC_LEAK(IN–) IN– DC Leakage Current Sleep Mode, IN– = GND l –10 1 10 nA
IDC_LEAK(REF+) REF+ DC Leakage Current Sleep Mode, REF+ = V CC l –100 1 100 nA
IDC_LEAK(REF–) REF– DC Leakage Current Sleep Mode, REF– = GND l –100 1 100 nA
tOPEN MUX Break-Before-Make 50 ns
QIRR MUX Off Isolation VIN = 2VP-P DC to 1.8MHz 120 dB

2C Inputs And Digital Outputs

I The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l 0.7VCC V
VIL Low Level Input Voltage l 0.3VCC V
VIHA Low Level Input Voltage for Address Pins CA0, CA1, CA2 l 0.05VCC V
and Pin fO
VILA High Level Input Voltage for Address Pins CA0, CA1, CA2 l 0.95VCC V
RINH Resistance from CA0, CA1, CA2 to VCC to Set Chip Address l 10 kΩ
Bit to 1
RINL Resistance from CA0, CA1, CA2 to GND to Set Chip Address l 10 kΩ
Bit to 0
RINF Resistance from CA0, CA1, CA2 to GND or VCC to Set Chip l 2 MΩ
Address Bit to Float
II Digital Input Current l –10 10 µA
VHYS Hysteresis of Schmitt Trigger Inputs (Note 5) l 0.05VCC V
VOL Low Level Output Voltage (SDA) I = 3mA l 0.4 V
tOF Output Fall Time VIH(MIN) to VIL(MAX) Bus Load CB 10pF to l 20 + 0.1CB 250 ns
400pF (Note 14)
IIN Input Leakage 0.1VCC ≤ VIN ≤ VCC l 1 µA
CCAX External Capacitative Load on Chip Address Pins (CA0, CA1, l 10 pF
CA2) for Valid Float

Power
The Requirements l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage l 2.7 5.5 V
ICC Supply Current Conversion Current (Note 11) l 160 275 µA
Temperature Measurement (Note 11) l 200 300 µA
Sleep Mode (Note 11) l 1 2 µA
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Digital
The Inputs And Digital Outputs l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range (Note 16) l 10 1000 kHz
tHEO External Oscillator High Period l 0.125 100 µs
tLEO External Oscillator Low Period l 0.125 100 µs
tCONV_1 Conversion Time for 1x Speed Mode 50Hz Mode l 157.2 160.3 163.5 ms
60Hz Mode l 131 133.6 136.3 ms
Simultaneous 50Hz/60Hz Mode l 144.1 146.9 149.9 ms
External Oscillator (Note 10) 41036/fEOSC (in kHz) ms
tCONV_2 Conversion Time for 2x Speed Mode 50Hz Mode l 78.7 80.3 81.9 ms
60Hz Mode l 65.6 66.9 68.2 ms
Simultaneous 50Hz/60Hz Mode l 72.2 73.6 75.1 ms
External Oscillator (Note 10) 20556/fEOSC (in kHz) ms

2C TIMING CHARACTERISTICS
I The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3, 15)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCL SCL Clock Frequency l 0 400 kHz
tHD(SDA) Hold Time (Repeated) START Condition l 0.6 µs
tLOW LOW Period of the SCL Pin l 1.3 µs
tHIGH HIGH Period of the SCL Pin l 0.6 µs
tSU(STA) Set-Up Time for a Repeated START Condition l 0.6 µs
tHD(DAT) Data Hold Time l 0 0.9 µs
tSU(DAT) Data Set-Up Time l 100 ns
tr Rise Time for SDA Signals (Note 14) l 20 + 0.1CB 300 ns
tf Fall Time for SDA Signals (Note 14) l 20 + 0.1CB 300 ns
tSU(STO) Set-Up Time for STOP Condition l 0.6 µs
tBUF Bus Free Time Between a Second START Condition l 1.3 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external
may cause permanent damage to the device. Exposure to any Absolute oscillator).
Maximum Rating condition for extended periods may affect device Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external
reliability and lifetime. oscillator).
Note 2: All voltage values are with respect to GND. Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
Note 3: Unless otherwise specified: VCC = 2.7V to 5.5V 280kHz ±2% (external oscillator).
VREFCM = VREF/2, FS = 0.5VREF Note 10: The external oscillator is connected to the fO pin. The external
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2, oscillator frequency, fEOSC, is expressed in kHz.
where IN+ and IN– are the selected input channels. Note 11: The converter uses its internal oscillator.
Note 4: Use internal conversion clock or external conversion clock source Note 12: The output noise includes the contribution of the internal
with fEOSC = 307.2kHz unless otherwise specified. calibration operations.
Note 5: Guaranteed by design, not subject to test. Note 13: Guaranteed by design and test correlation.
Note 6: Integral nonlinearity is defined as the deviation of a code from a Note 14: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).
straight line passing through the actual endpoints of the transfer curve. Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.
The deviation is measured from the center of the quantization band. Note 16: Refer to Applications Information section for Performance vs
Data Rate graphs.

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LTC2499
Typical Performance Characteristics
Integral Nonlinearity Integral Nonlinearity Integral Nonlinearity
(VCC = 5V, VREF = 5V) (VCC = 5V, VREF = 2.5V) (VCC = 2.7V, VREF = 2.5V)
3 3 3
VCC = 5V VCC = 5V VCC = 2.7V
VREF = 5V VREF = 2.5V VREF = 2.5V
2 VIN(CM) = 2.5V 2 VIN(CM) = 1.25V 2 VIN(CM) = 1.25V
fO = GND fO = GND fO = GND

INL (ppm of VREF)

1 –45°C 1

INL (ppm of VREF)

INL (ppm of VREF)

25°C –45°C, 25°C, 85°C –45°C, 25°C, 85°C

0 0 0
85°C
–1 –1 –1

–2 –2 –2

–3 –3 –3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –1.25 –0.75 –0.25 0.25 0.75 1.25 –1.25 –0.75 –0.25 0.25 0.75 1.25
INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
2499 G03
2499 G01 2499 G02

Total Unadjusted Error Total Unadjusted Error Total Unadjusted Error

(VCC = 5V, VREF = 5V) (VCC = 5V, VREF = 2.5V) (VCC = 2.7V, VREF = 2.5V)
12 12 12
VCC = 5V VCC = 5V VCC = 2.7V
VREF = 5V VREF = 2.5V 85°C VREF = 2.5V
8 VIN(CM) = 2.5V 8 VIN(CM) = 1.25V 8 VIN(CM) = 1.25V
fO = GND 85°C fO = GND fO = GND 85°C
25°C 25°C
25°C
TUE (ppm of VREF)

TUE (ppm of VREF)

TUE (ppm of VREF)

4 4 4

–45°C –45°C
0 –45°C 0 0

–4 –4 –4

–8 –8 –8

–12 –12 –12

–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –1.25 –0.75 –0.25 0.25 0.75 1.25 –1.25 –0.75 –0.25 0.25 0.75 1.25
INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
2499 G04 2499 G05 2499 G06

Noise Histogram (6.8sps) Noise Histogram (7.5sps)

14 14
10,000 CONSECUTIVE 10,000 CONSECUTIVE
READINGS READINGS RMS = 0.59µV
12 RMS = 0.60µV 12
VCC = 5V VCC = 2.7V AVERAGE = –0.19µV
VREF = 5V AVERAGE = –0.69µV VREF = 2.5V
NUMBER OF READINGS (%)

NUMBER OF READINGS (%)

10 VIN = 0V 10 VIN = 0V
TA = 25°C TA = 25°C
8 8

6 6

4 4

2 2

0 0
–3 –2.4 –1.8 –1.2 –0.6 0 0.6 1.2 1.8 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 1.2 1.8
OUTPUT READING (µV) OUTPUT READING (µV)
2499 G07 2499 G08

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 LTC2499
Typical Performance Characteristics
RMS Noise
Long-Term ADC Readings vs Input Differential Voltage RMS Noise vs VIN(CM)
5 1.0 1.0
VCC = 5V TA = 25°C VCC = 5V VCC = 5V
4 VREF = 5V RMS NOISE = 0.60µV VREF = 5V VREF = 5V
VIN = 0V 0.9 VIN(CM) = 2.5V 0.9 VIN = 0V
3 VIN(CM) = 2.5V TA = 25°C
TA = 25°C
2 fO = GND fO = GND
ADC READING (µV)

0.8 0.8

RMS NOISE (µV)

RMS NOISE (µV)
1
0 0.7 0.7
–1
0.6 0.6
–2
–3
0.5 0.5
–4
–5 0.4 0.4
0 10 20 30 40 50 60 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –1 0 1 2 3 4 5 6
TIME (HOURS) INPUT DIFFERENTIAL VOLTAGE (V) VIN(CM) (V)
2499 G09 2499 G10 2499 G11

RMS Noise vs Temperature (TA) RMS Noise vs VCC RMS Noise vs VREF
1.0 1.0 1.0
VCC = 5V VREF = 2.5V VCC = 5V
VREF = 5V VIN = 0V VIN = 0V
0.9 VIN = 0V 0.9 VIN(CM) = GND 0.9 VIN(CM) = GND
VIN(CM) = GND TA = 25°C TA = 25°C
fO = GND fO = GND fO = GND
0.8 0.8 0.8
RMS NOISE (µV)

RMS NOISE (µV)

RMS NOISE (µV)

0.7 0.7 0.7

0.6 0.6 0.6

0.5 0.5 0.5

0.4 0.4 0.4

–45 –30 –15 0 15 30 45 60 75 90 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0 1 2 3 4 5
TEMPERATURE (°C) VCC (V) VREF (V)
2499 G12 2499 G13 2499 G14

Offset Error vs VIN(CM) Offset Error vs Temperature

0.3 0.3
VCC = 5V VCC = 5V
VREF = 5V VREF = 5V
0.2 VIN = 0V 0.2 VIN = 0V
OFFSET ERROR (ppm of VREF)

OFFSET ERROR (ppm of VREF)

TA = 25°C VIN(CM) = GND

fO = GND fO = GND
0.1 0.1

0 0

–0.1 –0.1

–0.2 –0.2

–0.3 –0.3
–1 0 1 2 3 4 5 6 –45 –30 –15 0 15 30 45 60 75 90
VIN(CM) (V) TEMPERATURE (°C)
2499 G15 2499 G16

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LTC2499
Typical Performance Characteristics
On-Chip Oscillator Frequency
Offset Error vs VCC Offset Error vs VREF vs Temperature
0.3 0.3 310
REF+ = 2.5V VCC = 5V
REF– = GND REF– = GND
0.2 VIN = 0V 0.2 VIN = 0V
308
OFFSET ERROR (ppm of VREF)

OFFSET ERROR (ppm of VREF)

VIN(CM) = GND VIN(CM) = GND
TA = 25°C TA = 25°C
0.1 0.1

FREQUENCY (kHz)
fO = GND fO = GND
306
0 0
304
–0.1 –0.1
VCC = 4.1V
VREF = 2.5V
302 VIN = 0V
–0.2 –0.2
VIN(CM) = GND
fO = GND
–0.3 –0.3 300
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0 1 2 3 4 5 –45 –30 –15 0 15 30 45 60 75 90
VCC (V) VREF (V) TEMPERATURE (°C)
2499 G17 2499 G18 2499 G19

On-Chip Oscillator Frequency

vs VCC PSRR vs Frequency at VCC PSRR vs Frequency at VCC
310 0 0
VREF = 2.5V VCC = 4.1V DC VCC = 4.1V DC ±1.4V
VIN = 0V VREF = 2.5V VREF = 2.5V
–20 –20
VIN(CM) = GND IN+ = GND IN+ = GND
308 fO = GND IN– = GND IN– = GND
TA = 25°C –40 fO = GND –40 fO = GND
FREQUENCY (kHz)

TA = 25°C TA = 25°C
REJECTION (dB)

306 REJECTION (dB)

–60 –60

–80 –80
304
–100 –100
302
–120 –120

300 –140 –140

2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100 1k 10k 100k 1M 0 20 40 60 80 100 120 140 160 180 200 220
VCC (V) FREQUENCY AT VCC (Hz) FREQUENCY AT VCC (Hz)
2499 G20 2499 G21 2499 G22

Conversion Current
PSRR vs Frequency at VCC vs Temperature
0 200
VCC = 4.1V DC ±0.7V fO = GND
V = 2.5V
–20 INREF
+ = GND
IN – = GND 180
CONVERSION CURRENT (µA)

–40 fO = GND VCC = 5V

TA = 25°C
REJECTION (dB)

–60 160

–80 VCC = 2.7V

140
–100
120
–120

–140 100
30600 30650 3070030750 30800 –45 –30 –15 0 15 30 45 60 75 90
FREQUENCY AT VCC (Hz) TEMPERATURE (°C)
2499 G23 2499 G24

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Typical Performance Characteristics
Sleep Mode Current Conversion Current Integral Nonlinearity (2x Speed
vs Temperature vs Output Data Rate Mode; VCC = 5V, VREF = 5V)
2.0 500 3
fO = GND VREF = VCC VCC = 5V
1.8 +
450 IN– = GND VREF = 5V
IN = GND 2 VIN(CM) = 2.5V
1.6
SLEEP MODE CURRENT (µA)

400 fO = EXT OSC fO = GND

SUPPLY CURRENT (µA)

1.4 TA = 25°C
1
1.2 350
VCC = 5V

INL (µV)
25°C, 90°C
1.0 300 0
0.8 250
VCC = 5V –1
0.6 VCC = 2.7V
200 –45°C
0.4
–2
0.2 150
VCC = 3V
0 100 –3
–45 –30 –15 0 15 30 45 60 75 90 0 10 20 30 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
TEMPERATURE (°C) OUTPUT DATA RATE (READINGS/SEC) INPUT VOLTAGE (V)
2499 G25 2499 G26 2499 G27

Integral Nonlinearity (2x Speed Integral Nonlinearity (2x Speed Noise Histogram
Mode; VCC = 5V, VREF = 2.5V) Mode; VCC = 2.7V, VREF = 2.5V) (2x Speed Mode)
3 3 16
VCC = 5V VCC = 2.7V 10,000 CONSECUTIVE RMS = 0.85µV
VREF = 2.5V VREF = 2.5V AVERAGE = 0.184mV
14 READINGS
2 VIN(CM) = 1.25V 2 VIN(CM) = 1.25V VCC = 5V
fO = GND fO = GND 12 VREF = 5V

NUMBER OF READINGS (%)

VIN = 0V
INL (ppm OF VREF)

INL (ppm OF VREF)

1 1 T = 25°C
85°C 85°C 10 A

0 0 8

–45°C, 25°C 6
–1 –45°C, 25°C –1
4
–2 –2
2

–3 –3 0
–1.25 –0.75 –0.25 0.25 0.75 1.25 –1.25 –0.75 –0.25 0.25 0.75 1.25 179 181.4 183.8 186.2 188.6
INPUT VOLTAGE (V) INPUT VOLTAGE (V) OUTPUT READING (µV)
2499 G28 2499 G29 2499 G30

RMS Noise vs VREF Offset Error vs VIN(CM)

(2x Speed Mode) (2x Speed Mode)
1.0 200
VCC = 5V
198 VREF = 5V
VIN = 0V
0.8 196
fO = GND
194 TA = 25°C
OFFSET ERROR (µV)
RMS NOISE (µV)

0.6 192
190

0.4 188

VCC = 5V 186
VIN = 0V
0.2 184
VIN(CM) = GND
fO = GND 182
TA = 25°C
0 180
0 1 2 3 4 5 –1 0 1 2 3 4 5 6
VREF (V) VIN(CM) (V)
2499 G31 2499 G32

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LTC2499
Typical Performance Characteristics
Offset Error vs Temperature Offset Error vs VCC Offset Error vs VREF
(2x Speed Mode) (2x Speed Mode) (2x Speed Mode)
240 250 240
VCC = 5V VREF = 2.5V VCC = 5V
230 VREF = 5V VIN = 0V 230 VIN = 0V
VIN = 0V VIN(CM) = GND VIN(CM) = GND
200
220 VIN(CM) = GND fO = GND 220 fO = GND
fO = GND TA = 25°C TA = 25°C
OFFSET ERROR (µV)

OFFSET ERROR (µV)

OFFSET ERROR (µV)
210 210
150

200 200
100 190
190

180 180
50
170 170

160 0 160
–45 –30 –15 0 15 30 45 60 75 90 2 2.5 3 3.5 4 4.5 5 5.5 0 1 2 3 4 5
TEMPERATURE (°C) VCC (V) VREF (V)
2499 G33 2499 G34 2499 G35

PSRR vs Frequency at VCC PSRR vs Frequency at VCC PSRR vs Frequency at VCC

(2x Speed Mode) (2x Speed Mode) (2x Speed Mode)
0 0 0
VCC = 4.1V DC VCC = 4.1V DC ±1.4V VCC = 4.1V DC ±0.7V
REF+ = 2.5V REF+ = 2.5V REF+ = 2.5V
–20 –20 –20
REF– = GND REF– = GND REF– = GND
IN+ = GND IN+ = GND IN+ = GND
–40 IN– = GND –40 IN– = GND –40 IN– = GND
RREJECTION (dB)

fO = GND fO = GND fO = GND

REJECTION (dB)
REJECTION (dB)

–60 TA = 25°C –60 TA = 25°C –60 TA = 25°C

–80 –80 –80

–100 –100 –100

–120 –120 –120

–140 –140 –140

1 10 100 1k 10k 100k 1M 0 20 40 60 80 100 120 140 160 180 200 220 30600 30650 30700 30750 30800
FREQUENCY AT VCC (Hz) FREQUENCY AT VCC (Hz) FREQUENCY AT VCC (Hz)
2499 G36 2499 G37 2499 G38

pin functions
GND (Pins 1, 4, 6, 31, 32, 33, 34): Ground. Multiple SDA (Pin 3): Bidirectional Serial Data Line of the I2C Inter-
ground pins internally connected for optimum ground cur- face. In the transmitter mode (read), the conversion result
rent flow and VCC decoupling. Connect each one of these is output through the SDA pin, while in the receiver mode
pins to a common ground plane through a low impedance (write), the device channel select and configuration bits
connection. All seven pins must be connected to ground are input through the SDA pin. The pin is high impedance
for proper operation. during the data input mode and is an open drain output
SCL (Pin 2): Serial Clock Pin of the I2C Interface. The (requires an appropriate pull-up device to VCC) during the
data output mode.
LTC2499 can only act as a slave and the SCL pin only
accepts an external serial clock. Data is shifted into the NC (Pin 5): No Connect. This pin can be left floating or
SDA pin on the rising edges of the SCL clock and output tied to GND.
through the SDA pin on the falling edges of the SCL clock.
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 LTC2499
pin functions
COM (Pin 7): The Common Negative Input (IN –) for All REF+, REF – (Pin 29, Pin 30): Differential Reference Input.
Single-Ended Multiplexer Configurations. The voltage on The voltage on these pins can have any value between
CH0-CH15 and COM pins can have any value between GND and VCC as long as the reference positive input, REF+,
GND – 0.3V to VCC + 0.3V. Within these limits, the two remains more positive than the negative reference input,
selected inputs (IN+ and IN– ) provide a bipolar input range REF–, by at least 0.1V. The differential voltage (VREF = REF+
(VIN = IN+ – IN– ) from –0.5 • VREF to 0.5 • VREF . Outside – REF –) sets the full-scale range for all input channels.
this input range, the converter produces unique overrange When performing an on-chip measurement, the minimum
and underrange output codes. value of REF = 2V.
CH0 to CH15 (Pin 8-Pin 23): Analog Inputs. May be pro- fO (Pin 35): Frequency Control Pin. Digital input that
grammed for single-ended or differential mode. controls the internal conversion clock rate. When fO is
MUXOUTP (Pin 24): Positive Multiplexer Output. Connect connected to GND, the converter uses its internal oscil-
to the input of external buffer/amplifier or short directly lator running at 307.2kHz. The conversion clock may also
to ADCINP. be overridden by driving the fO pin with an external clock
in order to change the output rate and the digital filter
ADCINP (Pin 25): Positive ADC Input. Connect to the rejection null.
output of a buffer/amplifier driven by MUXOUTP or short
directly to MUXOUTP. CA0, CA1, CA2 (Pins 36, 37, 38): Chip Address Control
Pins. These pins are configured as a three-state (LOW,
ADCINN (Pin 26): Negative ADC Input. Connect to the
HIGH, floating) address control bits for the device I2C
output of a buffer/amplifier driven by MUXOUTN or short
address.
directly to MUXOUTN
Exposed Pad (Pin 39): Ground. This pin is ground and
MUXOUTN (Pin 27): Negative Multiplexer Output. Con-
nect to the input of an external buffer/amplifier or short must be soldered to the PCB ground plane. For prototyping
directly to ADCINN. purposes, this pin may remain floating.

VCC (Pin 28): Positive Supply Voltage. Bypass to GND with

a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.

functional block diagram

TEMP INTERNAL
SENSOR OSCILLATOR
VCC

GND MUXOUTP ADCINP AUTOCALIBRATION fO

AND CONTROL (INT/EXT)
REF+
REF–

CH0 – +
CH1
• DIFFERENTIAL
• MUX 3RD ORDER I2C SDA
• ∆Σ MODULATOR 2-WIRE
CH15 INTERFACE SCL
COM
DECIMATING FIR
ADDRESS
2499 BD

MUXOUTN ADCINN

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LTC2499
Applications Information
CONVERTER OPERATION POWER-ON RESET
DEFAULT CONFIGURATION:
IN+ = CH0, IN– = CH1
Converter Operation Cycle 50Hz/60Hz REJECTION
1x OUTPUT
The LTC2499 is a multichannel, low power, delta-sigma
analog-to-digital converter with a 2-wire, I2C interface. Its
operation is made up of four states (see Figure 1). The CONVERSION

converter operating cycle begins with the conversion,

followed by the sleep state and ends with the data input/ SLEEP
output cycle .
Initially, at power-up, the LTC2499 performs a conversion.
Once the conversion is complete, the device enters the NO
ACKNOWLEDGE
sleep state. While in the sleep state, power consumption
is reduced by two orders of magnitude. The part remains
YES
in the sleep state as long it is not addressed for a read/
write operation. The conversion result is held indefinitely DATA OUTPUT/INPUT
in a static shift register while the part is in the sleep state.
The device will not acknowledge an external request dur-
ing the conversion state. After a conversion is finished, NO STOP
OR READ
the device is ready to accept a read/write request. Once 32 BITS
the LTC2499 is addressed for a read operation, the device
YES
begins outputting the conversion result under the control 2499 F01

of the serial clock (SCL). There is no latency in the conver-

sion result. The data output is 32 bits long and contains a Figure 1. State Transition Table
24-bit plus sign conversion result. Data is updated on the
falling edges of SCL allowing the user to reliably latch data
The advantage of continuous calibration is extreme stability
on the rising edge of SCL. A new conversion is initiated by
of offset and full-scale readings with respect to time, sup-
a STOP condition following a valid write operation or an
ply voltage variation, input channel and temperature drift.
incomplete read operation. The conversion automatically
begins at the conclusion of a complete read cycle (all 32 Easy Drive Input Current Cancellation
bits read out of the device).
The LTC2499 combines a high precision, delta-sigma ADC
Ease of Use with an automatic, differential, input current cancellation
front end. A proprietary front-end passive sampling network
The LTC2499 data output has no latency, filter settling
transparently removes the differential input current. This
delay, or redundant data associated with the conversion
enables external RC networks and high impedance sen-
cycle. There is a one-to-one correspondence between the
sors to directly interface to the LTC2499 without external
conversion and the output data. Therefore, multiplexing
amplifiers. The remaining common mode input current
multiple analog inputs is straightforward. Each conversion,
is eliminated by either balancing the differential input im-
immediately following a newly selected input or mode, is
pedances or setting the common mode input equal to the
valid and accurate to the full specifications of the device.
common mode reference (see the Automatic Differential
The LTC2499 automatically performs offset and full-scale Input Current Cancellation section). This unique architec-
calibration every conversion cycle independent of the input ture does not require on-chip buffers, thereby enabling
channel selected. This calibration is transparent to the user signals to swing beyond ground and VCC. Moreover, the
and has no effect on the operation cycle described above. cancellation does not interfere with the transparent offset
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 LTC2499
Applications Information
and full-scale auto-calibration and the absolute accuracy Input Voltage Range
(full scale + offset + linearity + drift) is maintained even The LTC2499 input measurement range is –0.5 • VREF
with external RC networks. to +0.5 • VREF in both differential and single-ended
configurations as shown in Figure 38. Highest linearity
Power-Up Sequence
is achieved with fully differential drive and a constant
The LTC2499 automatically enters an internal reset state common-mode voltage (Figure 38b). Other drive schemes
when the power supply voltage VCC drops below approxi- may incur an INL error of approximately 50ppm. This error
mately 2.0V. This feature guarantees the integrity of the can be calibrated out using a three point calibration and a
conversion result and input channel selection. second-order curve fit.
When VCC rises above this threshold, the converter creates The analog inputs are truly differential with an absolute,
an internal power-on reset (POR) signal with a duration common mode range for the CH0-CH15 and COM input
of approximately 4ms. The POR signal clears all internal pins extending from GND – 0.3V to VCC + 0.3V. Outside
registers. The conversion immediately following a POR these limits, the ESD protection devices begin to turn on
cycle is performed on the input channel IN+ = CH0, IN – = and the errors due to input leakage current increase rap-
CH1 with simultaneous 50Hz/60Hz rejection and 1x output idly. Within these limits, the LTC2499 converts the bipolar
rate. The first conversion following a POR cycle is accurate differential input signal VIN = IN+ – IN– (where IN+ and IN –
within the specification of the device if the power supply are the selected input channels), from – FS = – 0.5 • VREF
voltage is restored to (2.7V to 5.5V) before the end of the to + FS = 0.5 • VREF where VREF = REF+ - REF–. Outside this
POR interval. A new input channel, rejection mode, speed range, the converter indicates the overrange or the under-
mode, or temperature selection can be programmed into range condition using distinct output codes (see Table 1).
the device during this first data input/output cycle.
Signals applied to the input (CH0-CH15, COM) may extend
Reference Voltage Range 300mV below ground and above VCC. In order to limit
any fault current, resistors of up to 5k may be added in
This converter accepts a truly differential external reference series with the input. The effect of series resistance on
voltage. The absolute/common mode voltage range for the converter accuracy can be evaluated from the curves
REF+ and REF – pins covers the entire operating range of presented in the Input Current/Reference Current sections.
the device (GND to VCC). For correct converter operation, In addition, series resistors will introduce a temperature
VREF must be positive (REF+ > REF –). dependent error due to input leakage current. A 1nA
The LTC2499 differential reference input range is 0.1V to input leakage current will develop a 1ppm offset error
VCC. For the simplest operation, REF+ can be shorted to VCC on a 5k resistor if VREF = 5V. This error has a very strong
and REF – can be shorted to GND. The converter output noise temperature dependency.
is determined by the thermal noise of the front-end circuits
and, as such, its value in nanovolts is nearly constant with MUXOUT/ADCIN
reference voltage. A decrease in reference voltage will not The outputs of the multiplexer (MUXOUTP/MUXOUTN) and
significantly improve the converter’s effective resolution. the inputs to the ADC (ADCINP/ADCINN) can be used to
On the other hand, a decreased reference will improve the perform input signal conditioning on any of the selected
converter’s overall INL performance. input channels or simply shorted together for direct
digitization. If an external amplifier is used, the LTC2499

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LTC2499
Applications Information
automatically calibrates both the offset and drift of this The LTC2499 can only be addressed as a slave. Once
circuit and the Easy Drive sampling scheme enables a addressed, it can receive configuration bits (channel
wide variety of amplifiers to be used. selection, rejection mode, speed mode) or transmit the
In order to achieve optimum performance, if an external last conversion result. The serial clock line, SCL, is always
amplifier is not used, short these pins directly together an input to the LTC2499 and the serial data line SDA is
(ADCINP to MUXOUTP and ADCINN to MUXOUTN) and bidirectional. The device supports the standard mode and
minimize their capacitance to ground. the fast mode for data transfer speeds up to 400kbits/s.
Figure 2 shows the definition of the I2C timing.
I2C INTERFACE
The START and STOP Conditions
The LTC2499 communicates through an I2C interface. The
I2C interface is a 2-wire open-drain interface supporting A START (S) condition is generated by transitioning SDA
multiple devices and multiple masters on a single bus. The from HIGH to LOW while SCL is HIGH. The bus is consid-
connected devices can only pull the data line (SDA) LOW ered to be busy after the START condition. When the data
and can never drive it HIGH. SDA is required to be exter- transfer is finished, a STOP (P) condition is generated by
nally connected to the supply through a pull-up resistor. transitioning SDA from LOW to HIGH while SCL is HIGH.
When the data line is not being driven, it is HIGH. Data on The bus is free after a STOP is generated. START and STOP
the I2C bus can be transferred at rates up to 100kbits/s in conditions are always generated by the master.
the standard mode and up to 400kbits/s in the fast mode. When the bus is in use, it stays busy if a repeated START
The VCC power should not be removed from the device (Sr) is generated instead of a STOP condition. The repeated
when the I2C bus is active to avoid loading the I2C bus START timing is functionally identical to the START and is
lines through the internal ESD protection diodes. used for writing and reading from the device before the
Each device on the I2C bus is recognized by a unique initiation of a new conversion.
address stored in that device and can operate either as a
Data Transferring
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices After the START condition, the I2C bus is busy and data
can also be considered as masters or slaves when perform- transfer can begin between the master and the addressed
ing data transfers. A master is the device which initiates a slave. Data is transferred over the bus in groups of nine
data transfer on the bus and generates the clock signals bits, one byte followed by one acknowledge (ACK) bit. The
to permit that transfer. Devices addressed by the master master releases the SDA line during the ninth SCL clock
are considered a slave. cycle. The slave device can issue an ACK by pulling SDA

SDA

tSU(DAT)
tf tLOW tr tf tHD(SDA) tSP tr tBUF

SCL

tHD(SDA) tSU(STA) tSU(STO)

S tHD(DAT) tHIGH Sr P S

2499 F02

Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
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 LTC2499
Applications Information
LOW or issue a Not Acknowledge (NACK) by leaving the cally enters the sleep state where the supply current is
SDA line high impedance (the external pull-up resistor will reduced to 1µA. When the LTC2499 is addressed for a read
hold the line HIGH). Change of data only occurs while the operation, it acknowledges (by pulling SDA LOW) and acts
clock line (SCL) is LOW. as a transmitter. The master/receiver can read up to four
bytes from the LTC2499. After a complete read operation
DATA FORMAT (4 bytes), a new conversion is initiated. The device will
After a START condition, the master sends a 7-bit address NACK subsequent read operations while a conversion is
followed by a read/write (R/W) bit. The R/W bit is 1 for a being performed.
read request and 0 for a write request. If the 7-bit address The data output stream is 32 bits long and is shifted out
matches the hard wired LTC2499’s address (one of 27 on the falling edges of SCL (see Figure 3a). The first bit is
pin-selectable addresses) the device is selected. When the conversion result sign bit (SIG) (see Tables 1 and 2).
the device is addressed during the conversion state, it will This bit is HIGH if VIN ≥ 0 and LOW if VIN < 0 (where VIN
not acknowledge R/W requests and will issue a NACK by corresponds to the selected input signal IN+ – IN–). The
leaving the SDA line HIGH. If the conversion is complete, second bit is the most significant bit (MSB) of the result.
the LTC2499 issues an ACK by pulling the SDA line LOW. The first two bits (SIG and MSB) can be used to indicate
The LTC2499 has two registers. The output register (32 over and under range conditions (see Table 2). If both bits
bits long) contains the last conversion result. The input are HIGH, the differential input voltage is equal to or above
register (16 bits long) sets the input channel, selects the +FS. If both bits are set LOW, the input voltage is below –FS.
temperature sensor, rejection mode, and speed mode. The function of these bits is summarized in Table 2. The
24 bits following the MSB bit are the conversion result in
DATA OUTPUT FORMAT binary two’s, complement format. The remaining six bits
are sub LSBs below the 24-bit level.
The output register contains the last conversion result.
After each conversion is completed, the device automati-

Table 1. Output Data Format

DIFFERENTIAL INPUT VOLTAGE BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 … BIT 6 BITs 5-0
VIN* SIG MSB LSB Sub LSBs
VIN* ≥ FS** 1 1 0 0 0 … 0 00000
FS** – 1LSB 1 0 1 1 1 … 1 XXXXX
0.5 • FS** 1 0 1 0 0 … 0 XXXXX
0.5 • FS** – 1LSB 1 0 0 1 1 … 1 XXXXX
0 1/   0† 0 0 0 0 … 0 XXXXX
–1LSB 0 1 1 1 1 … 1 XXXXX
–0.5 • FS** 0 1 1 0 0 … 0 XXXXX
–0.5 • FS** – 1LSB 0 1 0 1 1 … 1 XXXXX
–FS** 0 1 0 0 0 … 0 XXXXX
VIN* < –FS** 0 0 1 1 1 … X XXXXX***
*The differential input voltage VIN = IN+ – IN–.
**The full-scale voltage FS = 0.5 • VREF . Sub LSBs are below the 24-bit level. They may be included in averaging, or discarded without loss of resolution.
†The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
***The underrange code is Ox3FFFFxxx in 2x mode.

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LTC2499
Applications Information
As long as the voltage on the selected input channels (IN+ INPUT DATA FORMAT
and IN–) remains between –0.3V and VCC + 0.3V (absolute The serial input word to the LTC2499 is 13 bits long and
maximum operating range) a conversion result is gener-
is written into the device input register in two 8-bit words.
ated for any differential input voltage VIN from –FS = –0.5
The first word (SGL, ODD, A2, A1, A0) is used to select
• VREF to +FS = 0.5 • VREF . For differential input voltages
the input channel. The second word of data (IM, FA, FB,
greater than +FS, the conversion result is clamped to the
SPD) is used to select the frequency rejection, speed mode
value corresponding to +FS. For differential input volt- (1x, 2x), and temperature measurement.
ages below –FS, the conversion result is clamped to the
value –FS – 1LSB. After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN+ = CH0, IN– =
Table 2. LTC2499 Status Bits CH1), the frequency rejection to simultaneous 50Hz/60Hz,
BIT 31 BIT 30 and 1x output rate (auto-calibration enabled). The first
INPUT RANGE SIG MSB
VIN ≥ FS 1 1
conversion automatically begins at power-up using this
default configuration. Once the conversion is complete,
0V ≤ VIN < FS 1/  0 0
up to two words may be written into the device.
–FS ≤ VIN < 0V 0 1
VIN < –FS 0 0 The first three bits of the first input word consist of two
preamble bits and one enable bit. Valid settings for these
three bits are 000, 100, and 101. Other combinations
should be avoided.

1 … 7 8 9 1 2 … 9 1 2 3 4 5 6 7 8 9

7-BIT
ADDRESS R SGN MSB DIS LSB

ACK BY ACK BY SUB LSBs NACK BY

START BY LTC2499 MASTER MASTER
MASTER
SLEEP DATA OUTPUT
2499 F03a

Figure 3a. Timing Diagram for Reading from the LTC2499

SCL 1 2 … 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

7-BIT ADDRESS W 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD

ACK BY ACK (OPTIONAL 2ND BYTE) ACK

START BY LTC2499 LTC2499 LTC2499
MASTER
SLEEP DATA INPUT
2499 F03b

Figure 3b. Timing Diagram for Writing to the LTC2499

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 LTC2499
Applications Information
If the first three bits are 000 or 100, the following data The first input bit (SGL) following the 101 sequence de-
is ignored (don’t care) and the previously selected input termines if the input selection is differential (SGL = 0) or
channel remains valid for the next conversion single-ended (SGL = 1). For SGL = 0, two adjacent chan-
nels can be selected to form a differential input. For SGL
If the first three bits shifted into the device are 101, then
= 1, one of 16 channels is selected as the positive input.
the next five bits select the input channel for the next
The negative input is COM for all single-ended operations.
conversion cycle (see Table 3).
Table 3. Channel Selection
MUX ADDRESS CHANNEL SELECTION
ODD/
SGL SIGN A2 A1 A0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COM
*0 0 0 0 0 IN+ IN–
0 0 0 0 1 IN+ IN–
0 0 0 1 0 IN+ IN–
0 0 0 1 1 IN+ IN–
0 0 1 0 0 IN+ IN–
0 0 1 0 1 IN+ IN–
0 0 1 1 0 IN+ IN–
0 0 1 1 1 IN+ IN–
0 1 0 0 0 IN– IN+
0 1 0 0 1 IN– IN+
0 1 0 1 0 IN– IN+
0 1 0 1 1 IN– IN+
0 1 1 0 0 IN– IN+
0 1 1 0 1 IN– IN+
0 1 1 1 0 IN– IN+
0 1 1 1 1 IN– IN+
1 0 0 0 0 IN+ IN–
1 0 0 0 1 IN+ IN–
1 0 0 1 0 IN+ IN–
1 0 0 1 1 IN+ IN–
1 0 1 0 0 IN+ IN–
1 0 1 0 1 IN+ IN–
1 0 1 1 0 IN+ IN–
1 0 1 1 1 IN+ IN–
1 1 0 0 0 IN+ IN–
1 1 0 0 1 IN+ IN–
1 1 0 1 0 IN+ IN–
1 1 0 1 1 IN+ IN–
1 1 1 0 0 IN+ IN–
1 1 1 0 1 IN+ IN–
1 1 1 1 0 IN+ IN–
1 1 1 1 1 IN+ IN–
*Default at power-up
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LTC2499
Applications Information
The remaining four bits (ODD, A2, A1, A0) determine 1x output rate if SPD = 0 (auto-calibration is enabled and
which channel(s) is/are selected and the polarity (for a the offset is continuously calibrated and removed from
differential input). the final conversion result) or the 2x output rate if SPD
Once the first word is written into the device, a second = 1 (offset calibration disabled, multiplexing output rates
word may be input in order to select a configuration mode. up to 15Hz with no latency). When IM = 1 (temperature
The first bit of the second word is the enable bit for the measurement) SPD will be ignored and the device will
conversion configuration (EN2). If this bit is set to 0, then operate in 1x mode.
the next conversion is performed using the previously The configuration remains valid until a new input word
selected converter configuration. with EN = 1 (the first three bits are 101 for the first word)
A new configuration can be loaded into the device by and EN2 = 1 (for the second write byte) is shifted into
setting EN2 = 1 (see Table 4). The first bit (IM) is used the device.
to select the internal temperature sensor. If IM = 1, the
following conversion will be performed on the internal Rejection Mode (FA, FB)
temperature sensor rather than the selected input channel. The LTC2499 includes a high accuracy on-chip oscillator
The next two bits (FA and FB) are used to set the rejection with no required external components. Coupled with an
frequency. The final bit (SPD) is used to select either the integrated fourth order digital lowpass filter, the LTC2499

Table 4. Converter Configuration

1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD CONVERTER CONFIGURATION
1 0 0 X X X X X X X X X X Keep Previous
1 0 1 X X X X X 0 X X X X Keep Previous
0 0 1 X X X X X X X X X X Keep Previous
1 0 1 X X X X X 1 0 0 0 0 External Input (See Table 3)
50Hz/60Hz Rejection, 1x
1 0 1 X X X X X 1 0 0 1 0 External Input (See Table 3)
50Hz Rejection, 1x
1 0 1 X X X X X 1 0 1 0 0 External Input (See Table 3)
60Hz Rejection, 1x
1 0 1 X X X X X 1 0 0 0 1 External Input (See Table 3)
50Hz/60Hz Rejection, 2x
1 0 1 X X X X X 1 0 0 1 1 External Input (See Table 3)
50Hz Rejection, 2x
1 0 1 X X X X X 1 0 1 0 1 External Input (See Table 3)
60Hz Rejection, 2x
1 0 1 X X X X X 1 1 0 0 X Measure Temperature
50Hz/60Hz Rejection, 1x
1 0 1 X X X X X 1 1 0 1 X Measure Temperature
50Hz Rejection, 1x
1 0 1 X X X X X 1 1 1 0 X Measure Temperature
60Hz Rejection, 1x
1 0 1 X X X X X 1 X 1 1 X Reserved, Do Not Use

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 LTC2499
Applications Information
rejects line frequency noise. In the default mode, the The digital output is proportional to the absolute tem-
LTC2499 simultaneously rejects 50Hz and 60Hz by at least perature of the device. This feature allows the converter
87dB. If more rejection is required, the LTC2499 can be to perform cold junction compensation for external
configured to reject 50Hz or 60Hz to better than 110dB. thermocouples or continuously remove the temperature
effects of external sensors.
Speed Mode (SPD)
The internal temperature sensor output is 28mV at 27°C
Every conversion cycle, two conversions are combined (300°K), with a slope of 93.5µV/°C independent of VREF
to remove the offset (default mode). This result is free (see Figures 4 and 5). Slope calibration is not required if
from offset and drift. In applications where the offset is the reference voltage (VREF) is known. A 5V reference has
not critical, the auto-calibration feature can be disabled a slope of 314 LSBs24/°C. The temperature is calculated
with the benefit of twice the output rate. from the output code (where DATAOUT24 is the decimal
While operating in the 2x mode (SPD = 1), the linearity representation of the 24-bit result) for a 5V reference using
and full-scale errors are unchanged from the 1x mode the following formula:
performance. In both the 1x and 2x mode there is no DATAOUT24
latency. This enables input steps or multiplexer changes TK = in Kelvin
314
to settle in a single conversion cycle, easing system over-
head and increasing the effective conversion rate. During If a different value of VREF is used, the temperature
temperature measurements, the 1x mode is always used output is:
independent of the value of SPD.
DATAOUT24 • VREF
TK = in Kelvin
Temperature Sensor 1570
The LTC2499 includes an integrated temperature sensor. If the value of VREF is not known, the slope is determined
The temperature sensor is selected by setting IM = 1. by measuring the temperature sensor at a known tempera-
During temperature readings, MUXOUTN/MUXOUTP ture TN (in K) and using the following formula:
remains connected to the selected input channel. The
ADC internally connects to the temperature sensor and DATAOUT24
SLOPE =
performs a conversion. TN

140000 5
VCC = 5V
VREF = 5V 4
120000 SLOPE = 314 LSB /K
24
3
ABSOLUTE ERROR (°C)

100000 2
DATAOUT24

1
80000
0
60000
–1

40000 –2
–3
20000
–4
0 –5
0 100 200 300 400 –55 –30 –5 20 45 70 95 120
TEMPERATURE (K) TEMPERATURE (°C) 2499 F05
2499 F04

Figure 4. Internal PTAT Digital Output vs Temperature Figure 5. Absolute Temperature Error

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LTC2499
Applications Information
This value of slope can be used to calculate further tem- Table 5. Address Assignment
perature readings using: CA2 CA1 CA0 ADDRESS
DATAOUT24 LOW LOW LOW 0010100
TK = LOW LOW HIGH 0010110
SLOPE
LOW LOW Float 0010101
All Kelvin temperature readings can be converted to TC LOW HIGH LOW 0100110
(°C) using the fundamental equation: LOW HIGH HIGH 0110100
TC = TK – 273 LOW HIGH Float 0100111
LOW Float LOW 0010111
Initiating a New Conversion LOW Float HIGH 0100101
When the LTC2499 finishes a conversion, it automatically LOW Float Float 0100100
enters the sleep state. Once in the sleep state, the device is HIGH LOW LOW 1010110
ready for a read operation. After the device acknowledges HIGH LOW HIGH 1100100
a read request, the device exits the sleep state and enters HIGH LOW Float 1010111
the data output state. The data output state concludes HIGH HIGH LOW 1110100
and the LTC2499 starts a new conversion once a STOP HIGH HIGH HIGH 1110110
condition is issued by the master or all 32 bits of data are HIGH HIGH Float 1110101
read out of the device. HIGH Float LOW 1100101
During the data read cycle, a STOP command may be issued HIGH Float HIGH 1100111
by the master controller in order to start a new conversion HIGH Float Float 1100110
and abort the data transfer. This STOP command must be Float LOW LOW 0110101
issued during the ninth clock cycle of a byte read when Float LOW HIGH 0110111
the bus is free (the ACK/NACK cycle). Float LOW Float 0110110
Float HIGH LOW 1000111
LTC2499 Address
Float HIGH HIGH 1010101
The LTC2499 has three address pins (CA0, CA1, CA2). Float HIGH Float 1010100
Each may be tied HIGH, LOW, or left floating enabling one Float Float LOW 1000100
of 27 possible addresses (see Table 5).
Float Float HIGH 1000110
In addition to the configurable addresses listed in Table 5, Float Float Float 1000101
the LTC2499 also contains a global address (1110111)
which may be used for synchronizing multiple LTC2499s or Continuous Read
other LTC24XX delta-sigma I2C devices (see Synchronizing
Multiple LTC2499s with a Global Address Call section). In applications where the input channel/configuration does
not need to change for each cycle, the conversion can be
Operation Sequence continuously performed and read without a write cycle
(see Figure 7). The configuration/input channel remains
The LTC2499 acts as a transmitter or receiver, as shown unchanged from the last value written into the device. If
in Figure 6. The device may be programmed to perform the device has not been written to since power-up, the
several functions. These include input channel selection, configuration is set to the default value. At the end of a
measure the internal temperature, selecting the line fre- read operation, a new conversion automatically begins.
quency rejection (50Hz, 60Hz, or simultaneous 50Hz and At the conclusion of the conversion cycle, the next result
60Hz), and a 2x speed mode. may be read using the method described above. If the
conversion cycle is not concluded and a valid address
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 LTC2499
Applications Information

S 7-BIT ADDRESS R/W ACK DATA Sr DATA TRANSFERRING P

CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION

2499 F05

Figure 6. Conversion Sequence

S 7-BIT ADDRESS R ACK READ P S 7-BIT ADDRESS R ACK READ P

CONVERSION
CONVERSION SLEEP DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
2499 F07

Figure 7. Consecutive Reading with the Same Input/Configuration

S 7-BIT ADDRESS W ACK WRITE Sr 7-BIT ADDRESS R ACK READ P

CONVERSION SLEEP DATA INPUT ADDRESS DATA OUTPUT CONVERSION

2499 F08

Figure 8. Write, Read, START Conversion

S 7-BIT ADDRESS W ACK WRITE (OPTIONAL) P

CONVERSION SLEEP DATA INPUT CONVERSION

2499 F09

Figure 9. Start a New Conversion Without Reading Old Conversion Result

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LTC2499
Applications Information
selects the device, the LTC2499 generates a NACK signal channel or conversion configuration is required, this data
indicating the conversion cycle is in progress. can be written into the device and a STOP command will
initiate the next conversion (see Figure 9).
Continuous Read/Write
Synchronizing Multiple LTC2499s with a Global
Once the conversion cycle is concluded, the LTC2499
Address Call
can be written to and then read from using the repeated
START (Sr) command. In applications where several LTC2499s (or other I2C
delta-sigma ADCs from Linear Technology Corporation)
Figure 8 shows a cycle which begins with a data write, a
are used on the same I2C bus, all converters can be syn-
repeated START, followed by a read and concluded with a
chronized through the use of a global address call. Prior
STOP command. The following conversion begins after
to issuing the global address call, all converters must have
all 32 bits are read out of the device or after a STOP com-
completed a conversion cycle. The master then issues a
mand. The following conversion will be performed using the START, followed by the global address 1110111, and a write
newly programmed data. In cases where the same speed request. All converters will be selected and acknowledge
(1x/2x mode) and rejection frequency (50Hz, 60Hz, 50Hz the request. The master then sends a write byte (optional)
and 60Hz) is used but the channel is changed, a STOP or followed by the STOP command. This will update the chan-
repeated START may be issued after the first byte (channel nel selection (optional) converter configuration (optional)
selection data) is written into the device. and simultaneously initiate a START of conversion for all
delta-sigma ADCs on the bus (see Figure 10). In order
Discarding a Conversion Result and Initiating a New
to synchronize multiple converters without changing the
Conversion with Optional Write
channel or configuration, a STOP may be issued after
At the conclusion of a conversion cycle, a write cycle acknowledgement of the global write command. Global
can be initiated. Once the write cycle is acknowledged, a read commands are not allowed and the converters will
STOP command will start a new conversion. If a new input NACK a global read request.

SCL

SDA

LTC2499 LTC2499 … LTC2499

S GLOBAL ADDRESS W ACK WRITE (OPTIONAL) P

ALL LTC2499s IN SLEEP CONVERSION OF ALL LTC2499s

DATA INPUT 2499 F10

Figure 10. Synchronize Multiple LTC2499s with a Global Address Call

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 LTC2499
Applications Information
Driving the Input and Reference cancellation (Easy Drive) and the second is the insertion
The input and reference pins of the LTC2499 are connected of an external buffer between the MUXOUT and ADCIN
directly to a switched capacitor network. Depending on pins, thus isolating the input switching from the source
the relationship between the differential input voltage and resistance.
the differential reference voltage, these capacitors are
Automatic Differential Input Current Cancellation
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount In applications where the sensor output impedance is
of charge is transferred. A simplified equivalent circuit is low (up to 10kΩ with no external bypass capacitor or up
shown in Figure 11. to 500Ω with 0.001µF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
When using the LTC2499’s internal oscillator, the input
direct digitization is possible.
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the input/ For many applications, the sensor output impedance
reference pins. If the total external RC time constant is less combined with external input bypass capacitors produces
than 580ns the errors introduced by the sampling process RC time constants much greater than the 580ns required
are negligible since complete settling occurs. for 1ppm accuracy. For example, a 10kΩ bridge driving a
0.1µF capacitor has a time constant an order of magnitude
Typically, the reference inputs are driven from a low
greater than the required maximum.
impedance source. In this case, complete settling occurs
even with large external bypass capacitors. The inputs The LTC2499 uses a proprietary switching algorithm
(CH0-CH15, COM), on the other hand, are typically driven that forces the average differential input current to zero
from larger source resistances. Source resistances up independent of external settling errors. This allows direct
to 10k may interface directly to the LTC2499 and settle digitization of high impedance sensors without the need
completely; however, the addition of external capacitors for buffers.
at the input terminals in order to filter unwanted noise The switching algorithm forces the average input current
(anti-aliasing) results in incomplete settling. on the positive input (IIN+) to be equal to the average input
The LTC2499 offers two methods of removing these current on the negative input (IIN–). Over the complete
errors. The first is an automatic differential input current conversion cycle, the average differential input current

INPUT INTERNAL
MULTIPLEXER EXTERNAL SWITCH
IIN+ CONNECTION NETWORK
100Ω 10kΩ VIN(CM) − VREF(CM)
( )
I IN+ = I IN–
( )
IN+
=
MUXOUTP ADCINP AVG AVG 0.5•REQ

(
1.5VREF + VREF(CM) – VIN(CM) )– VIN2
IIN–
(
I REF + ) AVG
≈
0.5 • REQ VREF • REQ
where:
100Ω 10kΩ
IN– MUXOUTN ADCINN VREF = REF + − REF −
⎛ REF + – REF − ⎞
VREF(CM) = ⎜ ⎟
EXTERNAL ⎜⎝ 2 ⎟⎠
IREF+ CONNECTION CEQ
12µF VIN = IN+ − IN− , WHERE IN+ AND IN− ARE THE SELECTED INPUT CHANNELS
10kΩ
⎛ IN+ – IN− ⎞
REF+ VIN(CM) = ⎜ ⎟
⎜⎝ 2 ⎟⎠
REQ = 2.71MΩ INTERNAL OSCILLATOR 60Hz MODE
IREF– REQ = 2.98MΩ INTERNAL OSCILLATOR 50Hz/60Hz MODE
10kΩ REQ = 0.833• 1012 /fEOSC EXTERNAL OSCILLATOR
( )
REF– 2499 F11

SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR
Figure 11. Equivalent Analog Input Circuit
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LTC2499
Applications Information
(IIN+ – IIN–) is zero. While the differential input current is In applications where the common mode input voltage
zero, the common mode input current (IIN+ + IIN–)/2 is varies as a function of the input signal level (single-ended
proportional to the difference between the common mode type sensors), the common mode input current varies
input voltage (VIN(CM)) and the common mode reference proportionally with input voltage. For the case of balanced
voltage (VREF(CM)). input impedances, the common mode input current effects
In applications where the input common mode voltage is are rejected by the large CMRR of the LTC2499, leading
equal to the reference common mode voltage, as in the to little degradation in accuracy. Mismatches in source
case of a balanced bridge, both the differential and com- impedances lead to gain errors proportional to the dif-
mon mode input current are zero. The accuracy of the ference between the common mode input and common
converter is not compromised by settling errors. mode reference. 1% mismatches in 1k source resistances
lead to gain errors on the order of 15ppm. Based on the
In applications where the input common mode voltage is stability of the internal sampling capacitors and the ac-
constant but different from the reference common mode curacy of the internal oscillator, a one-time calibration will
voltage, the differential input current remains zero while remove this error.
the common mode input current is proportional to the
difference between VIN(CM) and VREF(CM). For a reference In addition to the input sampling current, the input ESD
common mode voltage of 2.5V and an input common mode protection diodes have a temperature dependent leakage
of 1.5V, the common mode input current is approximately current. This current, nominally 1nA (±10nA max), results
0.74µA (in simultaneous 50Hz/60Hz rejection mode). This in a small offset shift. A 1k source resistance will create a
common mode input current does not degrade the accuracy 1µV typical and a 10µV maximum offset voltage.
if the source impedances tied to IN+ and IN– are matched.
Automatic Offset Calibration of External Buffers/
Mismatches in source impedance lead to a fixed offset
Amplifiers
error but do not effect the linearity or full-scale reading.
A 1% mismatch in a 1k source resistance leads to a 74µV In addition to the Easy Drive input current cancellation,
shift in offset voltage. the LTC2499 allows an external amplifier to be inserted
between the multiplexer output and the ADC input (see
Figure 12). This is useful in applications where balanced
ANALOG
INPUTS
LTC2499 source impedances are not possible. One pair of external
∆Σ ADC
buffers/amplifiers can be shared between all 17 analog
17 SDA
INPUT
MUX
WITH
EASY DRIVE SCL
inputs. The LTC2499 performs an internal offset calibration
INPUTS every conversion cycle in order to remove the offset and
MUXOUTN
MUXOUTP

drift of the ADC. This calibration is performed through a

combination of front end switching and digital process-
ing. Since the external amplifier is placed between the
2
– 1k
multiplexer and the ADC, it is inside this correction loop.
1
1/2 LTC6078 This results in automatic offset correction and offset drift
3
+ 0.1µF removal of the external amplifier.
The LTC6078 is an excellent amplifier for this function.
6
It operates with supply voltages as low as 2.7V and its
– 1k noise level is 18nV/√Hz. The Easy Drive input technology
7
1/2 LTC6078 2499 F12

5 of the LTC2499 enables an RC network to be added directly

+ 0.1µF
to the output of the LTC6078. The capacitor reduces the
magnitude of the current spikes seen at the input to the
Figure 12. External Buffers Provide High Impedance Inputs
and Amplifier Offsets are Automatically Cancelled ADC and the resistor isolates the capacitor load from the
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 LTC2499
Applications Information
op amp output enabling stable operation. The LTC6078 For relatively small values of external reference capacitance
can also be biased at supply rails beyond those used by (CREF < 1nF), the voltage on the sampling capacitor settles
the LTC2499. This allows the external sensor to swing rail- for reference impedances of many kΩ (if CREF = 100pF up
to-rail (–0.3V to VCC + 0.3V) without the need of external to 10kΩ will not degrade the performance (see Figures 13
level-shift circuitry. and 14)).
In cases where large bypass capacitors are required on
Reference Current
the reference inputs (CREF > .01µF), full-scale and linear-
Similar to the analog inputs, the LTC2499 samples the ity errors are proportional to the value of the reference
differential reference pins (REF+ and REF–) transferring resistance. Every ohm of reference resistance produces
small amounts of charge to and from these pins, thus a full-scale error of approximately 0.5ppm (while operat-
producing a dynamic reference current. If incomplete set- ing in simultaneous 50Hz/60Hz mode (see Figures 15
tling occurs (as a function the reference source resistance and 16)). If the input common mode voltage is equal to
and reference bypass capacitance) linearity and gain errors the reference common mode voltage, a linearity error of
are introduced.

90 10
VCC = 5V
80 VREF = 5V 0
VIN+ = 3.75V
70 –10 CREF = 0.01µF
VIN– = 1.25V
fO = GND CREF = 0.001µF
60 –20 CREF = 100pF
+FS ERROR (ppm)

–FS ERROR (ppm)

TA = 25°C
50 –30 CREF = 0pF
CREF = 0.01µF
40 CREF = 0.001µF –40
30 CREF = 100pF
–50
CREF = 0pF VCC = 5V
20 –60 VREF = 5V
V + = 1.25V
10 –70 VIN– = 3.75V
IN
0 –80 fO = GND
TA = 25°C
–10 –90
0 10 100 1k 10k 100k 0 10 100 1k 10k 100k
RSOURCE (Ω) RSOURCE (Ω)
2499 F13 2499 F14

Figure 13. +FS Error vs RSOURCE at VREF (Small CREF) Figure 14. –FS Error vs RSOURCE at VREF (Small CREF)

500 0
VCC = 5V
CREF = 1µF, 10µF
VREF = 5V
VIN+ = 3.75V
400 VIN– = 1.25V –100
fO = GND CREF = 0.01µF
+FS ERROR (ppm)

–FS ERROR (ppm)

TA = 25°C CREF = 0.1µF

300 –200

CREF = 1µF, 10µF

200 –300
VCC = 5V CREF = 0.1µF
CREF = 0.01µF VREF = 5V
VIN+ = 1.25V
100 –400 VIN– = 3.75V
fO = GND
TA = 25°C
0 –500
0 200 400 600 800 1000 0 200 400 600 800 1000
RSOURCE (Ω) RSOURCE (Ω)
2499 F15 2499 F16

Figure 15. +FS Error vs RSOURCE at VREF (Large CREF) Figure 16. –FS Error vs RSOURCE at VREF (Large CREF)

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LTC2499
Applications Information
approximately 0.67ppm per 100Ω of reference resistance In addition to the reference sampling charge, the reference
results (see Figure 17). In applications where the input ESD protection diodes have a temperature dependent leak-
and reference common mode voltages are different, the age current. This leakage current, nominally 1nA (±10nA
errors increase. A 1V difference in between common mode max) results in a small gain error. A 100Ω reference
input and common mode reference results in a 6.7ppm resistance will create a 0.5µV full-scale error.
INL error for every 100Ω of reference resistance.
Normal Mode Rejection and Anti-Aliasing
10
VCC = 5V
8 VREF = 5V
One of the advantages delta-sigma ADCs offer over
VIN(CM) = 2.5V
6 T = 25°C
R = 1k conventional ADCs is on-chip digital filtering. Combined
A
4 CREF = 10µF
with a large oversample ratio, the LTC2499 significantly
INL (ppm OF VREF)

2 simplifies anti-aliasing filter requirements. Additionally,

R = 500Ω
0 the input current cancellation feature allows external
–2 R = 100Ω lowpass filtering without degrading the DC performance
–4 of the device.
The SINC4 digital filter provides excellent normal mode
–6
–8
–10
rejection at all frequencies except DC and integer multiples
–0.5 –0.3 –0.1 0.1 0.3 0.5 of the modulator sampling frequency (fS) (see Figures 18
VIN/VREF
2499 F17
and 19). The modulator sampling frequency is fS =
15,360Hz while operating with its internal oscillator and
Figure 17. INL vs Differential Input Voltage and
Reference Source Resistance for CREF > 1µF fS = fEOSC/20 when operating with an external oscillator
of frequency fEOSC .

0 0
–10
INPUT NORMAL MODE REJECTION (dB)

–10
INPUT NORMAL MODE REJECTION (dB)

–20 –20
–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
–110 –110
–120 –120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2499 F18
2499 F19

Figure 19. Input Normal Mode Rejection, Internal

Oscillator and 60Hz Rejection Mode
Figure 18. Input Normal Mode Rejection, Internal
Oscillator and 50Hz Rejection Mode

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 LTC2499
Applications Information
When using the internal oscillator, the LTC2499 is de- Traditional high order delta-sigma modulators suffer from
signed to reject line frequencies. As shown in Figure 20, potential instabilities at large input signal levels. The
rejection nulls occur at multiples of frequency fN, where proprietary architecture used for the LTC2499 third-order
fN is determined by the input control bits FA and FB modulator resolves this problem and guarantees stability
(fN = 50Hz or 60Hz or 55Hz for simultaneous rejection). with input signals 150% of full scale. In many industrial
Multiples of the modulator sampling rate (fS = fN • 256) applications, it is not uncommon to have microvolt level
only reject noise to 15dB (see Figure 21); if noise sources signals superimposed over unwanted error sources with
are present at these frequencies anti-aliasing will reduce several volts if peak-to-peak noise. Figures 25 and 26
their effects. show measurement results for the rejection of a 7.5V
The user can expect to achieve this level of performance peak-to-peak noise source (150% of full scale) applied to
using the internal oscillator, as shown in Figures 22, 23, the LTC2499. These curves show that the rejection perfor-
and 24. Measured values of normal mode rejection are mance is maintained even in extremely noisy environments.
shown superimposed over the theoretical values in all
three rejection modes.

0
fN = fEOSC/5120
–10
INPUT NORMAL MODE REJECTION (dB)

–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fN 2fN 3fN 4fN 5fN 6fN 7fN 8fN
INPUT SIGNAL FREQUENCY (Hz) 2499 F20

Figure 20. Input Normal Mode Rejection at DC

0
fN = fEOSC/5120
–10
INPUT NORMAL MODE REJECTION (dB)

–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
2499 F21

Figure 21. Input Normal Mode Rejection at fS = 256 • fN

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LTC2499
Applications Information
0 0
VCC = 5V VCC = 5V
MEASURED DATA MEASURED DATA
VREF = 5V VREF = 5V
–20 CALCULATED DATA –20 CALCULATED DATA
VIN(CM) = 2.5V
NORMAL MODE REJECTION (dB)

NORMAL MODE REJECTION (dB)

VIN(CM) = 2.5V
VIN(P-P) = 5V VIN(P-P) = 5V
–40 TA = 25°C –40 TA = 25°C

–60 –60

–80 –80

–100 –100

–120 –120
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz)
2498 F22 2498 F23

Figure 22. Input Normal Mode Rejection vs Input Frequency with Figure 23. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (60Hz Notch) Input Perturbation of 100% (50Hz Notch)

0 0
VCC = 5V VCC = 5V
MEASURED DATA VIN(P-P) = 5V
VREF = 5V VREF = 5V
–20 CALCULATED DATA –20 VIN(P-P) = 7.5V
NORMAL MODE REJECTION (dB)

VIN(CM) = 2.5V VIN(CM) = 2.5V

NORMAL MODE REJECTION (dB)

(150% OF FULL SCALE)

VIN(P-P) = 5V TA = 25°C
–40 TA = 25°C –40

–60 –60

–80 –80

–100 –100

–120 –120
0 20 40 60 80 100 120 140 160 180 200 220 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz)
2498 F24 2498 F26

Figure 24. Input Normal Mode Rejection vs Input Frequency with Figure 25. Measure Input Normal Mode Rejection vs Input
Input Perturbation of 100% (50Hz/60Hz Notch) Frequency with Input Perturbation of 150% (60Hz Notch)

0
VCC = 5V
VIN(P-P) = 5V
VREF = 5V
–20 VIN(P-P) = 7.5V
NORMAL MODE REJECTION (dB)

VIN(CM) = 2.5V
(150% OF FULL SCALE)
TA = 25°C
–40

–60

–80

–100

–120
0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2498 F27

Figure 26. Measure Input Normal Mode Rejection vs Input

Frequency with Input Perturbation of 150% (50Hz Notch)

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28 For more information www.linear.com/LTC2499

 LTC2499
Applications Information
Using the 2X speed mode of the LTC2499 alters the rejection output rate leads to degradation in offset, full-scale error,
characteristics around DC and multiples of fS. The device and effective resolution as well as a shift in frequency
bypasses the offset calibration in order to increase the output rejection. When using the integrated temperature sensor,
rate. The resulting rejection plots are shown in Figures 27 the internal oscillator should be used or an external oscil-
and 28. 1x type frequency rejection can be achieved us- lator fEOSC = 307.2kHz maximum.
ing the 2x mode by performing a running average of the A change in fEOSC results in a proportional change in the
previous two conversion results (see Figure 29). internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
Output Data Rate rejection of line frequencies remains unchanged, thus fully
When using its internal oscillator, the LTC2499 produces differential input signals with a high degree of symmetry
up to 7.5 samples per second (sps) with a notch frequency on both the IN+ and IN – pins will continue to reject line
of 60Hz. The actual output data rate depends upon the length frequency noise.
of the sleep and data output cycles which are controlled An increase in fEOSC also increases the effective dynamic
by the user and can be made insignificantly short. When input and reference current. External RC networks will
operating with an external conversion clock (fO connected continue to have zero differential input current, but the
to an external oscillator), the LTC2499 output data rate time required for complete settling (580ns for fEOSC =
can be increased. The duration of the conversion cycle is 307.2kHz) is reduced, proportionally.
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
Once the external oscillator frequency is increased above
as if the internal oscillator is used.
1MHz (a more than 3x increase in output rate) the effective-
An increase in fEOSC over the nominal 307.2kHz will trans- ness of internal auto calibration circuits begins to degrade.
late into a proportional increase in the maximum output This results in larger offset errors, full-scale errors, and
data rate (up to a maximum of 100sps). The increase in decreased resolution, as seen in Figures 30-37.

0 0

–20
INPUT NORMAL REJECTION (dB)

–20
INPUT NORMAL REJECTION (dB)

–40 –40

–60 –60

–80 –80

–100 –100

–120 –120
0 fN 2fN 3fN 4fN 5fN 6fN 7fN 8fN 248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (fN) INPUT SIGNAL FREQUENCY (fN)
2499 F27 2499 F28

Figure 27. Input Normal Mode Rejection 2x Speed Mode Figure 28. Input Normal Mode Rejection 2x Speed Mode

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 LTC2499
Applications Information
–70 50 3500
VIN(CM) = VREF(CM) VIN(CM) = VREF(CM)
VCC = VREF = 5V VCC = VREF = 5V
–80 40 VIN = 0V 3000 fO = EXT CLOCK
NORMAL MODE REJECTION (dB)

OFFSET ERROR (ppm OF VREF)

NO AVERAGE fO = EXT CLOCK TA = 25°C

+FS ERROR (ppm OF VREF)

–90 TA = 25°C 2500 TA = 85°C
30 TA = 85°C
–100 WITH 2000
RUNNING 20
–110 AVERAGE 1500
10
–120 1000

0 500
–130

–140 –10 0
48 50 52 54 56 58 60 62 0 10 20 30 0 10 20 30
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC)
2499 F29 2499 F30 2499 F31

Figure 29. Input Normal Mode Figure 30. Offset Error vs Output Data Figure 31. +FS Error vs Output Data
Rejection 2x Speed Mode with and Rate and Temperature Rate and Temperature
Without Running Averaging

0 24 22

–500 22
20
–FS ERROR (ppm OF VREF)

–1000 20
RESOLUTION (BITS)

RESOLUTION (BITS)
18
–1500 18
16
–2000 16 TA = 25°C
TA = 85°C TA = 25°C
VIN(CM) = VREF(CM) 14 TA = 85°C
–2500 TA = 25°C 14
TA = 85°C VCC = VREF = 5V VIN(CM) = VREF(CM)
V = VREF(CM) VIN = 0V 12 VCC = VREF = 5V
–3000 IN(CM) 12 fO = EXT CLOCK fO = EXT CLOCK
VCC = VREF = 5V
fO = EXT CLOCK RES = LOG 2 (VREF/NOISERMS) RES = LOG 2 (VREF/INLMAX)
–3500 10 10
0 10 20 30 0 10 20 30 0 10 20 30
OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC)
2499 F32 2499 F33 2499 F34

Figure 32.–FS Error vs Output Data Figure 33. Resolution (NoiseRMS ≤ 1LSB) Figure 34. Resolution (INLMAX ≤ 1LSB)
Rate and Temperature vs Output Data Rate and Temperature vs Output Data Rate and Temperature

20 24 22
VIN(CM) = VREF(CM)
VIN = 0V
22
15 fO = EXT CLOCK 20
OFFSET ERROR (ppm OF VREF)

TA = 25°C
VCC = VREF = 5V 20
RESOLUTION (BITS)

RESOLUTION (BITS)

10 V = 5V, V 18
CC REF = 2.5V
18
5 16 VCC = VREF = 5V
16 VCC = VREF = 5V VCC = 5V, VREF = 2.5V
VCC = 5V, VREF = 2.5V VIN(CM) = VREF(CM)
0 14
14 VIN(CM) = VREF(CM) VIN = 0V
VIN = 0V REF– = GND
–5 fO = EXT CLOCK 12 fO = EXT CLOCK
12 T = 25°C
A TA = 25°C
RES = LOG 2 (VREF/NOISERMS) RES = LOG 2 (VREF/INLMAX)
–10 10 10
0 10 20 30 0 10 20 30 0 10 20 30
OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC)
2499 F35 2499 F36 2499 F37

Figure 35. Offset Error vs Output Figure 36. Resolution (NoiseRMS ≤ 1LSB) Figure 37. Resolution (INLMAX ≤ 1LSB)
Data Rate and Reference Voltage vs Output Data Rate and Reference vs Output Data Rate and Reference
Voltage Voltage
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 LTC2499
Applications Information

VCC + 0.3V
VCC VCC

VREF
2
VREF VREF –VREF
2 2 2
–VREF
2
GND GND
–0.3V
(a) Arbitrary (b) Fully Differential

VCC VCC

VREF
2

–VREF VREF
2 2 –0.3V

GND
GND –0.3V
(c) Pseudo Differential Bipolar
IN– or COM Biased (d) Pseudo-Differential Unipolar
Selected IN+ Ch
IN– or COM Grounded
Selected IN– Ch or COM 2499 F38

Figure 38. Input Range

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LTC2499
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)

0.70 ±0.05

5.50 ±0.05
5.15 ±0.05

4.10 ±0.05

3.00 REF 3.15 ±0.05

PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
5.5 REF
6.10 ±0.05
7.50 ±0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH
R = 0.30 TYP OR
0.75 ±0.05 3.00 REF 0.35 × 45° CHAMFER
5.00 ±0.10
0.00 – 0.05 37 38

0.40 ±0.10
PIN 1
TOP MARK 1
(SEE NOTE 6)
2

5.15 ±0.10
7.00 ±0.10 5.50 REF

3.15 ±0.10

(UH) QFN REF C 1107

0.200 REF 0.25 ±0.05 R = 0.125 R = 0.10

0.50 BSC TYP TYP
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
OUTLINE M0-220 VARIATION WHKD MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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 LTC2499
Revision History (Revision history begins at Rev C)

REV DATE DESCRIPTION PAGE NUMBER

C 11/09 Update Tables 1 and 2 16
D 7/10 Revised Typical Application drawing. 1
Added fO pin to parameters of VIHA in I2C Inputs and Digital Outputs section 4
Added text to first paragraph of I2C Interface section 15
E 11/14 Clarified performance vs frequency, reduced External Oscillator Max frequency to 1MHz 5, 9, 30
Clarified Input Voltage Range 3, 4, 13, 31
Added underrange note to Table 1 15

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33
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTC2499
as described herein will not infringe on existing patent rights.
LTC2499
Typical Application
External Buffers Provide High Impedance Inputs and
Amplifier Offsets Are Automatically Cancelled

LTC2499
ΔΣ ADC
SDA
ANALOG 17 INPUT WITH

MUXOUTN
MUXOUTP
INPUTS MUX EASY DRIVE SCL
INPUTS

2
– 1k
1
1/2 LTC6078
3
+ 0.1µF

6
–

2499 TA03
7 1k
1/2 LTC6078
5
+ 0.1µF

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LTC2481/LTC2483/ 16-Bit/24-Bit ΔΣ ADCs with Easy Drive Inputs, 600nVRMS Noise, Pin-Compatible with 16-Bit and 24-Bit Versions
LTC2485 I2C Interface, Programmable Gain, and Temperature Sensor
LTC2496 16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Inputs and Pin-Compatible with LTC2498/LTC2449
SPI Interface
LTC2497 16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Inputs and Pin-Compatible with LTC2499
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SPI Interface, Temperature Sensor

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34 Linear Technology Corporation

LT 1114 REV E • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC2499
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2499  LINEAR TECHNOLOGY CORPORATION 2006