LTC3124

15V, 5A 2-Phase Synchronous

Step-Up DC/DC Converter with
Output Disconnect
FEATURES DESCRIPTION
n VIN Range: 1.8V to 5.5V, 500mV After Start-Up The LTC®3124 is a dual-phase, synchronous step-up DC/
n Adjustable Output Voltage: 2.5V to 15V DC converter with true output disconnect and inrush
n 1.5A Output Current for V = 5V and V
IN OUT = 12V current limiting capable of providing output voltages up
n Dual-Phase Control Reduces Output Voltage Ripple to 15V. Dual-phase operation significantly reduces peak
n Output Disconnects from Input When Shut Down inductor and capacitor ripple currents, minimizing induc-
n Synchronous Rectification: Up to 95% Efficiency tor and capacitor size. The 2.5A per phase current limit,
n Inrush Current Limit along with the ability to program output voltages up to 15V
n Up to 3MHz Programmable Switching Frequency make the LTC3124 well suited for a variety of demanding
Synchronizable to External Clock applications. Once started, operation will continue with
n Selectable Burst Mode® Operation: 25µA I inputs down to 500mV.
Q
n Output Overvoltage Protection
n Internal Soft-Start
The LTC3124 switching frequency can be programmed
n <1µA I in Shutdown
from 100kHz to 3MHz to optimize applications for highest
Q efficiency or smallest solution footprint. The oscillator can
n 16-Lead, Thermally- Enhanced 3mm × 5mm ×
be synchronized to an external clock for noise sensitive
0.75mm DFN and TSSOP Packages
applications. Selectable Burst Mode operation reduces
APPLICATIONS quiescent current to 25µA, ensuring high efficiency across
the entire load range. An internal soft-start limits inrush
n RF, Microwave Power Amplifiers current during start-up.
n Piezo Actuators
n Small DC Motors, Thermal Printers
Other features include a <1µA shutdown current and robust
n 12V Analog Rail from Battery, 5V, or Backup Capacitor
protection under short-circuit, thermal overload, and output
overvoltage conditions. The LTC3124 is offered in both
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the 16-lead DFN and thermally-enhanced TSSOP packages.
property of their respective owners.

TYPICAL APPLICATION
5V to 12V Synchronous Boost Converter Efficiency Curve
4.7µH 100 10
VIN SWB CAP Burst Mode
5V 90
100nF VOUT OPERATION
PGNDB VOUTB 12V 80 1
4.7µH 22µF 1.5A
×2 70 PWM
POWER LOSS (W)

SWA VOUTA
EFFICIENCY (%)

LTC3124 60 0.1
PGNDA
50
VIN SGND Burst Mode
40 OPERATION 0.01

BURST PWM PWM/SYNC SD OFF ON 1.02M 30

PWM
VCC FB 20 fSW = 1MHz 0.001
10µF
RT VC 113k 10 EFFICIENCY
4.7µF 84.5k POWER LOSS
56pF 0 0.0001
28k 0.01 0.1 1 10 100 1000
680pF
LOAD CURRENT (mA)
3124 TA01b
3124 TA01a

3124f

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LTC3124
ABSOLUTE MAXIMUM RATINGS (Note 1)

VIN Voltage.................................................... –0.3V to 6V All Other Pins................................................ –0.3V to 6V

VOUTA, VOUTB Voltages................................ –0.3V to 18V Operating Junction Temperature Range (Notes 3, 4)
SWA, SWB Voltages (Note 2)...................... –0.3V to 18V LTC3124E/LTC3124I............................ –40°C to 125°C
SWA, SWB (Pulsed < 100ns) (Note 2)........ –0.3V to 19V LTC3124H........................................... –40°C to 150°C
VC Voltage...................................................–0.3V to VCC Storage Temperature Range................... –65°C to 150°C
RT Voltage...................................................–0.3V to VCC Lead Temperature (Soldering, 10 sec)
CAP Voltage FE Package Only................................................ 300°C
VOUT < 5.7V.............................–0.3V to (VOUT + 0.3V)
5.7V ≤ VOUT ≤ 11.7V...... (VOUT – 6V) to (VOUT + 0.3V)
VOUT > 11.7V..................................(VOUT – 6V) to 12V

PIN CONFIGURATION
TOP VIEW TOP VIEW

SWB 1 16 CAP SWB 1 16 CAP

PGNDB 2 15 VOUTB PGNDB 2 15 VOUTB
SWA 3 14 NC SWA 3 14 NC
PGNDA 4 17 13 VOUTA PGNDA 4 17 13 VOUTA
VIN 5 PGND 12 SGND VIN 5 PGND 12 SGND
PWM/SYNC 6 11 SD PWM/SYNC 6 11 SD
VCC 7 10 FB VCC 7 10 FB
RT 8 9 VC RT 8 9 VC

DHC PACKAGE FE PACKAGE

16-LEAD (5mm × 3mm) PLASTIC DFN 16-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 43°C/W (NOTE 5), θJC = 5°C/W TJMAX = 150°C, θJA = 40°C/W (NOTE 5), θJC = 10°C/W
EXPOSED PAD (PIN 17) IS PGND AND MUST BE SOLDERED TO PCB EXPOSED PAD (PIN 17) IS PGND AND MUST BE SOLDERED TO PCB
FOR RATED THERMAL PERFORMANCE FOR RATED THERMAL PERFORMANCE

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3124EDHC#PBF LTC3124EDHC#TRPBF 3124 16-Lead (5mm × 3mm) Plastic DFN –40°C to 125°C
LTC3124IDHC#PBF LTC3124IDHC#TRPBF 3124 16-Lead (5mm × 3mm) Plastic DFN –40°C to 125°C
LTC3124EFE#PBF LTC3124EFE#TRPBF 3124FE 16-Lead Plastic TSSOP –40°C to 125°C
LTC3124IFE#PBF LTC3124IFE#TRPBF 3124FE 16-Lead Plastic TSSOP –40°C to 125°C
LTC3124HFE#PBF LTC3124HFE#TRPBF 3124FE 16-Lead Plastic TSSOP –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3124f

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 LTC3124
ELECTRICAL
CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 3). VIN = 3.6V, VOUTA = VOUTB = 12V, RT = 28k unless
otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Start-Up Voltage VOUT = 0V l 1.6 1.8 V
Input Voltage Range VOUT ≥ 2.5V l 0.5 5.5 V
Output Voltage Adjust Range l 2.5 15 V
Feedback Voltage l 1.176 1.200 1.224 V
Feedback Input Current FB = 1.4V 1 50 nA
Quiescent Current, Shutdown SD = 0V, VOUT = 0V, Not Including Switch Leakage 0.2 1 µA
Quiescent Current, Active FB = 1.4V, Measured on VIN, Non-Switching 600 840 µA
Quiescent Current, Burst Measured on VIN, FB = 1.4V 25 40 µA
Measured on VOUT, FB = 1.4V 10 20 µA
N-Channel MOSFET Switch Leakage Current SW = 15V, VOUT = 15V, Per Phase l 0.1 40 µA
P-Channel MOSFET Switch Leakage Current SW = 0V, VOUT = 15V, SD = 0V, Per Phase l 0.1 70 µA
N-Channel MOSFET Switch On-Resistance Per Phase 0.130 Ω
P-Channel MOSFET Switch On-Resistance Per Phase 0.200 Ω
N-Channel MOSFET Peak Current Limit Per Phase l 2.5 3.5 4.5 A
Maximum Duty Cycle FB = 1.0V l 90 94 %
Minimum Duty Cycle FB = 1.4V l 0 %
Switching Frequency Per Phase l 0.83 1 1.17 MHz
SYNC Frequency Range l 0.2 6.0 MHz
PWM/SYNC Input High Voltage l 0.9 • VCC V
PWM/SYNC Input Low Voltage l 0.1 • VCC V
PWM/SYNC Input Current VPWM/SYNC = 5.5V 0.01 1 µA
CAP Clamp Voltage VOUT > 6.2V, Referenced to VOUT –5.0 –5.4 –5.8 V
VCC Regulation Voltage VIN < 2.8V, VOUT > 5V 3.9 4.25 4.6 V
Error Amplifier Transconductance l 60 100 130 µS
Error Amplifier Sink Current FB = 1.6V, VC = 1.15V 25 µA
Error Amplifier Source Current FB = 800mV, VC = 1.15V –25 µA
Soft-Start Time 10 ms
SD Input High Voltage l 1.6 V
SD Input Low Voltage l 0.25 V
SD Input Current SD = 5.5V 1 2 µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note that the maximum ambient temperature consistent with these
may cause permanent damage to the device. Exposure to any Absolute specifications is determined by specific operating conditions in
Maximum Rating condition for extended periods may affect device conjunction with board layout, the rated package thermal impedance
reliability and lifetime. and other environmental factors. The junction temperature (TJ in °C) is
Note 2: Voltage transients on the SW pin beyond the DC limit specified in calculated from the ambient temperature (TA in °C) and power dissipation
the Absolute Maximum Ratings are non-disruptive to normal operations (PD in Watts) according to the formula:
when using good layout practices, as shown on the demo board or TJ = TA + (PD • θJA)
described in the data sheet or application notes. where θJA is the thermal impedance of the package.
Note 3: The LTC3124 is tested under pulsed load conditions such that Note 4: The LTC3124 includes overtemperature protection that is intended
TA ≈ TJ. The LTC3124E is guaranteed to meet performance specifications to protect the device during momentary overload conditions. Junction
from 0°C to 85°C junction temperature. Specifications over the –40°C temperature will exceed 150°C when overtemperature shutdown is active.
to 125°C operating junction temperature range are assured by design, Continuous operation above the specified maximum operating junction
characterization and correlation with statistical process controls. The temperature may result in device degradation or failure.
LTC3124I is guaranteed to meet specifications over the –40°C to 125°C Note 5: Failure to solder the exposed backside of the package to the PC
operating junction temperature range. The LTC3124H is guaranteed to board ground plane will result in a thermal impedance much higher than
meet specifications over the full –40°C to 150°C operating junction range. the rated package specifications.
High junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C.
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LTC3124
TYPICAL PERFORMANCE CHARACTERISTICS
Configured as front page application at TA = 25°C, unless otherwise specified.
Efficiency vs Load Current, Efficiency vs Load Current, Efficiency vs Load Current,
VOUT = 5V VOUT = 7.5V VOUT = 12V
100 100 100
Burst Mode Burst Mode
Burst Mode
90 OPERATION 90 OPERATION 90
OPERATION
80 80 80
PWM PWM
70 70 70
PWM
EFFICIENCY (%)

EFFICIENCY (%)

EFFICIENCY (%)
60 60 60
50 50 50
40 40 40
30 30 30
fSW = 1MHz fSW = 1MHz fSW = 1MHz
20 VIN = 4.2V 20 VIN = 5.4V 20 VIN = 5.4V
10 VIN = 3.3V 10 VIN = 3.8V 10 VIN = 4.2V
VIN = 0.6V VIN = 2.3V VIN = 2.6V
0 0 0
0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
3124 G01 3124 G02 3124 G03

PWM Mode Operation Load Transient Response Inrush Current Control

VOUT SD
VOUT
20mV/DIV 5V/DIV
500mV/DIV
AC-COUPLED
AC-COUPLED
PHASE A
INDUCTOR 1500mA VOUT
CURRENT 5V/DIV
500mA/DIV OUTPUT
PHASE B CURRENT INDUCTOR A
INDUCTOR 500mA/DIV CURRENT
CURRENT 150mA 150mA 1A/DIV
500mA/DIV INDUCTOR B
CURRENT
1A/DIV
3124 G04 3124 G06
ILOAD = 500mA 2µs/DIV RC = 169k 500µs/DIV 3124 G05
ILOAD = 100mA 2ms/DIV
CC = 330pF
NO CF

RDS(ON) vs Temperature, Switching Frequency

Feedback vs Temperature Both NMOS and PMOS vs Temperature
0.05 80 0.5
CHANGE IN FREQUENCY FROM 25°C (%)

0
CHANGE IN RDS(ON) FROM 25°C (%)

60
CHANGE IN VFB FROM 25°C (%)

0
–0.05
40
–0.10
–0.5
–0.15 20

–0.20 –1.0
0
–0.25
–1.5
–20
–0.30

–0.35 –40 –2.0

–40 0 40 80 120 160 –50 –10 30 70 110 150 –50 –20 10 40 70 100 130 160
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3124 G08
3124 G07 3124 G09

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 LTC3124
TYPICAL PERFORMANCE CHARACTERISTICS
Configured as front page application at TA = 25°C, unless otherwise specified.
PWM Mode Maximum Output Peak Current Limit Change PWM Operation No-Load Input
Current vs VIN vs Temperature Current vs VIN
4.0 2 200

PEAK CURRENT LIMIT CHANGE FROM 25°C (%)

VOUT = 5V VOUT = 15V
3.6 VOUT = 7.5V 180 VOUT = 12V
VOUT = 12V 1 VOUT = 7.5V
3.2 160
VOUT = 15V VOUT = 5V
OUTPUT CURRENT (A)

INPUT CURRENT (mA)

2.8 140 VOUT = 2.5V
0
2.4 120
2.0 –1 100
1.6 80
–2
1.2 60
0.8 40
–3
0.4 20
0 –4 0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 –50 –10 30 70 110 150 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VIN (V) TEMPERATURE (°C) VIN (V)
3124 G11
3124 G10 3124 G12

Burst Mode No-Load Input Burst Mode Quiescent Current

Burst Mode Output Current vs VIN Current vs VIN Change vs Temperature
400 10000 75
VOUT = 15V
350 VOUT = 12V

CHANGE IN CURRENT FROM 25°C (%)

VOUT = 7.5V 60
300 VOUT = 5V
OUTPUT CURRENT (mA)

INPUT CURRENT (µA)

VOUT = 2.5V
1000 45
250

200 30

150
100 15
100
0
50

0 10 –15
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 –50 –10 30 70 110 150
VIN, FALLING (V) 3124 G13 VIN, FALLING (V) TEMPERATURE (°C)
3124 G15
VOUT = 2.5V VOUT = 12V 3124 G14

VOUT = 5V VOUT = 15V

VOUT = 7.5V

SD Pin Threshold RT vs Frequency

VOUT 100
5V/DIV
RT RESISTANCE (kΩ)

900mV

VSD 400mV 10
500mV/DIV

3124 G16
1s/DIV

10
100 1000 3000
FREQUENCY (kHz)
3124 G17
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LTC3124
TYPICAL PERFORMANCE CHARACTERISTICS
Configured as front page application at TA = 25°C, unless otherwise specified.
Frequency Accuracy Efficiency vs Frequency CAP Pin Voltage vs VOUT
2 100 0
90
–1
80

VCAP, REFERRED TO VOUT (V)

CHANGE IN FREQUENCY (%)

1
70 –2

EFFICIENCY (%)
60
–3
0 50
40 –4

30 –5
–1
VOUT = 15V 20 100kHz EFFICIENCY
VOUT = 3.6V 1MHz EFFICIENCY –6
10
VOUT = 2.5V 3MHz EFFICIENCY
–2 0 –7
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 10 100 1000 0 2 4 6 8 10 12 14
VIN, FALLING (V) OUTPUT CURRENT (mA) VOUT (V)
3124 G21
3124 G19 3124 G20

Burst Mode Operation to

VCC vs VIN Burst Mode Operation PWM Mode
4.5

VOUT VOUT
4.0 100mV/DIV 50mV/DIV
AC-COUPLED AC-COUPLED
VSWA
VCC (V)

10V/DIV
3.5

PHASE A VPWM/SYNC
3.0 INDUCTOR 2V/DIV
CURRENT
VIN FALLING 500mA/DIV
VIN RISING
2.5 3124 G23
0 1 2 3 4 5 6 5µs/DIV 50µs/DIV 3124 G24

VIN (V) OUTPUT CURRENT = 50mA OUTPUT CURRENT = 100mA

3124 G22 TYPE III COMPENSATION—SEE FIGURE 10 FOR
COMPONENT VALUES

PWM Mode to Burst Mode

Operation Burst Mode Transient Synchronized Operation

VOUT VOUT
50mV/DIV 100mV/DIV VSWB
AC-COUPLED AC-COUPLED 10V/DIV

SYNCHRONIZED TO 1.3MHz
VSWA
10V/DIV

VPWM/SYNC 100mA SYNCHRONIZATION SIGNAL SET TO 2.6MHz

2V/DIV OUTPUT
VPWM/SYNC
CURRENT 10mA 10mA 5V/DIV
100mA/DIV

3124 G25 3124 G26 3124 G27

50µs/DIV 200µs/DIV 1µs/DIV
OUTPUT CURRENT = 100mA OUTPUT CURRENT = 1A
TYPE III COMPENSATION—SEE FIGURE 10 FOR
COMPONENT VALUES

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 LTC3124
TYPICAL PERFORMANCE CHARACTERISTICS
Configured as front page application at TA = 25°C, unless otherwise specified.

Short-Circuit Response SWA and SWB at 1MHz/Phase

SHORT-CIRCUIT
APPLIED
VOUT VSWB
5V/DIV 5V/DIV
SHORT-CIRCUIT
REMOVED

INDUCTOR B
CURRENT
2A/DIV
VSWA
5V/DIV
INDUCTOR A
CURRENT
2A/DIV
3124 G28 3124 G29
ILOAD = 500mA 100µs/DIV ILOAD = 1500mA 500ns/DIV

Output Voltage Ripple at 1.5A

SW Pins while Synchronizing Load with Two 10µF Ceramic
to 1.2MHz Capacitors

VOUT
VSWB 20mV/DIV
5V/DIV AC-COUPLED
INDUCTOR B
CURRENT
500mA/DIV
INDUCTOR A
CURRENT
VSWA 500mA/DIV
5V/DIV

3124 G30 3124 G31

ILOAD = 1500mA 500ns/DIV 500ns/DIV

PIN FUNCTIONS
SWB, SWA (Pin 1, Pin 3): Phase B and Phase A Switch PGNDB, PGNDA, PGND (Pin 2, Pin 4, Exposed Pad
Pins. Connect inductors from these pins to the input sup- Pin 17): Power Ground. When laying out your PCB, provide
ply. Keep PCB trace lengths as short and wide as possible a short, direct path between PGND and the output capaci-
to reduce EMI and voltage overshoot. When VOUT ≥ VIN + tors and tie directly to the ground plane. The exposed pad
2V, internal anti-ringing resistors are connected between is ground and must be soldered to the PCB ground plane
VIN and both SWA and SWB after their respective induc- for rated thermal and electrical performance.
tor currents have dropped to near zero, to minimize EMI.
VIN (Pin 5): Input Supply Pin. The device is powered from
These anti-ringing resistors are also activated in shutdown VIN if VIN is initially greater than approximately 3.5V, with
and during the sleep periods of Burst Mode operation. VIN continuing to supply the device down to approximately
3V; otherwise the greater of VIN and VOUT supplies the
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LTC3124
PIN FUNCTIONS
device. Place a low ESR ceramic bypass capacitor of at VC (Pin 9): Error Amplifier Output. A frequency com-
least 10µF from VIN to PGND. X5R and X7R dielectrics pensation network is connected from this pin to SGND
are preferred for their superior voltage and temperature to compensate the control loop. See Compensating the
characteristics. Feedback Loop section for guidelines.
PWM/SYNC (Pin 6): Burst Mode Operation Select and FB (Pin 10): Feedback Input to the Error Amplifier. Con-
Oscillator Synchronization. Do not leave this pin floating. nect the resistor divider tap to this pin. Connect the top
of the divider to VOUT and the bottom of the divider to
• PWM/SYNC = High. Disable Burst Mode operation and
SGND. The output voltage can be adjusted from 2.5V to
maintain low noise, constant frequency operation.
15V according to the formula:
• PWM/SYNC = Low. The converter operates in Burst
Mode, independent of load current.  R1
VOUT = 1.2V •  1+ 
 R2 
• PWM/SYNC = External CLK. The internal oscillator is
synchronized to the external CLK signal. Burst Mode SD (Pin 11): Logic Controlled Shutdown Input. Pulling this
operation is disabled. A clock pulse width of 100ns pin above 1.6V enables normal, free-running operation.
minimum is required to synchronize the oscillator. Forcing this pin below 0.25V shuts the LTC3124 off, with
An external resistor MUST BE connected between RT quiescent current below 1µA. Do not leave this pin floating.
and SGND to program the oscillator slightly below the
desired synchronization frequency. SGND (Pin 12): Signal Ground. When laying out your PC
board, provide a short, direct path between SGND and the
In non-synchronized applications, repeated clocking of ground referenced sides of all the appropriate components
the PWM/SYNC pin to affect an operating mode change connecting to pins RT, VC, and FB.
is supported with these restrictions:
VOUTA, VOUTB (Pin 13, Pin 15): Output Voltage Senses and
• Boost Mode (VOUT > VIN): IOUT < 3mA: fPWM/SYNC ≤ the Source of the Internal Synchronous Rectifier MOSFETs.
10Hz, IOUT ≥ 3mA: fPWM/SYNC ≤ 5kHz. Driver bias is derived from VOUT. Connect the output filter
• Buck Mode (VOUT < VIN): IOUT < 5mA: fPWM/SYNC ≤ capacitor from VOUT to PGND, close to the IC. A minimum
2.5Hz, IOUT ≥ 5mA: fPWM/SYNC ≤ 5kHz. value of 10µF ceramic per phase is recommended. VOUT is
disconnected from VIN when SD is low. VOUTA and VOUTB
VCC (Pin 7): VCC Regulator Output. Connect a low ESR must be tied together.
filter capacitor of at least 4.7µF from this pin to SGND to
provide a regulated rail approximately equal to the lower of NC (Pin 14): No Connect. Not connected internally. Connect
VIN and 4.25V. When VOUT is higher than VIN, and VIN falls this pin to VOUTA/VOUTB to provide a wider VOUT copper
below 3V, VCC will regulate to the lower of approximately plane on the printed circuit board.
VOUT and 4.25V. A UVLO event occurs if VCC drops below CAP (Pin 16): Serves as the Low Reference for the Syn-
1.5V, typical. Switching is inhibited, and a soft-start is chronous Rectifiers Gate Drives. Connect a low ESR filter
initiated when VCC returns above 1.6V, typical. capacitor (typically 100nF) from this pin to VOUT to provide
RT (Pin 8): Frequency Adjust Pin. Connect to SGND an elevated ground rail, approximately 5.4V below VOUT,
through an external resistor (RT) to program the oscillator used to drive the synchronous rectifiers.
frequency according to the formula:
56
fOSC ≅
RT
fOSC 28
fSWITCH = ≅
2 RT
where fOSC is in MHz and RT is in kΩ.
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 LTC3124
BLOCK DIAGRAM
BULK
CONTROL
VIN
SIGNALS

SWB VOUTB VOUT

1 15 2.5V TO 15V
SHUT SD COUT
PWM 11
DOWN
LOGIC
CCAP
ANTI- AND
EN 100nF
RING DRIVERS + – CAP
CURRENT IZERO VOUT – 5.4V RAIL 16
PWM SENSE COMP
COMP
+––
NC 14

+ OVLO –
16.5V
STOP SWITCHING
+ +
+

LB IPEAK
– 3.5A
BULK
COMP CONTROL
VIN
SIGNALS
ADAPTIVE SLOPE COMP
SWA VOUTA
3 13

PWM
LOGIC
AND TSD
ANTI-
RING DRIVERS + –
LA CURRENT IZERO
PWM THERMAL SD
SENSE COMP
COMP
+––
REFERENCE
BURST Burst
+ SLEEP Mode
1.2V
VIN VIN
5 CONTROL
1.8V TO 5.5V
+ + + VREFUP
CIN VIN
IPEAK
– 3.5A
COMP

ADAPTIVE SLOPE COMP 4.25V SOFT-

LDO START

OSCILLATOR
gm ERROR
SYNC AMPLIFIER
+
VC + R1
9 – FB
VCC 10
CF RC
EXPOSED R2
CC PGNDB RT PWM/SYNC SGND VCC PGNDA PAD
2 8 6 12 7 4 17
3124 BD

RT CVCC

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LTC3124
OPERATION
The LTC3124 is a dual-phase, adjustable frequency (100kHz The peak inductor current, reduced nearly by a factor of
to 3MHz) synchronous boost converter housed in either a 2 when compared to a single phase step-up converter,
16-lead 5mm × 3mm DFN or a thermally-enhanced TSSOP is given by:
package. The LTC3124 offers the unique ability to start up 1 I ∆I
from inputs as low as 1.8V and continue to operate from ILPEAK ≅ • O + L 1
inputs as low as 0.5V, for output voltages greater than 2 (1–D) 2
2.5V. The device also features fixed frequency, current where IO is the average load current, D is the PWM duty
mode PWM control for exceptional line and load regula- cycle, and ∆IL is the inductor ripple current. This relation-
tion. The current mode architecture with adaptive slope ship is shown graphically in Figure 1.
compensation provides excellent load transient response
and requires minimal output filtering. An internal 10ms With 2-phase operation, one of the phases is always de-
soft-start limits inrush current during start-up and simpli- livering current to the load whenever VIN is greater than
fies the design process while minimizing the number of one-half VOUT (duty cycles less than 50%). As the duty
external components. cycle decreases further, load current delivery between the
two phases begins to overlap, occurring simultaneously
With its low RDS(ON) and low gate charge internal N-channel for a growing portion of each phase as the duty cycle ap-
MOSFET switches and P-channel MOSFET synchronous proaches zero. This significantly reduces both the output
rectifiers, the LTC3124 achieves high efficiency over a ripple current and the peak current in each inductor, when
wide range of load current. High efficiency is achieved at compared with a single-phase converter. This is illustrated
light loads by utilizing Burst Mode operation. Operation in the waveforms of Figures 2 and 3.
can be best understood by referring to the Block Diagram.
3.5
SINGLE PHASE
MULTIPHASE OPERATION 3.0
OUTPUT RIPPLE CURRENT (A)

The LTC3124 uses a dual-phase architecture, rather than 2.5

the conventional single phase of other boost converters. 2.0 DUAL

By having two phases equally spaced 180° apart, not only PHASE

is the output ripple frequency increased by a factor of 1.5

two, but the output capacitor ripple current is significantly 1.0

reduced. Although this architecture requires two induc- 0.5

tors, rather than a single inductor, there are a number of
important advantages. 0
0 0.5 1.0 1.5
TIME (µs)
• Substantially lower peak inductor current allows the 3124 F01

use of smaller, lower cost inductors. Figure 1. Comparison of Output Ripple Current with Single Phase
• Significantly reduced output ripple current minimizes and Dual Phase Boost Converter in a 1.5A Load Application
Operating at 50% Duty Cycle
output capacitance requirement.
• Higher frequency output ripple is easier to filter for low
noise applications.
• Input ripple current is also reduced for lower noise on
VIN.

3124f

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 LTC3124
OPERATION
SWITCH A LOW VOLTAGE OPERATION
VOLTAGE
The LTC3124 is designed to allow start-up from input
SWITCH B
voltages as low as 1.8V. When VOUT exceeds 2.5V, the
VOLTAGE LTC3124 continues to regulate its output, even when VIN
falls as low as 0.5V. This feature extends operating times
INDUCTOR A
CURRENT by maximizing the amount of energy that can be extracted
INDUCTOR B
from the input source. The limiting factors for the applica-
CURRENT tion become the availability of the power source to supply
INPUT
sufficient power to the output at the low input voltage,
CURRENT and the maximum duty cycle, which is clamped at 94%.
RECTIFIER A Note that at low input voltages, small voltage drops due
CURRENT to series resistance become critical and greatly limit the
power delivery capability of the converter.
RECTIFIER B
CURRENT
LOW NOISE FIXED FREQUENCY OPERATION
OUTPUT
RIPPLE
CURRENT 3124 F02
Soft-Start
The LTC3124 contains internal circuitry to provide soft-
Figure 2. Simplified Voltage and Current Waveforms
for 2-Phase Operation at 50% Duty Cycle
start operation. The soft-start utilizes a linearly increasing
ramp of the error amplifier reference voltage from zero
to its nominal value of 1.2V in approximately 10ms, with
SWITCH A the internal control loop driving VOUT from zero to its
VOLTAGE
final programmed value. This limits the inrush current
drawn from the input source. As a result, the duration
SWITCH B
VOLTAGE of the soft-start is largely unaffected by the size of the
output capacitor or the output regulation voltage. The
INDUCTOR A
CURRENT
closed-loop nature of the soft-start allows the converter
to respond to load transients that might occur during
INDUCTOR B
CURRENT
the soft-start interval. The soft-start period is reset by a
shutdown command on SD, a UVLO event on VCC (VCC <
INPUT
CURRENT 1.5V), an overvoltage event on VOUT (VOUT ≥ 16.5V), or
an overtemperature event (TSD is invoked when the die
RECTIFIER A
CURRENT temperature exceeds 170°C). Upon removal of these fault
conditions, the LTC3124 will soft-start the output voltage.
RECTIFIER B
CURRENT Error Amplifier
OUTPUT The noninverting input of the transconductance error
RIPPLE
CURRENT
amplifier is internally connected to the 1.2V reference and
the inverting input is connected to FB. An external resistive
3124 F03

Figure 3. Simplified Voltage and Current Waveforms

voltage divider from VOUT to SGND programs the output
for 2-Phase Operation at 25% Duty Cycle voltage from 2.5V to 15V via FB as shown in Figure 4.
 R1
VOUT = 1.2V  1+ 
 R2 
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LTC3124
OPERATION
Selecting an R2 value of 113k to have approximately Thus RT (kΩ) ≅ 28/f (MHz). See Table 1 for various switch-
10µA of bias current in the VOUT resistor divider yields ing frequencies and their corresponding RT values.
the formula:
Table 1. Switching Frequency and Their Respective RT
R1 = 94 • (VOUT – 1.2V); VOUT in Volts and R1 in kΩ. SWITCHING
FREQUENCY (kHz) RT (kΩ)
Power converter control loop compensation is set with
100 316
a simple RC network connected between VC and SGND.
200 154
VOUT 300 100
LTC3124
500 57.6
R1
– FB 800 34.8
+ 1000 28
1.2V R2
1200 22.6
3124 F04 2000 13
Figure 4. Programming the Output Voltage 2200 11.5
3000 8.06
Internal Current Limit For desired switching frequencies not included in Table 1,
Current limit comparators shut off the N-channel MOSFET please refer to the Resistance vs Frequency curve in the
switches once their respective peak current is reached. Typical Performance Characteristics section.
Peak switch current per phase is limited to 3.5A, inde-
pendent of input or output voltage, unless VOUT is below The oscillator can be synchronized to an external frequency
approximately 1.5V, resulting in the current limit being by applying a pulse train of twice the desired switching
approximately half of the nominal peak values. frequency to the PWM/SYNC pin. An external resistor
must be connected between RT and SGND to program the
Lossless current sensing converts the peak current signals oscillator to a frequency approximately 25% below that of
of the N-channel MOSFET switches into voltages that are the externally applied pulse train used for synchronization.
summed with their respective internal slope compensation. The RT is selected in this case according to this formula:
summed signals are compared to the error amplifier outputs
to provide a peak current control command for the PWMs. RT(SYNC) (kΩ) ≥ 1.25 • RT(SWITCH) (kΩ)
where RT(SWITCH) is the value of RT at the desired switching
Zero Current Comparator
frequency, which is half of the synchronization frequency.
The zero current comparators monitor the inductor currents
being delivered to the output and shut off the synchronous Shutdown
rectifiers when the current is approximately 50mA. This The boost converter is disabled by pulling SD below 0.25V
prevents the inductor currents from reversing in polarity, and enabled by pulling SD above 1.6V. Note that SD can
improving efficiency at light loads. be driven above VIN or VOUT, as long as it is limited to less
than its absolute maximum rating.
Oscillator
The internal oscillator is programmed to twice the desired Thermal Shutdown
switching frequency with an external resistor from the RT If the die temperature exceeds 170°C typical, the LTC3124
pin to SGND according to the following formula: will go into thermal shutdown (TSD). All switches will be
 56  shut off until the die temperature drops by approximately
fOSC (MHz) ≅  = 2 • f (MHz) 7°C, when the device re-initiates a soft-start and switching
 R T (kΩ) 
is re-enabled.
where f = switching frequency of one phase.
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 LTC3124
OPERATION
Boost Anti-Ringing Control Output Disconnect
When VOUT ≥ VIN + 2V, the anti-ringing circuitry connects a The LTC3124’s output disconnect feature eliminates body
resistor across each inductor to VIN to damp high frequency diode conduction of the internal P-channel MOSFET recti-
ringing on the SW pins during discontinuous current mode fiers. This feature allows for VOUT to discharge to 0V during
operation. Although the ringing of the resonant circuits shutdown, and draw no current from the input source.
formed by the inductors and CSW(A/B) (capacitance on Inrush current will also be limited at turn-on, minimizing
the respective SW pins) is low energy, it can cause EMI surge currents seen by the input supply. Note that to obtain
radiation if not damped. the advantages of output disconnect, there must not be
an external Schottky diode connected between SWA, SWB
VCC Regulator and VOUT. The output disconnect feature also allows VOUT
An internal low dropout regulator generates the 4.25V to be pulled high, without backfeeding the power source
(nominal) VCC rail from VIN or VOUT, depending upon connected to VIN.
operating conditions. VCC is supplied from VIN if VIN is
VIN > VOUT Operation
initially greater than approximately 3.5V, with VIN continuing
to supply VCC down to approximately 3V; otherwise the The LTC3124 step-up converter will maintain voltage
greater of VIN and VOUT supplies VCC. The VCC rail powers regulation even when the input voltage is above the desired
the internal control circuitry and power MOSFET gate drivers output voltage. Note that operating in this mode will exhibit
of the LTC3124. The VCC regulator is disabled in shutdown lower efficiency and a reduced output current capability.
to reduce quiescent current and is enabled by forcing the Refer to the Typical Performance Characteristics for details.
SD pin above its input high threshold. A 4.7µF or larger
capacitor must be connected between VCC and SGND. Burst Mode OPERATION
Overvoltage Lockout When the PWM/SYNC pin is held low, the boost converter
operates in Burst Mode, independent of load current. This
An overvoltage condition occurs when VOUT exceeds
mode of operation is typically commanded to improve
approximately 16.5V. Switching is disabled and the in-
efficiency at light loads and reduce standby current at no
ternal soft-start ramp is reset. Once VOUT drops below
load. The output current (IOUT) capability in Burst Mode
approximately 16V a soft-start is initiated and switching operation is significantly less than in PWM mode and
is allowed to resume. If the boost converter output is varies with VIN and VOUT, as shown in Figure 5. The logic
lightly loaded such that the time constant of the output input thresholds for this pin are determined relative to VCC
capacitance, COUT, and the output load resistance, ROUT with a low being less than 10% of VCC and a high being
is near or greater than the soft-start time of approximately greater than 90% of VCC. The LTC3124 will operate in
10ms, the soft-start ramp may end before or soon after fixed frequency PWM mode even if Burst Mode operation
switching resumes, defeating the inrush current limiting of is commanded during soft-start.
the closed-loop soft-start following an overvoltage event.
In Burst Mode operation, only Phase A of the LTC3124
Short-Circuit Protection is operational, while Phase B is disabled. The Phase A
inductor current is initially charged to approximately
The LTC3124 output disconnect feature allows output
700mA by turning on the N-channel MOSFET switch, at
short-circuit protection while maintaining a maximum set
which point the N-channel switch is turned off and the
current limit. To reduce power dissipation under overload
P-channel synchronous switch is turned on, delivering
and short-circuit conditions, the peak switch current limits
current to the output. When the inductor current discharges
are reduced to approximately 2A. Once VOUT exceeds
approximately 1.5V, the current limits are reset to their to approximately zero, the cycle repeats. In Burst Mode
nominal values of 3.5A per phase. operation, energy is delivered to the output until the nominal
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LTC3124
OPERATION
400 regulation value is reached, then the LTC3124 transitions
350 into a very low quiescent current sleep state. In sleep, the
300
output switches are turned off and the LTC3124 consumes
OUTPUT CURRENT (mA)

only 25μA of quiescent current. When the output volt-

250
age droops approximately 1%, switching resumes. This
200
maximizes efficiency at very light loads by minimizing
150 switching and quiescent losses. Output voltage ripple in
100 Burst Mode operation is typically 1% to 2% peak-to-peak.
50 Additional output capacitance (22μF or greater), or the
0
addition of a small feedforward capacitor (10pF to 50pF)
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 connected between VOUT and FB can help further reduce
VIN, FALLING (V) 3124 F05
the output ripple.
VOUT = 2.5V VOUT = 12V
VOUT = 5V VOUT = 15V
VOUT = 7.5V

Figure 5. Burst Mode Output Current vs VIN

APPLICATIONS INFORMATION
PCB LAYOUT CONSIDERATIONS 3. PGNDA pin, PGNDB pin, and the exposed pad are the
power ground connections for the LTC3124. Multiple
The LTC3124 switches currents as high as 4.5A at high vias should connect the back pad directly to the ground
frequencies. Special attention should be paid to the PCB plane. In addition, maximization of the metallization
layout to ensure a stable, noise-free and efficient application connected to the back pad will improve the thermal
circuit. Figure 6 presents the LTC3124’s 4-layer PCB demo environment and improve the power handling capabili-
board layout (the schematic of which may be obtained ties of the IC.
from the Quick Start Guide) to outline some of the primary
considerations. A few key guidelines are outlined below: 4. The high current components and their connections
should all be placed over a complete ground plane to
1. A 4-layer board is highly recommended for the LTC3124 minimize loop cross-sectional areas. This minimizes
to ensure stable performance over the full operating EMI and reduces inductive drops.
voltage and current range. A dedicated/solid ground
plane should be placed directly under the VIN, VOUTA, 5. Connections to all of the high current components
VOUTB, SWA, and SWB traces to provide a mirror plane should be made as wide as possible to reduce the
to minimize noise loops from high dI/dt and dV/dt series resistance. This will improve efficiency and
edges (see Figure 6, 2nd layer). maximize the output current capability of the boost
converter.
2. All circulating high current paths should be kept as
short as possible. Capacitor ground connections 6. To prevent large circulating currents from disrupting
should via down to the ground plane in the shortest the converters’ output voltage sensing, compensation,
route possible. The bypass capacitors on VIN should be and programmed switching frequency, the ground for
placed as close to the IC as possible and should have the resistor divider, compensation components, and
the shortest possible paths to ground (see Figure 6, RT should be returned to the ground plane using a
top layer). via placed close to the IC and away from the power
connections.

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 LTC3124
APPLICATIONS INFORMATION
7. Keep the connections from the resistor divider to the 8. Crossover connections should be made on inner cop-
FB pin and from the compensation components to the per layers if available. If it is necessary to place these
VC pin as short as possible and away from the switch on the ground plane, make the trace on the ground
pin connections. plane as short as possible to minimize the disruption
to the ground plane (see Figure 6, 3rd layer).
Top Layer 2nd Layer

3rd Layer Bottom Layer (Top View)

Figure 6. Example PCB Layout

3124f

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LTC3124
APPLICATIONS INFORMATION
SCHOTTKY DIODE windings) to reduce the I2R power losses, and must be
able to support the peak inductor current without saturat-
Although it is not required, adding a Schottky diode from
ing. Molded chokes and most chip inductors usually do
both SW pins to VOUT can improve the converter efficiency
not have enough core area to support the peak inductor
by up to 4%. Note that this defeats the output disconnect
currents of 3A to 4A seen on the LTC3124. To minimize
and short-circuit protection features of the LTC3124.
radiated noise, use a shielded inductor.

COMPONENT SELECTION See Table 2 for suggested components and suppliers.

Inductor Selection Table 2. Recommended Inductors

VALUE DCR ISAT SIZE (mm)
The LTC3124 can utilize small inductors due to its capa- PART NUMBER (µH) (mΩ) (A) W×L×H
bility of setting a fast (up to 3MHz) switching frequency. Coilcraft XFL4020-102ME 1 12 5.4 4.3 × 4.3 × 2.1
Larger values of inductance will allow slightly greater Coilcraft MSS7341T-332NL 3.3 18 3.7 7.3 × 7.3 × 4.1
Coilcraft XAL5030-332ME 3.3 23 8.7 5.3 × 5.3 × 3.1
output current capability by reducing the inductor ripple Coilcraft XAL5030-472ME 4.7 36 6.7 5.3 × 5.3 × 3.1
current. To design a stable converter the range of induc- Coilcraft XAL5050-562ME 5.6 26 6.3 5.3 × 5.3 × 5.1
tance values is bounded by the targeted magnitude of the Coilcraft XAL6060-223ME 22 61 5.6 6.3 × 6.3 × 6.1
Coilcraft MSS1260T-333ML 33 57 4.34 12.3 × 12.3 × 6.2
internal slope compensation and is inversely proportional
Coiltronics SD53-1R1-R 1.1 20 4.8 5.2 × 5.2 × 3
to the switching frequency. The Inductor selection for the Coiltronics DR74-4R7-R 4.7 25 4.37 7.6 × 7.6 × 4.35
LTC3124 has the following bounds: Coiltronics DR125-330-R 33 51 3.84 12.5 × 12.5 × 6
Coiltronics DR127-470-R 47 72 5.28 12.5 × 12.5 × 8
10 3 Sumida CDR7D28MNNP-1R2NC 1.2 21 5.9 7.6 × 7.6 × 3
µH >L > µH
f f Sumida CDMC6D28NP-3R3MC 3.3 31 5 7.25 × 6.7 × 3
Taiyo-Yuden NR5040T3R3N 3.3 35 3.8 5×5×4
The inductor peak-to-peak ripple current is given by the TDK LTF5022T-1R2N4R2-LC 1.2 25 4.3 5 × 5.2 × 2.2
following equation: TDK SPM6530T-3R3M 3.3 30 6.8 7.1 × 6.5 × 3
TDK VLP8040T-4R7M 4.7 25 4.4 8 × 7.7 × 4
VIN • ( VOUT – VIN ) Würth WE-LHMI 74437324010 1 27 9 4.45 × 4.06 × 1.8
Ripple ( A ) = Würth WE-PD 7447789002 2.2 20 4.8 7.3 × 7.3 × 3.2
f •L • VOUT
Würth WE-PD 7447779002 2.2 20 6 7.3 × 7.3 × 4.5
Würth WE-PD 7447789003 3.3 30 4.2 7.3 × 7.3 × 3.2
where: Würth WE-PD 7447789004 4.7 35 3.9 7.3 × 7.3 × 3.2
Würth WE-HCI 7443251000 10 16 8.5 10 × 10 × 5
L = Inductor Value in μH Würth WE-PD 744770122 22 43 5 12 × 12 × 8
Würth WE-PD 744770133 33 64 3.6 12 × 12 × 8
f = Switching Frequency in MHz of One Phase Würth WE-PD 7447709470 47 60 4.5 12 × 12 × 10

The inductor ripple current is a maximum at the minimum

inductor value. Substituting 3/f for the inductor value in Output and Input Capacitor Selection
the above equation yields the following:
Low ESR (equivalent series resistance) capacitors should
VIN • ( VOUT – VIN ) be used to minimize the output voltage ripple. Multilayer
RippleMAX ( A ) = ceramic capacitors are an excellent choice as they have
3 • VOUT
extremely low ESR and are available in small footprints.
A reasonable operating range for the inductor ripple cur- X5R and X7R dielectric materials are preferred for their
rent is typically 10% to 40% of the maximum inductor ability to maintain capacitance over wide voltage and tem-
current. High frequency ferrite core inductor materials perature ranges. Y5V types should not be used. Although
reduce frequency dependent power losses compared to ceramic capacitors are recommended, low ESR tantalum
cheaper powdered iron types, improving efficiency. The capacitors may be used as well.
inductor should have low DCR (series resistance of the
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16 For more information www.linear.com/LTC3124

 LTC3124
APPLICATIONS INFORMATION
When selecting output capacitors, the magnitude of the Table 3: Representative Output Capacitors
peak inductor current, together with the ripple voltage Manufacturer, Value Voltage SIZE L × W × H (mm)
specification, determine the choice of the capacitor. Both Part Number (µF) (V) Type, ESR (mΩ)
the ESR (equivalent series resistance) of the capacitor and AVX, 22 16 3.2 × 1.6 × 1.78,
1206YD226KAT2A X5R Ceramic
the charge stored in the capacitor each cycle contribute
AVX, 22 16 3.2 × 2.5 × 2.79,
to the output voltage ripple. 1210YC226KAT2A X7R Ceramic
The peak-to-peak ripple due to the charge is approximately: Murata, 22 16 3.2 × 1.6 × 1.8,
GRM31CR61C226ME15L X5R Ceramic
IP • VIN Murata, 22 16 3.2 × 2.5 × 2.7,
VRIPPLE(CHARGE) (V) ≈ GRM32ER71C226KE18K X7R Ceramic
COUT • VOUT • f • 2
Murata, 22 16 4.5 × 3.2 × 2.7,
where: GRM43ER61C226KE01L X5R Ceramic
Murata, 47 16 3.2 × 2.5 × 2.5,
IP = Peak inductor current GRM32EB31C476ME15K X5R Ceramic
f = Switching frequency of one phase Panasonic, 22 16 3.2 × 2.5 × 2.7,
ECJ-4YB1C226M X5R Ceramic
The ESR of COUT is usually the most dominant factor for Taiyo Yuden, 22 16 3.2 × 1.6 × 1.8,
ripple in most power converters. The peak-to-peak ripple EMK316BJ226ML-T X5R Ceramic
due to the capacitor ESR is: Taiyo Yuden, 22 16 3.2 × 2.5 × 2.7,
EMK325B7226MM-TR X7R Ceramic
VOUT Taiyo Yuden, 22 16 4.5 × 3.2 × 2.7,
VRIPPLE(ESR)(V) =ILOAD • RESR • EMK432BJ226KM-T X5R Ceramic
VIN
TDK, 47 16 5.7 × 5 × 2.5,
where RESR = capacitor equivalent series resistance. C5750X7R1C476M X7R Ceramic
TDK, 100 6.3 4.5 × 3.2 × 2.8,
The input filter capacitor reduces peak currents drawn C4532X5R0J107M X5R Ceramic
from the input source and reduces input switching noise. Nichicon, 100 16 8.3 × 8.3 × 11.5,
A low ESR bypass capacitor with a minimum value of 10µF UBC1C101MNS1GS Aluminum Polymer
should be located as close to VIN as possible. Sanyo, 22 25 7.3 x 4.3 x 1.9,
25TQC22MV POSCAP, 45mΩ
Low ESR and high capacitance are critical to maintain low Sanyo, 47 16 7.3 × 4.3 × 3.1,
output ripple. Capacitors can be used in parallel for even 16TQC47MW POSCAP, 40mΩ
larger capacitance values and lower effective ESR. Ceramic Sanyo, 100 16 7.3 × 4.3 × 3.1,
16TQC100M POSCAP, 50mΩ
capacitors are often utilized in switching converter appli-
Sanyo, 47 25 6.6 × 6.6 × 5.9,
cations due to their small size, low ESR and low leakage 25SVPF47M OS-CON, 30mΩ
currents. However, many ceramic capacitors experience AVX, BestCap Series 1F 5.5 48 × 30 × 6.1,
significant loss in capacitance from their rated value with BZ125A105ZLB 35mΩ, 4 Lead
increased DC bias voltage. It is not uncommon for a small Cap-XX GS230F 1.2F 4.5 39 × 17 × 3.8, 28mΩ
surface mount capacitor to lose more than 50% of its rated Tecate Powerburst 100F 2.7 D = 22, H = 45
TPL-100/22X45 15mΩ
capacitance when operated near its rated voltage. As a
Cooper KR-5R5C155-R 1.5F 5.5 D = 21.5, H = 7.5
result it is sometimes necessary to use a larger capaci- 30mΩ
tor value or a capacitor with a larger value and case size, Cooper 110F 2.5 D = 18.5, H = 60
such as 1812 rather than 1206, in order to actually realize HB1860-2R5117-R 20mΩ
the intended capacitance at the full operating voltage. Be Maxwell 50F 2.5 D = 18, H = 40
BCAP0050-P270 20 mΩ
sure to consult the vendor’s curve of capacitance versus
DC bias voltage. Table 3 shows a sampling of capacitors
suited for the LTC3124 applications.

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LTC3124
APPLICATIONS INFORMATION
For applications requiring a very low profile and very large Thermal Considerations
capacitance, the GS, GS2 and GW series from Cap-XX, For the LTC3124 to deliver its full power, it is imperative
the BestCap series from AVX and PowerStor KR series that a good thermal path be provided to dissipate the
capacitors from Cooper all offer very high capacitance heat generated within the package. This can be accom-
and low ESR in various low profile packages. plished by taking advantage of the large thermal pad on
the underside of the IC. It is recommended that multiple
OPERATING FREQUENCY SELECTION vias in the printed circuit board be used to conduct heat
There are several considerations in selecting the operating away from the IC and into a copper plane with as much
frequency of the converter. Typically, the first consideration area as possible. If the junction temperature rises above
is to stay clear of sensitive frequency bands, which can- ~170°C, the part will trip an internal thermal shutdown,
not tolerate any spectral noise. For example, in products and all switching will stop until the junction temperature
incorporating RF communications, the 455kHz IF frequency drops ~7°C.
can be sensitive to any noise, therefore switching above
Compensating the Feedback Loop
600kHz is desired. Some communications have sensitivity
to 1.1MHz and in that case a 1.5MHz switching converter The LTC3124 uses current mode control, with internal
frequency may be employed. A second consideration is the adaptive slope compensation. Current mode control elimi-
physical size of the converter. As the operating frequency nates the second order filter due to the inductor and output
is increased, the inductor and filter capacitors typically capacitor exhibited in voltage mode control, and simplifies
can be reduced in value, leading to smaller sized external the power loop to a single pole filter response. Because
components. The smaller solution size is typically traded of this fast current control loop, the power stage of the IC
for efficiency, since the switching losses due to gate charge combined with the external inductor can be modeled by a
increase with frequency. transconductance amplifier gmp and a current controlled
current source. Figure 7 shows the key equivalent small
Another consideration is whether the application can allow
signal elements of a boost converter.
pulse-skipping. When the boost converter pulse-skips, the
minimum on-time of the converter is unable to support The DC small-signal loop gain of the system shown in
the duty cycle. This results in a low frequency component Figure 7 is given by the following equation:
to the output ripple. In many applications where physical R2
size is the main criterion, running the converter in this GBOOST = GEA •GMP •GPOWER •
R1+R2
mode is acceptable. In applications where it is preferred
not to enter this mode, the maximum operating frequency where GEA is the DC gain of the error amplifier, GMP is
is given by: the modulator gain, and GPOWER is the inductor current
to VOUT gain.
VOUT – VIN
f MAX _ NOSKIP < ≅ Hz GEA = gma • RO ≈ 1000V/V
VOUT • tON(MIN)

(Not Adjustable; gma ≈ 100µS, RO ≈ 10MΩ)
where tON(MIN) = minimum on-time, which is typically
∆IL
around 100ns. GMP = 2 • gmp ; gmp = ≈ 3.4S (Not Adjustable )
∆VC
∆VOUT η• VIN η• VIN •RL
GPOWER = = =
∆IL 2 •IOUT 2 • VOUT

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 LTC3124
APPLICATIONS INFORMATION
– MODULATOR
VOUT 1
+gmp Phase Lead Zero: Z4 = Hz
IL
η • VIN
•I
2 • VOUT L RESR 2π • (R1+RPL ) •CPL
RL
COUT 1
1.2V Phase Lead Pole: P4 = Hz
ERROR
REFERENCE
RPL
 R1•R2 
AMPLIFIER
2π •  +RPL  •CPL
VC + CPL R1  R1+R2 
gma FB
RC
–
CF RO R2 Error Amplifier Filter Pole:
CC CC: COMPENSATION CAPACITOR
RC: COMPENSATION RESISTOR 3124 F07 1 CC
CF: HIGH FREQUENCY FILTER CAPACITOR P5 = Hz, CF <
CPL: PHASE LEAD CAPACITOR CC •CF 10
RPL: PHASE LEAD RESISTOR 2π •RC •
gma: TRANSCONDUCTANCE AMPLIFIER INSIDE IC CC +CF
RO: OUTPUT RESISTANCE OF gma
gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER 1
COUT: OUTPUT CAPACITOR ≈ Hz
RESR: OUTPUT CAPACITOR ESR
RL: OUTPUT RESISTANCE DEFINED AS VOUT/ILOAD(MAX) 2π •RC •CF
R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK
η: CONVERSION EFFICIENCY (~90% AT HIGHER CURRENTS)
The current mode zero (Z3) is a right-half plane zero
Figure 7. Boost Converter Equivalent Model which can be an issue in feedback control design, but is
manageable with proper external component selection.
Combining the two equations above yields: Also note that the RHP zero is a minimum at minimum
3.4 • η• VIN •RL input voltage and maximum output current for a given
GDC = GMP •GPOWER ≈ V/V output voltage. As a general rule, the frequency at which
VOUT the open-loop gain of the converter is reduced to unity,
known as the crossover frequency fC , should be set to
Converter efficiency η will vary with IOUT and switching
less than one-sixth of the right-half plane zero (Z3), and
frequency fSWITCH as shown in the typical performance
under one-eighth of the switching frequency fSWITCH. Once
characteristics curves.
fC is selected, the compensation component values can
2 be calculated using a Bode plot of the power stage or two
Output Pole: P1 = Hz
2π •RL •COUT generally valid assumptions: P1 dominates the gain of the
Error Amplifier Pole: power stage for frequencies lower than fC and fC is much
higher than P2. First calculate the power stage gain at fC,
1 C GfC in V/V. Assuming the output pole P1 dominates GfC
P2 = Hz; CF < C
2π •RO • (CC +CF ) 10 for this range, it is expressed by:
1 GDC
≈ Hz; ExtremelyClose toDC G fC ≈ V/V
2π •RO •CC 2
f 
1 1+  C 
Error Amplifier Zero: Z1 = Hz  P1

2π •RC •CC
1
ESR Zero: Z2 = Hz
2π •RESR •COUT
VIN 2 • 2RL
RHP Zero: Z3 = Hz
2π • VOUT 2 •L
fOSC
High Frequency Pole: P3 > Hz
3
3124f

For more information www.linear.com/LTC3124 19

LTC3124
APPLICATIONS INFORMATION
Decide how much phase margin (Φm) is desired. Greater the transfer function of the converter. The values of these
phase margin can offer more stability while lower phase mar- phase lead components are given by the expressions:
gin can yield faster transient response. Typically, Φm ≈ 60°
 R1• R2 
is optimal for minimizing transient response time while R1− a2 • 
 R1+ R2 
allowing sufficient margin to account for component RPL = kΩ and
variability. Φ1 is the phase boost of Z1, P2, and P5 while a2 − 1
Φ2 is the phase boost of Z4 and P4. Select Φ1 and Φ2 106 ( a2 − 1) (R1+ R2)
such that: CPL = pF
2π • ƒC • R12 a2
ƒC 
1
Φ1 + Φ 2 = Φm + tan−   and
Z3 where R1, R2, and RPL are in kΩ and ƒC is in kHz.
 V  Note that selecting Φ2 = 0° forces a2 = 1, and so the
Φ1 ≤ 74° ; Φ 2 ≤  2 • tan−1 OUT  − 90° converter will have Type II compensation and therefore
 1.2V 
no feedforward: RPL is open (infinite impedance) and CPL
where VOUT is in V and ƒC and Z3 are in kHz. = 0pF. If a2 = 0.833 • VOUT (its maximum), feedforward is
maximized; RPL = 0 and CPL is maximized for this com-
Setting Z1, P5, Z4, and P4 such that pensation method.
ƒC ƒ
Z1= , P5 = ƒC a1, Z4 = C , P4 = ƒC a2 Once the compensation values have been calculated, ob-
a1 a2 taining a converter bode plot is strongly recommended to
allows a1 and a2 to be determined using Φ1 and Φ2 verify calculations and adjust values as required.
Using the circuit in Figure 8 as an example, Table 4 shows
 Φ + 90°   Φ + 90° 
a1 = tan2  1  , a2 = tan2  2  the parameters used to generate the Bode plot shown in
 2   2
Figure 9.
The compensation will force the converter gain GBOOST Table 4. Bode Plot Parameters
to unity at ƒC by using the following expression for CC: PARAMETER VALUE UNITS COMMENT

103 • g ma • R2 • GƒC ( a1 − 1) a2
VIN 5 V App Specific
CC = pF VOUT 12 V App Specific
2π • ƒC • (R1+ R2) a1 RL 8 Ω App Specific
COUT at No Bias 22 × 2 µF App Specific
(gma in µS, ƒC in kHz, GƒC in V/V) COUT at 12V Bias 14 × 2 µF App Specific
RESR 2.5 mΩ App Specific
Once CC is calculated, RC and CF are determined by:
LA, LB 4.7 µH App Specific
106 • a1 fSWITCH 1 MHz Adjustable
RC = kΩ (ƒC in kHz, C C in pF) R1 1020 kΩ Adjustable
2π • ƒC • CC
R2 113 kΩ Adjustable
CC gma 100 µS Fixed
CF =
a1 − 1 RO 10 MΩ Fixed
gmp 3.4 S Fixed
A method for improving the converter’s transient response η 90 % App Specific
uses a small feedforward series network of a capacitor and RC 84.5 kΩ Adjustable
a resistor across the top resistor of the feedback divider CC 680 pF Adjustable
(from VOUT to FB). This adds a phase-lead zero and pole to CF 56 pF Adjustable
RPL Open kΩ Optional
CPL 0 pF Optional
3124f

20 For more information www.linear.com/LTC3124

 LTC3124
APPLICATIONS INFORMATION
Switching Waveforms with 1.5A Load
LB
4.7µH VOUT
VIN 20mV/DIV
SWB CAP C1 INDUCTOR B
5V VOUT AC-COUPLED
100nF CURRENT
LA PGNDB VOUTB 12V
4.7µH COUT 1A/DIV
1.5A VSWB
SWA VOUTA 22µF
10V/DIV
LTC3124 ×2
INDUCTOR A
PGNDA
CURRENT
VSWA 1A/DIV
VIN SGND
10V/DIV
R1
BURST PWM PWM/SYNC SD OFF ON 1.02M
200ns/DIV 3124 F08b

CIN VCC FB
10µF RT VC R2
113k
RC Transient Response with 700mA to 1.5A Load Step
CVCC RT 84.5k
CC CF
4.7µF 28k VOUT
680pF 56pF
500mV/DIV
C1: 100nF, 16V, X5R, 0805 3124 F08 AC-COUPLED
CIN: 10µF, 10V, X5R, 1206
COUT: 22µF ×2, 16V, X5R, 1210
CVCC: 4.7µF, 10V, X5R, 1206
LA, LB: COILCRAFT XAL5030-472ME
1500mA
OUTPUT
Figure 8. 1MHz, 5V to 12V, 1.5A Boost Converter CURRENT
700mA 700mA
500mA/DIV

100µs/DIV 3124 F08c

45 90

30 45

PHASE
15 0
PHASE (DEG)

GAIN
GAIN (dB)

0 –45

–15 –90

–30 –135

–45 –180
100 1k 10k 100k
FREQUENCY (Hz)
3124 F09

Figure 9. Bode Plot for Example Converter

3124f

For more information www.linear.com/LTC3124 21

LTC3124
APPLICATIONS INFORMATION
From Figure 9, the phase is ~60° when the gain reaches LB
4.7µH
0dB, so the phase margin of the converter is ~60°. The VIN SWB CAP C1
5V VOUT
crossover frequency is ~10kHz, which is more than six LA PGNDB VOUTB
100nF
12V
times lower than the 94kHz frequency of the RHP zero to 4.7µH
SWA VOUTA
COUT
22µF
1.5A

achieve adequate phase margin. LTC3124 ×2

PGNDA
The circuit in Figure 10 shows the same application as VIN SGND
RPL
787k
that in Figure 8 with Type III compensation. This is ac- CPL R1
BURST PWM PWM/SYNC SD OFF ON
complished by adding CPL and RPL and adjusting CC, CF, CIN VCC FB
12pF 1.02M

and RC accordingly. Table 5 shows the parameters used 10µF RT VC R2

113k
RC
to generate the bode plot shown in Figure 11. CVCC RT 71.5k
CC CF
4.7µF 28k
470pF 120pF
From Figure 11, the phase margin is still optimized at ~60°
and the crossover frequency remains ~10kHz. Adding CPL C1: 100nF, 16V, X5R, 0805
CIN: 10µF, 10V, X5R, 1206
3124 F10

and RPL provides some feedforward signal in Burst Mode COUT: 22µF ×2, 16V, X5R, 1210
CVCC: 4.7µF, 10V, X5R, 1206
operation, leading to lower output voltage ripple. LA, LB: COILCRAFT XAL5030-472ME

Figure 10. Boost Converter with Phase Lead

Table 5. Bode Plot Parameters
PARAMETER VALUE UNITS COMMENT
VIN 5 V App Specific 45 90

VOUT 12 V App Specific

30 45
RL 8 Ω App Specific
PHASE
COUT at No Bias 22 × 2 µF App Specific 15 0
COUT at 12V Bias 14 × 2 µF App Specific

PHASE (DEG)
GAIN
GAIN (dB)

RESR 2.5 mΩ App Specific 0 –45

LA, LB 4.7 µH App Specific
–15 –90
fSWITCH 1 MHz Adjustable
R1 113 kΩ Adjustable –30 –135
R2 1020 kΩ Adjustable
gma 100 µS Fixed –45 –180
100 1k 10k 100k
RO 10 MΩ Fixed FREQUENCY (Hz)
gmp 3.4 S Fixed 3124 F11

η 90 % App Specific Figure 11. Bode Plot Showing Phase Lead

RC 71.5 kΩ Adjustable
CC 470 pF Adjustable
CF 120 pF Adjustable
RPL 787 kΩ Adjustable
CPL 12 pF Adjustable

3124f

22 For more information www.linear.com/LTC3124

 LTC3124
TYPICAL APPLICATIONS
Single Li Cell to 6V, 9W, 2.2MHz Synchronous Boost Converter Load Step
for RF Transmitter
VOUT
LB 500mV/DIV
2.2µH AC-COUPLED
VIN SWB CAP
2.7V TO 4.2V C1 1.5A
VOUT
100nF
LA PGNDB VOUTB 6V
COUT OUTPUT
2.2µH 1.5A
47µF CURRENT
SWA VOUTA 500mA/DIV
×2 150mA 150mA
LTC3124
PGNDA

VIN SGND VIN = 3.6V 100µs/DIV 3124 TA02b

R1
PWM/SYNC SD OFF ON 1.13M
CIN VCC FB
10µF RT VC R2 Bode Plot
CVCC RC 280k
CF 50 120
4.7µF RT 60.4k
CC 68pF 40 90
11.5k
1.2nF
30 60
PHASE
C1: 100nF, 16V, X5R, 0805 3124 TA02a
20 30
CIN: 10µF, 10V, X5R, 1206

PHASE (DEG)
COUT: 47µF × 2, 16V, X5R, 1210 10 0

GAIN (dB)
CVCC: 4.7µF, 10V, X5R, 1206 GAIN
LA, LB: WÜRTH WE-PD 7447779002 0 –30
–10 –60
–20 –90
–30 –120
–40 –150
–50 –180
100 1k 10k 100k
FREQUENCY (Hz)
3124 TA02c

2-Port USB-Powered 1MHz Synchronous Boost Converter to 5V, 500mA

LB
3.3µH
VIN SWB CAP
4.3V TO 5.5V C1
VOUT
LA PGNDB VOUTB
100nF
5V
2-Port USB 2.0 Hot Plugged
3.3µH COUT 500mA
SWA VOUTA 100µF
LTC3124 ×2 VIN
2V/DIV
PGNDA

VIN SGND VOUT

R1 2V/DIV
PWM/SYNC SD OFF ON 1.47M
VCC FB INPUT
C2 CIN CURRENT
10µF 10µF RT VC R2
464k 500mA/DIV
CVCC RC
4.7µF RT 35.7k CF
CC 270pF RLOAD = 10Ω 2ms/DIV 3124 TA03b
28k
2.7nF VIN = USB 2.0
2-PORT HOT PLUGGED
C1: 100nF, 16V, X5R, 0805 3124 TA03a
C2: KEMET T491C106K025AS
CIN: 10µF, 10V, X5R, 1206
COUT: 100µF × 2, 6.3V, X5R, 1812
CVCC: 4.7µF, 10V, X5R, 1206
LA, LB: COILCRAFT XAL5030-332ME

3124f

For more information www.linear.com/LTC3124 23

LTC3124
TYPICAL APPLICATIONS
3.3V to 12V, 300kHz Synchronous Boost Converter
with Output Disconnect, 1A

LB Efficiency
22µH
VIN SWB CAP 100
3.3V C1
VOUT Burst Mode
100nF 90
LA PGNDB VOUTB 12V OPERATION
22µH COUT 1A
47µF 80
SWA VOUTA
LTC3124 ×3 70

EFFICIENCY (%)
PGNDA
60
PWM
VIN SGND 50
R1 40
BURST PWM PWM/SYNC SD OFF ON 1.02M
VCC FB 30
CIN
R2 VCC DERIVED
10µF RT VC 20
RC 113k FROM VIN
CVCC
76.8k CF 10 VCC DERIVED
4.7µF RT 270pF FROM VOUT
100k CC
0
3.9nF 0.01 0.1 1 10 100 1000
C1: 100nF, 16V, X5R, 0805 3124 TA04a LOAD CURRENT (mA)
CIN: 10µF, 10V, X5R, 1206 3124 TA04b
COUT: 47µF × 3, 16V, X5R, 1210
CVCC: 4.7µF, 10V, X5R, 1206
LA, LB: WÜRTH WE-PDF 7447998221

Single Li Cell to 5V, 1.8A Synchronized 1.2MHz Switching Boost

Converter for RFPA Power Supply

LB Efficiency
3.3µH
VIN SWB CAP 100
2.7V TO 4.2V C1
VOUT
100nF 90 Burst Mode
LA PGNDB VOUTB 5V
3.3µH COUT 1.8A OPERATION
80
SWA VOUTA 22µF
LTC3124 ×2 70
EFFICIENCY (%)

PGNDA 60
PWM
VIN SGND 50
2.4MHz SYNC PULSE
R1 40
PWM/SYNC SD OFF ON 1.47M
VCC FB 30
CIN
10µF RT VC R2 20
RC 464k 4.2VIN
CVCC
31.6k 10 3.3VIN
4.7µF RT 2.7VIN
28.7k CF CC 0
150pF 1.5nF 0.01 0.1 1 10 100 1000
C1: 100nF, 16V, X7R, 0805 3124 TA05a
LOAD CURRENT (mA)
CIN: 10µF, 10V, X7R, 1206 3124 TA05b

COUT: 22µF × 2, 16V, X7R, 1210

CVCC: 4.7µF, 10V, X7R, 1206
LA, LB: COILCRAFT MSS7341T-332NL

3124f

24 For more information www.linear.com/LTC3124

 LTC3124
TYPICAL APPLICATIONS
1.8V to 5.5V Input to 15V Output, 500kHz Synchronous Boost
Converter with Output Disconnect, 300mA
LB
Efficiency
10µH
VIN SWB CAP 100
1.8V TO 5.5V C1 OUTPUT CURRENT = 300mA
VOUT
100nF
LA PGNDB VOUTB 15V
10µH COUT 300mA 95
SWA VOUTA 22µF
LTC3124 ×2

EFFICIENCY (%)
PGNDA 90

VIN SGND
R1 85
PWM/SYNC SD OFF ON 1.3M
CIN VCC FB
10µF RT VC R2 80
CVCC RC 113k
4.7µF 49.9k CF
RT 100pF
57.6k CC 75
3.3nF 1.5 2 2.5 3 3.5 4 4.5 5 5.5
C1: 100nF, 16V, X7R, 0805 VIN (V)
3124 TA06a
CIN: 10µF, 10V, X7R, 1206 3124 TA06b

COUT: 22µF × 2, 16V, X7R, 1210

CVCC: 4.7µF, 10V, X7R, 1206
LA, LB: WÜRTH WE-HCI 7443251000

Single Li Cell to 12V, 1MHz Synchronous Boost Converter

with Output Disconnect, 800mA
LB
5.6µH
VIN SWB CAP
2.7V TO 4.2V C1
VOUT
100nF
LA PGNDB VOUTB 12V
5.6µH COUT 800mA
SWA VOUTA 22µF
LTC3124 ×2
PGNDA

VIN SGND
R1
PWM/SYNC SD OFF ON 1.02M
CIN VCC FB
10µF RT VC R2
CVCC RC 113k
4.7µF 88.7k CF
RT 47pF
28k CC
680pF

C1: 100nF, 16V, X7R, 0805 3124 TA08

CIN: 10µF, 10V, X7R, 1206
COUT: 22µF × 2, 16V, X7R, 1210
CVCC: 4.7µF, 10V, X7R, 1206
LA, LB: COILCRAFT XAL5050-562ME

3124f

For more information www.linear.com/LTC3124 25

LTC3124
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706 Rev Ø)

0.65 ±0.05

3.50 ±0.05
1.65 ±0.05
2.20 ±0.05 (2 SIDES)

PACKAGE
OUTLINE

0.25 ± 0.05
0.50 BSC
4.40 ±0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.115 0.40 ±0.10

5.00 ±0.10
TYP
(2 SIDES)
9 16
R = 0.20
TYP

3.00 ±0.10 1.65 ±0.10

(2 SIDES) (2 SIDES)
PIN 1 PIN 1
TOP MARK NOTCH
(SEE NOTE 6)
(DHC16) DFN 1103

8 1
0.200 REF 0.75 ±0.05 0.25 ±0.05
0.50 BSC
4.40 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

3124f

26 For more information www.linear.com/LTC3124

 LTC3124
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev J)
Exposed Pad Variation BC

4.90 – 5.10*
3.58 (.193 – .201)
0.48
(.141) (.019)
3.58
(.141) REF
16 1514 13 12 11 10 9

6.60 ±0.10
2.94 0.51
(.116) DETAIL B (.020)
4.50 ±0.10
6.40 REF
SEE NOTE 4 2.94
(.252)
(.116) DETAIL B IS THE PART OF
0.45 ±0.05 BSC
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
1.05 ±0.10 NO MEASUREMENT PURPOSE

0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8
1.10
4.30 – 4.50* (.0433)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE16 (BC) TSSOP REV J 1012
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
MILLIMETERS FOR EXPOSED PAD ATTACHMENT
2. DIMENSIONS ARE IN
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3124f

27
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTC3124
as described herein will not infringe on existing patent rights.
LTC3124
TYPICAL APPLICATION
Dual Supercapacitor Backup Power Supply, 0.5V to 5.4V PWM Rundown Curve
VIN
2V/DIV
LB
3.3µH
VIN SWB CAP SD
C1 SUPPLY REMOVED
0.5V TO 5.4V 2V/DIV
100nF VOUT FROM SUPERCAP
LA PGNDB VOUTB
COUT 5V
3.3µH
SWA VOUTA 100µF VOUT
LTC3124 ×2 5V/DIV
PGNDA OUTPUT
VIN
CURRENT
VIN SGND R3 100mA/DIV
CIN 200s/DIV 3124 TA07b
1M
10µF
PWM/SYNC SD
R1
SC1 + OFF ON 1.47M Burst Mode Rundown Curve
100F VCC FB
SC2
+ R2
VIN
RT VC 2V/DIV
100F RC 464k
CVCC 59k CF
RT 47pF SD
4.7µF CC SUPPLY REMOVED
28k 2V/DIV
1.5nF FROM SUPERCAP
C1: 100nF, 16V, X5R, 0805 3124 TA07a
CIN: 10µF, 10V, X5R, 1206 VOUT
COUT: 100µF × 2, 6.3V, X5R, 1812 5V/DIV
CVCC: 4.7µF, 10V, X5R, 1206
OUTPUT
LA, LB: COILCRAFT XAL5030-332ME
CURRENT
SC1, SC2: TECATE POWERBURST TPL-100/22X45
20mA/DIV 3124 TA07c
500s/DIV

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC3459 70mA ISW, 10V Micropower Synchronous Boost Converter VIN: 1.5V to 5.5V, VOUT(MAX) = 10V, IQ = 10μA, ISD < 1μA,
with Output Disconnect, Burst Mode Operation ThinSOT Package
LTC3528 1A ISW, 1MHz, Synchronous Step-Up DC/DC Converter with 94% Efficiency VIN: 700mV to 5.25V, VOUT(MAX) = 5.25V, IQ = 12µA,
Output Disconnect, Burst Mode Operation ISD < 1µA, 2mm × 3mm DFN Package
LTC3539 2A ISW, 1MHz/2MHz, Synchronous Step-Up DC/DC Converters 94% Efficiency VIN: 700mV to 5.25V, VOUT(MAX) = 5.25V, IQ = 10uA,
with Output Disconnect, Burst Mode Operation ISD < 1µA, 2mm × 3mm DFN Package
LTC3421 3A ISW, 3MHz, Synchronous Step-Up DC/DC Converter with 95% Efficiency VIN: 0.5V to 4.5V, VOUT(MAX) = 5.25V, IQ = 12μA,
Output Disconnect ISD < 1μA, QFN24 Package
LTC3428 4A ISW, 2MHz (1MHz Switching), Dual Phase Step-Up 92% Efficiency VIN: 1.6V to 4.5V, VOUT(MAX) = 5.25V, ISD < 1µA,
DC/DC Converter 3mm × 3mm DFN Package
LTC3425 5A ISW, 8MHz, Low Ripple, 4-Phase Synchronous Step-Up 95% Efficiency VIN: 0.5V to 4.5V, VOUT(MAX) = 5.25V, IQ = 12μA,
DC/DC Converter with Output Disconnect ISD < 1μA, QFN32
LTC3122 2.5A ISW, 3MHz, Synchronous Step-Up DC/DC Converter with 95% Efficiency VIN: 1.8V to 5.5V [500mV After Start-Up],
Output Disconnect, Burst Mode Operation VOUT(MAX) = 15V, IQ = 25μA, ISD < 1μA, 3mm × 4mm DFN
and MSOP Packages
LTC3112 15V, 2.5A, 750kHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency VIN: 2.7V to 15V, VOUT(MAX) = 14V, IQ = 50μA,
with Output Disconnect, Burst Mode Operation ISD < 1μA, 4mm × 5mm DFN and TSSOP Packages
LTC3114-1 40V, 1A, 2MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency VIN: 2.2V to 40V, VOUT(MAX) = 40V, IQ = 30μA,
with Output Disconnect, Output Current Limit, Burst Mode ISD = 3μA, 3mm × 5mm DFN and TSSOP Packages
Operation
LTC3115-1 40V, 2A, 2MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency VIN: 2.7V to 40V, VOUT(MAX) = 40V, IQ = 30μA,
with Output Disconnect, Burst Mode Operation ISD = 3μA, 4mm × 5mm DFN and TSSOP Packages

3124f

Linear Technology Corporation

28
LT 0614 • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC3124
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3124  LINEAR TECHNOLOGY CORPORATION 2014