LTC3851A-1

Synchronous
Step-Down Switching
Regulator Controller
Features Description
n Wide VIN Range: 4V to 38V Operation The LTC®3851A-1 is a high performance synchronous
n RSENSE or DCR Current Sensing step-down switching regulator controller that drives
n ±1% Output Voltage Accuracy an all N-channel synchronous power MOSFET stage. A
n Power Good Output Voltage Monitor con­stant frequency current mode architecture allows a
n Phase-Lockable Fixed Frequency: 250kHz to 750kHz phase‑lockable frequency of up to 750kHz.
n Dual N-Channel MOSFET Synchronous Drive
OPTI-LOOP compensation allows the transient response
n Very Low Dropout Operation: 99% Duty Cycle
to be optimized over a wide range of output capacitance
n Adjustable Output Voltage Soft-Start or Tracking
and ESR values. The LTC3851A-1 features a precision 0.8V
n Output Current Foldback Limiting
reference and a power good indicator. A wide 4V to 38V
n Output Overvoltage Protection
(40V absolute maximum) input supply range encompasses
n OPTI-LOOP® Compensation Minimizes COUT
most battery configurations and intermediate bus voltages.
n Selectable Continuous, Pulse-Skipping or
Burst Mode® Operation at Light Loads The TK/SS pin ramps the output voltage during start‑up and
n Low Shutdown IQ: 20µA shutdown with coincident or ratiometric tracking. Current
n VOUT Range: 0.8V to 5.5V foldback limits MOSFET heat dissipation during short-
n Thermally Enhanced 16-Lead MSOP circuit conditions. The MODE/PLLIN pin selects among
or 3mm × 3mm QFN Package Burst Mode operation, pulse-skipping mode or continu-
ous inductor current mode at light loads and allows the IC
to be synchronized to an external clock. The LTC3851A-1
Applications contains an improved PLL compared to the LTC3851-1.
n Automotive Systems The LTC3851A-1 is identical to the LTC3851A except that
n Telecom Systems the ILIM pin is replaced by PGOOD.
n Industrial Equipment L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are registered
n Distributed DC Power Systems trademarks and No RSENSE, UltraFast are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
5408150, 5481178, 5705919, 5929620, 6304066, 6498466, 6580258, 6611131.

Typical Application
High Efficiency Synchronous Step-Down Converter Efficiency and Power Loss
vs Load Current
100k
VIN 100 10000
INTVCC PGO0D VIN
22µF 4.5V TO 38V VIN = 12V
FREQ/PLLFLTR TG 95 VOUT = 3.3V
0.1µF 0.68µH VOUT EFFICIENCY
82.5k RUN SW 90
3.3V
LTC3851A-1 0.1µF 15A 85
POWER LOSS (mW)

TK/SS BOOST 1000

EFFICIENCY (%)

330µF
0.1µF 3.01k 80
×2 POWER LOSS
75
INTVCC
2200pF 70
4.7µF
ITH BG 100
65
GND
15k 330pF 60
SENSE+ 55
MODE/PLLIN 0.047µF 30.1k 50 10
SENSE– 154k 10 100 1000 10000 100000
VFB LOAD CURRENT (mA)
3851A1 TA01b
48.7k

3851A1 TA01a
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LTC3851A-1
Absolute Maximum Ratings (Note 1)

Input Supply Voltage (VIN).......................... 40V to –0.3V INTVCC Peak Output Current...................................50mA
Topside Driver Voltage (BOOST)................. 46V to –0.3V Operating Junction Temperature Range (Notes 2, 3)
Switch Voltage (SW)...................................... 40V to –5V E-Grade, I-Grade................................. –40°C to 125°C
INTVCC , (BOOST – SW), RUN, PGOOD......... 6V to –0.3V H-Grade.............................................. –40°C to 150°C
TK/SS....................................................INTVCC to –0.3V MP-Grade........................................... –55°C to 150°C
SENSE+, SENSE–........................................... 6V to –0.3V Storage Temperature Range................... –65°C to 150°C
MODE/PLLIN, FREQ/PLLFLTR...............INTVCC to –0.3V Lead Temperature (Soldering, 10 sec)
ITH , VFB Voltages.......................................... 3V to –0.3V MSE................................................................... 300°C

Pin Configuration
TOP VIEW

FREQ/PLLFLTR
MODE/PLLIN
TOP VIEW

SW
TG
MODE/PLLIN 1 16 SW
FREQ/PLLFLTR 2 15 TG 16 15 14 13
RUN 3 14 BOOST RUN 1 12 BOOST
TK/SS 4 17 13 VIN
ITH 5 GND 12 INTVCC TK/SS 2 17 11 VIN
FB 6 11 BG GND
SENSE– 7 10 GND ITH 3 10 INTVCC
SENSE+ 8 9 PGOOD FB 4 9 BG
MSE PACKAGE 5 6 7 8
16-LEAD PLASTIC MSOP
SENSE–
SENSE+
PGOOD
GND
TJMAX = 125°C, θJA = 35°C/W TO 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3851AEMSE-1#PBF LTC3851AEMSE-1#TRPBF 3851A1 16-Lead Plastic MSOP –40°C to 125°C
LTC3851AIMSE-1#PBF LTC3851AIMSE-1#TRPBF 3851A1 16-Lead Plastic MSOP –40°C to 125°C
LTC3851AHMSE-1#PBF LTC3851AHMSE-1#TRPBF 3851A1 16-Lead Plastic MSOP –40°C to 150°C
LTC3851AMPMSE-1#PBF LTC3851AMPMSE-1#TRPBF 3851A1 16-Lead Plastic MSOP –55°C to 150°C
LTC3851AEUD-1#PBF LTC3851AEUD-1#TRPBF LFQB 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C
LTC3851AIUD-1#PBF LTC3851AIUD-1#TRPBF LFQB 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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 LTC3851A-1
Electrical Characteristics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
VIN Input Operating Voltage Range 4 38 V
VFB Regulated Feedback Voltage ITH = 1.2V (Note 4) 0°C to 85°C l 0.792 0.800 0.808 V
ITH = 1.2V (Note 4) –40°C to 125°C l 0.788 0.812 V
ITH = 1.2V (Note 4) –40°C to 150°C l 0.788 0.812 V
ITH = 1.2V (Note 4) –55°C to 150°C l 0.788 0.812 V
IFB Feedback Current (Note 4) –10 –50 nA
VREFLNREG Reference Voltage Line Regulation VIN = 6V to 38V (Note 4) 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop,
∆ITH = 1.2V to 0.7V l 0.01 0.1 %
(Note 4) Measured in Servo Loop,
∆ITH = 1.2V to 0.7V (H-Grade, MP-Grade) l 0.2 %
(Note 4) Measured in Servo Loop,
∆ITH = 1.2V to 1.6V l –0.01 –0.1 %
(Note 4) Measured in Servo Loop,
∆ITH = 1.2V to 1.6V (H-Grade, MP-Grade) l –0.2 %
gm Transconductance Amplifier gm ITH = 1.2V, Sink/Source = 5µA (Note 4) 2 mmho
gm GBW Transconductance Amp Gain Bandwidth ITH = 1.2V (Note 8) 3 MHz
IQ Input DC Supply Current (Note 5)
Normal Mode VRUN = 5V 1 mA
Shutdown VRUN = 0V 25 50 µA
UVLO Undervoltage Lockout on INTVCC VINTVCC Ramping Down 3.25 V
UVLO Hys UVLO Hysteresis 0.4 V
ISENSE SENSE Pins Current ±1 ±2 µA
ITK/SS Soft-Start Charge Current VTK/SS = 0V 0.6 1 2 µA
VRUN RUN Pin On—Threshold VRUN Rising l 1.10 1.22 1.35 V
VRUNHYS RUN Pin On—Hysteresis 120 mV
VSENSE(MAX) Maximum Current Sense Threshold VFB = 0.7V, VSENSE = 3.3V l 40 53 65 mV
VFB = 0.7V, VSENSE = 3.3V (H-Grade, MP-Grade) l 35 70 mV
TG RUP TG Driver Pull-Up On-Resistance TG High 2.2 Ω
TG RDOWN TG Driver Pull-Down On-Resistance TG Low 1.2 Ω
BG RUP BG Driver Pull-Up On-Resistance BG High 2.1 Ω
BG RDOWN BG Driver Pull-Down On-Resistance BG Low 1.1 Ω
TG Transition Time (Note 6)
TG tr Rise Time CLOAD = 3300pF 25 ns
TG tf Fall Time CLOAD = 3300pF 25 ns
BG Transition Time (Note 6)
BG tr Rise Time CLOAD = 3300pF 25 ns
BG tf Fall Time CLOAD = 3300pF 25 ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay CLOAD = 3300pF Each Driver 30 ns
Bottom Switch-On Delay Time (Note 6)
BG/TG t2D Bottom Gate Off to Top Gate On Delay CLOAD = 3300pF Each Driver 30 ns
Top Switch-On Delay Time (Note 6)
tON(MIN) Minimum On-Time (Note 7) 90 ns
INTVCC Linear Regulator
VINTVCC Internal VCC Voltage 6V < VIN < 38V 4.8 5 5.2 V
VLDO INT INTVCC Load Regulation ICC = 0mA to 50mA 0.5 %

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LTC3851A-1
Electrical Characteristics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Oscillator and Phase-Locked Loop
fNOM Nominal Frequency RFREQ = 60k 460 500 540 kHz
fLOW Lowest Frequency RFREQ = 160k 205 235 265 kHz
fHIGH Highest Frequency RFREQ = 36k 690 750 810 kHz
RMODE/PLLIN MODE/PLLIN Input Resistance 100 kΩ
fMODE MODE/PLLIN Minimum Input Frequency VMODE = External Clock 250 kHz
MODE/PLLIN Maximum Input Frequency VMODE = External Clock 750 kHz
IFREQ Phase Detector Output Current
Sinking Capability fMODE > fOSC –90 µA
Sourcing Capability fMODE < fOSC 75 µA
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPG PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Negative (UV) –12.5 –10 –7.5 %
VFB Ramping Positive (OV) 7.5 10 12.5 %

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: TJ is calculated from the ambient temperature TA and power
may cause permanent damage to the device. Exposure to any Absolute dissipation PD according to the following formulas:
Maximum Rating condition for extended periods may affect device LTC3851AMSE-1: TJ = TA + (PD • 40°C/W)
reliability and lifetime. LTC3851AUD-1: TJ = TA + (PD • 68°C/W)
Note 2: The LTC3851A-1 is tested under pulsed load conditions such that Note 4: The LTC3851A-1 is tested in a feedback loop that servos VITH to a
TA ≈ TJ. The LTC3851AE-1 is guaranteed to meet performance specified voltage and measures the resultant VFB.
specifications from 0°C to 85°C junction temperature. Specifications over
Note 5: Dynamic supply current is higher due to the gate charge being
the –40°C to 125°C operating junction temperature range are assured by
delivered at the switching frequency. See Applications Information.
design, characterization and correlation with statistical process controls.
The LTC3851AI-1 is guaranteed to meet specifications over the –40°C Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
to 125°C operating junction temperature range, the LTC3851AH-1 is times are measured using 50% levels. Rise and fall times are assured by
guaranteed over the –40°C to 150°C operating junction temperature range design, characterization and correlation with statistical process controls.
and the LTC3851AMP-1 is tested and guaranteed over the –55°C to 150°C Note 7: The minimum on-time condition is specified for an inductor
operating junction temperature range. High junction temperatures degrade peak-to-peak ripple current ~40% of IMAX (see Minimum On-Time
operating lifetimes; operating lifetime is derated for junction temperatures Considerations in the Applications Information section).
greater than 125°C. Note that the maximum ambient temperature Note 8: Guaranteed by design; not tested in production.
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.

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 LTC3851A-1
Typical Performance Characteristics
Efficiency vs Output Current Efficiency vs Output Current
and Mode and Mode
100 100
VIN = 12V
90 VOUT = 1.5V 90
BURST
80 80
BURST
70 70

EFFICIENCY(%)
EFFICIENCY(%)

60 PULSE 60
SKIP PULSE
50 50 SKIP
CCM
40 40
CCM
30 30
20 20
VIN = 12V
10 10 VOUT = 3.3V
FIGURE 11 CIRCUIT
0 0
10 100 1000 10000 100000 10 100 1000 10000 100000
LOAD CURRENT (mA) LOAD CURRENT (mA)
3851A1 G01 3851A1 G02

Efficiency vs Output Current Efficiency and Power Loss

and Mode vs Input Voltage
100 100 10000
90 EFFICIENCY,
95 IOUT = 5A POWER LOSS,
80
BURST IOUT = 5A
70

POWER LOSS (mW)

90
EFFICIENCY (%)

EFFICIENCY (%)

60 PULSE
SKIP
50 85 1000
CCM EFFICIENCY,
40 IOUT = 0.5A
80
30 POWER LOSS,
IOUT = 0.5A
20
75 VIN = 12V
10 VIN = 12V VOUT = 3.3V
VOUT = 5V FIGURE 11 CIRCUIT
0 70 100
10 100 1000 10000 100000 4 8 12 16 20 24 28 32
LOAD CURRENT (mA) INPUT VOLTAGE (V)
3851A1 G03 3851A1 G04

Load Step Load Step

(Burst Mode Operation) (Forced Continuous Mode)
ILOAD ILOAD
5A/DIV 5A/DIV
0.2A TO 7.5A 0.2A TO 7.5A

IL IL
5A/DIV 5A/DIV

VOUT VOUT
100mV/DIV 100mV/DIV
AC-COUPLED AC-COUPLED

3851A1 G05 3851A1 G06

VOUT = 1.5V 100µs/DIV VOUT = 1.5V 100µs/DIV
VIN = 12V VIN = 12V
FIGURE 11 CIRCUIT FIGURE 11 CIRCUIT

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LTC3851A-1
Typical Performance Characteristics
Load Step
(Pulse-Skipping Mode) Inductor Current at Light Load
ILOAD FORCED
5A/DIV CONTINOUS
0.2A TO 7.5A MODE
5A/DIV
IL Burst Mode
5A/DIV OPERATION
5A/DIV
VOUT
100mV/DIV PULSE SKIP
AC-COUPLED MODE
5A/DIV
3851A1 G07 3851A1 G08
VOUT = 1.5V 100µs/DIV VOUT = 1.5V 1µs/DIV
VIN = 12V VIN = 12V
FIGURE 11 CIRCUIT ILOAD = 1mA
FIGURE 11 CIRCUIT

Start-Up with Prebiased Output Coincident Tracking with Master

at 2V Supply

VMASTER
VOUT 0.5V/DIV
2V/DIV VOUT
TK/SS 2A LOAD
0.5V/DIV 0.5V/DIV

VFB
0.5V/DIV

3851A1 G09
20ms/DIV 10ms/DIV
3851A1 G10

Ratiometric Tracking with Master Input DC Supply Current

Supply vs Input Voltage
3.0

VMASTER 2.5
0.5V/DIV
SUPPLY CURRENT (mA)

2.0

VOUT
1.5
2A LOAD
0.5V/DIV
1.0

3851A1 G11
10ms/DIV 0.5

0
4 8 12 16 20 24 28 32 36 40
INPUT VOLTAGE (V)
3851A1 G12

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 LTC3851A-1
Typical Performance Characteristics
Maximum Current Sense Threshold Maximum Peak Current Sense
INTVCC Line Regulation vs Common Mode Voltage Threshold vs ITH Voltage
5.3 90 90
DUTY CYCLE RANGE: 0% TO 100%
5.1 ILOAD = 0mA 80 80

ILOAD = 25mA 70
4.9 70

VSENSE THRESHOLD (mV)

60
INTVCC VOLTAGE (V)

4.7 60
50

VSENSE (mV)
4.5 50 40
4.3 40 30

30 20
4.1
10
3.9 20
0
3.7 10 –10
3.5 0 –20
4 8 12 16 20 24 28 32 36 40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
INPUT VOLTAGE (V) VSENSE COMMON MODE VOLTAGE (V) VITH (V)
3851A1 G13 3851A1 G14 3851A1 G15

Maximum Current Sense

Burst Mode Peak Current Sense Maximum Current Sense Threshold vs Feedback Voltage
Threshold vs ITH Voltage Threshold vs Duty Cycle (Current Foldback)
60 90 90
MAXIMUIM 80 80
CURRENT SENSE THRESHOLD (mV)

50
70 70

MAXIMUM VSENSE (mV)

40 60 60
VSENSE (mV)

50 50
30
40 40
20 30 30
MINIMUIM
20 20
10
BURST COMPARATOR FALLING THESHOLD: 10 10
VITH = 0.4V
0 0 0
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0 20 40 60 80 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VITH (V) DUTY CYCLE (%) FEEDBACK VOLTAGE (V)
3851A1 G16 3851A1 G17 3851A1 G18

TK/SS Pull-Up Current Shutdown (RUN) Threshold Regulated Feedback Voltage

vs Temperature vs Temperature vs Temperature
1.5 1.4 806
1.4
REGULATED FEEDBACK VOLTAGE (mV)

804
1.3 1.3
RUN RISING THRESHOLD (ON)
RUN PIN VOLTAGE (V)

1.2
TK/SS CURRENT (µA)

802
1.1 1.2

1.0 RUN FALLING THRESHOLD (OFF) 800

0.9 1.1
798
0.8
0.7 1.0
796
0.6
0.5 0.9 794
–75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3851A1 G19 3851A1 G20 3851A1 G21

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LTC3851A-1
Typical Performance Characteristics
Oscillator Frequency Oscillator Frequency Undervoltage Lockout Threshold
vs Temperature vs Input Voltage (INTVCC) vs Temperature
900 420 5
RFREQ = 80k

INTVCC VOLTAGE AT UVLO THRESHOLD (V)

800 415
RPLLLPF = 36k
4 INTVCC RAMPING UP
410
700
FREQUENCY (kHz)

FREQUENCY (kHz)
405 3 INTVCC RAMPING DOWN
600
RPLLLPF = 60k 400
500
395 2

400
390
1
300 RPLLLPF = 160k 385

200 380 0
–75 –50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30 35 40 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C)
3851A1 G22 3851A1 G23 3851A1 G24

Shutdown Input DC Supply Shutdown Input DC Supply

Current vs Input Voltage Current vs Temperature
40 40
SHUTDOWN INPUT DC SUPPLY CURRENT (µA)

35
SHUTDOWN SUPPLY CURRENT (µA)

35

30 30

25 25

20 20

15 15

10 10

5 5

0 0
0 5 10 15 20 25 30 35 40 –75 –50 –25 0 25 50 75 100 125 150
INPUT VOLTAGE (V) TEMPERATURE (°C)
3851A1 G25 3851A1 G26

Input DC Supply Current Maximum Current Sense

vs Temperature Threshold vs INTVCC Voltage
3.0 90

80
CURRENT SENSE THRESHOLD (mV)
INPUT DC SUPPLY CURRENT (mA)

2.5
70

2.0 60

50
1.5
40

1.0 30

20
0.5
10
0 0
–75 –50 –25 0 25 50 75 100 125 150 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
TEMPERATURE (°C) INTVCC VOLTAGE(V)
3851A1 G27 3851A1 G28

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 LTC3851A-1
Pin Functions (MSE/UD)

MODE/PLLIN (Pin 1/Pin 15): Forced Continuous Mode, PGOOD (Pin 9/Pin 7): Power Good Indicator Output. Open-
Burst Mode or Pulse-Skipping Mode Selection Pin and drain logic out that is pulled to ground when the output
External Synchronization Input to Phase Detector Pin. voltage exceeds the ±10% regulation window, after the
Connect this pin to INTVCC to force continuous conduction internal 17µs power bad mask timer expires.
mode of operation. Connect to GND to enable pulse-skip-
GND (Pin 10/Pin 8, Exposed Pad Pin 17): Ground. All
ping mode of operation. To select Burst Mode operation,
small-signal components and compensation components
tie this pin to INTVCC through a resistor no less than 50k,
should be Kelvin connected to this ground. The (–) terminal
but no greater than 250k. A clock on the pin will force the
of CVCC and the (–) terminal of CIN should be closely con-
controller into forced continuous mode of operation and
nected to this pin. The exposed pad should be soldered
synchronize the internal oscillator.
to ground for good thermal conductivity.
FREQ/PLLFLTR (Pin 2/Pin 16): The phase-locked loop’s
BG (Pin 11/Pin 9): Bottom Gate Driver Output. This pin
lowpass filter is tied to this pin. Alternatively, a resistor
drives the gate of the bottom N-channel MOSFET between
can be connected between this pin and GND to vary the
GND and INTVCC.
frequency of the internal oscillator.
INTVCC (Pin 12/Pin 10): Internal 5V Regulator Output. The
RUN (Pin 3/Pin 1): Run Control Input. A voltage above
control circuit is powered from this voltage. Decouple this
1.22V on this pin turns on the IC. However, forcing this
pin to GND with a minimum 2.2μF low ESR tantalum or
pin below 1.1V causes the IC to shut down the IC. There
ceramic capacitor.
is a 2μA pull-up current on this pin.
VIN (Pin 13/Pin 11): Main Input Supply. Decouple this pin
TK/SS (Pin 4/Pin 2): Output Voltage Tracking and Soft-Start
to GND with a capacitor.
Input. A capacitor to ground at this pin sets the ramp rate
for the output voltage. An internal soft-start current of of BOOST (Pin 14/Pin 12): Boosted Floating Driver Supply.
1μA charges this capacitor. The (+) terminal of the boost-strap capacitor is connected
to this pin. This pin swings from a diode voltage drop
ITH (Pin 5/Pin 3): Current Control Threshold and Error
below INTVCC up to VIN + INTVCC.
Amplifier Compensation Point. The current comparator
tripping threshold increases with its ITH control voltage. TG (Pin 15/Pin 13): Top Gate Driver Output. This is the
output of a floating driver with a voltage swing equal to
FB (Pin 6/Pin 4): Error Amplifier Feedback Input. This pin
INTVCC superimposed on the switch node voltage.
receives the remotely sensed feedback voltage from an
external resistive divider across the output. SW (Pin 16/Pin 14): Switch Node Connection to the In-
ductor. Voltage swing at this pin is from a Schottky diode
SENSE– (Pin 7/Pin 5): Current Sense Comparator Inverting
(external) voltage drop below ground to VIN.
Input. The (–) input to the current comparator is connected
to the output.
SENSE+ (Pin 8/Pin 6): Current Sense Comparator Non-
inverting Input. The (+) input to the current comparator
is normally connected to the DCR sensing network or
current sensing resistor.

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LTC3851A-1
Functional Diagram
FREQ/PLLFLTR MODE/PLLIN VIN
VIN
+
CIN
100k

0.8V 5V REG
MODE/SYNC
DETECT

PLL-SYNC – +
BOOST

BURSTEN
OSC S TG CB

R Q PULSE SKIP M1
SW
ON SWITCH
5k
LOGIC SENSE+
+ – AND
DB
L1
ICMP IREV ANTI- VOUT
SHOOT SENSE–
– + THROUGH

RUN INTVCC +
COUT
BG
OV
M2

CVCC
SLOPE COMPENSATION
GND

PGOOD
INTVCC UVLO

1
100k + 0.72V
R2
ITHB UV VFB
–
R1

VIN SLEEP +
OV
– 0.88V
RUN
0.8V – SS + – +
REF EA 1µA
– + – + +
0.64V 1.22V

0.4V 2µA

3851A1 FD

ITH RUN TK/SS

RC CSS

CC1

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 LTC3851A-1
Operation
Main Control Loop by logic. Be careful not to exceed the absolute maximum
The LTC3851A-1 is a constant frequency, current mode rating of 6V on this pin.
step-down controller. During normal operation, the top The start-up of the controller’s output voltage, VOUT , is
MOSFET is turned on when the clock sets the RS latch, controlled by the voltage on the TK/SS pin. When the
and is turned off when the main current comparator, ICMP , voltage on the TK/SS pin is less than the 0.8V internal
resets the RS latch. The peak inductor current at which reference, the LTC3851A-1 regulates the VFB voltage to
ICMP resets the RS latch is controlled by the voltage on the TK/SS pin voltage instead of the 0.8V reference. This
the ITH pin, which is the output of the error ampli­fier, EA. allows the TK/SS pin to be used to program a soft-start
The VFB pin receives the voltage feedback signal, which is by connecting an external capacitor from the TK/SS pin to
compared to the internal reference voltage by the EA. When GND. An internal 1µA pull-up current charges this capacitor
the load current increases, it causes a slight decrease in creating a voltage ramp on the TK/SS pin. As the TK/SS
VFB relative to the 0.8V reference, which in turn causes the voltage rises linearly from 0V to 0.8V (and beyond), the
ITH voltage to increase until the average inductor current output voltage VOUT rises smoothly from zero to its final
matches the new load current. After the top MOSFET has value. Alternatively, the TK/SS pin can be used to cause
turned off, the bottom MOSFET is turned on until either the start-up of VOUT to track another supply. Typically,
the inductor current starts to reverse, as indicated by the this requires connecting to the TK/SS pin an external
reverse current comparator, IREV, or the beginning of the resistor divider from the other supply to ground (see the
next cycle. Applica­tions Information section). When the RUN pin
is pulled low to disable the controller, or when INTVCC
INTVCC Power drops below its undervoltage lockout threshold of 3.2V,
Power for the top and bottom MOSFET drivers and most the TK/SS pin is pulled low by an internal MOSFET. When
other internal circuitry is derived from the INTVCC pin. An in undervoltage lockout, the controller is disabled and the
internal 5V low dropout linear regulator supplies INTVCC external MOSFETs are held off.
power from VIN.
Light Load Current Operation (Burst Mode Operation,
The top MOSFET driver is biased from the floating boot­ Pulse-Skipping or Continuous Conduction)
strap capacitor, CB , which normally recharges during each
off cycle through an external diode when the top MOSFET The LTC3851A-1 can be enabled to enter high efficiency
turns off. If the input voltage, VIN, decreases to a voltage Burst Mode operation, constant frequency pulse-skipping
close to VOUT, the loop may enter dropout and attempt mode or forced continuous conduction mode. To select
to turn on the top MOSFET continuously. The dropout forced continuous operation, tie the MODE/PLLIN pin to
detec­tor detects this and forces the top MOSFET off for INTVCC. To select pulse-skipping mode of operation, float
the MODE/PLLIN pin or tie it to GND. To select Burst Mode
about 1/10 of the clock period every tenth cycle to allow
operation, tie MODE/PLLIN to INTVCC through a resistor
CB to recharge. However, it is recommended that there is
no less than 50k, but no greater than 250k.
always a load present during the drop-out transition to
ensure CB is recharged. When the controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
Shutdown and Start-Up (RUN and TK/SS) one-forth of the maximum sense voltage even though
The LTC3851A-1 can be shut down using the RUN pin. the voltage on the ITH pin indicates a lower value. If the
Pulling this pin below 1.1V disables the controller and average inductor current is higher than the load current,
most of the internal circuitry, including the INTVCC regula- the error amplifier, EA, will decrease the voltage on the ITH
tor. Releasing the RUN pin allows an internal 2µA current pin. When the ITH voltage drops below 0.4V, the internal
to pull up the pin and enable that controller. Alternatively, sleep signal goes high (enabling “sleep” mode) and both
the RUN pin may be externally pulled up or driven directly external MOSFETs are turned off.
3851a1fa

11
LTC3851A-1
Operation
In sleep mode, the load current is supplied by the output pin. If the MODE/PLLIN pin is not being driven by an ex-
capacitor. As the output voltage decreases, the EA’s output ternal clock source, the FREQ/PLLFLTR pin can be used
begins to rise. When the output voltage drops enough, the to program the controller’s operating frequency from
sleep signal goes low, and the controller resumes normal 250kHz to 750kHz.
operation by turning on the top external MOSFET on the A phase-locked loop (PLL) is available on the LTC3851A-1
next cycle of the internal oscillator. When a controller is to synchronize the internal oscillator to an external clock
enabled for Burst Mode operation, the inductor current is source that is connected to the MODE/PLLIN pin. The
not allowed to reverse. The reverse current comparator, controller operates in forced continuous mode of operation
IREV , turns off the bottom external MOSFET just before the when it is synchronized. A series RC should be connected
inductor current reaches zero, preventing it from revers­ between the FREQ/PLLFLTR pin and GND to serve as the
ing and going negative. Thus, the controller operates in PLL’s loop filter.
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or It is suggested that the external clock be applied before
under large transient conditions. The peak inductor cur­ enabling the controller unless a second resistor is con-
rent is determined by the voltage on the ITH pin, just as in nected in parallel with the series RC loop filter network.
normal operation. In this mode the efficiency at light loads The second resistor prevents low switching frequency
is lower than in Burst Mode operation. However, continu- operation if the controller is enabled before the clock.
ous mode has the advantages of lower output ripple and
less interference to audio circuitry. Output Overvoltage Protection

When the MODE/PLLIN pin is connected to GND, the An overvoltage comparator, OV, guards against transient
LTC3851A-1 operates in PWM pulse-skipping mode at overshoots (>10%) as well as other more serious con­
light loads. At very light loads the current comparator, ditions that may overvoltage the output. In such cases,
ICMP , may remain tripped for several cycles and force the the top MOSFET is turned off and the bottom MOSFET is
external top MOSFET to stay off for the same number of turned on until the overvoltage condition is cleared.
cycles (i.e., skipping pulses). The inductor current is not
Power Good (PGOOD) Pin
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output ripple The PGOOD pin is connected to an open drain of an internal
as well as low audio noise and reduced RF interference N-channel MOSFET. The MOSFET turns on and pulls the
as compared to Burst Mode operation. It provides higher PGOOD pin low when the VFB pin voltage is not within
low current efficiency than forced continuous mode, but ±10% of the 0.8V reference voltage. The PGOOD pin is
not nearly as high as Burst Mode operation. also pulled low when the RUN pin is low (shut down) or
when the LTC3851A-1 is in the soft-start or tracking phase.
Frequency Selection and Phase-Locked Loop When the VFB pin voltage is within the ±10% requirement,
(FREQ/PLLFLTR and MODE/PLLIN Pins) the MOSFET is turned off and the pin is allowed to be
The selection of switching frequency is a trade-off between pulled up by an external resistor to a source of up to 6V.
efficiency and component size. Low frequency operation The PGOOD pin will flag power good immediately when
increases efficiency by reducing MOSFET switching losses, the VFB pin is within the ±10% window. However, there is
but requires larger inductance and/or capacitance to main­ an internal 17µs power bad mask when VFB goes out of
tain low output ripple voltage. The switching frequency of the ±10% window.
the LTC3851A-1 can be selected using the FREQ/PLLFLTR

3851a1fa

12
 LTC3851A-1
Applications Information
The Typical Application on the first page of this data sheet
VIN VIN
is a basic LTC3851A-1 application circuit. The LTC3851A-1 INTVCC
can be configured to use either DCR (inductor resistance)
sensing or low value resistor sensing. The choice of the BOOST
TG
two current sensing schemes is largely a design trade-off RSENSE VOUT
SW
between cost, power consumption and accuracy. DCR LTC3851A-1
sensing is becoming popular because it saves expensive BG
current sensing resis­tors and is more power efficient, GND

especially in high current applications. However, current SENSE+

sensing resistors provide the most accurate current limits SENSE–
for the controller. Other external component selection
is driven by the load require­ment, and begins with the
FILTER COMPONENTS 3851A1 F01

selection of RSENSE (if RSENSE is used) and the inductor PLACED NEAR SENSE PINS
value. Next, the power MOSFETs and Schottky diodes are Figure 1. Using a Resistor to Sense Current with the LTC3851A-1
selected. Finally, input and output capacitors are selected.
The circuit shown on the first page can be configured for
of 20% for variations in the IC and external component
operation up to 38V at VIN.
values yields:
SENSE+ and SENSE– Pins VMAX
RSENSE = 0.8 •
The SENSE+ and SENSE– pins are the inputs to the current IMAX + ∆IL /2
comparators. The common mode input voltage range of
the current comparators is 0V to 5.5V. Both SENSE pins Inductor DCR Sensing
are high impedance inputs with small base currents of
less than 1μA. When the SENSE pins ramp up from 0V For applications requiring the highest possible efficiency,
to 1.4V, the small base currents flow out of the SENSE the LTC3851A-1 is capable of sensing the voltage drop
pins. When the SENSE pins ramp down from 5V to 1.1V, across the inductor DCR, as shown in Figure 2. The
the small base currents flow into the SENSE pins. The DCR of the inductor represents the small amount of
high impedance inputs to the current comparators allow DC winding resis­tance of the copper, which can be less
accurate DCR sensing. However, care must be taken not than 1mΩ for today’s low value, high current inductors.
to float these pins during normal operation. If the external R1||R2 • C1 time constant is chosen to
be exactly equal to the L/DCR time constant, the voltage
Low Value Resistors Current Sensing drop across the external capacitor is equal to the voltage
drop across the inductor DCR multiplied by R2/(R1 + R2).
A typical sensing circuit using a discrete resistor is shown Therefore, R2 may be used to scale the voltage across the
in Figure 1. RSENSE is chosen based on the required output sense terminals when the DCR is greater than the target
current. sense resistance. Check the manufacturer’s data sheet
The current comparator has a maximum threshold, for specifications regarding the inductor DCR, in order
VMAX = 53mV. The current comparator threshold sets the to properly dimension the external filter components.
maximum peak of the inductor current, yielding a maximum The DCR of the inductor can also be measured using a
average output current, IMAX , equal to the peak value less good RLC meter.
half the peak-to-peak ripple current, ∆IL. Allowing a margin

3851a1fa

13
LTC3851A-1
Applications Information
Accepting larger values of ∆IL allows the use of low
VIN VIN
INTVCC inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
BOOST setting ripple current is ∆IL = 0.3(IMAX). The maximum
TG
INDUCTOR
∆IL occurs at the maximum input voltage.
SW L DCR
LTC3851A-1 VOUT The inductor value also has secondary effects. The tran­
BG sition to Burst Mode operation begins when the average
GND inductor current required results in a peak current below
SENSE+
R1
≈10% of the current limit determined by RSENSE. Lower
C1* R2 inductor values (higher ∆IL) will cause this to occur at
SENSE– lower load currents, which can cause a dip in efficiency in
L the upper range of low current operation. In Burst Mode
*PLACE C1 NEAR SENSE+, SENSE– PINS R1||R2 • C1 = 3851A1 F02
DCR
R2
operation, lower inductance values will cause the burst
RSENSE(EQ) = DCR
R1 + R2 frequency to increase.
Figure 2. Current Mode Control Using the Inductor DCR
Inductor Core Selection
Slope Compensation and Inductor Peak Current Once the value for L is known, the type of inductor must
Slope compensation provides stability in constant fre- be selected. High efficiency converters generally cannot
quency architectures by preventing sub-harmonic oscil- afford the core loss found in low cost powdered iron cores,
lations at high duty cycles. It is accomplished inter­nally forcing the use of more expensive ferrite or molypermalloy
by adding a compensating ramp to the inductor current cores. Actual core loss is independent of core size for a
signal. Normally, this results in a reduction of maximum fixed inductor value, but it is very dependent on inductance
inductor peak cur­rent for duty cycles >40%. However, the selected. As inductance increases, core losses go down.
LTC3851A-1 uses a novel scheme that allows the maximum Unfortunately, increased inductance requires more turns
inductor peak current to remain unaffected throughout all of wire and therefore copper losses will increase.
duty cycles. Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con­
Inductor Value Calculation
centrate on copper loss and preventing saturation. Ferrite
The operating frequency and inductor selection are inter­ core material saturates hard, which means that induc­
related in that higher operating frequencies allow the use of tance collapses abruptly when the peak design current is
smaller inductor and capacitor values. A higher frequency exceeded. This results in an abrupt increase in inductor
generally results in lower efficiency because of MOSFET ripple current and consequent output voltage ripple. Do
gate charge losses. In addition to this basic trade-off, the not allow the core to saturate!
effect of inductor value on ripple current and low current
operation must also be considered. Power MOSFET and Schottky Diode (Optional)
Selection
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL decreases with higher Two external power MOSFETs must be selected for the
inductance or frequency and increases with higher VIN: LTC3851A-1 controller: one N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
1 ⎛ V ⎞
∆IL = VOUT ⎜1– OUT ⎟ bottom (synchronous) switch.
f •L ⎝ VIN ⎠

3851a1fa

14
 LTC3851A-1
Applications Information
The peak-to-peak drive levels are set by the INTVCC voltage. Both MOSFETs have I2R losses while the topside N-channel
This voltage is typically 5V during start-up. Consequently, equation includes an additional term for transition losses,
logic-level threshold MOSFETs must be used in most ap- which are highest at high input voltages. For VIN < 20V,
plications. The only exception is if low input voltage is ex- the high current efficiency generally improves with larger
pected (VIN < 5V); then, sub-logic level threshold MOSFETs MOSFETs, while for VIN > 20V, the transition losses rapidly
(VGS(TH) < 3V) should be used. Pay close attention to the increase to the point that the use of a higher RDS(ON) device
BVDSS specification for the MOSFETs as well; most of the with lower CMILLER actually provides higher efficiency. The
logic-level MOSFETs are limited to 30V or less. synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
Selection criteria for the power MOSFETs include the on-
short-circuit when the synchronous switch is on close to
resistance, RDS(ON), Miller capacitance, CMILLER , input
100% of the period.
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve The term (1 + δ) is generally given for a MOSFET in the
usually provided on the MOSFET manufacturers’ data form of a normalized RDS(ON) vs Temperature curve, but
sheet. CMILLER is equal to the increase in gate charge δ = 0.005/°C can be used as an approximation for low
along the horizontal axis while the curve is approximately voltage MOSFETs.
flat divided by the specified change in VDS. This result is The optional Schottky diode conducts during the dead time
then multiplied by the ratio of the application applied VDS between the conduction of the two power MOSFETs. This
to the gate charge curve specified VDS. When the IC is prevents the body diode of the bottom MOSFET from turn-
operating in continuous mode, the duty cycles for the top ing on, storing charge during the dead time and requiring
and bottom MOSFETs are given by: a reverse recovery period that could cost as much as 3%
VOUT in efficiency at high VIN. A 1A to 3A Schottky is generally
Main Switch Duty Cycle = a good size due to the relatively small average current.
VIN
Larger diodes result in additional transition losses due to
VIN – VOUT their larger junction capacitance.
Synchronous Switch Duty Cycle =
VIN
Soft-Start and Tracking
The MOSFET power dissipations at maximum output
current are given by: The LTC3851A-1 has the ability to either soft-start by itself
with a capacitor or track the output of another channel
VOUT or external supply. When the LTC3851A-1 is configured
PMAIN = (IMAX )2 (1+ δ) RDS(ON) + to soft-start by itself, a capacitor should be connected to
VIN
⎛I ⎞ the TK/SS pin. The LTC3851A-1 is in the shutdown state if
( VIN )2 ⎜ MAX ⎟ (RDR ) (CMILLER ) • the RUN pin voltage is below 1.10V. TK/SS pin is actively
⎝ 2 ⎠ pulled to ground in this shutdown state.
⎡ 1 1 ⎤
⎢ + ⎥(f) Once the RUN pin voltage is above 1.22V, the LTC3851A-1
⎢⎣ VINTVCC – VTH(MIN) VTH(MIN) ⎥⎦ powers up. A soft-start current of 1μA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
VIN – VOUT achieved not by limiting the maximum output current of
PSYNC = (IMAX )2 (1+ δ) RDS(ON) the controller but by controlling the output ramp voltage
VIN
according to the ramp rate on the TK/SS pin. Current
where δ is the temperature dependency of RDS(ON) and foldback is disabled during this phase to ensure smooth
RDR (approximately 2Ω) is the effective driver resistance soft-start or tracking. The soft-start or tracking range is
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
3851a1fa

15
LTC3851A-1
Applications Information
0V to 0.8V on the TK/SS pin. The total soft-start time can Output Voltage Tracking
be calculated as:
The LTC3851A-1 allows the user to program how its
CSS output ramps up and down by means of the TK/SS pins.
tSOFT-START = 0.8 •
1.0µA Through this pin, the output can be set up to either co-
incidentally or ratiometrically track with another supply’s
Regardless of the mode selected by the MODE/PLLIN pin, output, as shown in Figure 3. In the following discussions,
the regulator will always start in pulse-skipping mode up VMASTER refers to a master supply and VOUT refers to the
to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.72V, it LTC3851A-1’s output as a slave supply. To implement the
will operate in forced continuous mode and revert to the coincident tracking in Figure 3a, connect a resistor divider
selected mode once TK/SS > 0.72V. The output ripple to VMASTER and connect its midpoint to the TK/SS pin of
is minimized during the 80mV forced continuous mode the LTC3851A-1. The ratio of this divider should be selected
window. the same as that of the LTC3851A-1’s feedback divider as
shown in Figure 4a. In this tracking mode, VMASTER must
When the regulator is configured to track another supply,
be higher than VOUT. To implement ratiometric tracking,
the feedback voltage of the other supply is duplicated by a
the ratio of the resistor divider connected to VMASTER is
resistor divider and applied to the TK/SS pin. Therefore, the
determined by:
voltage ramp rate on this pin is determined by the ramp rate
of the other supply’s voltage. Note that the small soft-start VOUT R2 ⎛ R3 + R4 ⎞
capacitor charging current is always flowing, producing a = ⎜ ⎟
VMASTER R4 ⎝ R1+ R2 ⎠
small offset error. To minimize this error, one can select
the tracking resistive divider value to be small enough to So which mode should be programmed? While either
make this error negligible. mode in Figure 4 satisfies most practical applications,
In order to track down another supply after the soft-start the coincident mode offers better output regulation.
phase expires, the LTC3851A-1 must be configured for This concept can be better understood with the help of
forced continuous operation by connecting MODE/PLLIN Figure 5. At the input stage of the LTC3851A-1’s error
to INTVCC. amplifier, two common anode diodes are used to clamp

VMASTER VMASTER
OUTPUT VOLTAGE

OUTPUT VOLTAGE

VOUT VOUT

3851A1

TIME TIME 3851A1 F03

(3a) Coincident Tracking (3b) Ratiometric Tracking

Figure 3. Two Different Modes of Output Voltage Tracking

3851a1fa

16
 LTC3851A-1
Applications Information
VMASTER VOUT VMASTER VOUT
R3 R3 R1 R3
TO TO TO TO
TK/SS VFB TK/SS VFB
PIN PIN PIN PIN
R4 R4 R2 R4

3851A1 F04

(4a) Coincident Tracking Setup (4b) Ratiometric Tracking Setup

Figure 4. Setup for Coincident and Ratiometric Tracking

The LDO can supply a peak current of 50mA and must

I I be bypassed to ground with a minimum of 2.2μF ceramic
capacitor or low ESR electrolytic capacitor. No matter
+
what type of bulk capaci­tor is used, an additional 0.1μF
D1 D2 EA
TK/SS ceramic capacitor placed directly adjacent to the INTVCC
–
0.8V D3
and GND pins is highly recommended. Good bypassing
VFB 3851A1 F05 is needed to supply the high transient currents required
by the MOSFET gate drivers.
Figure 5. Equivalent Input Circuit of Error Amplifier
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi­
the equivalent reference voltage and an additional diode mum junction temperature rating for the LTC3851A-1 to
is used to match the shifted common mode voltage. The be exceeded. The INTVCC current, which is dominated by
top two current sources are of the same amplitude. In the the gate charge current, is supplied by the 5V LDO.
coincident mode, the TK/SS voltage is substantially higher
than 0.8V at steady state and effectively turns off D1. D2 Power dissipation for the IC in this case is highest and
and D3 will therefore conduct the same current and offer is approximately equal to VIN • IINTVCC. The gate charge
tight matching between VFB and the internal precision current is dependent on operating frequency as discussed
0.8V reference. In the ratiometric mode, however, TK/SS in the Efficiency Considerations section. The junction tem-
equals 0.8V at steady state. D1 will divert part of the bias perature can be estimated by using the equa­tions given in
current to make VFB slightly lower than 0.8V. Note 3 of the Electrical Characteristics. For example, the
LTC3851A-1 INTVCC current is limited to less than 17mA
Although this error is minimized by the exponential I-V from a 36V supply in the GN package:
characteristic of the diode, it does impose a finite amount
of output voltage deviation. Furthermore, when the master TJ = 70°C + (17mA)(36V)(90°C/W) = 125°C
supply’s output experiences dynamic excursion (under To prevent the maximum junction temperature from being
load transient, for example), the slave channel output will exceeded, the input supply current must be checked while
be affected as well. For better output regulation, use the operating in continuous conduction mode (MODE/PLLIN
coincident tracking mode instead of ratiometric. = INTVCC) at maximum VIN .
INTVCC Regulator Topside MOSFET Driver Supply (CB, DB)
The LTC3851A-1 features a PMOS low dropout linear An external bootstrap capacitor, CB, connected to the
regula­tor (LDO) that supplies power to INTVCC from the BOOST pin supplies the gate drive voltage for the topside
VIN supply. INTVCC powers the gate drivers and much of MOSFET. Capacitor CB in the Functional Diagram is charged
the LTC3851A-1 ’s internal circuitry. The LDO regulates though external diode DB from INTVCC when the SW pin
the voltage at the INTVCC pin to 5V.
3851a1fa

17
LTC3851A-1
Applications Information
is low. When the topside MOSFET is to be turned on, the required. Several capacitors may also be paralleled to meet
driver places the CB voltage across the gate source of the size or height requirements in the design. Always consult
MOSFET. This enhances the MOSFET and turns on the the manufacturer if there is any question.
topside switch. The switch node voltage, SW, rises to VIN COUT Selection
and the BOOST pin follows. With the topside MOSFET on,
the boost voltage is above the input supply: The selection of COUT is primarily determined by the effec-
tive series resistance, ESR, to minimize voltage ripple. The
VBOOST = VIN + VINTVCC output ripple, ∆VOUT, in continuous mode is determined by:
The value of the boost capacitor, CB, needs to be 100 times ⎛
that of the total input capa­citance of the topside MOSFET. 1 ⎞
∆VOUT ≈ ∆IL ⎜ESR + ⎟
The reverse break­down of the external Schottky diode ⎝ 8fCOUT ⎠
must be greater than VIN(MAX).
where f = operating frequency, COUT = output capaci­tance
Undervoltage Lockout and ∆IL = ripple current in the inductor. The output ripple
The LTC3851A-1 has two functions that help protect the is highest at maximum input voltage since ∆IL increases
controller in case of undervoltage conditions. A precision with input voltage. Typically, once the ESR requirement
UVLO comparator constantly monitors the INTVCC voltage for COUT has been met, the RMS current rating gener-
to ensure that an adequate gate-drive voltage is present. ally far exceeds the IRIPPLE(P-P) requirement. With ∆IL =
It locks out the switching action when INTVCC is below 0.3IOUT(MAX) and allowing 2/3 of the ripple to be due to
3.2V. To prevent oscillation when there is a disturbance ESR, the output ripple will be less than 50mV at maximum
on the INTVCC , the UVLO comparator has 400mV of preci­ VIN and:
sion hysteresis. COUT Required ESR < 2.2RSENSE
Another way to detect an undervoltage condition is to moni- 1
tor the VIN supply. Because the RUN pin has a precision COUT >
8fRSENSE
turn-on reference of 1.22V, one can use a resistor divider
to VIN to turn on the IC when VIN is high enough. The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran­tees
CIN Selection
that the output capacitance does not significantly discharge
In continuous mode, the source current of the top N-chan- during the operating frequency period due to ripple current.
nel MOSFET is a square wave of duty cycle VOUT/VIN . To The choice of using smaller output capaci­tance increases
prevent large voltage transients, a low ESR input capacitor the ripple voltage due to the discharging term but can be
sized for the maximum RMS current must be used. The compensated for by using capacitors of very low ESR to
maximum RMS capacitor current is given by: maintain the ripple voltage at or below 50mV. The ITH pin
OPTI-LOOP compensation compo­nents can be optimized
VOUT ⎛ VIN ⎞1/2 to provide stable, high perfor­mance transient response
IRMS ≅ IO(MAX) ⎜ – 1⎟
VIN ⎝ VOUT ⎠ regardless of the output capaci­tors selected.
The selection of output capacitors for applications with
This formula has a maximum at VIN = 2VOUT, where IRMS = large load current transients is primarily determined by the
IO(MAX)/2. This simple worst-case condition is com­monly voltage tolerance specifications of the load. The resistive
used for design because even significant deviations do not component of the capacitor, ESR, multiplied by the load
offer much relief. Note that capacitor manufacturers’ ripple current change, plus any output voltage ripple must be
current ratings are often based on only 2000 hours of life. within the voltage tolerance of the load.
This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
3851a1fa

18
 LTC3851A-1
Applications Information
The required ESR due to a load current step is: AVX TPSV or the KEMET T510 series of surface mount
tantalums, available in case heights rang­ing from 1.5mm
∆V
R ESR ≤ to 4.1mm. Aluminum electrolytic capaci­tors can be used
∆I in cost-driven applications, provided that consideration is
where ∆I is the change in current from full load to zero load given to ripple current ratings, tempera­ture and long-term
(or minimum load) and ∆V is the allowed voltage devia- reliability. A typical application will require several to many
tion (not including any droop due to finite capacitance). aluminum electrolytic capacitors in parallel. A combina-
tion of the above mentioned capaci­tors will often result
The amount of capacitance needed is determined by the in maximizing performance and minimizing overall cost.
maximum energy stored in the inductor. The capacitance Other capacitor types include Nichicon PL series, NEC
must be sufficient to absorb the change in inductor Neocap, Panasonic SP and Sprague 595D series. Consult
current when a high current to low current transition manufacturers for other specific recommendations.
occurs. The opposite load current transition is generally
determined by the control loop OPTI-LOOP components, Like all components, capacitors are not ideal. Each
so make sure not to over compensate and slow down ca­pacitor has its own benefits and limitations. Combina­
the response. The minimum capacitance to assure the tions of different capacitor types have proven to be a very
inductors’ energy is adequately absorbed is: cost effective solution. Remember also to include high
frequency decoupling capacitors. They should be placed
2
L ( ∆I) as close as possible to the power pins of the load. Any
COUT >
2 ( ∆V ) VOUT inductance present in the circuit board traces negates
their usefulness.
where ∆I is the change in load current.
Setting Output Voltage
Manufacturers such as Nichicon, United Chemi-Con and
Sanyo can be considered for high performance through- The LTC3851A-1 output voltage is set by an external feed-
hole capacitors. The OS-CON semiconductor electrolyte back resistive divider carefully placed across the output,
capacitor available from Sanyo has the lowest (ESR)(size) as shown in Figure 6. The regulated output volt­age is
product of any aluminum electrolytic at a somewhat determined by:
higher price. An additional ceramic capacitor in parallel ⎛ R ⎞
with OS-CON capacitors is recommended to reduce the VOUT = 0.8V ⎜1+ B ⎟
inductance effects. ⎝ RA ⎠
In surface mount applications, ESR, RMS current han­dling To improve the transient response, a feed-forward
and load step specifications may require multiple capaci- ca­pacitor, CFF , may be used. Great care should be taken
tors in parallel. Aluminum electrolytic, dry tantalum and to route the VFB line away from noise sources, such as
special polymer capacitors are available in surface mount the inductor or the SW line.
packages. Special polymer surface mount capaci­tors offer
very low ESR but have much lower capacitive density per VOUT

unit volume than other capacitor types. These capacitors

LTC3851A-1 RB CFF
offer a very cost-effective output capacitor solution and are
VFB
an ideal choice when combined with a controller having
RA
high loop bandwidth. Tantalum capaci­tors offer the highest
capacitance density and are often used as output capaci- 3851A1 F06

tors for switching regulators having controlled soft-start. Figure 6. Settling Output Voltage
Several excellent surge-tested choices are the AVX TPS,

3851a1fa

19
LTC3851A-1
Applications Information
Fault Conditions: Current Limit and Current Foldback Phase-Locked Loop and Frequency Synchronization
The LTC3851A-1 includes current foldback to help limit The LTC3851A-1 has a phase-locked loop (PLL) comprised
load current when the output is shorted to ground. If the of an internal voltage-controlled oscillator (VCO) and a
output falls below 40% of its nominal output level, the phase detector. This allows the turn-on of the top MOSFET
maximum sense voltage is progressively lowered from to be locked to the rising edge of an external clock signal
its maximum programmed value to about 25% of the applied to the MODE/PLLIN pin. This phase detector is
that value. Foldback current limiting is disabled during an edge sensitive digital type that provides zero degrees
soft-start or tracking. Under short-circuit conditions phase shift between the external and internal oscillators.
with very low duty cycles, the LTC3851A-1 will begin This type of phase detector does not exhibit false lock to
cycle skipping in order to limit the short-circuit current. harmonics of the external clock.
In this situation the bottom MOSFET will be dissipating The output of the phase detector is a pair of complemen­
most of the power but less than in normal operation. The tary current sources that charge or discharge the external
short-circuit ripple current is determined by the minimum filter network connected to the FREQ/PLLFLTR pin. Note
on-time, tON(MIN), of the LTC3851A-1 (≈90ns), the input that the LTC3851A-1 can only be synchronized to an
voltage and inductor value:
external clock whose frequency is within range of the
VIN LTC3851A-1’s internal VCO.This is guaranteed to be be-
∆IL(SC) = tON(MIN) •
L tween 250kHz and 750kHz. A simplified block diagram is
shown in Figure 8.
The resulting short-circuit current is:
If the external clock frequency is greater than the internal
1/4MaxVSENSE 1 oscillator’s frequency, fOSC , then current is sunk con­
ISC = – ∆IL(SC)
RSENSE 2 tinuously from the phase detector output, pulling down the
FREQ/PLLFLTR pin. When the external clock frequency is
Programming Switching Frequency less than fOSC , current is sourced continuously, pulling up
the FREQ/PLLFLTR pin. If the external and internal frequen-
To set the switching frequency of the LTC3851A-1, connect
cies are the same but exhibit a phase difference, the current
a resistor, RFREQ, between FREQ/PLLFLTR and GND. The
sources turn on for an amount of time corresponding to the
relationship between the oscillator frequency and RFREQ
phase difference. The voltage on the FREQ/PLLFLTR pin is
is shown in Figure 7. A 0.1µF bypass capacitor should be
adjusted until the phase and frequency of the internal and
connected in parallel with RFREQ.
external oscillators are identical. At the stable operating
750 point, the phase detector output is high impedance and
700 the filter capacitor CLP holds the voltage.
OSCILLATOR FREQUENCY (kHz)

650
2.7V RLP
600
550 CLP

500
FREQ/PLLFLTR
450 MODE/
PLLIN DIGITAL
400
EXTERNAL PHASE/
350 OSCILLATOR FREQUENCY VCO
DETECTOR
300
250
20 40 60 80 100 120 140 160
RFREQ (kΩ)
3851A1 F07

3851A1 F08
Figure 7. Relationship Between Oscillator Frequency
and Resistor Connected Between FREQ/PLLFLTR and GND Figure 8. Phase-Locked Loop Block Diagram
3851a1fa

20
 LTC3851A-1
Applications Information
The loop filter components, CLP and RLP , smooth out minimum on-time gradually increases. This is of particu­
the current pulses from the phase detector and provide lar concern in forced continuous applications with low
a stable input to the voltage-controlled oscillator. The ripple current at light loads. If the duty cycle drops below
filter components CLP and RLP determine how fast the the minimum on-time limit in this situation, a significant
loop acquires lock. Typically RLP is 1k to 10k and CLP is amount of cycle skipping can occur with correspondingly
2200pF to 0.01μF. larger current and voltage ripple.
When the external oscillator is active before the LTC3851 Efficiency Considerations
is enabled, the internal oscillator frequency will track the
external oscillator frequency as described in the preceding The percent efficiency of a switching regulator is equal to
paragraphs. In situations where the LTC3851 is enabled the output power divided by the input power times 100%.
before the external oscillator is active, a low free-running It is often useful to analyze individual losses to determine
oscillator frequency of approximately 50kHz will result. It is what is limiting the efficiency and which change would
possible to increase the free-running, pre-synchronization produce the most improvement. Percent efficiency can
frequency by adding a second resistor, RFREQ, in parallel be expressed as:
with RLP and CLP . RFREQ will also cause a phase difference %Efficiency = 100% – (L1 + L2 + L3 + ...)
between the internal and external oscillator signals. The
magnitude of the phase difference is inversely proportional where L1, L2, etc. are the individual losses as a percent­
to the value RFREQ. The free-running frequency may be age of input power.
programmed by using Figure 7 to determine the appropri- Although all dissipative elements in the circuit produce
ate value of RFREQ. In order to maintain adequate phase losses, four main sources usually account for most of
margin for the PLL, the typical value for CLP is 0.01µF and the losses in LTC3851A-1 circuits: 1) IC VIN current, 2)
the typical value for RLP is 1k. INTVCC regulator current, 3) I2R losses, 4) topside MOSFET
The external clock (on MODE/PLLIN pin) input high transition losses.
threshold is nominally 1.6V, while the input low thres­hold 1. The VIN current is the DC supply current given in the
is nominally 1.2V. Electrical Characteristics table, which excludes MOSFET
driver current. VIN current typi­cally results in a small
Minimum On-Time Considerations (<0.1%) loss.
Minimum on-time, tON(MIN), is the smallest time dura- 2. INTVCC current is the sum of the MOSFET driver and
tion that the LTC3851A-1 is capable of turning on the top control currents. The MOSFET driver current results
MOSFET. It is determined by internal timing delays and the from switching the gate capacitance of the power
gate charge required to turn on the top MOSFET. Low duty MOSFETs. Each time a MOSFET gate is switched from
cycle applications may approach this minimum on-time low to high to low again, a packet of charge dQ moves
limit and care should be taken to ensure that: from INTVCC to ground. The resulting dQ/dt is a cur­rent
VOUT out of INTVCC that is typically much larger than the
tON(MIN) < control circuit current. In continuous mode, IGATECHG
VIN (f)
= f(QT + QB), where QT and QB are the gate charges of
If the duty cycle falls below what can be accommodated the topside and bottom side MOSFETs.
by the minimum on-time, the controller will begin to skip 3. I2R losses are predicted from the DC resistances of
cycles. The output voltage will continue to be regulated, the fuse (if used), MOSFET, inductor and current sense
but the ripple voltage and current will increase. resistor. In continuous mode, the average output current
The minimum on-time for the LTC3851A-1 is approximately flows through L and RSENSE, but is chopped between
90ns. However, as the peak sense voltage decreases the the topside MOSFET and the synchronous MOSFET.
3851a1fa

21
LTC3851A-1
Applications Information
If the two MOSFETs have approximately the same time VOUT can be monitored for excessive overshoot or
RDS(ON), then the resistance of one MOSFET can simply ringing, which would indicate a stability problem. The
be summed with the resistances of L and RSENSE to availability of the ITH pin not only allows optimization of
obtain I2R losses. For example, if each RDS(ON) = 10mΩ, control loop behavior but also provides a DC-coupled and
DCR = 10mΩ and RSENSE = 5mΩ, then the total resis- AC-filtered closed-loop response test point. The DC step,
tance is 25mΩ. This results in losses ranging from 2% rise time and settling at this test point truly reflects the
to 8% as the output current increases from 3A to 15A closed-loop response. Assuming a predominantly second
for a 5V output, or a 3% to 12% loss for a 3.3V output. order system, phase margin and/or damping factor can be
Efficiency varies as the inverse square of VOUT for the estimated using the percentage of overshoot seen at this
same external components and output power level. The pin. The bandwidth can also be estimated by examining the
combined effects of increasingly lower output voltages rise time at the pin. The ITH external components shown
and higher currents required by high performance digital in the Typical Application circuit will provide an adequate
systems is not doubling but quadrupling the importance starting point for most applications.
of loss terms in the switching regulator system! The ITH series RC-CC filter sets the dominant pole-zero
4. Transition losses apply only to the topside MOSFET(s), loop compensation. The values can be modified slightly
and become significant only when operating at high (from 0.5 to 2 times their suggested values) to optimize
input voltages (typically 15V or greater). Transition transient response once the final PC layout is done and
losses can be estimated from: the particular output capacitor type and value have been
determined. The output capacitors need to be selected
Transition Loss = (1.7)VIN2 • IO(MAX) • CRSS • f
because the various types and values determine the loop
Other hidden losses such as copper trace and the battery gain and phase. An output current pulse of 20% to 80%
internal resistance can account for an additional 5% to of full-load current having a rise time of 1μs to 10μs will
10% efficiency degradation in portable systems. It is very produce output voltage and ITH pin waveforms that will
important to include these system level losses during the give a sense of the overall loop stability without break­ing
design phase. The internal battery and fuse resistance the feedback loop. Placing a power MOSFET directly
losses can be minimized by making sure that CIN has ad- across the output capacitor and driving the gate with an
equate charge storage and very low ESR at the switch­ing appropriate signal generator is a practical way to produce
frequency. A 25W supply will typically require a minimum of a realistic load step condition. The initial output voltage
20μF to 40μF of capacitance having a maximum of 20mΩ step resulting from the step change in output current may
to 50mΩ of ESR. Other losses including Schottky con- not be within the bandwidth of the feedback loop, so this
duction losses during dead time and inductor core losses signal cannot be used to determine phase margin. This
generally account for less than 2% total additional loss. is why it is better to look at the ITH pin signal which is in
the feedback loop and is the filtered and compensated
Checking Transient Response control loop response. The midband gain of the loop will
The regulator loop response can be checked by looking at be in­creased by increasing RC and the bandwidth of the
the load current transient response. Switching regulators loop will be increased by decreasing CC. If RC is increased
take several cycles to respond to a step in DC (resistive) by the same factor that CC is decreased, the zero frequency
load current. When a load step occurs, VOUT shifts by an will be kept the same, thereby keeping the phase shift the
amount equal to ∆ILOAD (ESR), where ESR is the effective same in the most critical frequency range of the feedback
series resistance of COUT. ∆ILOAD also begins to charge or loop. The output voltage settling behavior is related to the
discharge COUT generating the feedback error signal that stability of the closed-loop system and will demonstrate
forces the regulator to adapt to the current change and the actual overall supply performance.
return VOUT to its steady-state value. During this recovery

3851a1fa

22
 LTC3851A-1
Applications Information
A second, more severe transient is caused by switching PC Board Layout Checklist
in loads with large (>1μF) supply bypass capacitors. The
When laying out the printed circuit board, the following
discharged bypass capacitors are effectively put in parallel
checklist should be used to ensure proper operation of the
with COUT, causing a rapid drop in VOUT. No regulator can
LTC3851A-1. These items are also illustrated graphically
alter its delivery of current quickly enough to prevent this
in the layout diagram of Figure 9. Check the following in
sudden step change in output voltage if the load switch
your layout:
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time 1. Are the board signal and power grounds segregated?
should be controlled so that the load rise time is limited The LTC3851A-1 GND pin should tie to the ground plane
to approximately 25 • CLOAD. Thus a 10μF capacitor would close to the input capacitor(s). The low current or signal
require a 250μs rise time, limiting the charging current ground lines should make a single point tie directly to
to about 200mA. the GND pin. The synchronous MOSFET source pins
should connect to the input capacitor(s) ground.

+
0.1mF
1 16
MODE/PLLIN SW

RFREQ CIN
2 15
FREQ/PLLFLTR TG M1
+
3 14
RUN BOOST
VIN
CSS LTC3851A-1
4 13 D1
TK/SS VIN
CC CC2 DB CB
RC M2
5 12
ITH INTVCC
47pF
6 11 +
VFB BG 4.7µF

7 10
SENSE– GND –
1000pF
8 9 RPGOOD
SENSE+ PGOOD VPULL-UP
L1

–
R1

+ COUT VOUT
RSENSE
R2

3851A1 F09
+

Figure 9. LTC3851A-1 Layout Diagram

3851a1fa

23
LTC3851A-1
Applications Information
2. Does the VFB pin connect directly to the feedback resis- PC Board Layout Debugging
tors? The resistive divider R1, R2 must be connected
It is helpful to use a DC-50MHz current probe to monitor
between the (+) plate of COUT and signal ground. The
the current in the inductor while testing the circuit. Monitor
47pF to 100pF capacitor should be as close as possible
the output switching node (SW pin) to synchronize the
to the LTC3851A-1. Be careful locating the feedback
oscilloscope to the internal oscillator and probe the actual
resistors too far away from the LTC3851A-1. The VFB
output voltage as well. Check for proper performance over
line should not be routed close to any other nodes with
the operating voltage and current range expected in the
high slew rates.
application. The frequency of operation should be main-
3. Are the SENSE– and SENSE+ leads routed together tained over the input voltage range down to dropout and
with minimum PC trace spacing? The filter capacitor until the output load drops below the low current opera-
between SENSE+ and SENSE– should be as close as tion threshold—typically 10% of the maximum designed
possible to the LTC3851A-1. Ensure accurate current cur­rent level in Burst Mode operation.
sensing with Kelvin connections as shown in Figure 10.
The duty cycle percentage should be maintained from cycle
Series resistance can be added to the SENSE lines to
to cycle in a well designed, low noise PCB imple­mentation.
increase noise rejection and to compensate for the ESL
Variation in the duty cycle at a subharmonic rate can sug-
of RSENSE.
gest noise pick-up at the current or voltage sensing inputs
4. Does the (+) terminal of CIN connect to the drain of or inadequate loop compensation. Overcompensation of
the topside MOSFET(s) as closely as possible? This the loop can be used to tame a poor PC layout if regulator
capacitor provides the AC current to the MOSFET(s). bandwidth optimization is not required.
5. Is the INTVCC decoupling capacitor connected closely Reduce VIN from its nominal level to verify operation
between INTVCC and GND? This capacitor carries the of the regulator in dropout. Check the operation of the
MOSFET driver peak currents. An addi­tional 1μF ceramic undervoltage lockout circuit by further lowering VIN while
capacitor placed immediately next to the INTVCC and monitoring the outputs to verify operation.
GND pins can help improve noise performance.
Investigate whether any problems exist only at higher out­
6. Keep the switching node (SW), top gate node (TG) and put currents or only at higher input voltages. If problems
boost node (BOOST) away from sensitive small-signal coincide with high input voltages and low output currents,
nodes, especially from the voltage and current sensing look for capacitive coupling between the BOOST, SW, TG
feedback pins. All of these nodes have very large and and possibly BG connections and the sensitive voltage
fast moving signals and therefore should be kept on and current pins. The capacitor placed across the current
the “output side” (Pin 9 to Pin 16) of the LTC3851A-1 sensing pins needs to be placed immediately adjacent to
and occupy minimum PC trace area. the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
HIGH CURRENT PATH
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, the Schottky and the
top MOSFET to the sensitive current and voltage sens-
3851A1 F10 ing traces. In addition, investigate common ground path
voltage pickup between these components and the GND
CURRENT SENSE pin of the IC.
RESISTOR
(RSENSE)
SENSE+ SENSE–

Figure 10. Kelvin Sensing RSENSE

3851a1fa

24
 LTC3851A-1
Applications Information
Design Example The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
As a design example, assume VIN = 12V (nominal), VIN =
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF.
22V (maximum), VOUT = 1.8V, IMAX = 5A, and f = 250kHz
At maximum input voltage with T (estimated) = 50°C:
(refer to Figure 12).
1.8V 2 ⎡
The inductance value is chosen first based on a 30% PMAIN = (5) ⎣1+ (0.005) (50°C − 25°C)⎤⎦ •
ripple current assumption. The highest value of ripple 22V
current occurs at the maximum input voltage. Connect a ⎛ 5A ⎞
(0.035Ω) + (22V )2 ⎜ ⎟ (2Ω) (215pF ) •
160k resistor between the FREQ/PLLFLTR and GND pins, ⎝ 2 ⎠
generating 250kHz op­eration. The minimum inductance ⎡ 1 1⎤
for 30% ripple current is: ⎢⎣ + ⎥ (250kHz ) = 185mW
5 − 2.3 2.3 ⎦
1 ⎛ V ⎞
∆IL = VOUT ⎜1− OUT ⎟ A short-circuit to ground will result in a folded back cur-
( f) (L) ⎝ VIN ⎠
rent of:
A 4.7µH inductor will produce 28% ripple current and 29mV 1 ⎛ 90ns (22V ) ⎞
a 3.3µH will result in 40%. The peak inductor current ISC = – ⎜ ⎟ = 2.02A
0.0125Ω 2 ⎝ 3.3µH ⎠
will be the maximum DC value plus one-half the ripple
current, or 6A, for the 3.3µH value. Increasing the ripple
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
current will also help ensure that the minimum on-time
= 0.125. The resulting power dissipated in the bottom
of 90ns is not violated. The minimum on-time occurs at
MOSFET is:
maximum VIN:
22V
tON(MIN) =
VOUT 1.8V
= 327ns
PSYNC = (2.02A )2 (1.125) (0.022Ω) = 101.0mW
= 22V
VIN(MAX) ( f) 22V (250kHz )
which is less than under full-load conditions.
The RSENSE resistor value can be calculated by using the
CIN is chosen for an RMS current rating of at least 3A at
maximum current sense voltage specification with some
temperature. COUT is chosen with an ESR of 0.02Ω for
accommodation for tolerances.
low output ripple. The output ripple in continuous mode
50mV will be highest at the maximum input voltage. The output
RSENSE ≤ = 0.0083Ω
6A voltage ripple due to ESR is approximately:
VORIPPLE = RESR (∆IL) = 0.02Ω (2A) = 40mVP-P
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.

3851a1fa

25
LTC3851A-1
Typical Applications
VIN
4.5V TO 32V
MODE/PLLIN VIN
RFREQ
+ CIN
82.5k 22µF
M1
FREQ/PLLFLTR TG
CB HAT2170H
0.1µF
C20 RUN BOOST
0.1µF CSS L1
0.1µF LTC3851A-1
0.68µH VOUT
TK/SS SW 3.3V
CC DB 15A
RC 2200pF CC2 R2
R27 C15
15k 330pF CMDSH05-4 154k
3.01k 47pF
ITH INTVCC 1% + COUT
330µF
4.7µF ×2
R1
M2
VFB BG 48.7k
HAT2170H
1%

SENSE– GND
C5
0.047µF RPG
30.1k
SENSE+ PGOOD VPULL-UP COUT: SANYO 6TPE330MIL
CIN: SANYO 63HVH22M
L1: VISHAY IHLP5050-EZERR68M01

3851A1 F11

Figure 11. High Efficiency 3.3V/15A Step-Down Converter

VIN
4.5V TO 22V
MODE/PLLIN VIN
RFREQ
+ CIN
22µF
160k M1 25V
FREQ/PLLFLTR TG
CB FDS6982S
0.1µF
0.1µF
RUN BOOST
CSS L1
0.1µF LTC3851A-1 RSENSE
3.3µH 0.01Ω VOUT
TK/SS SW 1.8V
CC DB R2 5A
RC 470pF CC2
CMDSH-3 32.4k COUT
33k 220pF
ITH INTVCC
1% + 150µF
6.3V
4.7µF R1 ×2
M2 25.5k PANASONIC SP
VFB BG 1%
FDS6982S

SENSE– GND
1000pF
RPG
SENSE+ PGOOD VPULL-UP COUT: PANASONIC EEFUEOG151R
CIN: MARCON THCR70LE1H226ZT
L1: PANASONIC ETQP6F3R3HFA
RSENSE: IRC LR 2010-01-R010F
3851A1 F12

Figure 12. 1.8V/5A Converter from Design Example with Pulse Skip Operation

3851a1fa

26
 LTC3851A-1
Package Description
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)

0.70 ±0.05

3.50 ± 0.05 1.45 ± 0.05

2.10 ± 0.05 (4 SIDES)

PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

R = 0.115 PIN 1 NOTCH R = 0.20 TYP
3.00 ± 0.10 0.75 ± 0.05 OR 0.25 × 45° CHAMFER
TYP
(4 SIDES) 15 16
PIN 1 0.40 ± 0.10
TOP MARK
(NOTE 6) 1

1.45 ± 0.10 2
(4-SIDES)

(UD16) QFN 0904

0.200 REF 0.25 ± 0.05

0.00 – 0.05 0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

3851a1fa

27
LTC3851A-1
Package Description
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev C)

BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ± 0.102 2.845 ± 0.102
(.112 ± .004) 0.889 ± 0.127 (.112 ± .004)
(.035 ± .005)
1 8 0.35
REF

5.23 1.651 ± 0.102

1.651 ± 0.102 3.20 – 3.45
(.206) 0.12 REF
(.065 ± .004) (.126 – .136) (.065 ± .004)
MIN
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
16 9 FOR REFERENCE ONLY
0.305 ± 0.038 0.50 NO MEASUREMENT PURPOSE
(.0120 ± .0015) (.0197) 4.039 ± 0.102
TYP BSC (.159 ± .004)
(NOTE 3) 0.280 ± 0.076
RECOMMENDED SOLDER PAD LAYOUT
16151413121110 9 (.011 ± .003)
REF
DETAIL “A”
0.254
(.010) 3.00 ± 0.102
0° – 6° TYP 4.90 ± 0.152
(.118 ± .004)
(.193 ± .006)
GAUGE PLANE (NOTE 4)

0.53 ± 0.152
(.021 ± .006)
1234567 8
DETAIL “A” 1.10 0.86
0.18 (.043) (.034)
(.007) MAX REF

SEATING
PLANE 0.17 – 0.27 0.1016 ± 0.0508
(.007 – .011) (.004 ± .002)
TYP 0.50
NOTE: (.0197)
MSOP (MSE16) 0910 REV C

1. DIMENSIONS IN MILLIMETER/(INCH) BSC

2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

3851a1fa

28
 LTC3851A-1
Revision History
REV DATE DESCRIPTION PAGE NUMBER
A 5/11 Added H-Grade and MP-Grade parts. Reflected througout the data sheet. 1-30

3851a1fa

29
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3851A-1
Typical Application
1.5V/15A Synchronized at 350kHz

VIN
6V TO 14V
PLLIN
MODE/PLLIN VIN
C2 350kHz +
0.01µF R5 CIN
1k M1 180µF
FREQ/PLLFLTR TG
CB RJK0305DPB
C1
0.1µF
1000pF
RUN BOOST
CSS L1
0.1µF LTC3851A-1 RSENSE
0.68µH 0.002Ω VOUT
TK/SS SW 1.5V
CC R2 15A
RC 1000pF CC2 DB C10
7.5k CMDSH-3 43.2k
100pF
ITH INTVCC
33pF
1% + COUT
330µF
R1 ×2
4.7µF 20k
M2 1%
VFB BG
RJK0301DPB

SENSE– GND
1000pF COUT: SANYO 2R5TPE330M9
RPG L1: SUMIDA CEP125-OR6MC
SENSE+ PGOOD VPULL-UP
R22 10Ω

R20 10Ω
3851A1 TA03

Related Parts
PART NUMBER DESCRIPTION COMMENTS
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DC/DC Controller 0.8V ≤ VOUT ≤ 5.25V, 2mm × 3mm QFN-12
LTC3878 No RSENSE™ Constant On-Time Synchronous Step-Down Very Fast Transient Response, tON(MIN) = 43ns, 4V≤ VIN ≤ 38V,
DC/DC Controller 0.8V ≤ VOUT ≤ 0.9VIN, SSOP-16
LTC3879 No RSENSE Constant On-Time Synchronous Step-Down Very Fast Transient Response, tON(MIN) = 43ns, 4V≤ VIN ≤ 38V,
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LTC3850/LTC3850-1 Dual 2-Phase, High Efficiency Synchronous Step-Down Phase-Lockable Fixed Operating Frequency 250kHz to 780kHz,
LTC3850-2 DC/DC Controllers, RSENSE or DCR Current Sensing and 4V≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V
Tracking
LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz,
Controller, RSENSE or DCR Current Sensing and Tracking 4V≤ VIN ≤ 24V, VOUT Up to 13.5V
LTC3834/LTC3834-1 Low IQ, Synchronous Step-Down DC/DC Controller Phase-Lockable Fixed Operating Frequency 140kHz to 650kHz,
4V≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, IQ = 30µA,
LT®3845A Low IQ , High Voltage Synchronous Step-Down DC/DC Adjustable Fixed Operating Frequency 100kHz to 500kHz,
Controller 4V≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 36V, IQ = 30µA, TSSOP-16
LTC3775 High Frequency Synchronous Voltage Mode Step-Down Synchronizable Fixed Frequency 250kHz to 1MHz, tON(MIN) = 30ns,
DC/DC Controller 4V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 0.8VIN, MSOP-16E, 3mm × 3mm
QFN-16

3851a1fa

30 Linear Technology Corporation

LT 0511 REV A • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

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