LTC3612

3A, 4MHz Monolithic

Synchronous Step-Down
DC/DC Converter
Features Description
n 3A Output Current The LTC®3612 is a low quiescent current monolithic syn-
n 2.25V to 5.5V Input Voltage Range chronous buck regulator using a current mode, constant
n Low Output Ripple Burst Mode® Operation: IQ = 70µA frequency architecture. The no-load DC supply current
n ±1% Output Voltage Accuracy in sleep mode is only 70µA while maintaining the output
n Output Voltage Down to 0.6V voltage (Burst Mode operation) at no load, dropping to zero
n High Efficiency: Up to 95% current in shutdown. The 2.25V to 5.5V input supply voltage
n Low Dropout Operation: 100% Duty Cycle range makes the LTC3612 ideally suited for single Li-Ion
n Shutdown Current: ≤1µA as well as fixed low voltage input applications. 100% duty
n Adjustable Switching Frequency: Up to 4MHz cycle capability provides low dropout operation, extending
n Optional Active Voltage Positioning (AVP) with the operating time in battery-powered systems.
Internal Compensation The operating frequency is externally programmable up to
n Selectable Pulse-Skipping/Forced Continuous/ 4MHz, allowing the use of small surface mount inductors.
Burst Mode Operation with Adjustable Burst Clamp For switching noise-sensitive applications, the LTC3612
n Programmable Soft-Start can be synchronized to an external clock at up to 4MHz.
n Inputs for Start-Up Tracking or External Reference
n DDR Memory Mode, IOUT = ±1.5A Forced continuous mode operation in the LTC3612 reduces
n Available in Thermally Enhanced 20-Pin noise and RF interference. Adjustable compensation allows
(3mm × 4mm) QFN and TSSOP Packages the transient response to be optimized over a wide range
of loads and output capacitors.
Applications The internal synchronous switch increases efficiency and
n Point-of-Load Supplies eliminates the need for an external catch diode, saving
n Distributed Power Supplies external components and board space. The LTC3612 is
n Portable Computer Systems offered in a leadless 20-pin 3mm × 4mm QFN or a thermally
n DDR Memory Termination enhanced 20-pin TSSOP package.
n Handheld Devices L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 6580258, 5481178, 5994885, 6304066, 6498466,
6611131.

Typical Application Efficiency and Power Loss vs Load Current

100 10
VIN 90
2.5V TO 5.5V 22µF
80 1
s2
SVIN PVIN 70
POWER LOSS (W)

RUN PVIN_DRV
EFFICIENCY (%)

TRACK/SS DDR 60 0.1

RT/SYNC 560nH VOUT 50
LTC3612 SW 2.5V
3A 40 0.01
PGOOD SGND 47µF
ITH PGND 30
MODE VFB 20 0.001
665k VIN = 5V
3612 TA01a
10 VIN = 3.3V
VIN = 2.8V
210k 0
1 10 100 1000 10000
OUTPUT CURRENT (mA) 3612 TA01b

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LTC3612
Absolute Maximum Ratings (Notes 1, 11)
PVIN, SVIN, PVIN_DRV Voltages...................... –0.3V to 6V Operating Junction Temperature Range
SW Voltage...................................–0.3V to (PVIN + 0.3V) (Notes 2, 11)........................................... –40°C to 125°C
ITH, RT/SYNC Voltages................ –0.3V to (SVIN + 0.3V) Storage Temperature............................... –65°C to 150°C
DDR, TRACK/SS Voltages............ –0.3V to (SVIN + 0.3V) Reflow Peak Body Temperature (QFN)................... 260°C
MODE, RUN, VFB Voltages........... –0.3V to (SVIN + 0.3V) Lead Temperature (Soldering, 10 sec)
PGOOD Voltage............................................. –0.3V to 6V TSSOP............................................................... 300°C

Pin Configuration
TOP VIEW TOP VIEW
TRACK/SS

SVIN 1 20 PVIN_DRV
MODE
VFB
ITH

RUN 2 19 SW
20 19 18 17
PGOOD 3 18 NC
DDR 1 16 PGOOD
MODE 4 17 SW
RT/SYNC 2 15 RUN
VFB 5 16 PVIN
SGND 3 14 SVIN 21
21 ITH 6 15 PVIN
NC 4 13 PVIN_DRV
TRACK/SS 7 14 SW
SW 5 12 SW
DDR 8 13 NC
SW 6 11 SW
RT/SYNC 9 12 SW
7 8 9 10
SGND 10 11 NC
NC
PVIN
PVIN
NC

FE PACKAGE
UDC PACKAGE
20-LEAD PLASTIC TSSOP
20-LEAD (3mm s 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 38°C/W
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB

order information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3612EUDC#PBF LTC3612EUDC#TRPBF LDQT 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC3612IUDC#PBF LTC3612IUDC#TRPBF LDQT 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC3612EFE#PBF LTC3612EFE#TRPBF LTC3612FE 20-Lead Plastic TSSOP –40°C to 125°C
LTC3612IFE#PBF LTC3612IFE#TRPBF LTC3612FE 20-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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 LTC3612
Electrical Characteristics The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, RT/SYNC = SVIN, unless otherwise specified (Note 2).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage Range l 2.25 5.5 V
VUVLO Undervoltage Lockout Threshold SVIN Ramping Down l 1.7 V
SVIN Ramping Up l 2.25 V
VFB Feedback Voltage Internal Reference (Notes 3, 4) VTRACK/SS = SVIN, VDDR = 0V
0°C < TJ < 85°C 0.594 0.6 0.606 V
–40°C < TJ < 125°C l 0.591 0.609 V
Feedback Voltage External Reference (Notes 3, 4) VTRACK/SS = 0.3V, VDDR = SVIN 0.289 0.3 0.311 V
(Note 7) (Notes 3, 4) VTRACK/SS = 0.5V, VDDR = SVIN 0.489 0.5 0.511 V
IFB Feedback Input Current VFB = 0.6V l ±30 nA
∆VLINEREG Line Regulation SVIN = PVIN = 2.25V to 5.5V l 0.2 %/V
(Notes 3, 4) TRACK/SS = SVIN
∆VLOADREG Load Regulation ITH from 0.5V to 0.9V (Notes 3, 4) 0.25 %
VITH = SVIN (Note 5) 2.6 %
IS Active Mode VFB = 0.5V, VMODE = SVIN (Note 6) 1100 µA
Sleep Mode VFB = 0.7V, VMODE = 0V, ITH = SVIN 70 100 µA
(Note 5)
VFB = 0.7V, VMODE = 0V (Note 4) 120 160 µA
Shutdown SVIN = PVIN = 5.5V, VRUN = 0V 0.1 1 µA
RDS(ON) Top Switch On-Resistance PVIN = 3.3V (Note 10) 70 mΩ
Bottom Switch On-Resistance PVIN = 3.3V (Note 10) 45 mΩ
ILIM Top Switch Current Limit Sourcing (Note 8), VFB = 0.5V
Duty Cycle <35% 5.2 6 6.8 A
Duty Cycle = 100% 4 A
Bottom Switch Current Limit Sinking (Note 8), VFB = 0.7V, –3 –4 –5 A
Forced Continuous Mode
gm(EA) Error Amplifier Transconductance –5µA < IITH < 5µA (Note 4) 200 µS
IEAO Error Amplifier Max Output Current (Note 4) ±30 µA
tSS Internal Soft-Start Time VFB from 0.06V to 0.54V, 0.65 1 1.5 ms
TRACK/SS = SVIN
VTRACK/SS Enable Internal Soft-Start (Note 7 ) 0.62 V
tTRACK/SS_DIS Soft-Start Discharge Time at 70 µs
Start-Up
RON(TRACK/SS_DIS) TRACK/SS Pull-Down Resistor at 200 Ω
Start-Up
fOSC Oscillator Frequency RT/SYNC = 370k l 0.8 1 1.2 MHz
Internal Oscillator Frequency VRT/SYNC = SVIN l 1.8 2.25 2.7 MHz
fSYNC Synchronization Frequency 0.3 4 MHz
VRT/SYNC SYNC Level High 1.2 V
SYNC Level Low . 0.3 V
ISW(LKG) Switch Leakage Current SVIN = PVIN = 5.5V, VRUN = 0V 0.1 1 µA
VDDR DDR Option Enable Voltage SVIN – 0.3 V
VMODE Internal Burst Mode Operation 0.3 V
(Note 9) Pulse-Skipping Mode SVIN – 0.3 V
Forced Continuous Mode 1.1 SVIN • 0.58 V
External Burst Mode Operation 0.45 0.8 V
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LTC3612
Electrical Characteristics The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, RT/SYNC = SVIN, unless otherwise specified (Note 2).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PGOOD Power Good Voltage Windows TRACK/SS = SVIN, Entering Window
VFB Ramping Up –3.5 –6 %
VFB Ramping Down 3.5 6 %
TRACK/SS = SVIN, Leaving Window
VFB Ramping Up 9 11 %
VFB Ramping Down –9 –11 %
tPGOOD Power Good Blanking Time Entering and Leaving Window 70 105 140 µs
RPGOOD Power Good Pull-Down On-Resistance 8 17 33 Ω
VRUN RUN Voltage Input High l 1 V
Input Low l 0.4 V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: This parameter is tested in a feedback loop which servos VFB to
may cause permanent damage to the device. Exposure to any Absolute the midpoint for the error amplifier (VITH = 0.75V).
Maximum Rating condition for extended periods may affect device Note 4: External compensation on ITH pin.
reliability and lifetime. Note 5: Tying the ITH pin to SVIN enables the internal compensation and
Note 2: The LTC3612 is tested under pulsed load conditions such that AVP mode.
TJ ≈ TA. The LTC3612E is guaranteed to meet performance specifications Note 6: Dynamic supply current is higher due to the internal gate charge
from 0°C to 85°C junction temperature. Specifications over the being delivered at the switching frequency.
–40°C to 125°C operating junction temperature range are assured by
Note 7: See description of the TRACK/SS pin in the Pin Functions section.
design, characterization and correlation with statistical process controls.
The LTC3612I is guaranteed over the full –40°C to 125°C operating Note 8: In sourcing mode the average output current is flowing out of SW
pin. In sinking mode the average output current is flowing into the SW Pin.
junction temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating Note 9: See description of the MODE pin in the Pin Functions section.
conditions in conjunction with board layout, the rated package thermal Note 10: Guaranteed by correlation and design to wafer level
impedance and other environmental factors. The junction temperature measurements for QFN packages.
(TJ, in °C) is calculated from the ambient temperature (TA, in °C) and Note 11: This IC includes overtemperature protection that is intended
power dissipation (PD, in watts) according to the formula: to protect the device during momentary overload conditions. Junction
TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal temperature will exceed 125°C when overtemperature protection is active.
impedance. Continuous operation above the specified maximum operating junction
temperature may impair device reliability.

Typical Performance Characteristics VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.

Efficiency vs Load Current Efficiency vs Load Current

(VMODE = 0V) (VMODE = 0V)
100 100
VOUT = 1.8V VOUT = 1.2V
90 90
80 80
70 70
EFFICIENCY (%)

EFFICIENCY (%)

60 60
50 50
40 40
30 30
20 20
VIN = 5V VIN = 5V
10 VIN = 3.3V 10 VIN = 3.3V
VIN = 2.5V VIN = 2.5V
0 0
1 10 100 1000 10000 1 10 100 1000 10000
OUTPUT CURRENT (mA) 3612 G01
OUTPUT CURRENT (mA) 3612 G02

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 LTC3612
Typical Performance Characteristics VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
Efficiency vs Input Voltage Efficiency vs Frequency
Efficiency vs Load Current (VMODE = 0V) (VMODE = 0V), IOUT = 1A
100 100 95
VOUT = 1.8V VOUT = 1.8V VOUT = 1.8V
90 94
90 93
80
92
70 Burst Mode 80 91
EXTERNAL

EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)

60 CLAMP = 0.7V 90
70 89
Burst Mode
50 INTERNAL 88
40 CLAMP 60
87
PULSE-
30 SKIPPING 50 86
MODE IOUT = 3mA 85
20 IOUT = 300mA
FORCED 84 1µH
40 IOUT = 1A
10 CONTINUOUS 0.68µH
MODE IOUT = 3A 83 0.33µH
0 30 82
1 10 100 1000 10000 2.25 2.75 3.25 3.75 4.25 4.75 5.25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
OUTPUT CURRENT (mA) INPUT VOLTAGE (V) FREQUENCY (MHz)
3612 G03 3612 G04 3612 G05

Load Regulation Line Regulation Burst Mode Operation

1.5 0.3
FORCED CONTINUOUS MODE
1.3 INTERNAL Burst Mode OPERATION
PULSE-SKIPPING MODE 0.2 VOUT
1.1 20mV/DIV
0.9 0.1
VOUT ERROR (%)
VOUT ERROR (%)

0.7 IL
0
500mA/DIV
0.5

0.3 –0.1 VOUT = 1.8V 20µs/DIV 3612 G08

IOUT = 75mA
0.1 VMODE = 0V
–0.2
–0.1
VOUT = 1.8V
–0.3 –0.3
0 500 1000 1500 2000 2500 3000 2.20 2.75 3.30 3.85 4.40 4.95 5.50
OUTPUT CURRENT (mA) INPUT VOLTAGE (V)
3612 G06 3612 G07

Pulse-Skipping Mode Operation Forced Continuous Mode Operation

VOUT
20mV/DIV
VOUT
20mV/DIV

IL
200mA/DIV
IL
500mA/DIV
3612 G10
VOUT = 1.8V 20µs/DIV 3612 G09
VOUT = 1.8V 1µs/DIV
IOUT = 75mA IOUT = 100mA
VMODE = 3.3V VMODE = 1.5V

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LTC3612
Typical Performance Characteristics VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
Load Step Transient in Load Step Transient in
Pulse-Skipping Mode Burst Mode Operation

VOUT VOUT
200mV/DIV 200mV/DIV

IL IL
1A/DIV 1A/DIV

3612 G11 3612 G12

VOUT = 1.8V 50µs/DIV VOUT = 1.8V 50µs/DIV
ILOAD = 100mA TO 3A ILOAD = 100mA TO 3A
VMODE = 3.3V VMODE = 0V
COMPENSATION FIGURE 1 COMPENSATION FIGURE 1

Load Step Transient in Forced Load Step Transient in Forced

Continuous Mode without AVP Mode Continuous Mode with AVP Mode
VOUT
100mV/DIV
VOUT
200mV/DIV
IL
1A/DIV
IL
1A/DIV

3612 G14
VOUT = 1.8V 50µs/DIV
VOUT = 1.8V 50µs/DIV 3612 G13
ILOAD = 100mA TO 3A
ILOAD = 100mA TO 3A VMODE = 1.5V
VMODE = 1.5V VITH = VIN
COMPENSATION FIGURE 1 OUTPUT CAPACITOR VALUE FIGURE 1

Load Step Transient in Forced

Continuous Mode Sourcing and
Sinking Current Sinking Current
VOUT
VOUT 20mV/DIV
200mV/DIV
SW
2V/DIV
IL
2A/DIV 0A
IL
500mA/DIV
3612 G15 3612 G16
VOUT = 1.8V 50µs/DIV VOUT = 1.2V 1µs/DIV
ILOAD = –1.5A TO 3A IOUT = –1A
VMODE = 1.5V VMODE = 1.5V
COMPENSATION FIGURE 1

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 LTC3612
Typical Performance Characteristics VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
Tracking Up/Down in
Internal Start-Up in Forced Forced Continuous Mode,
Continuous Mode DDR Pin Tied to 0V
RUN
1V/DIV VOUT
1V/DIV
VOUT
500mV/DIV VTRACK/SS
IL 500mV/DIV
1A/DIV
PGOOD
PGOOD 2V/DIV
2V/DIV
3612 G17
VOUT = 1.8V 500µs/DIV
3612 G18
IOUT = 3A 2ms/DIV
VMODE = 1.5V VOUT = 0V TO 1.8V
IOUT = 3A
VTRACK/SS = 0V TO 0.7V
VMODE = 1.5V
VDDR = 0V

Tracking Up/Down in Forced

Continuous Mode, DDR Pin Tied Reference Voltage
to SVIN vs Temperature
0.606
VOUT
500mV/DIV 0.604
REFERENCE VOLTAGE (V)

VTRACK/SS
200mV/DIV 0.602

PGOOD
2V/DIV 0.600

2ms/DIV 3612 G19 0.598

VOUT = 0V TO 1.2V
IOUT = 3A
VTRACK/SS = 0V TO 0.4V 0.596
VMODE = 1.5V
VDDR = 3.3V 0.594
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3612 G20

Switch On-Resistance Switch On-Resistance

vs Input Voltage vs Temperature
0.10 0.09
0.09 0.08
MAIN SWITCH
0.08 0.07
0.07 MAIN SWITCH
0.06
RDS(0N) (Ω)

0.06 SYNCHRONOUS SWITCH

RDS(ON) (Ω)

0.05
0.05 SYNCHRONOUS SWITCH
0.04
0.04
0.03
0.03
0.02 0.02

0.01 0.01

0 0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 –50 –30 –10 10 30 50 70 90 110 130
INPUT VOLTAGE (V) TEMPERATURE (°C)
3612 G21 3612 G22

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LTC3612
Typical Performance Characteristics VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
Frequency vs Resistor on
RT/SYNC Pin Frequency vs Temperature
0.8
4500
0.6
4000
0.4

FREQUENCY VARIATION (%)

3500
0.2
3000
FREQUENCY (kHz)

0
2500 –0.2
2000 –0.4
1500 –0.6

1000 –0.8
–1.0
500
–1.2
0 –50 –30 –10 10 30 50 70 90 100 130
0 200 400 600 800 1000 1200 1400
TEMPERATURE (°C)
RESISTOR ON RT/SYNC PIN (kΩ)
3612 G24
3612 G23

Switch Leakage vs Temperature,

Frequency vs Input Voltage Main Switch
1.0 4000
VIN = 2.25V
3500 VIN = 3.3V
0.5
VIN = 5.5V
FREQUENCY VARIATION (%)

3000
SWITCH LEAKAGE (nA)

0
2500
–0.5
2000
–1.0
1500
–1.5
1000

–2.0 500

–2.5 0
2.25 2.75 3.25 3.75 4.25 4.75 5.25 –50 –30 –10 10 30 50 70 90 110 130
INPUT VOLTAGE (V) TEMPERATURE (°C)
3612 G25 3612 G26

Switch Leakage vs Temperature, Dynamic Supply Current vs Input

Synchronous Switch Voltage without AVP Mode
4000 100
VIN = 2.25V
3500 VIN = 3.3V
VIN = 5.5V
DYNAMIC SUPPLY CURRENT (mA)

FORCED CONTINUOUS MODE

3000 10
SWITCH LEAKAGE (nA)

2500
PULSE-SKIPPING MODE
2000 1

1500
Burst Mode OPERATION
1000 0.1

500

0 0.01
–50 –30 –10 10 30 50 70 90 110 130 2.25 2.75 3.25 3.75 4.25 4.75 5.25
TEMPERATURE (°C) INPUT VOLTAGE (V)
3612 G27 3612 G28

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 LTC3612
Typical Performance Characteristics VIN = 3.3V, RT/SYNC = SVIN, unless otherwise noted.
Start-Up from Shutdown with
Dynamic Supply Current vs VOUT Short to GND, Prebiased Output
Temperature without AVP Mode Forced Continuous Mode (Forced Continuous Mode)
100 PGOOD
5V/DIV
VOUT
DYNAMIC SUPPLY CURRENT (mA)

FORCED CONTINUOUS MODE 1V/DIV VOUT

10 500mV/DIV

IL
2A/DIV
PULSE-SKIPPING MODE IL
1 2A/DIV

3612 G30 3612 G31

Burst Mode OPERATION VOUT = 2.5V 50µs/DIV 20µs/DIV
0.1 IOUT = 0A PREBIASED VOUT = 2.2V
VMODE = 1.5V VOUT = 1.2V
IOUT = 0A
VMODE = 1.5V
0.01
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3612 G29

Output Voltage During Sinking Output Voltage During Sinking

vs Input Voltage vs Input Voltage
1.90 0.95
VOUT = 1.8V VOUT = 0.9V
1µH INDUCTOR 1µH INDUCTOR
1.88 0.94

1.86 0.93

1.84 0.92
VOUT (V)
VOUT (V)

–1.5A, 2MHz, 120°C

1.82 0.91 –1.5A, 1MHz, 120°C
–1.5A, 2MHz, 25°C
1.80 0.90
–1.5A, 1MHz, 25°C
1.78 0.89

1.76 0.88
2.25 2.75 3.25 3.75 4.25 4.75 5.25 2.25 2.75 3.25 3.75 4.25 4.75 5.25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
3612 G32 3612 G33

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LTC3612
Pin Functions (QFN/FE)

DDR (Pin 1/Pin 8): DDR Mode Pin. Tying the DDR pin to window for more than 105µs the PGOOD pin is released.
SVIN selects DDR mode and TRACK/SS can be used as If the FB voltage leaves the power good window for more
an external reference input. If DDR is tied to SGND, the than 105µs the PGOOD pin is pulled down.
internal 0.6V reference will be used.
In DDR mode (DDR = VIN), the power good window moves
RT/SYNC (Pin 2/Pin 9): Oscillator Frequency. This pin in relation to the actual TRACK/SS pin voltage. During up/
provides three ways of setting the constant switching down tracking the PGOOD pin is always pulled down.
frequency:
In shutdown the PGOOD output will actively pull down
1. Connecting a resistor from RT/SYNC to ground will set and may be used to discharge the output capacitors via
the switching frequency based on the resistor value. an external resistor.
2. Driving the RT/SYNC pin with an external clock signal MODE (Pin 17/Pin 4): Mode Selection. Tying the MODE
will synchronize the LTC3612 to the applied frequency. pin to SVIN or SGND enables pulse-skipping mode or Burst
The slope compensation is automatically adapted to the Mode operation (with an internal Burst Mode clamp),
external clock frequency. respectively. If this pin is held at slightly higher than half
3. Tying the RT/SYNC pin to SVIN enables the internal of SVIN, forced continuous mode is selected. Connecting
2.25MHz oscillator frequency. this pin to an external voltage selects Burst Mode opera-
tion with the burst clamp set to the pin voltage. See the
SGND (Pin 3/Pin 10): Signal Ground. All small-signal and Operation section for more details.
compensation components should connect to this ground,
which in turn should connect to PGND at a single point. VFB (Pin 18/Pin 5): Voltage Feedback Input Pin. Senses
the feedback voltage from the external resistive divider
NC (Pins 4, 7, 10/Pins 11, 13, 18): Can be connected to across the output.
ground or left open.
ITH (Pin 19/Pin 6): Error Amplifier Compensation. The
SW (Pins 5, 6, 11, 12/Pins 12, 14, 17, 19): Switch Node. current comparator’s threshold increases with this control
Connection to the inductor. This pin connects to the drains voltage. Tying this pin to SVIN enables internal compensa-
of the internal synchronous power MOSFET switches. tion and AVP mode.
PVIN (Pins 8, 9/Pins 15, 16): Power Input Supply. PVIN TRACK/SS (Pin 20/Pin 7): Track/External Soft-Start/Ex-
connects to the source of the internal P-channel power ternal Reference. Start-up behavior is programmable with
MOSFET. This pin is independent of SVIN and may be con- the TRACK/SS pin:
nected to the same voltage or to a lower voltage supply.
1. Tying this pin to SVIN selects the internal soft-start
PVIN_DRV (Pin 13/Pin 20): Internal Gate Driver Input Sup- circuit.
ply. This pin must be connected to PVIN.
2. External soft-start timing can be programmed with a
SVIN (Pin 14/Pin 1): Signal Input Supply. This pin pow- capacitor to ground and a resistor to SVIN.
ers the internal control circuitry and is monitored by the
undervoltage lockout comparator. 3. TRACK/SS can be used to force the LTC3612 to track
the start-up behavior of another supply.
RUN (Pin 15/Pin 2): Enable Pin. Forcing this pin to ground
shuts down the LTC3612. In shutdown, all functions are The pin can also be used as external reference input. See the
disabled and the chip draws <1µA of supply current. Applications Information section for more information.

PGOOD (Pin 16/Pin 3): Power Good. This open-drain PGND (Pin 21/Pin 21): Power Ground. The exposed pad
output is pulled down to SGND on start-up and while the connects to the source of the internal N-channel power
FB voltage is outside the power good voltage window. If MOSFET. This pin should be connected close to the (–)
the FB voltage increases and stays inside the power good terminal of CIN and COUT and soldered to PCB ground for
rated thermal performance.
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10
 LTC3612
FUNCTIONAL Block Diagram
SVIN SGND RT/SYNC ITH PVIN PVIN_DRV
ITH SENSE
COMPARATOR
+
RUN BANDGAP
INTERNAL CURRENT
AND OSCILLATOR
COMPENSATION SENSE
BIAS
SVIN – 0.3V –

PMOS CURRENT
– ITH COMPARATOR
LIMIT +

+
FOLDBACK –
– AMPLIFIER
0.3V

SLOPE
+ COMPENSATION

ERROR
0.6V AMPLIFIER
BURST
+ COMPARATOR
–
VFB SLEEP
–
+
DRIVER
+
MODE
TRACK/SS
SOFT-START

SW

0.555V + SW

SW
– LOGIC
SW

REVERSE
+ COMPARATOR
+
IREV
0.645V –
PGND
PGOOD –

EXPOSED PAD
DDR MODE

3612 BD

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11
LTC3612
Operation
Main Control Loop Mode Selection
The LTC3612 is a monolithic, constant frequency, current The MODE pin is used to select one of four different
mode step-down DC/DC converter. During normal opera- operating modes:
tion, the internal top power switch (P-channel MOSFET) is
Mode Selection Voltage
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips SVIN
PS PULSE-SKIPPING MODE ENABLE
and turns off the top power switch. The peak inductor cur- SVIN – 0.3V
SVIN • 0.58
rent at which the current comparator trips is controlled by
the voltage on the ITH pin. The error amplifier adjusts the FC FORCED CONTINUOUS MODE ENABLE
voltage on the ITH pin by comparing the feedback signal
from a resistor divider on the VFB pin with an internal 0.6V 1.1V

reference. When the load current increases, it causes a 0.8V

BM Burst Mode ENABLE—EXTERNAL CLAMP,
CONTROLLED BY VOLTAGE APPLIED AT
reduction in the feedback voltage relative to the reference. 0.45V
EXT
MODE PIN
The error amplifier raises the ITH voltage until the average 0.3V
BM Burst Mode ENABLE—INTERNAL CLAMP
inductor current matches the new load current. Typical SGND
3612 OP01

voltage range for the ITH pin is from 0.1V to 1.05V with
0.45V corresponding to zero current. Burst Mode Operation—Internal Clamp
When the top power switch shuts off, the synchronous Connecting the MODE pin to SGND enables Burst Mode
power switch (N-channel MOSFET) turns on until either operation with an internal clamp. In Burst Mode operation
the bottom current limit is reached or the next clock cycle the internal power switches operate intermittently at light
begins. The bottom current limit is typically set at –4A for loads. This increases efficiency by minimizing switching
forced continuous mode and 0A for Burst Mode operation losses. During the intervals when the switches are idle,
and pulse-skipping mode. the LTC3612 enters sleep state where many of the internal
circuits are disabled to save power. During Burst Mode
The operating frequency defaults to 2.25MHz when
operation, the minimum peak inductor current is internally
RT/SYNC is connected to SVIN, or can be set by an external
clamped and the voltage on the ITH pin is monitored by
resistor connected between the RT/SYNC pin and ground,
the burst comparator to determine when sleep mode is
or by a clock signal applied to the RT/SYNC pin. The switch-
enabled and disabled. When the average inductor current
ing frequency can be set from 300kHz to 4MHz.
is greater than the load current, the voltage on the ITH pin
Overvoltage and undervoltage comparators pull the drops. As the ITH voltage falls below the internal clamp,
PGOOD output low if the output voltage varies typically the burst comparator trips and enables sleep mode. Dur-
more than ±7.5% from the set point. ing sleep mode, the power MOSFETs are held off and the
load current is solely supplied by the output capacitor.
When the output voltage drops, the top power switch is
turned back on and the internal circuits are re-enabled.
This process repeats at a rate that is dependent on the
load current.

3612fa

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 LTC3612
Operation
Burst Mode Operation—External Clamp Dropout Operation
Connecting the MODE pin to a voltage in the range of 0.45V As the input supply voltage approaches the output voltage,
to 0.8V enables Burst Mode operation with external clamp. the duty cycle increases toward the maximum on-time.
During this mode of operation the minimum voltage on the Further reduction of the supply voltage forces the main
ITH pin is externally set by the voltage on the MODE pin. switch to remain on for more than one cycle, eventually
It is recommended to use Burst Mode operation with an reaching 100% duty cycle. The output voltage will then be
internal clamp for temperatures above 85°C ambient. determined by the input voltage minus the voltage drop
across the internal P-channel MOSFET and the inductor.
Pulse-Skipping Mode Operation
Low Supply Operation
Pulse-skipping mode is similar to Burst Mode operation,
but the LTC3612 does not disable power to the internal The LTC3612 is designed to operate down to an input
circuitry during sleep mode. This improves output voltage supply voltage of 2.25V. An important consideration at low
ripple but uses more quiescent current, compromising input supply voltages is that the RDS(ON) of the P-channel
light load efficiency. and N-channel power switches increases. The user should
calculate the power dissipation when the LTC3612 is used
Tying the MODE pin to SVIN enables pulse-skipping mode.
at 100% duty cycle with low input voltages to ensure that
As the load current decreases, the peak inductor current
thermal limits are not exceeded. See the Typical Perfor-
will be determined by the voltage on the ITH pin until the
mance Characteristics graphs.
ITH voltage drops below the voltage level corresponding to
0A. At this point, the peak inductor current is determined Short-Circuit Protection
by the minimum on-time of the current comparator. If the
load demand is less than the average of the minimum on- The peak inductor current at which the current comparator
time inductor current, switching cycles will be skipped to shuts off the top power switch is controlled by the voltage
keep the output voltage in regulation. on the ITH pin.
If the output current increases, the error amplifier raises the
Forced Continuous Mode ITH pin voltage until the average inductor current matches
In forced continuous mode the inductor current is con- the new load current. In normal operation the LTC3612
stantly cycled which creates a minimum output voltage clamps the maximum ITH pin voltage at approximately
ripple at all output current levels. 1.05V which corresponds typically to 6A peak inductor
current.
Connecting the MODE pin to a voltage in the range of
1.1V to SVIN • 0.58 will enable forced continuous mode When the output is shorted to ground, the inductor current
operation. decays very slowly during a single switching cycle. The
LTC3612 uses two techniques to prevent current runaway
At light loads, forced continuous mode operation is less
from occurring.
efficient than Burst Mode or pulse-skipping operation, but
may be desirable in some applications where it is necessary
to keep switching harmonics out of the signal band.
Forced continuous mode must be used if the output is
required to sink current.

3612fa

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LTC3612
Operation
If the output voltage drops below 50% of its nominal value, current when the output is shorted to ground. It is disabled
the clamp voltage at ITH pin is lowered causing the maxi- during internal or external soft-start and tracking up/down
mum peak inductor current to decrease gradually with the operation (see the Applications Information section).
output voltage. When the output voltage reaches 0V the A secondary limit is also imposed on the valley inductor
clamp voltage at the ITH pin drops to 40% of the clamp current. If the inductor current measured through the
voltage during normal operation. The short-circuit peak bottom MOSFET increases beyond 6A typical, the top
inductor current is determined by the minimum on-time power MOSFET will be held off and switching cycles will
of the LTC3612, the input voltage and the inductor value. be skipped until the inductor current is reduced.
This foldback behavior helps in limiting the peak inductor

Applications Information
The basic LTC3612 application circuit is shown in Figure 1. the ramp current that is used to charge and discharge an
internal timing capacitor within the oscillator and can be
Operating Frequency calculated by using the following equation:
Selection of the operating frequency is a trade-off between
3.82 • 1011Hz
efficiency and component size. High frequency operation RT = Ω – 16kΩ
allows the use of smaller inductor and capacitor values. fOSC Hz ( )
Operation at lower frequencies improves efficiency by Although frequencies as high as 4MHz are possible, the
reducing internal gate charge losses but requires larger minimum on-time of the LTC3612 imposes a minimum
inductance values and/or capacitance to maintain low limit on the operating duty cycle. The minimum on-time
output ripple voltage. is typically 60ns; therefore, the minimum duty cycle is
equal to 100 • 60ns • fOSC(Hz)%.
The operating frequency of the LTC3612 is determined
by an external resistor that is connected between the Tying the RT/SYNC pin to SVIN sets the default internal
RT/SYNC pin and ground. The value of the resistor sets operating frequency to 2.25MHz ±20%.

VIN
2.25V TO 5.5V CIN1 CIN2
RSS 22µF 22µF
2M SVIN PVIN
RUN PVIN_DRV
TRACK/SS DDR L1
CSS RT/SYNC 470nH VOUT
22nF RT 1.8V
RC LTC3612 SW
130k COUT1 COUT2 3A
15k PGOOD SGND
ITH PGND 47µF 22µF
CC1 MODE VFB R1
CC 10pF 392k
470pF (OPT) 3612 F01

R2
196k

Figure 1. 1.8V, 3A Step-Down Regulator

3612fa

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 LTC3612
Applications Information
Frequency Synchronization Inductor Selection
The LTC3612’s internal oscillator can be synchronized to For a given input and output voltage, the inductor value
an external frequency by applying a square wave clock and operating frequency determine the ripple current. The
signal to the RT/SYNC pin. During synchronization, the top ripple current ∆IL increases with higher VIN and decreases
switch turn-on is locked to the falling edge of the external with higher inductance:
frequency source. The synchronization frequency range
is 300kHz to 4MHz. During synchronization all operation  V   V 
∆IL =  OUT  •  1– OUT 
modes can be selected.  fSW • L   VIN 
It is recommended that the regulator is powered down
Having a lower ripple current reduces the core losses
(RUN pin to ground) before removing the clock signal
in the inductor, the ESR losses in the output capacitors
on the RT/SYNC pin in order to reduce inductor current
and the output voltage ripple. A reasonable starting point
ripple.
for selecting the ripple current is ∆IL = 0.3 • IOUT(MAX).
AC coupling should be used if the external clock genera- The largest ripple current occurs at the highest VIN. To
tor cannot provide a continuous clock signal throughout guarantee that the ripple current stays below a specified
start-up, operation and shutdown of the LTC3612. The maximum, the inductor value should be chosen according
size of capacitor CSYNC depends on parasitic capacitance to the following equation:
on the RT/SYNC pin and is typically in the range of 10pF
to 22pF  VOUT   VOUT 
L=  •  1– V 
 fSW • ∆IL(MAX)   IN 
VIN
LTC3612
SVIN fOSC
RT/SYNC 2.25MHz The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
VIN when the peak inductor current falls below a level set by the
LTC3612
SVIN
burst clamp. Lower inductor values result in higher ripple
fOSC t1/RT
0.4V
RT/SYNC current which causes this to occur at lower load currents.
RT SGND
This causes a dip in efficiency in the upper range of low cur-
rent operation. In Burst Mode operation, lower inductance
VIN
values will cause the burst frequency to increase.
LTC3612
SVIN fOSC
RT/SYNC 1/TP Inductor Core Selection
SGND
Once the value for L is known, the type of inductor must be
1.2V
0.3V selected. Actual core loss is independent of core size for
TP
fixed inductor value, but it is very dependent on the induc-
VIN tance selected. As the inductance increases, core losses de-
LTC3612
CSYNC
SVIN fOSC
crease. Unfortunately, increased inductance requires more
RT/SYNC 1/TP turns of wire and therefore, copper losses will increase.
SGND

RT
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can con-
3612 F02 centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” meaning that inductance
Figure 2. Setting the Switching Frequency collapses abruptly when the peak design current is ex-
ceeded. This results in an abrupt increase in inductor
3612fa

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LTC3612
Applications Information
ripple current and consequently output voltage ripple. Do Table 1. Representative Surface Mount Inductors
not allow a ferrite core to saturate! INDUCTANCE DCR MAX DIMENSIONS HEIGHT
(µH) (mΩ) CURRENT (A) (mm) (mm)
Different core materials and shapes will change the size/cur- Vishay IHLP-2525AH-01 Series
rent and price/current relationship of an inductor. Toroid 0.33 7 12 6.7 × 7 1.8
or shielded pot cores in ferrite or permalloy materials are 0.47 9 11 6.7 × 7 1.8
small and do not radiate much energy, but generally cost 0.68 13 9 6.7 × 7 1.8
more than powdered iron core inductors with similar 0.82 15 8 6.7 × 7 1.8
characteristics. The choice of which style inductor to use 1.0 18 7 6.7 × 7 1.8
mainly depends on the price versus size requirements Vishay IHLP-1616BZ-01 Series
and any radiated field/EMI requirements. Table 1 shows 0.22 8 24 4.3 × 4.7 2
some typical surface mount inductors that work well in 0.47 18 11.5 4.3 × 4.7 2
LTC3612 applications. 1.00 37 8.5 4.3 × 4.7 2
Sumida CDMC6D28 Series
Input Capacitor (CIN) Selection 0.3 3.2 15.4 6.7 × 7.25 3

In continuous mode, the source current of the top P-chan- 0.47 4.2 13.6 6.7 × 7.25 3

nel MOSFET is a square wave of duty cycle VOUT/VIN. To 0.68 5.4 11.3 6.7 × 7.25 3

prevent large voltage transients, a low ESR capacitor sized 1 8.8 8.8 6.7 × 7.25 3

for the maximum RMS current must be used at VIN. NEC/Tokin MPLC0730L Series
0.47 4.5 16.6 6.9 × 7.7 3.0
The maximum RMS capacitor current is given by: 0.75 7.5 12.2 6.9 × 7.7 3.0
1.0 9.0 10.6 6.9 × 7.7 3.0
V  V 
IRMS =IOUT(MAX) • OUT •  IN – 1 Cooper HCP0703 Series
VIN  VOUT  0.22 2.8 23 7 × 7.3 3.0
0.47 4.2 17 7 × 7.3 3.0
This formula has a maximum at VIN = 2VOUT , where IRMS =
0.68 5.5 15 7 × 7.3 3.0
IOUT/2. This simple worst-case condition is commonly used
0.82 8.0 13 7 × 7.3 3.0
for design because even significant deviations do not offer
1.0 10.0 11 7 × 7.3 3.0
much relief. Note that ripple current ratings from capacitor
1.5 9.6 61 6.9 × 7.3 3.2
manufacturers are often based on only 2000 hours of life
Würth Elektronik WE-HC744312 Series
which makes it advisable to further derate the capacitor, 0.25 2.5 18 3.8
7 × 7.7
or choose a capacitor rated at a higher temperature than 0.47 3.4 16 3.8
7 × 7.7
required. Several capacitors may also be paralleled to meet 0.72 7.5 12 3.8
7 × 7.7
size or height requirements in the design. 1.0 9.5 11 3.8
7 × 7.7
1.5 10.5 9 7 × 7.7 3.8
Output Capacitor (COUT ) Selection
Coilcraft DO1813H Series
The selection of COUT is typically driven by the required 0.33 4 10 8.9 × 6.1 5
ESR to minimize voltage ripple and load step transients 0.56 10 7.7 8.9 × 6.1 5
(low ESR ceramic capacitors are discussed in the next Coilcraft v Series
section). Typically, once the ESR requirement is satisfied, 0.27 0.1 14 7.5 × 6.7 3
the capacitance is adequate for filtering. The output ripple 0.35 0.1 11 7.5 × 6.7 3
∆VOUT is determined by: 0.4 0.1 8 7.5 × 6.7 3

 1 
∆VOUT ≤ ∆IL •  ESR +
 8 • fSW • COUT 
3612fa

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 LTC3612
Applications Information
where fOSC = operating frequency, COUT = output capaci- must instantaneously supply the current to support the
tance and ∆IL = ripple current in the inductor. The output load until the feedback loop raises the switch current
ripple is highest at maximum input voltage since ∆IL enough to support the load. The time required for the
increases with input voltage. feedback loop to respond is dependent on the compensa-
tion components and the output capacitor size. Typically,
In surface mount applications, multiple capacitors may
3 to 4 cycles are required to respond to a load step, but
have to be paralleled to meet the capacitance, ESR or RMS
only in the first cycle does the output drop linearly. The
current handling requirement of the application. Aluminum
output droop, VDROOP , is usually about 2 to 4 times the
electrolytic, special polymer, ceramic and dry tantalum
linear drop of the first cycle; however, this behavior can
capacitors are all available in surface mount packages.
vary depending on the compensation component values.
Tantalum capacitors have the highest capacitance density, Thus, a good place to start is with the output capacitor
but can have higher ESR and must be surge tested for size of approximately:
use in switching power supplies. Aluminum electrolytic
3.5 • ∆IOUT
capacitors have significantly higher ESR, but can often COUT ≈
be used in extremely cost-sensitive applications provided fSW • VDROOP
that consideration is given to ripple current ratings and
This is only an approximation; more capacitance may
long term reliability.
be needed depending on the duty cycle and load step
Ceramic Input and Output Capacitors requirements.

Ceramic capacitors have the lowest ESR and can be cost In most applications, the input capacitor is merely required
effective, but also have the lowest capacitance density, to supply high frequency bypassing, since the impedance
high voltage and temperature coefficients, and exhibit to the supply is very low.
audible piezoelectric effects. In addition, the high-Q of
Output Voltage Programming
ceramic capacitors along with trace inductance can lead
to significant ringing. The output voltage is set by an external resistive divider
according to the following equation:
They are attractive for switching regulator use because
of their very low ESR, but great care must be taken when  R1
VOUT = 0.6 •  1+  V
using only ceramic input and output capacitors.  R2 
Ceramic capacitors are prone to temperature effects
The resistive divider allows pin VFB to sense a fraction of
which require the designer to check loop stability over
the output voltage, as shown in Figure 1.
the operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R Burst Clamp Programming
ceramic capacitors should be used.
If the voltage on the MODE pin is less than 0.8V, Burst
When a ceramic capacitor is used at the input and the power Mode operation is enabled.
is being supplied through long wires, such as from a wall
adapter, a load step at the output can induce ringing at the If the voltage on the MODE pin is less than 0.3V, the internal
VIN pin. At best, this ringing can couple to the output and default burst clamp level is selected. The minimum voltage
be mistaken as loop instability. At worst, the ringing at the on the ITH pin is typically 525mV (internal clamp).
input can be large enough to damage the part. If the voltage is between 0.45V and 0.8V, the voltage on
Since the ESR of a ceramic capacitor is so low, the input the MODE pin (VBURST) is equal to the minimum voltage
and output capacitor must instead fulfill a charge storage on the ITH pin (external clamp) and determines the burst
requirement. During a load step, the output capacitor clamp level IBURST (typically from 0A to 3.5A).

3612fa

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LTC3612
Applications Information
When the ITH voltage falls below the internal (or external) ITH pin allows the transient response to be optimized over
clamp voltage, the sleep state is enabled. a wide range of output capacitance.
As the output load current drops, the peak inductor current The ITH external components (RC and CC) shown in Fig-
decreases to keep the output voltage in regulation. When ure 1 provide adequate compensation as a starting point
the output load current demands a peak inductor current for most applications. The values can be modified slightly
that is less than IBURST , the burst clamp will force the peak to optimize transient response once the final PCB layout
inductor current to remain equal to IBURST regardless of is done and the particular output capacitor type and value
further reductions in the load current. have been determined. The output capacitors need to be
selected because the various types and values determine
Since the average inductor current is greater than the output
the loop gain and phase. The gain of the loop will be in-
load current, the voltage on the ITH pin will decrease. When
creased by increasing RC and the bandwidth of the loop
the ITH voltage drops, sleep mode is enabled in which
will be increased by decreasing CC. If RC is increased by
both power switches are shut off along with most of the
the same factor that CC is decreased, the zero frequency
circuitry to minimize power consumption. All circuitry is
will be kept the same, thereby keeping the phase shift the
turned back on and the power switches resume opera-
same in the most critical frequency range of the feedback
tion when the output voltage drops out of regulation. The
loop. The output voltage settling behavior is related to the
value for IBURST is determined by the desired amount of
stability of the closed-loop system. The external capaci-
output voltage ripple. As the value of IBURST increases, the
tor, CC1, (Figure 1) is not needed for loop stability, but it
sleep period between pulses and the output voltage ripple
helps filter out any high frequency noise that may couple
increase. Note that for very high VBURST voltage settings,
onto that node. The general purpose buck regulator ap-
the power good comparator may trip, since the output
plication in the Typical Applications section uses a faster
ripple may get bigger than the power good window.
compensation to improve load step response.
Pulse-skipping mode, which is a compromise between low
A second, more severe transient is caused by switching
output voltage ripple and efficiency, can be implemented
in loads with large (>1μF) supply bypass capacitors. The
by connecting MODE to SVIN. This sets IBURST to 0A. In
discharged bypass capacitors are effectively put in parallel
this condition, the peak inductor current is limited by the
with COUT , causing a rapid drop in VOUT . No regulator can
minimum on-time of the current comparator. The lowest
alter its delivery of current quickly enough to prevent this
output voltage ripple is achieved while still operating
sudden step change in output voltage if the load switch
discontinuously. During very light output loads, pulse
resistance is low and it is driven quickly. More output
skipping allows only a few switching cycles to skip while
capacitance may be required depending on the duty cycle
maintaining the output voltage in regulation.
and load step requirements.
Internal and External Compensation
AVP Mode
The regulator loop response can be checked by looking at
Fast load transient response, limited board space and low
the load current transient response. Switching regulators
cost are typical requirements of microprocessor power
take several cycles to respond to a step in DC load current.
supplies. A microprocessor has typical full load step with
When a load step occurs, VOUT shifts by an amount equal
very fast slew rate. The voltage at the microprocessor must
to ∆ILOAD(ESR), where ESR is the effective series resistance
be held to about ±0.1V of nominal in spite of these load
of COUT . ∆ILOAD also begins to charge or discharge COUT ,
current steps. Since the control loop cannot respond this
generating the feedback error signal that forces the regula-
fast, the output capacitors must supply the load current
tor to adapt to the current change and return VOUT to its
until the control loop can respond.
steady-state value. During this recovery time VOUT can
be monitored for excessive overshoot or ringing, which Normally, several capacitors in parallel are required to
would indicate a stability problem. The availability of the meet microprocessor transient requirements. Capacitor
3612fa

18
 LTC3612
Applications Information
ESR and ESL primarily determine the amount of droop or output voltage can have more overshoot and stay within
overshoot in the output voltage. the specified voltage range (see Figures 3 and 4).
Consider the LTC3612 without AVP with a bank of tantalum The benefit is a lower peak-to-peak output voltage deviation
output capacitors. If a load step with very fast slew rate for a given load step without having to increase the output
occurs, the voltage excursion will be seen in both direc- filter capacitance. Alternatively, the output voltage filter ca-
tions, for full load to minimum load transient and for the pacitance can be reduced while maintaining the same peak
minimum load to full load transient. to peak transient response. Due to the reduced loop gain
in AVP mode, no external compensation is required.
If the ITH pin is tied to SVIN, the active voltage positioning
(AVP) mode and internal compensation are selected. DDR Mode
AVP mode intentionally compromises load regulation by The LTC3612 can both source and sink current if the MODE
reducing the gain of the feedback circuit, resulting in an pin is configured to forced continuous mode.
output voltage that varies with load current. When the load
current suddenly increases, the output voltage starts from Current sinking is typically limited to 1.5A, for 1MHz
a level slightly higher than nominal so the output voltage frequency and a 1µH inductor, but can be lower at higher
can droop more and stay within the specified voltage frequencies and low output voltages. If higher ripple current
range. When the load current suddenly decreases the can be tolerated, smaller inductor values can increase the
output voltage starts at a level lower than nominal so the sink current limit. See the Typical Performance Charac-
teristics curves for more information.
In addition, tying the DDR pin to SVIN, lower external
VOUT
200mV/DIV
reference voltage and tracking output voltage between
channels are possible. See the Output Voltage Tracking
IL and External Reference Input sections.
1A/DIV

Soft-Start
3612 F03
VIN = 3.3V 50µs/DIV
VOUT = 1.8V The RUN pin provides a means to shut down the LTC3612.
ILOAD = 100mA TO 3A
VMODE = 1.5V
Tying the RUN pin to SGND places the LTC3612 in a low
COMPENSATION FIGURE 1 quiescent current shutdown state (IQ < 1µA).
Figure 3. Load Step Transient Forced Continuous Mode The LTC3612 is enabled by pulling the RUN pin high.
(AVP Inactive)
However, the applied voltage must not exceed SVIN. In
some applications, the RUN signal is generated within
another power domain and is driven high while the SVIN
VOUT
100mV/DIV
and PVIN is still 0V. In this case, it’s required to limit the
current into the RUN pin by either adding a 1MΩ resistor
IL
1A/DIV
or a 100kΩ resistor, plus a Schottky diode, to SVIN. After
pulling the RUN pin high, the chip enters a soft start-up
state. This type of soft start-up behavior is set by the
VIN = 3.3V 50µs/DIV 3612 F04 TRACK/SS pin:
VOUT = 1.8V
ILOAD = 100mA TO 3A 1. Tying TRACK/SS to SVIN selects the internal soft-start
VMODE = 1.5V
VITH = 3.3V circuit. This circuit ramps the output voltage to the final
OUTPUT CAPACITOR VALUE FIGURE 1
value within 1ms.
Figure 4. Load Step Transient Forced Continuous Mode 2. If a longer soft-start period is desired, it can be set ex-
with AVP Mode
ternally with a resistor and capacitor on the TRACK/SS
3612fa

19
LTC3612
Applications Information
pin, as shown in Figure 1. The TRACK/SS pin reduces VOUT1
the value of the internal reference at VFB until TRACK/SS
is pulled above 0.6V. The external soft-start duration

OUTPUT VOLTAGE
can be calculated by using the following formula:
VOUT2
 SVIN 
t SS = RSS • CSS • ln
 SVIN – 0.6V 

3. The TRACK/SS pin can be used to track the output TIME
voltage of another supply. (5a) Coincident Tracking
Each time the RUN pin is tied high and the LTC3612 is
turned on, the TRACK/SS pin is internally pulled down
for ten microseconds in order to discharge the external VOUT1

capacitor. This discharging time is typically adequate

OUTPUT VOLTAGE
for capacitors up to about 33nF. If a larger capacitor is
required, connect the external soft-start resistor to the VOUT2
RUN pin.
Regardless of either internal or external soft-start state,
the MODE pin is ignored and soft-start will always be
in pulse-skipping mode. In addition, the PGOOD pin
3612 F05
TIME
is kept low and foldback of the switching frequency is (5b) Ratiometric Tracking
disabled.
Figure 5. Two Different Modes of Output Voltage Tracking
Output Voltage Tracking Input
If the DDR pin is not tied to SVIN, once VTRACK/SS exceeds To implement the coincident tracking behavior in Fig-
0.6V, the run state is entered and the MODE selection, power ure 5a, connect an extra resistive divider to the output
good and current foldback circuits are enabled. of the master channel and connect its midpoint to the
In the run state, the TRACK/SS pin can be used for track- TRACK/SS pin for the slave channel. The ratio of this
ing down/up the output voltage of another supply. If the divider should be selected to be the same as that of the
VTRACK/SS drops below 0.6V, the LTC3612 enters the down slave channel’s feedback divider (Figure 6a). In this track-
tracking state and VOUT is referenced to the TRACK/SS volt- ing mode, the master channel’s output must be set higher
age. If the TRACK/SS pin drops below 0.2V, the switching than slave channel’s output. To implement the ratiometric
frequency is reduced to ensure that the minimum duty tracking behavior in Figure 5b, different resistor divider
cycle limit does not prevent the output from following values must be used as specified in Figure 6b.
the TRACK/SS pin. The run state will resume if VTRACK/SS For coincident start-up, the voltage value at the TRACK/SS
again exceeds 0.6V and VOUT is referenced to the internal pin for the slave channel needs to reach the final reference
precision reference (see Figure 7). value after the internal soft-start time (around 1ms). The
Through the TRACK/SS pin, the output voltage can be set master start-up time needs to be adjusted with an external
up for either coincident or ratiometric tracking, as shown capacitor and resistor to ensure this.
in Figure 5.

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20
 LTC3612
Applications Information
VOUT2
VOUT1 where L1, L2, etc. are the individual losses as a percent-
age of input power.
R4 R4 R3
VFB2 VFB1 VIN Although all dissipative elements in the circuit produce
R2 LTC3612 R2 R2 LTC3612
losses, two main sources usually account for most of
the losses: VIN quiescent current and I2R losses. The VIN
TRACK/SS2 TRACK/SS1
R4 ≤ R3 quiescent current loss dominates the efficiency loss at
LTC3612 CHANNEL 2 LTC3612 CHANNEL 1
3612 F06a
very low load currents whereas the I2R loss dominates
SLAVE MASTER the efficiency loss at medium to high load currents. In a
Figure 6a. Set-Up for Coincident Tracking typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
VOUT2
VOUT1
usually of no consequence.
R1 R5 R3 R1/R2 < R5/R6 1. The VIN quiescent current is due to two components: the
VFB2 VFB1 DC bias current as given in the Electrical Characteristics
R2 LTC3612 R6 R4 LTC3612 and the internal main switch and synchronous switch
TRACK/SS2 TRACK/SS1 VIN
gate charge currents. The gate charge current results
LTC3612 CHANNEL 2 LTC3612 CHANNEL 1
from switching the gate capacitance of the internal power
SLAVE MASTER 3612 F06b MOSFET switches. Each time the gate is switched from
Figure 6b. Set-Up for Ratiometric Tracking low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current
External Reference Input (DDR Mode) out of VIN due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
If the DDR pin is tied to SVIN (DDR mode), the run state
charge losses are proportional to VIN; thus, their effects
is entered when VTRACK/SS exceeds 0.3V and tracking
will be more pronounced at higher supply voltages.
down behavior is possible if the VTRACK/SS voltage is
below 0.6V. 2. I2R losses are calculated from the resistances of the
internal switches, RSW , and external inductor, RL. In
This allows TRACK/SS to be used as an external reference
continuous mode the average output current flowing
between 0.3V and 0.6V if desired. During the run state in
through inductor L is “chopped” between the main
DDR mode, the power good window moves in relation
switch and the synchronous switch. Thus, the series
to the actual TRACK/SS pin voltage if the voltage value
resistance looking into the SW pin is a function of both
is between 0.3V and 0.6V. Note: if TRACK/SS voltage is
top and bottom MOSFET RDS(ON) and the duty cycle
0.6V, either the tracking circuit or the internal reference
(DC) as follows:
can be used.
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
During up/down tracking the output current foldback is
disabled and the PGOOD pin is always pulled down (see The RDS(ON) for both the top and bottom MOSFETs can
Figure 8). be obtained from the Typical Performance Character-
istics curves. To obtain I2R losses, simply add RSW to
Efficiency Considerations RL and multiply the result by the square of the average
The efficiency of a switching regulator is equal to the output output current.
power divided by the input power times 100%. It is often Other losses including CIN and COUT ESR dissipative
useful to analyze individual losses to determine what is losses and inductor core losses generally account for
limiting the efficiency and which change would produce less than 2% of the total loss.
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
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21
LTC3612
Applications Information

VFB PIN 0.6V

VOLTAGE 0V

0.6V
TRACK/SS
PIN VOLTAGE 0.2V
0V

VIN
RUN PIN
VOLTAGE
0V
VIN
SVIN PIN
VOLTAGE
0V
TIME
SHUTDOWN SOFT-START RUN STATE REDUCED RUN STATE
STATE STATE SWITCHING 3612 F07
tSS > 1ms FREQUENCY
DOWN UP
TRACKING TRACKING
STATE STATE

Figure 7. DDR Pin Not Tied to SVIN

0.45V
VFB PIN 0.3V
VOLTAGE 0V
EXTERNAL
VOLTAGE
REFERENCE 0.45V
0.45V
TRACK/SS 0.3V
PIN VOLTAGE 0.2V
0V

VIN
RUN PIN
VOLTAGE
0V
VIN
SVIN PIN
VOLTAGE
0V
TIME
SHUTDOWN SOFT-START RUN STATE REDUCED RUN STATE
STATE STATE SWITCHING 3612 F08
tSS > 1ms FREQUENCY
DOWN UP
TRACKING TRACKING
STATE STATE

Figure 8. DDR Pin Tied to SVIN. Example DDR Application

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22
 LTC3612
Applications Information
Thermal Considerations Note that for very low input voltage, the junction tempera-
In most applications, the LTC3612 does not dissipate much ture will be higher due to increased switch resistance,
heat due to its high efficiency. RDS(ON). It is not recommended to use full load current
for high ambient temperature and low input voltage.
However, in applications where the LTC3612 is running at
high ambient temperature with low supply voltage and high To maximize the thermal performance of the LTC3612 the
duty cycles, such as in dropout, the heat dissipated may Exposed Pad should be soldered to a ground plane. See
exceed the maximum junction temperature of the part. If the PCB Layout Board Checklist.
the junction temperature reaches approximately 160°C,
Design Example
both power switches will be turned off and the SW node
will become high impedance. As a design example, consider using the LTC3612 in an
application with the following specifications:
To prevent the LTC3612 from exceeding the maximum
junction temperature, some thermal analysis is required. VIN = 2.25V to 5.5V, VOUT = 1.8V, IOUT(MAX) = 3A, IOUT(MIN)
The temperature rise is given by: = 100mA, f = 2.6MHz.
TRISE = (PD)(θJA) Efficiency is important at both high and low load current,
so Burst Mode operation will be utilized.
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to First, calculate the timing resistor:
the ambient temperature. The junction temperature, TJ,
is given by: 3.82 • 1011Hz
RT = Ω – 16kΩ = 130kΩ
2.6MHz
TJ = TA + TRISE
where TA is the ambient temperature. Next, calculate the inductor value for about 30% ripple
current at maximum VIN:
As an example, consider the case when the LTC3612 is in
dropout at an input voltage of 3.3V with a load current of  1.8V   1.8V 
L= • 1– = 0.466µH
3A at an ambient temperature of 70°C. From the Typical  2.6MHz • 1A   5.5V 
Performance Characteristics graph of Switch Resistance,
the RDS(ON) resistance of the P‑channel switch is 0.075Ω. Using a standard value of 0.47µH inductor results in a
Therefore, power dissipated by the part is: maximum ripple current of:
PD = (IOUT)2 • RDS(ON) = 675mW  1.8V   1.8V 
∆IL =  •  1–  = 0.99A
For the QFN package, the θJA is 43°C/W.  2.6MHz • 0.47µH  5.5V 

Therefore, the junction temperature of the regulator operat- COUT will be selected based on the ESR that is required to
ing at 70°C ambient temperature is approximately: satisfy the output voltage ripple requirement and the bulk
TJ = 0.675W • 43°C/W + 70°C = 99°C capacitance needed for loop stability. For this design, a
68µF (or 47µF plus 22µF) ceramic capacitor is used with
We can safely assume that the actual junction temperature a X5R or X7R dielectric.
will not exceed the absolute maximum junction tempera-
ture of 125°C.

3612fa

23
LTC3612
Applications Information
CIN should be sized for a maximum current rating of: PC Board Layout Checklist

1.8V  3.6V  When laying out the printed circuit board, the following
IRMS = 3A • •  – 1 = 1.5ARMS checklist should be used to ensure proper operation of
3.6V  1.8V 
the LTC3612:
Decoupling the PVIN with two 22µF capacitors, is adequate 1. A ground plane is recommended. If a ground plane layer
for most applications. is not used, the signal and power grounds should be
segregated with all small-signal components returning
If we set R2 = 196k, the value of R1 can now be determined
to the SGND pin at one point which is then connected
by solving the following equation.
to the PGND pin close to the LTC3612.
 1.8V  2. Connect the (+) terminal of the input capacitor(s), CIN,
R1 = 196k •  −1
 0.6V  as close as possible to the PVIN pin, and the (–) terminal
as close as possible to the exposed pad, PGND. This
A value of 392k will be selected for R1.
capacitor provides the AC current into the internal power
Finally, define the soft start-up time choosing the proper MOSFETs.
value for the capacitor and the resistor connected to
3. Keep the switching node, SW, away from all sensitive
TRACK/SS. If we set minimum tSS = 5ms and a resistor
small-signal nodes.
of 2M, the following equation can be solved with the
maximum SVIN = 5.5V : 4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
5ms
CSS = = 21.6nF power components. Connect the copper areas to PGND
 5.5V  (exposed pad) for best performance.
2M •In 
 5.5V – 0.6V 
5. Connect the VFB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
The standard value of 22nF guarantees the minimum
and SGND.
soft-start up time of 5ms.
Figure 1 shows the schematic for this design example.

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24
 LTC3612
Typical Applications
General Purpose Buck Regulator Using Ceramic Capacitors, 2.25MHz

VIN
2.25V TO 5.5V C2 C1 RF
22µF 22µF 24Ω
CF
1µF
RSS SVIN PVIN
4.7M RUN PVIN_DRV
TRACK/SS DDR
CSS RT/SYNC L1
10nF LTC3612 470nH
R4 VOUT
RC 100k SW 1.8V
CO1 CO2 3A
43k PGOOD PGOOD SGND
47µF 22µF
ITH PGND
CC CC1 R5A MODE VFB R1
220pF 10pF 1M 392k

R5B R2 C3
1M 196k 22pF
L1: VISHAY IHLP-2020BZ 0.47µH 3612 TA02a

Efficiency vs Output Current Load Step Response in Forced Continuous Mode

100
90
VOUT
80 100mV/DIV
70
EFFICIENCY (%)

60
50 IOUT
1A/DIV
40
30
VIN = 2.5V
20
VIN = 3.3V VIN = 3.3V 20µs/DIV 3612 TA02c

10 VIN = 4V VOUT = 1.8V

VIN = 5.5V IOUT = 100mA TO 3A
0 VMODE = 1.5V
1 10 100 1000 10000
OUTPUT CURRENT (mA)
3612 TA02b

3612fa

25
LTC3612
Typical Applications
Master and Slave for Coincident Tracking Outputs Using a 1MHz External Clock

VIN
2.25V TO 5.5V C2 C1 RF1
22µF 22µF 4.7M 24Ω
CF1
10nF
1µF
SVIN PVIN
RUN PVIN_DRV
TRACK/SS DDR CHANNEL 1
1MHz MASTER
RT/SYNC L1
CLOCK
R5 LTC3612 1µH VOUT1
RC1 100k SW 1.8V
CO11 CO12 3A
15k PGOOD PGOOD SGND
47µF 22µF
ITH PGND
CC1 CC2 MODE VFB R1
470pF 10pF 4.7M R3
715k 464k
R2 C3
4.7M 357k 22pF R4
464k

C5 C6 RF2
22µF 22µF 24Ω
CF2
1µF
SVIN PVIN
RUN PVIN_DRV CHANNEL 2
TRACK/SS DDR SLAVE
RT/SYNC L2
R7 LTC3612 1µH VOUT2
RC2 100k SW 1.2V
CO21 CO22 3A
15k PGOOD PGOOD SGND
47µF 22µF
ITH PGND
CC3 CC4 MODE VFB R5
470pF 10pF 301k

R6 C7
301k 22pF
3612 TA03a

Coincident Start-Up Coincident Tracking Up/Down

VOUT1

VOUT2 VOUT1
500mV/DIV 500mV/DIV VOUT2

2ms/DIV 3612 TA03b

200ms/DIV 3612 TA03c

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26
 LTC3612
Package Description
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)

0.70 ±0.05

3.50 ± 0.05
2.10 ± 0.05 2.65 ± 0.05
1.50 REF
1.65 ± 0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ± 0.05
4.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.25
0.75 ± 0.05
1.50 REF s 45° CHAMFER
3.00 ± 0.10 R = 0.05 TYP
19 20
0.40 ± 0.10

PIN 1 1
TOP MARK 2
(NOTE 6)
2.65 ± 0.10
4.00 ± 0.10 2.50 REF
1.65 ± 0.10

(UDC20) QFN 1106 REV Ø

0.200 REF 0.25 ± 0.05

R = 0.115
0.00 – 0.05 TYP 0.50 BSC
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

3612fa

27
LTC3612
Package Description
FE Package
20-Lead Plastic eTSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev G)
Exposed Pad Variation CB

6.40 – 6.60*
3.86 (.252 – .260)
(.152) 3.86
(.152)
20 1918 17 16 15 14 13 12 11

6.60 p0.10
2.74
4.50 p0.10 (.108)
6.40
SEE NOTE 4 2.74 (.252)
(.108) BSC
0.45 p0.05

1.05 p0.10

0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0o – 8o

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE20 (CB) eTSSOP REV G 0510
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
MILLIMETERS FOR EXPOSED PAD ATTACHMENT
2. DIMENSIONS ARE IN
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

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28
 LTC3612
Revision History
REV DATE DESCRIPTION PAGE NUMBER
A 08/10 Updated Temperature Range in Order Information 2
Edited Electrical Characteristics table and updated Note 2 3, 4
Updated text in graphs G19, G31 7, 9
Updated Pin 16/Pin 3 and Pin 21/Pin 21 text 10
Updated Functional Block Diagram 11
Updated Burst Mode Operation—External Clamp section 13
Updated Internal and External Compensation section 18
Updated Soft-Start section 19
Updated Timing Resistor equation in Design Example section 23
Updated TA02a and TA02c in Typical Applications 25
Updated Related Parts 30

3612fa

29
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3612
Typical Application
DDR Termination with Ratiometric Tracking of VDD, 1MHz

VIN
3.3V C1 C2
22µF 22µF SVIN PVIN
RUN PVIN_DRV
VDD
1.8V TRACK/SS DDR
R6 RT/SYNC
562k R3 R8
100k LTC3612 L1
365k
R7 1µH VTT
187k PGOOD PGOOD SW 0.9V
C4 C5 ±1.5A
RC
SGND 100µF 47µF
6k
ITH PGND
CC CC1 MODE VFB R1
R4 2.2nF 10pF 200k
1M
R2 C3
R5 L1: COILCRAFT DO3316T 200k 22pF
1M 3612 TA04a

Ratiometric Start-Up

VDD

500mV/DIV VTT

500µs/DIV 3612 TA04b

Related Parts
PART NUMBER DESCRIPTION COMMENTS
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Converter with Tracking and DDR ISD < 1µA, 3mm × 5mm QFN-24 Package
LTC3616 5.5V, 6A (IOUT), 4MHz, Synchronous Step-Down DC/DC 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA,
Converter with Tracking and DDR ISD < 1µA, 3mm × 5mm QFN-24 Package
LTC3601 15V, 1.5A (IOUT), Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA,
ISD < 1µA, MSOP-16E and 3mm × 3mm QFN-16 Packages
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4mm × 4mm QFN-16 Package
LTC3605 15V, 5A (IOUT), Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4V to 15V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15µA,
4mm × 4mm QFN-24 Package
LTC3412A 5.5V, 3A (IOUT), 4MHz, Synchronous Step-Down 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA,
DC/DC Converter ISD < 1µA, TSSOP-16E and 4mm × 4mm QFN-16 Packages
LTC3413 5.5V, 3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous 90% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = VREF /2, IQ = 280µA,
Regulator for DDR/QDR Memory Termination ISD < 1µA, TSSOP-16E Package

3612fa

30 Linear Technology Corporation

LT 0810 REV A • PRINTED IN USA

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