LTC3536

1A Low Noise, Buck-Boost

DC/DC Converter

Features Description
n Regulated Output with Input Voltage Above, Below The LTC®3536 is an extended VIN range, fixed frequency,
or Equal to the Output Voltage synchronous buck-boost DC/DC converter that operates
n 1.8V to 5.5V Input and Output Voltage Range from input voltages above, below or equal to the regulated
n 1A Continuous Output Current for output voltage. The topology incorporated in the LTC3536
VIN ≥ 3V, VOUT = 3.3V provides low noise operation, making it ideal for RF and
n ±1% Output Voltage Accuracy precision measurement applications.
n Low Noise Buck-Boost Architecture
The device can produce up to 1A of continuous output
n Up to 95% Efficiency
current, and it includes two N-channel and two P-channel
n Programmable Frequency from 300kHz to 2MHz
MOSFET switches. Switching frequencies up to 2MHz can
n Synchronizable Oscillator
be programmed with an external resistor and the oscilla-
n Burst Mode® Operation: 32µA IQ tor can be synchronized to an external clock. Quiescent
n Internal 1ms Soft-Start
current is only 32µA in Burst Mode operation, maximizing
n Output Disconnect in Shutdown
battery life in portable applications. Burst Mode operation
n Shutdown Current: 1µA
is user controlled and improves efficiency at light loads.
n Short-Circuit Protection
n Small Thermally Enhanced 12-Pin MSOP Other features include a 1µA shutdown current, internal
and 10-Pin (3mm × 3mm) DFN Packages soft-start, overtemperature protection and current limit.
The LTC3536 is available in 12-pin thermally enhanced
MSOP and 10-pin (3mm × 3mm) DFN packages.
Applications L, LT, LTC, LTM, Burst Mode, LTspice, Linear Technology and the Linear logo are registered
n Wireless Inventory Terminals trademarks and PowerPath and No RSENSE are trademarks of Linear Technology Corporation. All
other trademarks are the property of their respective owners.
n Handheld Medical Instruments
n Wireless Locators, Microphones
n Supercapacitor Backup Power Supply

Typical Application
Efficiency vs Input Voltage
100
4.7µH ILOAD = 200mA
95
90
SW1 SW2 VOUT
VIN 85
VIN VOUT 3.3V ILOAD = 1A
1.8V TO 5.5V
EFFICIENCY (%)

47pF 1A FOR VIN ≥ 3V 80

LTC3536
6.49k 75
1000k
PWM BURST MODE/SYNC FB 70
10µF OFF ON 220pF 22µF
SHDN 49.9k
RT 65
VC
PGND SGND 60
221k
55
3536 TA01a
50
1.5 2 2.5 3 3.5 4 4.5 5 5.5
INPUT VOLTAGE (V)
3536 TA01b

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LTC3536
Absolute Maximum Ratings (Note 1)
VIN, VOUT, (SVIN, PVIN) Voltage..................... –0.3V to 6V Operating Junction Temperature Range
SW1, SW2 Voltage (Notes 2, 3)............................................. –40°C to 125°C
DC............................................................. –0.3V to 6V Storage Temperature Range................... –65°C to 150°C
Pulsed (<100ns).........................................–1.0V to 7V Lead Temperature (Soldering, 10 sec)
VC, RT, FB, SHDN Voltage............................. –0.3V to 6V MSE................................................................... 300°C
MODE/SYNC Voltage.................................... –0.3V to 6V

Pin Configuration
TOP VIEW TOP VIEW

RT 1 12 VC
RT 1 10 VC
SGND 2 11 FB
SGND 2 9 FB MODE/SYNC 3 13 10 SHDN
11 PGND
MODE/SYNC 3 8 SHDN SW1 4 9 VIN
PGND
SW1 4 7 VIN PGND 5 8 VIN
SW2 6 7 VOUT
SW2 5 6 VOUT
MSE PACKAGE
DD PACKAGE 12-LEAD PLASTIC MSOP
10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 40°C/W
TJMAX = 125°C, θJA = 39.7°C/W EXPOSED PAD (PIN 13) IS PGND MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 11) IS PGND, MUST BE SOLDERED TO PCB FOR RATED THERMAL PERFORMANCE AND LOAD REGULATION

Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3536EDD#PBF LTC3536EDD#TRPBF LFZD 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3536IDD#PBF LTC3536IDD#TRPBF LFZD 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LTC3536EMSE#PBF LTC3536EMSE#TRPBF 3536 12-Lead Plastic MSOP –40°C to 125°C
LTC3536IMSE#PBF LTC3536IMSE#TRPBF 3536 12-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Electrical Characteristics The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 3.3V, VOUT = 3.3V, RT = 100kΩ unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Operating Range l 1.8 5.5 V
Output Voltage Adjust Range l 1.8 5.5 V
Undervoltage Lockout Threshold VIN Ramping Down l 1.6 1.67 V
VIN Ramping Up l 1.75 1.8 V
Feedback Voltage 0°C < TJ < 85°C (Note 5) 0.594 0.6 0.606 V
–40°C < TJ < 125°C l 0.591 0.6 0.609 V
Feedback Pin Input Current (FB) VFB = 0.6V in Servo Loop, VMODE/SYNC = 0V 50 nA
Quiescent Current, Burst Mode Operation VFB = 0.7V, VMODE/SYNC = VIN 32 42 µA
Quiescent Current, Shutdown (IVIN) VSHDN = 0V 0.1 1 µA
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 LTC3536
Electrical Characteristics The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 3.3V, VOUT = 3.3V, RT = 100kΩ unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Quiescent Current, Active (IVIN) VFB = 0.7V, VMODE/SYNC = 0V 800 µA
Input Current Limit VMODE/SYNC = 0V (Note 4) l 2 2.5 A
Peak Current Limit VMODE/SYNC = 0V (Note 4) 3.4 4 A
Burst Mode Peak Current Limit VMODE/SYNC = VIN (Note 4) 0.4 0.6 A
Reverse Current Limit (Note 4) l 0.3 0.55 A
NMOS Switch Leakage Switch B, C: SW1 = SW2 = 5.5V, VIN = 5.5V, VOUT = 5.5V 0.1 1 µA
PMOS Switch Leakage Switch A, D: SW1 = SW2 = 0V, VIN = 5.5V, VOUT = 5.5V 0.1 1 µA
NMOS Switch On-Resistance Switch B (From SW1 to GND) (Note 6) 0.11 Ω
Switch C (From SW2 to GND) (Note 6) 0.1 Ω
PMOS Switch On-Resistance Switch A (From VIN to SW1) (Note 6) 0.12 Ω
Switch D (From VOUT to SW2) (Note 6) 0.145 Ω
Frequency Accuracy RT = 100k l 0.8 1 1.2 MHz
Frequency Accuracy Default RT = VIN l 0.96 1.2 1.44 MHz
Internal Soft-Start Time VFB from 0.06V to 0.54V 0.6 0.9 1.2 ms
Maximum Duty Cycle Percentage of Period SW2 is Low in Boost Mode l 88 91 %
Minimum Duty Cycle Percentage of Period SW1 is High in Buck Mode l 0 %
Error Amplifier AVOL 90 dB
Error Amplifier Sink Current FB = 1.3V, VC = 1V 250 300 µA
Error Amplifier Source Current FB = 0.3V, VC = 0V 400 480 µA
MODE/SYNC Input Logic Threshold Disable Burst Mode Operation 0.3 1 V
MODE/SYNC External Synchronization SYNC Level High l 1.2 V
SYNC Level Low l 0.4 V
MODE/SYNC Synchronization Frequency l 0.3 2 MHz
MODE/SYNC Input Current VMODE/SYNC = 5.5V = VIN 1 µA
SHDN Input Logic Threshold l 0.3 1 V
SHDN Input Current VSHDN = 5.5V = VIN 1 µA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: This IC includes overtemperature protection that is intended to
may cause permanent damage to the device. Exposure to any Absolute protect the device during momentary overload conditions. The maximum
Maximum Rating condition for extended periods may affect device rated junction temperature will be exceeded when this protection is active.
reliability and lifetime. Continuous operation above the specified absolute maximum operating
Note 2: The LTC3536 is tested under pulsed load conditions such that junction temperature may impair device reliability or permanently damage
TJ ≈ TA. The LTC3536E is guaranteed to meet specifications the device.
from 0°C to 125°C junction temperature. Specifications over the Note 4: Current measurements are performed when the LTC3536 is
–40°C to 125°C operating junction temperature range are assured by not switching. The current limit values measured in operation will be
design, characterization and correlation with statistical process controls. somewhat higher due to the propagation delay of the comparators.
The LTC3536I is guaranteed over the full –40°C to 125°C operating Note 5: Guaranteed by design characterization and correlation with
junction temperature range. Note that the maximum ambient temperature statistical process controls.
consistent with these specifications is determined by specific operating Note 6: Guaranteed by correlation and design.
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature
(TJ, in °C) is calculated from the ambient temperature (TA, in °C) and
power dissipation (PD, in watts) according to the formula:
TJ = TA + (PD • θJA),
where θJA (in °C/W) is the package thermal impedance.

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LTC3536
Typical Performance Characteristics TA = 25°C, VIN = VOUT = 3.3 V unless otherwise noted.

Efficiency Li-Ion (3V, 3.7V, 4.2V) No-Load Quiescent Current in Burst

Efficiency 3.3V vs Load Current to 3.3V Output Mode Operation (MODE = VIN)
100 100 60
90 90
55

INPUT QUIESCENT CURRENT (µA)

80 80
50
70 70
EFFICIENCY (%)

EFFICIENCY (%)
60 60 45

50 50 40
40 40
VIN = 1.8V VIN = 3V 35
30 VIN = 2.5V 30 VIN = 3.7V
VIN = 5.5V VIN = 4.2V 30
20 VIN = 1.8V BURST 20 VIN = 3V BURST VOUT = 1.8V
VIN = 2.5V BURST VIN = 3.7V BURST 25 VOUT = 3.3V
10 10
VIN = 5.5V BURST VIN = 4.2V BURST VOUT = 5.5V
0 0 20
0.001 0.01 0.1 1 0.001 0.01 0.1 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
LOAD CURRENT (A) LOAD CURRENT (A) INPUT VOLTAGE (V)
3536 G01 3536 G02 3536 G03

No-Load Quiescent Current in Input Current Limit vs Supply Input Current Limit vs Supply
PWM Mode Operation Voltage, VOUT = GND Voltage, VOUT = 3.3V
14 2.0 3.1
VOUT = 3.3V 1.9 3.0
12 VOUT = 1.8V 1.8 2.9
INPUT QUIESCENT CURRENT (mA)

VOUT = 5.5V 1.7 2.8

INPUT CURRENT LIMIT (A)

INPUT CURRENT LIMIT (A)

10 1.6 2.7
1.5 2.6
1.4 2.5
8
1.3 2.4
1.2 2.3
6 1.1 2.2
1.0 2.1
4 0.9 2.0
125°C 125°C
0.8 85°C 1.9 85°C
2 0.7 25°C 1.8 25°C
0.6 –40°C 1.7 –40°C
0 0.5 1.6
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
3536 G04 3536 G05 3536 G06

RDS(ON) for P-Channel Switch A RDS(ON) for N-Channel Switch B RDS(ON) for N-Channel Switch C
280 280 280
–45°C –45°C –45°C
260 0°C 260 0°C 260 0°C
240 25°C 240 25°C 240 25°C
85°C 85°C 85°C
220 125°C 220 125°C 220 125°C
200 200 200
RDS(ON) (mΩ)

RDS(ON) (mΩ)

RDS(ON) (mΩ)

180 180 180

160 160 160
140 140 140
120 120 120
100 100 100
80 80 80
60 60 60
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
3536 G07 3536 G08 3536 G09

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 LTC3536
Typical Performance Characteristics TA = 25°C, VIN = VOUT = 3.3 V unless otherwise noted.

RDS(ON) for P-Channel Switch D Feedback Voltage Oscillator Frequency vs RT

280 1.0 2.0
–45°C
260 0°C 0.8 1.8

CHANGE IN VOLTAGE FROM 25°C (%)

240 25°C

OSCILLATOR FREQUENCY (MHz)

0.6 1.6
85°C
220 125°C 0.4 1.4
200
RDS(ON) (mΩ)

0.2 1.2
180
0 1.0
160
–0.2 0.8
140
120 –0.4 0.6

100 –0.6 0.4

80 –0.8 0.2
60 –1.0 0
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 – 50 – 30 – 10 10 30 50 70 90 110 130 150 40 90 140 190 240 290 340
INPUT VOLTAGE (V) TEMPERATURE (°C) RT (kΩ)
3536 G10 3536 G11 3536 G12

Maximum Load Current in PWM Mode

vs Input Voltage 1MHz Switching Maximum Load Current in Burst Negative Inductor Current
Frequency, 4.7µH Inductor Value Mode Operation vs Input Voltage vs Oscillator Frequency
2500 300 0
VOUT PULLED UP TO 3.6V
VIN = 1.8V
250 L = 4.7µH
MAXIMUM LOAD CURRENT (mA)

MAXIMUM LOAD CURRENT (mA)

2000

REVERSE CURRENT LIMIT (A)

–0.5
200
1500
150 –1.0

1000
100
–1.5
500 VOUT = 1.8V VOUT = 1.8V
50
VOUT = 3.3V VOUT = 3.3V
VOUT = 5.5V VOUT = 5.5V
0 0 –2.0
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
INPUT VOLTAGE (V) INPUT VOLTAGE (V) OSCILLATOR FREQUENCY (MHz)
3536 G13 3536 G14 3536 G15

Change in Output Voltage vs Load

Current for 3.3V Output and 3.3V
Input Load Step 0A to 1A Load Step 0mA to 300mA
1
VOUT VOUT
OUTPUT VOLTAGE REGULATION (%)

200mV/DIV 200mV/DIV
0

ILOAD ILOAD
500mA/DIV 100mA/DIV
–1
VIN = 3.2V 100µs/DIV 3536 G17
VIN = 1.8V 100µs/DIV 3536 G18

VOUT = 3.3V VOUT = 3.3V

–2

PWM
BURST
–3
0.001 0.01 0.1 1 10
LOAD CURRENT (mA)
3536 G16

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LTC3536
Typical Performance Characteristics TA = 25°C, VIN = VOUT = 3.3 V unless otherwise noted.

Output Voltage Ripple in Output Voltage Ripple in Burst Burst Mode Operation to PWM
PWM Mode Mode Operation Mode Transient
VOUT VOUT
20mV/DIV VOUT 50mV/DIV
VIN = 2.5V 50mV/DIV VIN = 5.5V
VOUT VOUT
20mV/DIV 50mV/DIV
INDUCTOR VIN = 3.3V
VIN = 3.3V
CURRENT
VOUT VOUT
200mA/DIV
20mV/DIV 50mV/DIV
VIN = 5V VIN = 1.8V
VOUT = 3.3V 2µs/DIV 3536 G19
VOUT = 3.3V 50µs/DIV 3536 G20 VOUT = 3.3V 100µs/DIV 3536 G21

ILOAD = 0.5A ILOAD = 4mA ILOAD = 25mA

COUT = 22µF
L = 4.7µH

Start-Up in Burst Mode Operation Start-Up in PWM Mode Operation

Soft-Start with Output Precharged with Output Precharged

VOUT VOUT VOUT

1V/DIV 100mV/DIV 500mV/DIV

SHDN
2V/DIV SHDN SHDN
ILOAD 1V/DIV 1V/DIV
500mA/DIV
VIN = 3V 200µs/DIV 3536 G22
VIN = 3V 5ms/DIV 3536 G23
VIN = 3V 500µs/DIV 3536 G24

VOUT = 3.3V VOUT = 3.3V VOUT = 3.3V

COUT = 22µF COUT = 22µF COUT = 22µF
ILOAD = 1mA ILOAD = 20mA

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 LTC3536
Pin Functions (DFN/MSOP)

RT (Pin 1/Pin 1): Oscillator Frequency Programming VOUT (Pin 6/Pin 7): Output Voltage. This pin is the power
Input. Connect a resistor from RT to GND to program the output for the regulator. A low ESR capacitor should be
internal oscillator frequency. The frequency is given by: placed between this pin and the ground plane. The capaci-
tor should be placed as close to this pin as possible and
fOSC (MHz) = 100/RT (kΩ)
have a short return path to ground.
where RT is in kΩ and fOSC is between 0.3MHz and 2MHz.
Tying the RT pin to VIN enables the internal 1.2MHz default VIN (Pin 7/Pins 8, 9): Power Input for the Converter. A low
ESR 10µF or larger bypass capacitor should be connected
oscillator frequency.
between this pin and ground. The capacitor should be
SGND (Pin 2/Pin 2): Ground Connection for the LTC3536. placed as close to this pin as possible and have a short
A ground plane is highly recommended. Sensitive analog return path to ground.
components terminated at ground should connect to the
SHDN (Pin 8/Pin 10): Enable Input. A logic 1 on SHDN
GND pin with a Kelvin connection, separated from the
activates the buck-boost regulator. A logic 0 on SHDN
high current path.
deactivates the buck-boost regulator.
MODE/SYNC (Pin 3/Pin 3): Pulse Width Modulation/Burst
FB (Pin 9/Pin 11): Output Voltage Programming Feedback
Mode Selection and Synchronization Input. Driving MODE
Divider Input. The regulator output voltage is programmed
to a logic 0 state programs fixed frequency, low noise
by the voltage divider connected to FB. The buck-boost
PWM operation. Driving MODE to logic 1 state programs
output is given by the following equation:
Burst Mode operation for highest efficiency at light loads.
In Burst Mode operation, the output current capability is VOUT = 0.6V • (1 + RTOP/RBOT) (V)
significantly less than what is available in PWM operation. where RBOT is a resistor connected between FB and ground
Refer to the Applications Information section of this data and RTOP is a resistor connected between FB and VOUT.
sheet for details. Frequency synchronization is achieved The buck-boost output voltage can be adjusted from 1.8V
if a clock pulse is applied to MODE/SYNC. The external to 5.5V.
clock pulse amplitude must have an amplitude equal or
higher than 1.2V and duty cycle from 10% and 90%. The VC (Pin 10/Pin 12): Error Amplifier Output. Frequency
free-running frequency of the LTC3536 oscillator can be compensation components are connected between VC
programmed slower or faster than the synchronization and FB to provide stable operation of the converter. Refer
clock frequency. to the Applications Information section of this data sheet
for design details.
SW1 (Pin 4/Pin 4): Switch Pin. Connect to internal power
switches A and B. Connect one side of the buck-boost PGND (Exposed Pad Pin 11/Pin 5, Exposed Pad Pin 13):
inductor to SW1. Provide a short wide PCB trace from the Power Ground. The exposed pad must be soldered to the
inductor to SW1 to minimize voltage transients and noise. PCB and electrically connected to ground through the
shortest and lowest impedance connection possible.
SW2 (Pin 5/Pin 6): Switch Pin. Connect to internal power
switches C and D. Connect one side of the buck-boost
inductor to SW2. Provide a short wide PCB trace from the
inductor to SW2 to minimize voltage transients and noise.

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LTC3536
Block Diagram
L

SW1 SW2
VIN VOUT
1.8V TO 5.5V SWA SWD 1.8V TO 5.5V
–0.4A

+ GATE – +
DRIVERS
CIN
AND
REVERSE
ANTICROSS
SWB SWC CURRENT
CONDUCTION
LIMIT
PGND
CURRENT
LIMIT
+ RTOP COUT
PEAK
CURRENT
+ LIMIT 2.5A –

ERROR
3.4A – AMP
PWM + SOFT-START
AND
OUTPUT + 0.6V
UVLO PHASING FB
+ –
CFB
VC
1.75V –

RT

RT OSC
SYNC

RBOT
Burst Mode
SLEEP
CONTROL
SHDN 1 = ON
RUN LOGIC
MODE/SYNC 0 = OFF
1 = BURST
0 = PWM SGND

3635 BD

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 LTC3536
Operation
Introduction Figure 1 shows the topology of the LTC3536 power stage
The LTC3536 is a monolithic buck-boost converter that which is comprised of two P-channel MOSFET switches
can operate with input and output voltages from as low and two N-channel MOSFET switches and their associated
as 1.8V to as high as 5.5V. A proprietary switch control gate drivers. In response to the error amplifier output, an
algorithm allows the buck-boost converter to maintain internal pulse-width modulator generates the appropriate
output voltage regulation with input voltages that are switch duty cycles to maintain regulation of the output
above, below or equal to the output voltage. Transitions voltage.
between these operating modes are seamless and free of VIN VOUT
transients and subharmonic switching.
The LTC3536 can be configured to operate over a wide PMOS A PMOS D
range of switching frequencies, from 300kHz to 2MHz, SW1 L SW2
allowing applications to be optimized for board area and
efficiency. The LTC3536 has an internal fixed-frequency NMOS B NMOS C
oscillator with a switching frequency that is easily set by
a single external resistor. In noise sensitive applications, 3536 F01

the converter can also be synchronized to an external clock Figure 1. Power Stage Schematic
via the MODE/SYNC pin. The operating frequency defaults
to 1.2MHz when RT is connected to VIN eliminating the When the input voltage is significantly greater than the
external resistor. output voltage, the buck-boost converter operates in
buck mode. Switch D turns on continuously and switch
The LTC3536 has been optimized to reduce input current
C remains off. Switch A and B are pulse-width modulated
in shutdown and standby for applications that are sensi-
to produce the required duty cycle to support the output
tive to quiescent current draw, such as battery-powered
regulation voltage. As the input voltage decreases, switch A
devices. In Burst Mode operation, the no-load standby
remains on for a larger portion of the switching cycle.
current is only 32µA and in shutdown the total supply
When the duty cycle reaches approximately 90% the
current is reduced to less than 1µA.
switch pair AC begins turning on for a small fraction of the
switching period. As the input voltage decreases further,
PWM Mode Operation the AC switch pair remains on for longer durations and
With the MODE/SYNC pin forced low or driven by an ex- the duration of the BD phase decreases proportionally. At
ternal clock, the LTC3536 operates in a fixed-frequency this point, switch A remains on continuously while switch
pulse-width modulation (PWM) mode using a voltage mode pair CD is pulse-width modulated to obtain the desired
control loop. This mode of operation maximizes the output output voltage. At this point, the converter is operating
current that can be delivered by the converter, reduces out- solely in boost mode.
put voltage ripple, and yields a low noise fixed-frequency
switching spectrum. A proprietary switching algorithm Oscillator and Phase-Locked Loop
provides seamless transitions between operating modes The LTC3536 operates from an internal oscillator with a
and eliminates discontinuities in the average inductor cur- switching frequency that can be configured by a single
rent, inductor current ripple, and loop transfer function external resistor between RT and ground. Tying RT to VIN
throughout all regions of operation. These advantages sets the default internal operating frequency to typically
result in increased efficiency, improved loop stability, and 1.2MHz. If the RT pin is driven externally to a level higher
lower output voltage ripple in comparison to the traditional than VIN, a current limiting resistor should be used. 1M for
4-switch buck-boost converter. 6V on the RT pin limits the current to 6µA. Also, a Schottky

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LTC3536
Operation
diode from the RT pin to VIN can be used in addition to input current limit operates by injecting a current into the
current limiting resistor. For noise sensitive applications, feedback pin, which is proportional to the extent that the
an internal phase-locked loop allows the LTC3536 to inductor current exceeds the input current limit threshold
be synchronized to an external clock signal applied to (typically 2.5A). Due to the high gain of the feedback loop,
the MODE/SYNC pin. The free-running frequency of the this injected current forces the error amplifier output to
oscillator can be programmed slower or faster than the decrease until the average current through the inductor
synchronization clock frequency. is approximately reduced to the current limit threshold.
Whether operating from its internal oscillator or when For this current limit feature to be most effective, the
synchronized to an external clock signal, the LTC3536 is Thevenin resistance (RBOT//RTOP) from FB to ground
should exceed 100kΩ.
able to operate with a switching frequency from 300kHz
to 2MHz, providing the ability to minimize the size of the
15
external components and optimize the power conversion 14
efficiency. 13
12
11

CURRENT FB PIN (µA)

Error Amplifier 10
9
The LTC3536 has an internal high gain operational ampli- 8
7
fier which provides frequency compensation of the control 6
5
loop that maintains output voltage regulation. To ensure 4
stability of this control loop, an external compensation 3
2
network must be installed in the application circuit. A 1
Type III compensation network as shown in Figure 2 is 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
recommended for most applications since it provides the CURRENT OUT OF SW1 PIN (A)

flexibility to optimize the converter’s transient response 3536 F03

while simultaneously minimizing any DC error in the output Figure 3. FB Current for Input Current Limitation
voltage. Details on designing the compensation network
in LTC3536 applications can be found in the Applications Since this input current limit circuit maintains the error
Information section of this data sheet. amplifier in an active state it ensures a smooth recovery
and minimal overshoot once the current limit fault condi-
VOUT
RFF LTC3536
tion is removed. On a hard output short, it is possible for
RTOP 0.6V + the inductor current to increase substantially beyond the
CFF
FB
–
PWM current limit threshold before the input current limit has
RBOT
CFB
RFB
VC
time to react and reduce the inductor current. For this
GND reason, there is a second current limit circuit (peak cur-
CPOLE 3536 F02
rent limit), which turns off power switch A if the current
through switch A exceeds the approximately 3.4A limit
threshold. This provides additional protection in the case of
an instantaneous hard output short and provides time for
Figure 2. Error Amplifier and Compensation Network the primary current limit to react. When the input voltage
is lower than 2.4V, the input and peak current limit thresh-
Input and Peak Current Limits olds are gradually decreased. For minimum input voltage
The LTC3536 has two current limit circuits that are de- (1.8V) they are typically 1.7A and 2.3A respectively. See
signed to limit the peak inductor current to ensure that the Typical Performance Characteristics and the Inductor
the switch currents remain within the capabilities of the Selection section for information about the inductor value
IC during output short-circuit or overload conditions. The for maximum output current capability.
3536fa

10
 LTC3536
Operation
Reverse Current Limit Burst Mode OPERATION
In PWM mode operation the LTC3536 has the ability to When MODE/SYNC is held high, the buck-boost converter
actively conduct current away from the output if that is operates in Burst Mode operation using a variable frequency
necessary to maintain regulation. If the output is held above switching algorithm that minimizes the no-load input
regulation, this could result in large reverse currents. This quiescent current and improves efficiency at light load by
situation can occur if the output of the LTC3536 is held reducing the amount of switching to the minimum level
up momentarily by another supply as may occur during a required to support the load. The output current capabil-
power-up or power-down sequence. To prevent damage to ity in Burst Mode operation is substantially lower than in
the part under such conditions, the LTC3536 has a reverse PWM mode and is intended to support light stand-by loads.
current comparator that monitors the current entering Curves showing the maximum Burst Mode load current
power switch D from the load. If this current exceeds 0.55A as a function of the input and output voltage can be found
(typical) switch D is turned off for the remainder of the in the Typical Performance Characteristics section of this
switching cycle in order to prevent the reverse inductor data sheet. If the converter load in Burst Mode operation
current from reaching unsafe levels. exceeds the maximum Burst Mode current capability, the
output will lose regulation.
For no-load current application, the inductor current ripple
must be lower than double the minimum reverse current Each Burst Mode cycle is initiated when switches A and
limit (0.3A • 2 = 0.6A maximum inductor current ripple). C turn on producing a linearly increasing current through
See the Inductor Selection section for information about the inductor. When the inductor current reaches the Burst
how to calculate the inductor current ripple. Mode peak current limit (0.6A typically), switches B and D
are turned on, discharging the energy stored in the induc-
Output Current Capability tor into the output capacitor and load. Once the inductor
The maximum output current that can be delivered by current reaches zero, all switches are turned off and the
the LTC3536 is dependent upon many factors, the most cycle is complete. Current pulses generated in this manner
significant being the input and output voltages. For VOUT are repeated as often as necessary to maintain regulation
= 3.3V and VIN ≥ 3V, the LTC3536 is able to support a of the output voltage. In Burst Mode operation, the error
1A load continuously. For VOUT = 3.3V and VIN =1.8V, the amplifier is used as burst comparator. If the MODE pin
LTC3536 is able to support a 300mA load continuously. is driven externally to a level higher than VIN, a current
limiting resistor should be used. 1M for 6V on the MODE
Typically, the output current capability is greatest when pin limits the current to 6µA. Also, a Schottky diode from
the input voltage is approximately equal to the output the MODE pin to VIN can be used in addition to current
voltage. At larger step-up voltage ratios, the output cur- limiting resistor.
rent capability is reduced because the lower duty cycle of
switch D results in a larger inductor current being needed
Soft-Start
to support a given load. Additionally, the output current
capability generally decreases at large step-down voltage To minimize input current transients on power-up, the
ratios due to higher inductor current ripple which reduces LTC3536 incorporates an internal soft-start circuit with a
the maximum attainable inductor current. nominal duration of 0.9ms. The soft-start is implemented
by a linearly increasing ramp of the error amplifier refer-
The output current capability can also be affected by induc-
ence voltage during the soft-start duration. As a result,
tor characteristics. An inductor with large DC resistance
the duration of the soft-start period is largely unaffected
will degrade output current capability, particularly in boost
by the size of the output capacitor or the output regula-
mode operation. In addition, larger value inductors gener-
tion voltage. Given the closed-loop nature of the soft-start
ally maximize output current capability by reducing inductor
implementation, the converter is able to respond to load
current ripple. See the Typical Performance Characteristics
transients that occur during the soft-start interval. The
and the Inductor Selection section for information.
3536fa

11
LTC3536
Operation
soft-start period is reset by thermal shutdown and UVLO VOUT to go to zero volts during shutdown, drawing no
events on VIN and the mode of operation is always PWM. current from the input source.
In case the output voltage at start -up is already precharged
above 90% (typically) of the target value, the internal soft- Thermal Considerations
start is skipped and the LTC3536 immediately enters the The power switches in the LTC3536 are designed to operate
mode of operation that has been set on the MODE pin. continuously with currents up to the internal current limit
If the MODE pin is tied high and Burst Mode operation is thresholds. However, when operating at high current levels
selected, the output voltage is regulated smoothly to the there may be significant heat generated within the IC. As a
target voltage value. Instead if the MODE pin is tied low and result, careful consideration must be given to the thermal
PWM mode is selected, the error amplifier needs to charge environment of the IC in order to optimize efficiency and
up the VC pin and the output voltage might be pulled to ensure that the LTC3536 is able to provide its full-rated
lower voltage values for a short period of time, proportional output current. Specifically, the exposed pad of both the
to the value of the main compensation capacitor. DD and MSOP packages shall be soldered to the PC board
and the PC board should be designed to maximize the
Undervoltage Lockout conduction of heat out of the IC package.

To ensure proper operation, the LTC3536 incorporates If the die temperature exceeds approximately 165°C, the
internal undervoltage lockout (UVLO) circuitry. The con- IC will enter overtemperature shutdown and all switching
verter is disabled if VIN falls below its respective UVLO will be inhibited. The part will remain disabled until the
threshold (typical 1.67V). If the input voltage falls below die cools by approximately 10°C. The soft-start circuit
this level all switching is disabled until the input voltage is reinitialized in overtemperature shutdown to provide
rises above 1.75V (nominal). a smooth recovery when the fault condition is removed.
If the SHDN pin is driven externally to a level higher than
Output Disconnect VIN, a current limiting resistor should be used. 1M for 6V
on the SHDN pin limits the current to 6µA. Also, a Schottky
The LTC3536 is designed to allow true output disconnect diode from the SHDN pin to VIN can be used in addition
by opening both P-channel MOSFET rectifiers. This allows to current limiting resistor.

Applications Information
The standard LTC3536 application circuit is shown as the Inductor Selection
Typical Application on the front page of this data sheet. The The choice of inductor used in LTC3536 application circuits
appropriate selection of external components is dependent influences the maximum deliverable output current, the
upon the required performance of the IC in each particular magnitude of the inductor current ripple, and the power
application given considerations and trade-offs such as conversion efficiency. The inductor must have low DC
PCB area, cost, output and input voltage, allowable ripple series resistance or output current capability and efficiency
voltage, efficiency and thermal considerations. This section will be compromised. Larger inductance values reduce
of the data sheet provides some basic guidelines and con- inductor current ripple and will therefore generally yield
siderations to aid in the selection of external components
greater output current capability. For a fixed DC resistance,
and the design of the application circuit.
a larger value of inductance will yield higher efficiency by

3536fa

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 LTC3536
Applications Information
reducing the peak current to be closer to the average out- accordingly in order to have the same current ripple
put current and therefore minimize resistive losses due to (2.2µH for 2MHz, 15µH for 300kHz).
high RMS currents. However, a larger inductor within any
Different inductor core materials and styles have an impact
given inductor family will generally have a greater series
on the size and price of an inductor at any given current
resistance, thereby counteracting this efficiency advantage.
rating. Shielded construction is generally preferred as it
An inductor used in LTC3536 applications should have a minimizes the chances of interference with other circuitry.
saturation current rating that is greater than the worst-case The choice of inductor style depends upon the price, sizing,
average inductor current plus half the ripple current. The and EMI requirements of a particular application. Table 1
peak-to-peak inductor current ripple for each operational provides a small sampling of inductors that are well suited
mode can be calculated from the following formula, where to many LTC3536 applications.
f is the switching frequency in MHz, L is the inductance
Table 1. Recommended Inductors
in µH.
VENDOR PART/STYLE
V  V –V  Coilcraft LPO2506
∆IL(P-P)(BUCK) = OUT  IN OUT  847-639-6400 LPS4012, LPS4018
f •L  V IN www.coilcraft.com MSS6122
MSS4020
MOS6020
VIN  VOUT – VIN 
∆IL(P-P)(BOOST) = DS1605, DO1608
f •L  VOUT  XPL4020
XAL4040
XFL4020
In addition to its influence on power conversion efficiency, Coiltronics SD52, SD53
the inductor DC resistance can also impact the maximum www.cooperet.com SD3114, SD311B
output capability of the buck-boost converter particularly Murata LQH55D
at low input voltages. In buck mode, the output current of 714-852-2001
www.sumida.com
the buck-boost converter is limited only by the inductor
Sumida CDH40D11
current reaching the current limit threshold. However, in 847-956-0666
boost mode, especially at large step-up ratios, the output www.sumida.com
current capability can also be limited by the total resistive Taiyo Yuden NP04S8
losses in the power stage. These include switch resis- www.t-yuden.com NR3015
NR4018
tances, inductor resistance and PCB trace resistance. Use
TDK VLP, LTF
of an inductor with high DC resistance can degrade the 847-803-6100 VLF, VLCF
output current capability from that shown in the Typical www.component.tdk.com
Performance Characteristics section of this data sheet. Würth Elektronik WE-TPC Type S, M, MH
As a guideline, in most applications the inductor DC re- 201-785-8800
www.we-online.com
sistance should be significantly smaller than the typical
power switch resistance of 120mΩ. Output Capacitor Selection
The minimum inductor value must guarantee that the A low ESR output capacitor should be utilized at the buck-
worst-case average input current plus half the ripple boost converter output in order to minimize output voltage
current don’t reach the input current limit threshold. ripple. Multilayer ceramic capacitors are an excellent option
For a switching frequency of 1MHz the recommended as they have low ESR and are available in small footprints.
typical inductor value is 4.7µH. For a higher and lower The capacitor value should be chosen large enough to
switching frequency the inductor value should be changed reduce the output voltage ripple to acceptable levels.

3536fa

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LTC3536
Applications Information
Neglecting the capacitor ESR and ESL, the peak-to-peak low leakage currents. However, many ceramic capacitors
output voltage ripple can be calculated by the following designed for power applications experience significant
formulas, where f is the frequency in MHz, COUT is the loss in capacitance from their rated value with increased
capacitance in µF and ILOAD is the output current in amps. DC bias voltages. For example, it is not uncommon for
a small surface mount ceramic capacitor to lose more
VOUT  VIN – VOUT 
∆V(P-P)(BUCK) = than 50% of its rated capacitance when operated near its
2  V 
8 • f •L • COUT IN rated voltage. As a result, it is sometimes necessary to
use a larger value capacitance or a capacitor with a higher
ILOAD  VOUT – VIN  voltage rating than required in order to actually realize the
∆V(P-P)(BOOST) =
f • COUT  VOUT  intended capacitance at the full operating voltage. To ensure
that the intended capacitance is realized in the application
Given that the output current is discontinuous in boost circuit, be sure to consult the capacitor vendor’s curve of
mode, the ripple in this mode will generally be much larger capacitance versus DC bias voltage.
than the magnitude of the ripple in buck mode. The capacitors listed in Table 2 provide a sampling of small
In addition to output voltage ripple generated across the surface mount ceramic capacitors that are well suited to
output capacitance, there is also output voltage ripple LTC3536 application circuits. All listed capacitors are either
produced across the internal resistance of the output X5R or X7R dielectric in order to ensure that capacitance
capacitor. The ESR-generated output voltage ripple is loss over temperature is minimized.
proportional the series resistance of the output capacitor.
Table 2. Representative Bypass and Output Capacitors
Input Capacitor Selection VALUE VOLTAGE SIZE (mm)
PART NUMBER (µF) (V) L × W × H (FOOTPRINT)
The PVIN pin carries the full inductor current and provides AVX
power to internal control circuits in the IC. To minimize 12066D106K 10 6.3 3.2 × 1.6 × 0.5 (1206)
12066D226K 22 6.3 3.2 × 1.6 × 0.5 (1206)
input voltage ripple and ensure proper operation of the IC, 12066D476K 47 6.3 3.2 × 1.6 × 0.5 (1206)
a low ESR bypass capacitor with a value of at least 10µF Kemet
should be located as close to this pin as possible. The C0603C106K9P 10 6.3 1.6 × 0.8 × 0.8 (0603)
C0805C226K9P 22 6.3 2.0 × 1.25 × 1.25 (0805)
traces connecting this capacitor to PVIN and the ground C0805C476K9P 47 6.3 2.0 × 1.25 × 1.25 (0805)
plane should be made as short as possible. The SVIN pin Murata
provides power to the internal circuitry. In every applica- GRM21 10 10 2.0 × 1.25 × 1.25 (0805)
tion, the SVIN and PVIN must be connected together on GRM21 22 6.3 2.0 × 1.25 × 1.25 (0805)
the PC Board. TDK
C2102X5R0J 22 6.3 2.0 × 1.25 × 0.85 (0805)
C2102X5R0J 47 6.3 2.0 × 1.25 × 1.25 (0805)
Recommended Input and Output Capacitors
Taiyo Yuden
The capacitors used to filter the input and output of the JMK212BJ 22 6.3 2.0 × 1.25 × 0.85 (0805)
JMK212BJ 47 6.3 2.0 × 1.25 × 0.85 (0805)
LTC3536 must have low ESR and must be rated to handle
the large AC currents generated by switching converters. Small-Signal Model
This is important to maintain proper functioning of the IC
The LTC3536 uses a voltage mode control loop to maintain
and to reduce output voltage ripple.
regulation of the output voltage. An externally compen-
The choice of capacitor technology is primarily dictated sated error amplifier drives the VC pin to generate the
by a trade-off between cost, size and leakage current. appropriate duty cycle of the power switches. Use of an
Ceramic capacitors are often utilized in switching con- external compensation network provides the flexibility for
verter applications due to their small size, low ESR and optimization of closed-loop performance over the wide

3536fa

14
 LTC3536
Applications Information
VIN VOUT The denominator of the buck mode transfer function
COUT
exhibits a pair of resonant poles generated by the LCOUT
A D
L RS
RC RLOAD
filtering of the power stage. The resonant frequency of
VC PWM the power stage, fO, is given by the following expression
B C where L is the value of the inductor in henries.
1 1
3536 F04
ωO = , fO =
Figure 4. Small-Signal Model
LCOUT 2π LCOUT

The quality factor, Q, has a significant impact on compensa-

variety of output voltages, switching frequencies, and
tion of the voltage loop since a higher Q factor produces
external component values supported by the LTC3536.
a sharper loss of phase near the resonant frequency. The
VIN is the input supply voltage, VOUT the programmed quality factor is inversely related to the amount of damping
output voltage, L is the external buck-boost inductor, COUT in the power stage and is substantially influenced by the
the output capacitor, RS the series resistance in the power average series resistance of the power stage, RS. Lower
path (it can be approximated as twice the average power values of RS will increase the Q and result in a sharper
switch resistance plus the DC resistance of the inductor) loss of phase near the resonant frequency and will require
and RC is the output capacitor ESR. more phase boost or lower bandwidth to maintain an
adequate phase margin.
Buck Mode
LCOUT
The small-signal transfer function of the buck-boost Q=
L
converter is different in the buck and boost modes of op- COUT (RC +RS ) +
eration and care must be taken to ensure stability in both RLOAD
operating regions. When stepping down from a higher
input voltage to a lower output voltage, the converter Boost Mode
will operate in buck mode and the small-signal transfer When stepping up from a lower input voltage to a higher
function from the error amplifier output, VC, to the con- output voltage, the buck-boost converter will operate in
verter output voltage is given by the following equation: boost mode where the small-signal transfer function from
control voltage, VC, to the output voltage is given by the
VOUT 1+ sRCCOUT
VC
(s) = 2.64 • VIN • 2
following expression:
Buck Mode  s 
s  
1+ +
ω OQ  ω O 
VOUT
(1+ sRCCOUT )  1– ωs 
VC
(s) = 2.64 • G 2
Z
This transfer function has a single zero created by the Boost Mode s  s 
output capacitor ESR and a resonant pair of poles. In most 1+ +
ω OQ  ω O 
applications, an output capacitor with a very low ESR is
utilized in order to reduce the output voltage ripple to ac- In boost mode operation, the transfer function is character-
ceptable levels. Such low values of capacitor ESR result ized by a pair of resonant poles and a zero generated by
in a very high frequency zero and as a result the zero is the ESR of the output capacitor as in buck mode. However,
commonly too high in frequency to significantly impact in addition there is a right-half plane zero which generates
compensation of the feedback loop.

3536fa

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LTC3536
Applications Information
increasing gain and decreasing phase at higher frequen- Buck-Boost Mode
cies. As a result, the crossover frequency in boost mode
When the converter operates in buck-boost mode and the
operation generally must be set lower than in buck mode
small-signal transfer function from control voltage, VC, to
in order to maintain sufficient phase margin. the output voltage is given by the following expression:
2
RS V  VOUT
R
1–
RLOAD
•  OUT 
 V  VC
(s) =
IN Buck-Boost Mode
G = VIN • LOAD • 2
RS R  V   
1+ LOAD
RS
•  IN 
 VOUT 
(1+ sRCCOUT )  1– ωs 
Z
17.62 • G 2
2 s s 
 V  1+ +
RS +RLOAD  IN  ω OQ  ω O 
 VOUT 
ωO =
LCOUT (RLOAD +RC ) Also in buck-boost mode operation, the transfer function
is characterized by a pair of resonant poles and a zero
In boost mode operation, the frequency of the right-half generated by the ESR of the output capacitor as in buck
plane zero, fZ, is given by the following expression. The mode and a right half plane zero.
frequency of the right half plane zero decreases at higher
loads and with larger inductors.
G=
(
0.15 • VOUT RLOAD • ε 2 • 1.85 – RS • (1.85 – ε ) )
 VIN 
2
 VIN 
2 (
ε • (1.85 – ε ) • RS +RLOAD • ε 2 )
 V  R LOAD – R S  V  RLOAD – RS
ωZ = OUT
, fZ = OUT where the variable ε is defined:
L 2πL
VIN • 1.85
ε=
Finally, the magnitude of the quality factor of the power VOUT + VIN
stage in boost mode operation is given by the following
expression: RS +RLOAD • ε 2
ωO =
LCOUT (RLOAD +RC )
2
 V 
LCOUT (RLOAD +RC ) RS +RLOAD  IN  In buck-boost mode operation, the frequency of the right-
 VOUT 
Q= 2
half plane zero, fZ, is given by the following expression.
 V  The frequency of the right-half plane zero decreases at
L + COUTRLOADRC  IN  +RSCOUT (RLOAD +RC )
 VOUT  higher loads and with larger inductors.
1.85 • ε 2RLOAD – RS • (1.85 – ε )
ωZ =
L • (1.85 – ε )

3536fa

16
 LTC3536
Applications Information
Finally, the magnitude of the quality factor of the power low enough that the resultant crossover frequency of the
stage in buck-boost mode operation is given by the fol- control loop is well below the resonant frequency.
lowing expression: In most applications, the low bandwidth of the Type I com-
pensated loop will not provide sufficient transient response
LCOUT (RLOAD +RC ) RS +RLOAD • ε 2
Q= performance. To obtain a wider bandwidth feedback loop,
L + COUTRLOADRC • ε 2 +RSCOUT (RLOAD +RC ) optimize the transient response, and minimize the size of
the output capacitor, a Type III compensation network as
Compensation of the Voltage Loop shown in Figure 7 is required.

The small-signal models of the LTC3536 reveal that the VOUT

LTC3536
transfer function from the error amplifier output, VC, to
RTOP 0.6V +
the output voltage is characterized by a set of resonant FB
–
poles and a possible zero generated by the ESR of the RBOT
C1
VC
output capacitor as shown in the Bode plot of Figure 5.
GND
In boost mode operation, there is an additional right-half 3536 F06

plane zero that produces phase lag and increasing gain at

higher frequencies. Typically, the compensation network
Figure 6. Error Amplifier with Type I Compensation
is designed to ensure that the loop crossover frequency
is low enough that the phase loss from the right-half VOUT
plane zero is minimized. The low frequency gain in buck RFF LTC3536
mode is a constant, but varies with both VIN and VOUT in RTOP CFF 0.6V +
boost mode. FB
–
CFB
RBOT RFB
VC
GND
GAIN CPOLE 3536 F07

–40dB/DEC

–20dB/DEC
Figure 7. Error Amplifier with Type III Compensation
PHASE
0°

–90° A Bode plot of the typical Type III compensation network

BUCK MODE
–180° is shown in Figure 8. The Type III compensation network
–270° BOOST MODE provides a pole near the origin which produces a very high
loop gain at DC to minimize any steady-state error in the
f
fO fRHPZ 3536 F05 regulation voltage. Two zeros located at fZERO1 and fZERO2
provide sufficient phase boost to allow the loop crossover
Figure 5. Buck-Boost Converter Bode Plot frequency to be set above the resonant frequency, fO, of
the power stage. The Type III compensation network also
For charging or other applications that do not require an introduces a second and third pole. The second pole, at
optimized output voltage transient response, a simple frequency fPOLE2, reduces the error amplifier gain to a
Type I compensation network as shown in Figure 6 can zero slope to prevent the loop crossover from extending
be used to stabilize the voltage loop. To ensure sufficient too high in frequency. The third pole at frequency fPOLE3
phase margin, the gain of the error amplifier must be provides attenuation of high frequency switching noise.

3536fa

17
LTC3536
Applications Information
In most applications the compensation network is designed
GAIN so that the loop crossover frequency is above the resonant
frequency of the power stage, but sufficiently below the
–20dB/DEC boost mode right-half plane zero to minimize the additional
phase loss. Once the crossover frequency is decided upon,
–20dB/DEC
90° the phase boost provided by the compensation network
is centered at that point in order to maximize the phase
0°
margin. A larger separation in frequency between the
PHASE
–90° zeros and higher order poles will provide a higher peak
f
fZERO1 fPOLE2 fPOLE3 3536 F08 phase boost but may also increase the gain of the error
fZERO2 amplifier which can push out the loop crossover to a
Figure 8. Type III Compensation Bode Plot higher frequency.
The Q of the power stage can have a significant influence
The transfer function of the compensated Type III error on the design of the compensation network because it
amplifier from the input of the resistor divider to the output determines how rapidly the 180° of phase loss in the power
of the error amplifier, VC, is: stage occurs. For very low values of series resistance, RS,
 s  s  the Q will be higher and the phase loss will occur sharply.
VC(S)  1+ 2πf   1+ 2πf  In such cases, the phase of the power stage will fall rapidly
= GEA ZERO1 ZERO2 to –180° above the resonant frequency and the total phase
VOUT(S)  s  s  margin must be provided by the compensation network.
s  1+ 1+
 2πfPOLE1   2πfPOLE2 
 
However, with higher losses in the power stage (larger RS)
The error amplifier gain is given by the following equation. the Q factor will be lower and the phase loss will occur
The simpler approximate value is sufficiently accurate in more gradually. As a result, the power stage phase will
most cases since CFB is typically much larger in value not be as close to –180° at the crossover frequency and
than CPOLE. less phase boost is required of the compensation network.

1 1 The LTC3536 error amplifier is designed to have a fixed

GEA = ≈ maximum bandwidth in order to provide rejection of
R TOP (CFB + CPOLE ) R TOPCFB
switching noise to prevent it from interfering with the
The pole and zero frequencies of the Type III compensation control loop. From a frequency domain perspective, this
network can be calculated from the following equations can be viewed as an additional single pole as illustrated
where all frequencies are in Hz, resistances are in ohms, in Figure 9. The nominal frequency of this pole is 400kHz.
and capacitances are in farads. For typical loop crossover frequencies below about 40kHz
the phase contributed by this additional pole is usually
1
fZERO1 =
2πRFBCFB LTC3536
0.6V + RFILT
1 1 INTERNAL
fZERO2 = ≈ FB
– VC
2π (R TOP +RFF ) CFF 2πR TOPCFF VC
CFILT

CFB + CPOLE 1
3536 F09

fPOLE2 = ≈ Figure 9. Internal Loop Filter

2πCFBCPOLERFB 2πCPOLERFB

1
fPOLE3 =
2πCFFRFF
3536fa

18
 LTC3536
Applications Information
negligible (for 40kHz is around –5.7°). However, for loops at which the phase of the buck-boost converter reaches
with higher crossover frequencies this additional phase –180°. It is generally difficult to determine this frequency
lag should be taken into account when designing the analytically, because it is significantly impacted by the Q
compensation network. factor of the resonance in the power stage. As a result,
it is best determined from a Bode plot of the buck-boost
Loop Compensation Example converter as shown in Figure 10. This Bode plot is for
This section provides an example illustrating the design of the LTC3536 buck-boost converter using the previously
a compensation network for a typical LTC3536 application specified power stage parameters and was generated from
circuit. In this example a 3.3V regulated output voltage is the small signal model equations using LTspice® software.
generated with the ability to supply 300mA load from an In this case, the phase reaches –180° at 37.8kHz making
input power source ranging from 1.8V to 5.5V. To optimize fC = 37.8kHz the target crossover frequency for the com-
efficiency 1MHz switching frequency has been chosen. In pensated loop. From the Bode plot of Figure 9 the gain of
this application the maximum inductor current ripple will the power stage at the target crossover frequency is –2dB.
occur at the highest input voltage. An inductor value of
At this point in the design process, there are three con-
4.7µH has been chosen to limit the worst-case inductor
straints that have been established for the compensation
current ripple. A low ESR output capacitor with a value
network. It must have +2dB gain at fC = 37.8kHz, a peak
of 22µF is specified to yield a worst-case output voltage
phase boost of 60° and the phase boost must be centered
ripple of approximately 10mV (occurring at the worst-case
at fC = 37.8kHz.
step-up ratio and maximum load current). In summary, the
key power stage specifications for this LTC3536 example An analytical approach can be used to design a compensa-
application are given below: tion network with the desired phase boost, center frequency
and gain. In general, this procedure can be cumbersome
f = 1MHz
VIN = 1.8V to 5.5V due to the large number of degrees of freedom in a Type III
VOUT = 3.3V at 300mA compensation network. However the design process can
COUT = 22µF, be simplified by assuming that both compensation zeros
RC = 10mΩ 30
VO/VC
0
L = 4.7µH,
24 –20
RL = 60mΩ
18 –40
With the power stage parameters specified, the compen-
–60
sation network can be designed. A reasonable approach 12
GAIN
is to design the compensation network at this worst-case 6 –80
PHASE
corner and then verify that sufficient phase margin exists 0 –100
PHASE (DEG)
GAIN (dB)

across all other operating conditions. In this example ap- –6 –120

plication, at VIN = 1.8V and the full 300mA load current,
–12 –140
the right-half plane zero will be located at 100kHz and this
will be a dominant factor in determining the bandwidth of –18 –160

the control loop. –24 –180

The first step in designing the compensation network –30 –200

is to determine the target crossover frequency for the –36 –220

compensated loop. This example will be designed for a –42 –240

60° phase margin to ensure adequate performance over 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
parametric variations and varying operating conditions. As
3536 F10

a result, the target crossover frequency, fC, will be the point Figure 10. Converter Bode Plot, VIN = 1.8V, ILOAD = 300mA
3536fa

19
LTC3536
Applications Information
occur at the same frequency, fZ, and both higher order poles Assuming a multiple of 50 separation between the pole
(fPOLE2 and fPOLE3) occur at the common frequency, fP . frequencies and zero frequencies this can be simplified
This is a good starting point for determining the compen- to the following expression:
sation network. However the Bode plot for the complete  50 
loop should be checked overall operating conditions and GCENTER = 20log  
for variations in components values to ensure that suf-  ( 2πfC ) (R TOPCFB ) 
ficient phase margin and gain margin exists in all cases.
The first step in defining the compensation component
A reasonable choice is to pick the frequency of the poles, values is to pick a value for RTOP that provides an accept-
fP, to be about 50 times higher than the frequency of the ably low quiescent current through the resistor divider.
zeros, fZ, which provides a peak phase boost of approxi- A value of RTOP = 845k is a reasonable choice. Next, the
mately ΦMAX = 60° as was assumed previously. Next, the value of CFB can be found:
phase boost must be centered so that the peak phase
GCENTER = 2dB
occurs at the target crossover frequency. The frequency
of the maximum phase boost, fC, is the geometric mean 50
CFB = 198pF ≈ 180pF
of the pole and zero: 2dB
2π • ( 37.8kHz ) • 845kΩ • 10 20
fC = fP • fZ = 50 • fZ 2 = 7 • fZ

Therefore, in order to center the phase boost given a factor The compensation poles can be set at 264.6kHz and the
of 50 separation between the pole and zero frequencies, zeros at 5.4kHz by using the expressions for the pole and
the zeros should be located at one-seventh of the cross- zero frequencies given in the previous section. Setting the
over frequency and the poles should be located at seven frequency of the first zero, fZERO1, to 5.4kHz results in the
times the crossover frequency as given by the following following value for RFB:
equations: 1
RFB = = 163kΩ ≈ 162kΩ
1 1 2π • (180pF ) • 5.4kHz
fZ = • fC = • ( 37.8kHz ) = 5.4kHz
7 7
This leaves the free parameter, CPOLE, to set the frequency
fP = 7 • fC = 7 • ( 37.8kHz ) = 264.6kHz fPOLE1 to the common pole frequency of 264.6kHz as given:
1
This placement of the poles and zeros will yield a peak phase CPOLE = = 3.71pF ≈ 3.9pF
boost of 60° that is centered at the crossover frequency, 2π • (162kΩ ) • 264.6kHz
fC. Next, in order to produce the desired target crossover
Next, CFF can be chosen to set the second zero, fZERO2, to
frequency, the gain of the compensation network at the
the common zero frequency of 5.4kHz.
point of maximum phase boost, GCENTER, must be set to
+2dB. The gain of the compensated error amplifier at the 1
CFF = = 34.9pF ≈ 33pF
point of maximum phase gain is given by: 2π • ( 845kΩ ) • 5.4kHz
 2πfP 
  Finally, the resistor value RFF can be chosen to place the
GCENTER = 10log
 ( 2πf )3 (R C )2  second pole at 264.6kHz:
 Z TOP FB 
1
RFF = = 18.2kΩ
2π • ( 33pF ) • 264.6kHz

3536fa

20
 LTC3536
Applications Information
A Bode plot of the error amplifier with the designed com- 140
VO/VC
–40
pensation component values is shown in Figure 11. The
120 –60
Bode plot confirms that the peak phase occurs at 37.8kHz
and the phase boost at that point is about 60°. In addition, 100 –80

the gain at the peak phase frequency is 2dB which is close 80 –100
PHASE
to the design target. 60 –120

VO/VC 40 –140

PHASE (DEG)
GAIN (dB)
81 60
20 –160
72 50
GAIN
63 40 0 –180

54 30 –20 –200
PHASE
45 20
–40 –220
36 10
–60 –240
27 0
PHASE (DEG)
GAIN (dB)

18 –10 –80 –260

GAIN
9 –20 –100 –280
–30 1 10 100 1k 10k 100k 1M 10M 100M
0
FREQUENCY (Hz) 3536 F12
–9 –40

–18 –50 Figure 12. Complete Loop Bode Plot for Boost Operation Mode
–27 –60

–36 –70 VO/VC

100 0
–45 –80
–54 –90
1 10 100 1k 10k 100k 1M 10M 100M 80 –30
FREQUENCY (Hz) 3536 F11

60 –60

Figure 11. Compensated Error Amplifier Bode Plot PHASE

40 –90

GAIN
The final step in the design process is to compute the Bode

PHASE (DEG)
20 –120
GAIN (dB)

plot for the entire loop using the designed compensation

network and confirm its phase margin and crossover 0 –150

frequency. The complete loop Bode plot for this example –20 –180
is shown in Figure 12. The loop crossover frequency is
37.8kHz which matches the design target and the phase –40 –210

margin is approximately 60°.

–60 –240
The Bode plot for the complete loop should be checked
overall operating conditions and for variations in compo- –80
1 10 100 1k 10k 100k 1M 10M
–270
100M
nent values to ensure that sufficient phase margin and FREQUENCY (Hz) 3536 F13

gain margin exists in all cases. The stability of the loop

should also be confirmed via time domain simulation and Figure 13. Complete Loop Bode Plot for
Buck-Boost Operation Mode
by evaluating the transient response of the converter in
the actual circuit. 40° for VIN = VOUT = 3.3V. In fact in this mode of operation
In this example the VIN varies from 1.8V to 5.5V. In buck- the DC gain increase and often make this the most critical
boost operation (when 0.85 • VOUT < VIN < VOUT/0.85) the region to compensate.
Bode plot of the complete loop shows a phase margin of
3536fa

21
 LTC3536
Applications Information
In order to improve the stability also in buck-boost mode 140
VO/VC
–20
of operation, the two compensation zeros could be move 120 –40
to different frequency:
100 –60
1
fZERO2 = = 5.4kHz 80 –80
2πR TOPCFF 60 –100

40 –120
1 PHASE
fZERO1 = = 2 • fZERO2 = 10.8kHz

PHASE (DEG)
GAIN (dB)
20 –140
2πRFBCFB GAIN
0 –160

The new RFB value is: –20 –180

–40 –200
1
RFB = = 81.9kΩ ≈ 80.6kΩ
2π • (180pF ) • 10.8kHz
–60 –220

–80 –240

As consequence the fPOLE2 will move to higher frequency: –100 –260

–120 –280
1 1 10 100 1k 10k 100k 1M 10M 100M
fPOLE2 = = 532kHz FREQUENCY (Hz)
2πCPOLERFB 3536 F15

Figure 15. Complete Loop Bode Plot for

As shown from Figures 14 and 15, the stability is now Buck-Boost Operation Mode
improved for the buck-boost region (VIN = 3V) and remains
good for the boost region (VIN = 1.8V). Output Voltage Programming
In buck mode there is no right-half plane zero and the The output voltage is set via the external resistor divider
stability is normally achieved. comprised of resistors RTOP and RBOT. The resistor divider
values determine the output regulation voltage according to:
VO/VC
120 –60
 R 
100 –80 VOUT = 0.6  1+ TOP  V
 RBOT 
80 –100

60 –120 In addition to setting the output voltage, the value of RTOP

PHASE is instrumental in controlling the dynamics of the compen-
40 –140
GAIN
sation network. When changing the value of this resistor,
PHASE (DEG)

care must be taken to understand the impact this will have

GAIN (dB)

20 –160

0 –180 on the compensation network. As noted in the Input and

Peak Current Limit section, “for current limit feature to
–20 –200
be most effected, the Thevenin resistance (RTOP//RBOT)
–40 –220 from FB to ground should exceed 100k.”
–60 –240
VOUT
–80 –260
LTC3536 RTOP

–100 –280 FB
1 10 100 1k 10k 100k 1M 10M 100M RBOT
FREQUENCY (Hz) 3536 F14
3536 F16

Figure 14. Complete Loop Bode Plot for Boost Operation Mode Figure 16. FB Resistor Network

3536fa

22
 LTC3536
Applications Information
Switching Frequency Selection 2. The exposed pad is the electrical power ground connec-
tion for the LTC3536 in the DD package. Multiple vias
Higher switching frequencies facilitate the use of smaller
should connect the backpad directly to the ground plane.
inductors as well as smaller input and output filter capaci-
tors which results in a smaller solution size and reduced In addition, maximization of the metallization connected
component height. However, higher switching frequencies to the backpad will improve the thermal environment
also generally reduce conversion efficiency due to the and improve the power handling capabilities of the IC
increased switching losses. In addition, the maximum in either package.
voltage step-up ratio is reduced slightly at higher switching 3. The components their connections with high current
frequencies as shown in the maximum duty cycle versus should all be placed over a complete ground plane to
switching frequency curve in the Typical Performance minimize loop cross-sectional areas. This minimizes
Characteristics section of this data sheet. EMI and reduces inductive drops.

PCB Layout Considerations 4. Connections to all of the components with high current
should be made as wide as possible to reduce the series
The LTC3536 buck-boost converter switches large currents resistance. This will improve efficiency and maximize the
at high frequencies. Special attention should be paid to the output current capability of the buck-boost converter
PC board layout to ensure a stable, noise-free and efficient
application circuit. A few key guidelines are provided: 5. To prevent large circulating currents in the ground plane
from disrupting operation of the LTC3536, all small-
1. The parasitic inductance and resistance of all circulating signal grounds should return directly to GND by way
high current paths should be minimized. This can be of a dedicated Kelvin route. This includes the ground
accomplished by keeping the routes as short and as connection for the RT pin resistor and the ground con-
wide as possible. Capacitor ground connections should nection for the feedback network.
via down to the ground plane by way of the shortest
6. Keep the routes connecting to the high impedance,
route possible. The bypass capacitors on PVIN and
VOUT should be placed as close to the IC as possible noise sensitive inputs FB and RT as short as possible
and should have the shortest possible paths to ground. to reduce noise pick-up. Example from MODE route in
case the chip is synchronized with external clock.

3536fa

23
LTC3536
Applications Information

Figure 17a. Fabrication Layer of Example PCB with 4 Layers

Figure 17b. Top Layer of Example PCB Figure 17c. Bottom Layer of Example PCB

3536fa

24
 LTC3536
Typical Applications
300kHz High Efficiency Li-Ion to 3.6V at 1A, Efficiency 3.6V, 300kHz vs Load Current
Pulsed with Manual Mode Control
100
15µH*
90

SW1 SW2 VOUT 80

VIN
VIN VOUT 3.6V 70
3V TO 4.2V
10µF 100pF 47µF 100µF 1A

EFFICIENCY (%)
15k 60
LTC3536
845k 50
MODE/SYNC FB
40
OFF ON SHDN
1nF 30
332k 49.9k
RT VC 20 VIN = 3V
GND VIN = 3.6V
169k 10
VIN = 4.2V
3536 TA02
0
0.001 0.01 0.1 1
*COILCRAFT XAL4040
LOAD CURRENT (A)
3536 TA02b

USB to 5V Converter

2.2µH*
Load Step

SW1 SW2 VOUT

USB POWER
VIN VOUT 5V VOUT
4.3V TO 5.5V
47µF 18pF 22µF 1A 200mV/DIV
22.6k
LTC3536
1100k ILOAD
2MHz EXTERNAL CLOCK MODE/SYNC FB 500mA/DIV
OFF ON SHDN
200pF
49.9k 33k
RT VC
VIN = 4.3V 100µs/DIV 3536 TA03b
GND
150k VOUT = 5V

3536 TA03

*COILCRAFT XFL4020

3536fa

25
LTC3536
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
R = 0.125 0.40 ± 0.10
TYP
6 10
0.70 ±0.05

3.55 ±0.05 1.65 ±0.05 3.00 ±0.10 1.65 ± 0.10

2.15 ±0.05 (2 SIDES) (4 SIDES) (2 SIDES) PIN 1 NOTCH
PIN 1 R = 0.20 OR
PACKAGE TOP MARK 0.35 × 45°
OUTLINE (SEE NOTE 6) CHAMFER
(DD) DFN REV C 0310

5 1
0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05
0.50 0.50 BSC
BSC 2.38 ±0.10
2.38 ±0.05 (2 SIDES)
0.00 – 0.05
(2 SIDES) BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev D)

BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ± 0.102
2.845 ± 0.102 (.112 ± .004)
(.112 ± .004) 0.889 ± 0.127
(.035 ± .005) 1 6 0.35
REF

5.23 1.651 ± 0.102

1.651 ± 0.102 3.20 – 3.45 0.12 REF
(.206) (.065 ± .004)
MIN (.065 ± .004) (.126 – .136) DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
12 7 FOR REFERENCE ONLY
0.65 NO MEASUREMENT PURPOSE
0.42 ± 0.038 4.039 ± 0.102
(.0165 ± .0015) (.0256) (.159 ± .004)
TYP BSC (NOTE 3) 0.406 ± 0.076
RECOMMENDED SOLDER PAD LAYOUT
12 11 10 9 8 7 (.016 ± .003)
REF
DETAIL “A”
0.254
(.010) 3.00 ± 0.102
0° – 6° TYP 4.90 ± 0.152
(.118 ± .004)
(.193 ± .006) (NOTE 4)
GAUGE PLANE

0.53 ± 0.152
(.021 ± .006)
1 2 3 4 5 6
DETAIL “A” 1.10 0.86
0.18 (.043) (.034)
(.007) MAX REF

SEATING
PLANE 0.22 – 0.38 0.1016 ± 0.0508
(.009 – .015) (.004 ± .002)
TYP 0.650
MSOP (MSE12) 0910 REV D
NOTE: (.0256)
1. DIMENSIONS IN MILLIMETER/(INCH) BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3536fa

26
 LTC3536
Revision History
REV DATE DESCRIPTION PAGE NUMBER
A 11/11 Add new bullet Output Disconnect in Shutdown to Features bullet list. 1
In the Absolute Maximum Ratings section change (Notes 1, 2) to (Note 1) and (Note 2) to (Notes 2, 3). 2
In Electrical Characteristics table add conditions for Error Amplifier Sink Current and Error Amplifier Source Current. 3
In Pin Functions add Exposed Pad Pin 13 and remove last sentence to PGND pin description. 7
Change negative input of Peak Current Limit comparator to 3.4V and negative input of UVLO comparator to 1.75V. 8
Add new section Output Disconnect to Operations section. 12

3536fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27
LTC3536
Typical Application
Backup Power Supply

MAIN POWER
4.7µH* 300mA FOR VIN ≥ 1.8V 12V
1A FOR VIN ≥ 3V
VSYS DC/DC
SW1 SW2 3.3V
VSUPERCAP
1.8V TO 5.5V VIN VOUT
10µF 6.49k 22µF 0.1µF
MODE/SYNC 845k R2 20k
LTC3536 47pF
VCC 20k
SHDN FB VH UV
330pF
100k 49.9k VL OV
RT VC LTC2912-2
GND 182k R1
866k
DIS
10pF GND TMR
6.04k
CRT
PWM BURST
3536 TA04
*COILCRAFT XFL4020

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3536fa

28 Linear Technology Corporation

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