LTC3816

Single-Phase Wide VIN

Range DC/DC Controller for
Intel IMVP-6/IMVP-6.5 CPUs
Features Description
n Supports 7-Bit IMVP-6/IMVP-6.5 VID Code and The LTC®3816 is a single-phase synchronous step-down
Features DC/DC switching regulator controller that drives N-channel
n Wide VIN Range: 4.5V to 36V Operation with power MOSFETs in a constant-frequency voltage mode
Optional Line Feedforward Compensation architecture. The controller’s leading edge modulation to-
n tON(MIN) < 35ns, Capable of Very Low Duty Cycle pology allows extremely low output voltages and supports
n Temperature Compensated Inductor DCR or Sense a phase-lockable switching frequency up to 550kHz. The
Resistor Output Current Monitoring output voltage is programmed using a 7-bit VID code.
n Differential Remote Output Voltage Sensing with
The LTC3816 features all of the IMVP-6/IMVP-6.5 require-
Programmable Active Voltage Positioning
ments, including start-up to a preset boot voltage, differ-
n Phase-Lockable Fixed Frequency: 150kHz to 550kHz
ential remote output voltage sensing with programmable
n Programmable UVLO, Preset VOUT at Boot-Up
active voltage positioning, IMON output current reporting,
n Programmable Slow Slew Rate Sleep State Exit
power optimization during sleep state, and fast or slow
n Internal LDO for Single Supply Operation
slew rate sleep state exit.
n Overvoltage and Overcurrent Protection
n PWRGD and VRTT# Thermal Throttling Flags Fault protection features include input undervoltage
n Power Optimization During Sleep and Light Load lockout, cycle-by-cycle current limit, output overvoltage
n 38-Pin Thermally Enhanced eTSSOP and 5mm × 7mm protection, and PWRGD and overtemperature flags.
QFN Packages L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and RSENSE
is a trademark of Linear Technology Corporation. All other trademarks are the property of their

Applications respective owners. Protected by U.S. Patents, including 5408150, 5055767, 5481178, 6580258.

n Embedded Computing
n Mobile Computers, Internet Devices
n Navigation Displays

Typical Application
High Efficiency, Synchronous IMVP-6/ IMVP-6.5 Step-Down Controller
VCCP V3
VIN
1.1V 3.3V
+ 4.5V TO 36V Efficiency and Power Loss
4.7µF 47µF s2 + 10µF s2 vs Load Current
56Ω 1.9k 1.9k VIN EXTVCC INTVCC 100 10
PWRGD PWRGD TG VIN = 12V, fOSC = 400kHz
CLKEN# CLKEN# 0.1µF 0.33µH, 90 VCC(CORE) = 0.75V, VEXTVCC = 5V 9
BOOST 1.3mΩ FORCED CONTINUOUS MODE
VRTT# VRTT# 80 8
VRON VRON SW VCC(CORE)
DPRSLPVR DPRSLPVR NTC + 70 7
BG
POWER LOSS (W)

MODE/SYNC MODE/SYNC 330µF s3

EFFICIENCY (%)

INTVCC RFREQ BSOURCE + 10µF s20 60 6

LFF 2.55k EFFICIENCY
LTC3816 50 5
ISENP
VID0-VID6 0.1µF 40 4
ISENN
RPTC 6.98k 30 3
CSLEW IMAX 8.25k
RPTC 22pF 10k 20 2
SS
ITCFB VIN + VEXTVCC LOSS
470pF 15nF 14k 10 1
ITC
10k 5.1k IMON 0 0
SERVO PREIMON 0.01 0.1 1 10
12k 22pF 21k 15nF
IMON LOAD CURRENT (A)
VFB
2.2nF 10pF VCC(SEN) 3816 TA01b
COMP VSS(SEN) 3816 TA01
GND

3816f


LTC3816
Absolute Maximum Ratings (Notes 1, 8)

Input Supply Voltage (VIN).......................... –0.3V to 40V DPRSLPVR, VRTT# .................................. –0.3V to 3.3V
Topside Driver Voltage (BOOST)................. –0.3V to 46V VSS(SEN), BSOURCE .................................. –0.3V to 0.3V
Switch Voltage (SW)...................................... –5V to 40V INTVCC RMS Output Current . ................................50mA
INTVCC, EXTVCC, (BOOST-SW) . ................. –0.3V to 6V Operating Junction Temperature Range
ISENN, ITCFB, PREIMON, IMON, RPTC, VRON, VCC(SEN), (Note 3)................................................... –40°C to 125°C
VFB, SS, VIDn, RFREQ, MODE/SYNC, Storage Temperature Range................... –65°C to 125°C
LFF, ISENP, IMAX ..........................–0.3V to INTVCC + 0.3V Lead Temperature (Soldering, 10sec)
PWRGD, CLKEN# . ....................................... –0.3V to 6V eTSSOP.............................................................. 300°C

Pin Configuration
TOP VIEW

ISENN 1 38 IMAX
TOP VIEW
ITCFB 2 37 ISENP

VRTT#
ISENN

ISENP
ITCFB

IMAX

LFF
ITC 3 36 LFF

ITC
PREIMON 4 35 VRTT# 38 37 36 35 34 33 32

IMON 5 34 CLKEN# PREIMON 1 31 CLKEN#

RPTC 6 33 PWRGD IMON 2 30 PWRGD

7 32 SW RPTC 3 29 SW
VRON
VRON 4 28 TG
VSS(SEN) 8 31 TG
VSS(SEN) 5 27 BOOST
VCC(SEN) 9 30 BOOST
39 VCC(SEN) 6 39 26 VIN
SERVO 10 29 VIN
GND SERVO 7 GND 25 EXTVCC
VFB 11 28 EXTVCC
VFB 8 24 INTVCC
COMP 12 27 INTVCC
COMP 9 23 BG
SS 13 26 BG
SS 10 22 BSOURCE
DPRSLPVR 14 25 BSOURCE DPRSLPVR 11 21 MODE/SYNC
CSLEW 15 24 MODE/SYNC CSLEW 12 20 RFREQ
VID0 16 23 RFREQ 13 14 15 16 17 18 19
VID1 17 22 VID6
VID0
VID1
VID2
VID3
VID4
VID5
VID6

VID2 18 21 VID5
UHF PACKAGE
VID3 19 20 VID4 38-LEAD (5mm s 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
FE PACKAGE EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
38-LEAD PLASTIC eTSSOP
TJMAX = 125°C, θJA = 29°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

3816f


 LTC3816
Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3816EFE#PBF LTC3816EFE#TRPBF LTC3816FE 38-Lead Plastic eTSSOP –40°C to 125°C
LTC3816IFE#PBF LTC3816IFE#TRPBF LTC3816FE 38-Lead Plastic eTSSOP –40°C to 125°C
LTC3816EUHF#PBF LTC3816EUHF#TRPBF 3816 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
LTC3816IUHF#PBF LTC3816IUHF#TRPBF 3816 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating junction temperature ranges.
*The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Electrical Characteristics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, BSOURCE = EXTVCC = 0V, VRON = 5V, unless
otherwise noted. (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Input and INTVCC Linear Regulator
VIN VIN Supply Voltage Range VINTVCC > VUVLO l 4.5 36 V
IVIN VIN Supply Current
Normal Mode VBOOST = VINTVCC, fOSC = 400kHz (Note 4) 11 mA
Shutdown VRON = 0V 27 100 µA
INTVCC Internal VCC Voltage l 4.9 5.2 5.5 V
VINTVCC(LINE) Line Regulation 7.5V < VIN < 36V ±1.0 %
VINTVCC(LOAD) Load Regulation Load = 0mA to 20mA –0.25 –1.0 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive 4.25 4.50 4.75 V
VEXTVCC(HYS) EXTVCC Hysteresis 0.4 V
VEXTVCC(DROP) EXTVCC Voltage Drop Load = 20mA, VEXTVCC = 5V 40 100 mV
VUVLO INTVCC Undervoltage Reset INTVCC Ramping Positive 3.7 3.9 4.1 V
Undervoltage Hystersis 0.4 V
Switcher Control Loop
VCC(CORE) VCC(CORE) = (VCC(SEN) – VSS(SEN)) VCC(CORE) > 0.75V (Note 5) l ±0.75 %
0.5V ≤ VCC(CORE) ≤ 0.75V (Note 5) l ±6 mV
0.3V ≤ VCC(CORE) < 0.5V (Note 5) l ±10 mV
∆VCC(CORE) VCC(CORE) Voltage Line Regulation VIN = 7.5V to 36V (Note 5) ±0.002 %/V
AEA Error Amplifier DC Gain No load 80 dB
fBW Error Amplifier Unity-Gain Bandwidth (Note 6) 20 MHz
ICOMP Error Amplifier Output Source Current VCOMP = 0V –1.5 mA
Error Amplifier Output Sink Current VCOMP = 5V 5 mA
IVCC(SEN) VCC(SEN) Input Current VISENN = VCC(SEN), 0V ≤ VCC(SEN) ≤ 1.5V ±30 µA
IVSS(SEN) VSS(SEN) Input Current VSS(SEN) = 0V –60 µA
IVFB VFB Input Current 0V ≤ VFB ≤ 2V ±0.1 µA
IITCFB ITCFB Input Current 0V ≤ VITCFB ≤ 1.5V ±0.1 µA

3816f


LTC3816
Electrical Characteristics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, BSOURCE = EXTVCC = 0V, VRON = 5V, unless
otherwise noted. (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VBOOT Core Supply Start-Up Voltage VIMON = INTVCC (IMVP-6 Configuration) 1.2 V
VIMON < 1.1V (IMVP-6.5 Configuration) 1.1 V
VOVF Overvoltage Fault Threshold VIMON = INTVCC (IMVP-6 Configuration) l 1.65 1.7 V
VIMON < 1.1V (IMVP-6.5 Configuration) l 1.53 1.55 V
ISS SS Pull-Up Current VSS = 0V –1 µA
ICSLEW CSLEW Pull-Up Current VCSLEW = 0V
IMVP-6 and VDPRSLPVR = INTVCC –10 µA
IMVP-6.5 or VDPRSLPVR = 0V –40 µA
IRPTC RPTC Source Current RPTC = 0V –90 –100 –110 µA
VRPTC RPTC Thermal Shutdown Threshold 0.47 V
IMAX IMAX Source Current VIMAX = 0V, 1× Current Limit Duration l –9 –10 –11 µA
VIMAX = 0V, 2× Current Limit Duration –20 µA
tIMAX2× 2× Current Limit Duration 35 45 µs
2× Current Limit Period 630 µs
VILIM Current Comparator Offset VIMAX = 1.0V, VILIM = VISENP – VIMAX ±3 mV
VIREV Reverse-Current Comparator Offset VISENN = 1.0V, VIREV = VISENP – VISENN ±2 mV
IISENP ISENP Input Current 0V ≤ VISENP ≤ 1.5V ±1 µA
IISENN ISENN Input Current 0V ≤ VISENN ≤ 1.5V ±20 µA
VIMON IMVP-6/IMVP-6.5 Selection Threshold 2.4 V
IVRON Regulator On Source Current VRON = 0V –1 µA
VRON Regulator On Threshold Rising Edge 1.18 1.2 1.22 V
Regulator Power-Down Threshold Falling Edge 0.65 V
Oscillator and Drivers
fOSC Oscillator Frequency RFREQ Floats 375 400 425 kHz
VRFREQ = 0V 180 210 240 kHz
VRFREQ = 2.5V 530 580 640 kHz
fSYNC Minimum Synchronization Input Frequency 150 kHz
Maximum Synchronization Input Frequency 550 kHz
VSYNC MODE/SYNC Synchronization Threshold 1.6 V
IRFREQ RFREQ Source Current VRFREQ = 0V –9 –10 –11 µA
VMODE MODE/SYNC Force Continuous Threshold VIMON = INTVCC (IMVP-6 Configuration) 1.6 V
VIMON < 1.1V (IMVP-6.5 Configuration) 0.5 V
DCMAX Maximum TG Duty Cycle MODE/SYNC = 0, RFREQ Floats 90 %
tON(MIN) TG Minimum Pulse Width (Note 6) 35 ns
tDEAD Driver Dead-Time 30 ns
TG RUP TG Driver Pull-Up On-Resistance TG High, IOUT = –100mA (Note 7) 2.6 Ω
TG RDOWN TG Driver Pull-Down On-Resistance TG Low, IOUT = 100mA (Note 7) 1.2 Ω
BG RUP BG Driver Pull-Up On-Resistance BG High, IOUT = –100mA (Note 7) 2.6 Ω
BG RDOWN BG Driver Pull-Down On-Resistance BG Low, IOUT = 100mA (Note 7) 0.9 Ω

3816f


 LTC3816
Electrical Characteristics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, BSOURCE = EXTVCC = 0V, VRON = 5V, unless
otherwise noted. (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VID, DPRSLPVR, LFF Parameters
VIL(VID) VID Input Low Threshold 0.3 V
VIH(VID) VID Input High Threshold 0.7 V
IVID VID Input Leakage Current 0V ≤ VVID ≤ 5V ±1 µA
VDPRSLPVR DPRSLPVR Input Threshold VIMON = INTVCC (IMVP-6 Configuration) 1.6 V
ILFF LFF Pull-Up Current VLFF = 0V –1 µA
VLFF LFF Input Threshold 1 V
PWRGD, CLKEN#, VRTT#
VPWRGD Positive Power Good Threshold With Respect to VID VCC(CORE) 150 175 200 mV
Negative Power Good Threshold –240 –270 –300 mV
ILEAK PWRGD, CLKEN# Leakage Current VPWRGD = VCLKEN# = 5V 10 µA
VRTT# Leakage Current VVRTT# = 3.3V 100 µA
VOL PWRGD, CLKEN# Output Low Voltage IOUT = 2mA 0.1 0.3 V
VRTT# Output Low Voltage IOUT = 20mA 0.075 0.18 V
tPWRGD PWRGD Glitch Filter Power Good to Power Bad 750 µs
tCLKEN# CLKEN# Falling Edge Delay Rising VBOOT Edge to CLKEN# l 50 75 100 µs
Falling Edge
tCLK(PWRGD) CLKEN# to PWRGD Rising Edge Delay l 5 10 20 ms
tVR(PWRGD) VRON to PWRGD Falling Edge Delay VRON Falling Edge 100 ns

Note 1: Stresses beyond those listed under Absolute Maximum Note 4: The dynamic input supply current is a function of the power
Ratings may cause permanent damage to the device. Exposure to any MOSFET gate charging (QG • fOSC). See Applications Information for
Absolute Maximum Rating condition for extended periods may affect more information.
device reliability and lifetime. Note 5: The LTC3816 is measured in a feedback loop that adjusts
Note 2: All currents into device pins are positive; all currents out of VCC(SEN) – VSS(SEN) to achieve a specified COMP pin voltage. The AITC
device pins are negative. All voltages are referenced to ground unless amplifier is configured as an inverter with gain = –1.
otherwise specified. Note 6: Guaranteed by design, not subject to test.
Note 3: The LTC3816 is tested under pulse load conditions such that Note 7: On-resistance limit is guaranteed by design and correlation
TJ ≈ TA. The LTC3816E is guaranteed to meet performance specifications with statistical process controls.
from 0°C to 85°C. Specifications over the –40°C to 125°C operating Note 8: The LTC3816 includes overtemperature protection that is
junction temperature range are assured by design, characterization and intended to protect the device during momentary overload conditions.
correlation with statistical process controls. LTC3816I specifications are The maximum rated junction temperature will be exceeded when this
guaranteed over the full –40°C to 125°C operating junction temperature protection is active. Continuous operation above the specified absolute
range. Note that the maximum ambient temperature consistent with maximum operating junction temperature may impair device reliability
these specifications is determined by specific operating conditions in or permanently damage the device.
conjunction with board layout, the rated package thermal impedance
and other environmental factors. TJ is calculated from the ambient
temperature, TA, and power dissipation, PD, according to the following
formula,
LTC3816EFE: TJ = TA + (PD • 29°C/W)
LTC3816EUHF: TJ = TA + (PD • 34°C/W)

3816f


LTC3816
Typical Performance Characteristics
Efficiency vs Load Current Efficiency vs VCC(CORE) Efficiency vs VIN with VEXTVCC = 0V
100 100 100
VIN = 12V, fOSC = 400kHz VIN = 12V, fOSC = 400kHz, VEXTVCC = 0V VCC(CORE) = 0.75V, fOSC = 400kHz
90 VCC(CORE) = 0.75V, VEXTVCC = 0V 90 FORCED CONTINOUS MODE 90 VEXTVCC = 0V
LAST PAGE CIRCUIT LAST PAGE CIRCUIT FORCED CONTINOUS MODE
80 80 80
LAST PAGE CIRCUIT
70 70 70

EFFICIENCY (%)
EFFICIENCY (%)

EFFICIENCY (%)
60 60 60
50 PULSE-SKIPPING 50 50
MODE
40 40 40
30 30 30
FORCED CONTINUOUS VCC(CORE) = 0.50V
20 MODE 20 20 VIN = 5V
VCC(CORE) = 0.75V
10 10 VCC(CORE) = 1.00V 10 VIN = 12V
VCC(CORE) = 1.20V VIN = 24V
0 0 0
0.01 0.1 1 10 0.01 0.1 1 10 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
3816 G01 3816 G02 3816 G03

Efficiency vs fOSC with Efficiency vs fOSC with

Efficiency vs VIN with VEXTVCC = 5V VEXTVCC = 0V VEXTVCC = 5V
100 100 100
VCC(CORE) = 0.75V, fOSC = 400kHz VIN = 12V, VCC(CORE) = 0.75V VIN = 12V, VCC(CORE) = 0.75V
90 VEXTVCC = 5V 90 VEXTVCC = 0V 90 VEXTVCC = 5V
FORCED CONTINOUS MODE FORCED CONTINOUS MODE FORCED CONTINOUS MODE
80 80 80
LAST PAGE CIRCUIT LAST PAGE CIRCUIT LAST PAGE CIRCUIT
70 70 70
EFFICIENCY (%)

EFFICIENCY (%)
EFFICIENCY (%)

60 60 60
50 50 50
40 40 40
30 30 30
20 20 fOSC = 210kHz 20 fOSC = 210kHz
10 VIN = 12V 10 fOSC = 400kHz 10 fOSC = 400kHz
VIN = 24V fOSC = 580kHz fOSC = 580kHz
0 0 0
0.01 0.1 1 10 0.01 0.1 1 10 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
3816 G04 3816 G05 3816 G06

Load Regulation with

VCC(CORE) vs Temperature AVP Slope = –3mV/A
0.755 10
VIN = 12V, fOSC = 400kHz
0.754 0 VEXTVCC = 0V
0.753 AVP SLOPE = –3mV/A
–10 FORCED CONTINOUS MODE
0.752 LAST PAGE CIRCUIT
–20
∆VCC(CORE) (mV)
VCC(CORE) (V)

0.751
–30
0.750
–40
0.749
–50
0.748
0.747 –60

0.746 –70 VCC(CORE) = 0.5V

VCC(CORE) = 1.2V
0.745 –80
–50 –25 0 25 50 75 100 125 0 4 8 12 16 20 24 28
TEMPERATURE (°C) LOAD CURRENT (A)
3816 G07 3816 G08

3816f


 LTC3816
Typical Performance Characteristics
Load Regulation vs Temperature Line Regulation
0 0.7520
fOSC = 400kHz, VEXTVCC = 0V
–10 5A LOAD FORCED CONTINUOUS MODE
0.7515
NO LOAD
–20
10A LOAD PTC CONFIGURATION (FIGURE 12) 0.7510 LAST PAGE CIRCUIT
–30 RLPTC = VISHAY TFPT1206L1002FV
∆VCC(CORE) (mV)

RVDCRP = 23.2k, CVDCRP = 10nF 0.7505

VCC(CORE) (V)
–40
NTC CONFIGURATION,
–50 LAST PAGE CIRCUIT 0.7500
20A LOAD NO TEMPERATURE COMPENSATION
–60 0.7495
LAST PAGE CIRCUIT, REPLACE NTC
–70 WITH 10k RESISTOR
IDEAL VALUE 0.7490
–80 VIN = 12V, fOSC = 400kHz
VEXTVCC = 0V, AVP = –3mV/A 0.7485
–90
L = VISHAY IHLP5050CE01 0.33µH
–100 0.7480
–50 –25 0 25 50 75 100 125 0 4 8 12 16 20 24 28
TEMPERATURE (°C) VIN (V)
3816 G09 3816 G10

Load Step in Forced Continuous

VIMON vs Temperature Mode
1.1
VIN = 12V, fOSC = 400kHz
1.0 VEXTVCC = 0V, AVP = –3mV/A
0.9 RPREIMON = 5.1k, RIMON = 21k
20A LOAD PTC CONFIGURATION (FIGURE 12)
0.8
RLPTC = VISHAY TFPT1206L1002FV VCC(CORE)
0.7 RVDCRP = 23.2k, CVDCRP = 10nF 50mV/DIV
VIMON (V)

0.6 NTC CONFIGURATION,

LAST PAGE CIRCUIT
0.5
10A LOAD NO TEMPERATURE COMPENSATION
0.4 LAST PAGE CIRCUIT, REPLACE NTC LOAD
WITH 10k RESISTOR CURRENT
0.3 20A/DIV
5A LOAD IDEAL VALUE
0.2
0.1
L = VISHAY IHLP5050CE01 0.33µH
0 3816 G12
–50 –25 0 25 50 75 100 125 VIN = 12V 20µs/DIV
TEMPERATURE (°C) VCC(CORE) = 0.75V
fOSC = 400kHz
3816 G11
FORCED CONTINUOUS MODE
AVP SLOPE = –3mV/A

Narrow TG Pulse Width with Low Pulse-Skipping Mode at No Load Pulse-Skipping Mode
VCC(CORE) Ripple with Low VCC(CORE) Ripple at 0.2A Load
VCC(CORE)
20mV/DIV VCC(CORE) VCC(CORE)
VTG-VSW 20mV/DIV 20mV/DIV
2V/DIV

VBG
5V/DIV VTG-VSW
2V/DIV
VTG-VSW
2V/DIV
ZOOM IN
VTG-VSW
1V/DIV VBG VBG
20ns/DIV 5V/DIV 5V/DIV
∆t = 24.6ns
3816 G13 3816 G14 3816 G15
VIN = 28V 20µs/DIV VIN = 12V 100µs/DIV VIN = 12V 5µs/DIV
VCC(CORE) = 0.5V (ILOAD = 0.5A) VCC(CORE) = 0.75V, NO LOAD VCC(CORE) = 0.75V (ILOAD = 0.2A)
fOSC = 400kHz fOSC = 400kHz fOSC = 400kHz
FORCED CONTINUOUS MODE PULSE-SKIPPING MODE PULSE-SKIPPING MODE
3816f


LTC3816
Typical Performance Characteristics
Start-Up to VBOOT VBOOT to PWRGD Delay VRON Shutdown

VCC(CORE) VCC(CORE) VCC(CORE)

200mV/DIV 200mV/DIV 200mV/DIV

CLKEN# CLKEN# CLKEN#

5V/DIV 5V/DIV 5V/DIV
PWRGD PWRGD
PWRGD 5V/DIV 5V/DIV
5V/DIV

VRON VRON VRON

5V/DIV 5V/DIV 5V/DIV
3816 G16 3816 G17 3816 G18
VIN = 12V 100µs/DIV VIN = 12V 2ms/DIV VIN = 12V 10µs/DIV
IMVP6 CONFIGURATION IMVP6 CONFIGURATION VID = 0.75V
CSS = 470pF CSS = 470pF NO LOAD
VID = 0.75V VID = 0.75V
NO LOAD NO LOAD

Momentary Overcurrent, Momentary Overcurrent,

45µs IMAX Pulse 90µs IMAX Pulse 2x Overcurrent

VCC(CORE) VCC(CORE) VCC(CORE)

100mV/DIV 100mV/DIV 100mV/DIV

20µs ILOAD 60µs ILOAD 20µs ILOAD

10A/DIV 10A/DIV 20A/DIV

IL IL IL
10A/DIV 10A/DIV 20A/DIV

VRIMAX VRIMAX VRIMAX

20mV/DIV 20mV/DIV 20mV/DIV

3816 G19 3816 G20 3816 G21

VIN = 12V 10µs/DIV VIN = 12V 20µs/DIV VIN = 12V 10µs/DIV
VCC(CORE) = 1V VCC(CORE) = 1V VCC(CORE) = 1V
RIMAX = 1.5k RIMAX = 1.5k RIMAX = 1.5k
RSENSE = 1mΩ RSENSE = 1mΩ RSENSE = 1mΩ
FORCED CONTINUOUS MODE FORCED CONTINUOUS MODE FORCED CONTINUOUS MODE

Current Comparator Offset Current Comparator Offset Duty Cycle vs VCOMP with Line
vs Common Mode Range vs Temperature Feedforward
2.0 2.0 100
VIN = 12V VIN = 12V
90
1.5 VIMAX – VISENN = 20mV 1.5 VISENN = 1V
VIMAX – VISENN = 20mV 80
1.0 1.0
70
VISENP – VIMAX (mV)

VISENP – VIMAX (mV)

DUTY CYCLE (%)

0.5 0.5 60
0 0 50

–0.5 40
–0.5 fOSC = 400kHz
30 LFF = FLOAT
–1.0 –1.0 VIN = 5V
20 VIN = 12V
–1.5 –1.5 10 VIN = 24V
VIN = 36V
–2.0 –2.0 0
0 0.25 0.5 0.75 1 1.25 1.5 –50 –25 0 25 50 75 100 125 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VISENN (V) TEMPERATURE (°C) VCOMP (V)
3816 G22 3816 G23 3816 G24

3816f


 LTC3816
Typical Performance Characteristics
Duty Cycle vs VCOMP without Line
Feedforward fOSC vs Temperature VRPTC vs Temperature
100 700 480 120
VIN = 12V
90 fOSC = 400kHz VRFREQ = 2.5V

VRPTC NEGATIVE THRESHOLD (mV)

VRPTC POSITIVE THRESHOLD (mV)
LFF = 0V 600 475 115
80
VRPTC POSITIVE THRESHOLD
70
500 470 110
DUTY CYCLE (%)

60

fOSC (kHz)
RFREQ FLOATS
50 400 465 105
40 VRPTC NEGATIVE THRESHOLD
300 460 100
30
VRFREQ = 0V
20
200 455 95
10
0 100 450 90
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
VCOMP (V) TEMPERATURE (°C) TEMPERATURE (°C)
3816 G25 3816 G26 3816 G27

IIMAX, IRFREQ and IRPTC

vs Temperature VRON vs Temperature INTVCC UVLO vs Temperature
11.50 105.0 1.4 4.1
VEXTVCC = 0V
11.25 102.5 1.3 VRON RAMPS HIGH,
4.0
IRPTC REGULATOR ON THRESHOLD
11.00 100.0 1.2 VIN RAMPS HIGH
VRON RAMPS LOW, 3.9
VRON THRESHOLD (V)

1.1
IRFREQ, IIMAX (µA)

REGULATOR OFF THRESHOLD

INTVCC UVLO (V)
10.75 97.5
IRPTC (µA)

1.0 3.8
10.50 95.0
0.9 VRON RAMPS HIGH, 3.7
10.25 92.5 POWER-UP THRESHOLD
IRFREQ, IIMAX 0.8
3.6
10.00 90.0
0.7 VIN RAMPS LOW
9.75 87.5 3.5
0.6 VRON RAMPS LOW,
POWER-DOWN THRESHOLD
9.50 85.0 0.5 3.4
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3816 G28 3816 G29 3816 G30

INTVCC Line Regulation INTVCC Load Regulation INTVCC Dropout vs Temperature

5.4 0 0 0
VEXTVCC = 0V VEXTVCC = 0V VEXTVCC = 0V
fOSC = 400kHz fOSC = 400kHz
5.2
LOAD CURRENT = 20mA
INTVCC DROPOUT VOLTAGE (V)

–0.2
∆INTVCC WITH VIN = 12V (mV)

∆INTVCC WITH VIN = 5V (mV)

–10 –300 ∆INTVCC = –1%

5.0
–0.4
VINTVCC (V)

4.8
–20 VIN = 12V –600
4.6 –0.6
VIN = 5V
4.4
–30 –900
–0.8
4.2

4.0 –40 –1200 –1.0

0 5 10 15 20 25 30 35 40 0 10 20 30 40 50 –50 –25 0 25 50 75 100 125
VIN (V) ILOAD (mA) TEMPERATURE (°C)
3816 G31 3816 G32 3816 G33

3816f


LTC3816
Typical Performance Characteristics
EXTVCC Switchover Voltage EXTVCC Voltage Drop
vs Temperature vs Temperature IVIN
4.8 120 15 50
VEXTVCC = 5V VEXTVCC = 0V
4.7 fOSC = 400kHz fOSC = 400kHz
EXTVCC SWITCHOVER VOLTAGE (V)

100 14 40
4.6 ILOAD = 50mA

VEXTVCC – VINTVCC (mV)

IVIN (SHUTDOWN) (µA)

EXTVCC RAMPS HIGH
4.5 80
13 30

IVIN (mA)
4.4 IVIN (SHUTDOWN)
60
4.3 ILOAD = 20mA 12 20
4.2 40
IVIN
EXTVCC RAMPS LOW
4.1 11 10
20 NO LOAD
4.0

3.9 0 10 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 0 5 10 15 20 25 30 35 40
TEMPERATURE (°C) TEMPERATURE (°C) VIN (V)
3816 G34 3816 G35 3816 G36

IVIN (Shutdown) vs Temperature IVIN and IEXTVCC vs Temperature

60 15
VEXTVCC = VRON = 0V VIN = 12V
fOSC = 400kHz
50 VIN = 40V 14

13
40
IVIN, IEXTVCC (mA)

VEXTVCC = 0V, IVIN

IVIN (µA)

VIN = 12V 12
30
11
20 VIN = 5V VEXTVCC = 5V, IEXTVCC
10

10
9

0 8
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
3816 G37 3816 G38

VCC(SEN) and ISENN Input Current

vs Common Mode Range VSS(SEN) Input Current
20 0
VIN = 12V VIN = 12V
VISENN = VCC(SEN) VISENN = VCC(SEN)
15 VITC = VITCFB VITC = VITCFB
VSS(SEN) = 0V –10
VCC(CORE) = 0.3V
IVCC(SEN), IISENN (µA)

10
IVCC(SEN)
IVSS(SEN) (µA)

–20 VCC(CORE) = 0.9V

5 IISENN
VCC(CORE) = 1.5V
–30
0

–5 –40

–10 –50
0 0.25 0.50 0.75 1.00 1.25 1.50 –0.3 –0.2 –0.1 0 0.1 0.2 0.3
VCC(SEN) (V) VSS(SEN) (V)
3816 G39 3816 G40

3816f

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 LTC3816
Pin Functions (eTSSOP/QFN)

ISENN (Pin 1/Pin 36): Current Sense Negative Input. Con- VRON (Pin 7/Pin 4): Voltage Regulator Enable Input. The
nect this pin to the negative terminal of the current sense VRON pin power-up threshold is 1.2V. When forced below
resistor or the negative terminal of the inductor DCR 0.65V, a power-down sequence is initiated where the
lowpass filter. VCC(CORE) output is ramped down near 0V before the IC
is put into a low current shutdown mode. The VRON pin
ITCFB (Pin 2/Pin 37): Inductor DCR Temperature Compen-
has an internal 1µA pull-up current.
sation Amplifer Feedback Input. To derive the temperature
compensated voltage dropped across the inductor DCR, VSS(SEN) (Pin 8/Pin 5): Processor VCC(CORE) Negative
connect a resistor from the SW node to this pin. An NTC Terminal Voltage Sense. Negative input of the differential
network, in parallel with a capacitor, forms the feedback sense amplifier. Connect to the processor VSS(SEN) pin.
path of this amplifier. For applications that use a discrete VCC(SEN) (Pin 9/Pin 6): Processor VCC(CORE) Positive
resistor for current sensing, replace the NTC network Terminal Voltage Sense. Positive input of the differential
with a resistor. sense amplifier. Connect to the processor VCC(SEN) pin.
ITC (Pin 3/Pin 38): Inductor DCR Temperature Compen- SERVO (Pin 10/Pin 7): Error Amplifier AC Input. The
sation Amplifer Output. The IMON circuitry and the error controller servos the switcher output voltage to the VID
amplifier obtain the temperature compensated DCR voltage
DAC voltage through the error amplifier.
through this amplifier.
VFB (Pin 11/Pin 8): Error Amplifier Negative Input Pin.
PREIMON (Pin 4/Pin 1): IMON Current Output Setting. VFB is servoed to 1.3V.
PREIMON is servoed to the ISENN potential. A resistor from
PREIMON to ITC sets the IMON output current. For the IMVP-6 COMP (Pin 12/Pin 9): Error Amplifier Output. The COMP
configuration, connect this pin to INTVCC. pin is connected directly to the error amplifier output and
the input of the line feedforward circuit. Use an RC network
IMON (Pin 5/Pin 2): IMVP-6/IMVP-6.5 Configuration Selec-
between the COMP pin and the VFB pin to compensate
tion and Output Current Monitor. Connect this pin to INTVCC the feedback loop for stability and optimum transient
to select the IMVP-6 configuration. At start-up, the switcher
response.
VOUT is ramped to 1.2V (VBOOT). In deeper sleep mode,
the controller enables the slow VOUT slew rate. Connect a SS (Pin 13/Pin 10): Soft-Start Input. The SS pin has an
resistor to VSS(SEN) to select the IMVP-6.5 configuration. internal 1µA current source pull-up. A capacitor connected
In this case, VBOOT equals 1.1V, slow slew rate is disabled to this pin controls the output voltage start-up. SS is
and the IMON current source is proportional to the load. In forced low if VRON or PWRGD is low, or if an overvoltage
the IMVP-6.5 configuration, this pin is internally clamped or overcurrent fault occurs. If the potential at SS is less
to 1.1V with respect to the VSS(SEN) pin. than 0.3V, the IMAX sourcing current is reduced to 2.5µA
and the current limit threshold is reduced to 25% of its
RPTC (Pin 6/Pin 3): Nonlinear PTC Thermistor Input.
nominal value.
Connect to a nonlinear PTC thermistor for MOSFET or
inductor temperature sensing. This pin is pulled up by a DPRSLPVR (Pin 14/Pin 11): Deeper Sleep Mode. For the
100µA current source. If the potential at RPTC is higher IMVP-6 configuration, 25µs after DPRSLPVR is asserted
than 0.47V, thermal flag VRTT# is pulled low. RPTC is high, the controller enables the VOUT slow slew rate tran-
sensitive to noise pickup. Avoid coupling high frequency sition. To disable slow slew rate mode, force DPRSLPVR
switching signals to this pin. If required, bypass this low. Upon power-up, the DPRSLPVR input is ignored until
pin with a capacitor to GND. PWRGD is asserted.

3816f

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LTC3816
Pin Functions (eTSSOP/QFN)

CSLEW (Pin 15/Pin 12): VID DAC Slew Rate Control. BSOURCE (Pin 25/Pin 22): Bottom MOSFET Source. Con-
CSLEW is internally pulled up by a current source. Add a nect this pin to the source of the bottom power MOSFET.
capacitor to program the VID DAC transition slew rate. If Do not short BSOURCE to the LTC3816 exposed pad
slow slew rate is selected, a 100pF capacitor connected directly.
to CSLEW results in a VID DAC slew rate of 1.25mV/µs.
BG (Pin 26/Pin 23): Bottom Gate Drive. The BG pin drives
When slow slew rate is disabled, a 100pF capacitor results
the gate of the bottom N-channel synchronous switch
in a VID DAC slew rate of 5mV/µs. Avoid coupling high
MOSFET.
frequency switching signals to this pin. For the IMVP-6.5
configuration, the slow slew rate function is disabled. INTVCC (Pin 27/Pin 24): Output of the Internal Linear
Low Dropout Regulator. The driver and control circuits
VID0-VID6 (Pins 16-22/Pins 13-19): VID DAC Voltage are powered from this voltage source. The INTVCC pin
Control Logic Inputs. See Table 1. must be decoupled to GND with a minimum 4.7µF low
RFREQ (Pin 23/Pin 20): Frequency Setting. The voltage ESR ceramic capacitor (X5R or better).
on the RFREQ pin determines the free-running operating EXTVCC (Pin 28/Pin 25): External Power Input to an Inter-
frequency. The RFREQ pin has an internal 10µA current nal Switch Connected to INTVCC. This switch closes and
source pull-up allowing the switching frequency to be supplies the IC power, bypassing the internal low dropout
programmed by a single external resistor to GND. Alter- regulator, whenever EXTVCC is higher than 4.5V. Do not
natively, this pin can be driven with a DC voltage source exceed 6V on this pin.
to control the frequency of the internal oscillator. Floating
this pin or shorting this pin to INTVCC allows the controller VIN (Pin 29/Pin 26): Main Supply Pin. A bypass capacitor
to run at a fixed 400kHz frequency. should be connected from this pin to the GND pin.
MODE/SYNC (Pin 24/Pin 21): Mode Select/Synchroniza- BOOST (Pin 30/Pin 27): Top Gate Driver Supply. The BOOST
tion Input. This pin is pulled up by an internal 1µA current pin should be decoupled to the SW node with a 0.1µF low
source. Floating this pin or shorting it to INTVCC enables ESR (X5R or better) ceramic capacitor. An external Schottky
pulse-skipping mode. Shorting this pin to ground con- diode from INTVCC to BOOST creates a complete floating
figures forced continuous mode. During frequency syn- charge-pumped supply from BOOST to SW.
chronization, the phase-locked loop forces the controller TG (Pin 31/Pin 28): Top Gate Drive. The TG pin drives
to operate in continuous mode with the falling top gate the top N-channel MOSFET with a voltage swing equal to
signal synchronized to the falling edge of the MODE/SYNC INTVCC superimposed on the switch node voltage.
input pulse. During start-up, the controller is forced to run
in pulse-skipping mode.

3816f

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 LTC3816
Pin Functions (eTSSOP/QFN)

SW (Pin 32/Pin 29): Switching Node. Connect SW to the LFF (Pin 36/Pin 33): Line Feedforward. This pin has a
source of the upper power MOSFET and to the negative 1µA pull-up current source to INTVCC. Floating this pin
terminal of the BOOST pin decoupling capacitor. or connecting it to INTVCC enables the line feedforward
compensation. Connect this pin to GND to disable the line
PWRGD (Pin 33/Pin 30): Open-Drain Power Good Out-
feedforward compensation.
put/Power Bad Latchoff Input. PWRGD is an open-drain
output pin and can be connected to other open-drain ISENP (Pin 37/Pin 34): Current Sense Positive Input. Con-
outputs to implement wire-ORing. PWRGD is externally nect this pin to the positive terminal of the current sense
pulled high 10ms after the output regulates. After start-up, resistor or to the output of the inductor DCR lowpass
if a fault condition causes PWRGD to go low, or PWRGD filter.
is externally pulled low, the regulator output voltage is IMAX (Pin 38/Pin 35): Current Comparator Threshold Set-
actively ramped to 0V and PWRGD remains latched low ting. The IMAX pin has an internal 10µA pull-up current
until either the power is cycled or VRON toggles. PWRGD source, allowing the current limit comparator threshold to
has a 750µs de-glitch delay and is masked for 100µs after
be programmed by a single external resistor. The control-
the VID code changes. In deeper sleep mode, the PWRGD
ler allows a momentary 45µs overcurrent event to occur
comparators are disabled and not allowed to de-assert
within a period of 630µs. See Current Sense and Current
the PWRGD pin.
Limit in Applications Information.
CLKEN# (Pin 34/Pin 31): Open-Drain Clock Enable Indica-
GND (Exposed Pad Pin 39/Exposed Pad Pin 39): Ground.
tor. 75µs after VCC(CORE) reaches the VBOOT voltage, CLKEN#
The soft-start and slew rate control capacitors as well as
pulls low to enable the processor phase-locked loop.
the frequency setting and thermal shutdown resistors
VRTT# (Pin 35/Pin 32): Open-Drain Output for Voltage should return to this exposed pad ground pin. This GND
Regulator Thermal Throttling. The VRTT# pin pulls low if pin should also be connected to the negative terminals of
the RPTC voltage exceeds 0.47V or if the control IC junc- the local voltage regulator output capacitors through vias
tion temperature exceeds 150°C. to the PCB ground plane.

3816f

13
LTC3816
Functional Diagram
3.3V 3.3V 1.1V
CINTVCC
1.9k 1.9k 56Ω

PWRGD CLKEN# VRTT# DPRSLPVR LFF EXTVCC INTVCC VIN

VIN
EN CLK +
– CIN

PWRGD
+ LDO
4.7V

100µA
RPTC
+
VID0-VID6 BANDGAP
+ TSD
– 0.47V INTVCC PTC
CHIP TSD – 0.5V/1.6V INTVCC
DB
10µA/40µA DAC BOOST
1µA
CSLEW CB
TG
QT
CSLEW L
INTVCC SW
SAW VOUT
+ LOGIC INTVCC +
PWM D COUT
1µA VIN LFF – BG
QB
NTC
MODE/SYNC
EN CLK
BSOURCE
10µA DELAY INTVCC
RFREQ POWER
PWRGD AND
DOWN –OVP+ OVF IREV –ILIM+
LATCH – + – + 10µA
RFREQ RIDCR
ISENP
DAC 1.65V/1.53V IMAX RIMAX CIDCR
+ 25mV IMVP-6
ISENN
1µA
VRON ON RAVPDCRN
+ VAVP
+ +
–
– + RSER RPAR
–NPG+ AITC ITCFB
1.2V – PPG
– + 1x –
2.4V INTVCC ITC CVDCR
INTVCC
PREIMON RPREIMON
DAC + 0.175V
1µA IMON
SS DAC – 0.270V
IMON
DA OUT
CSS OC FAULT RIMON CIMON
OV FAULT 1.3V DAC – VAVP VSS(SEN)
+
–
EA + DAMP VCC(SEN)
–
+

GND
COMP VFB SERVO
CC
RC R1

CC1 CFF

Figure 1. Functional Diagram

3816f

14
 LTC3816
Operation (Refer to Funtional Diagram)
Table 1. IMVP-6/IMVP-6.5 VID Output Voltage Programming
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC(CORE) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC(CORE)
0 0 0 0 0 0 0 1.5000 1 0 0 0 0 0 0 0.7000
0 0 0 0 0 0 1 1.4875 1 0 0 0 0 0 1 0.6875
0 0 0 0 0 1 0 1.4750 1 0 0 0 0 1 0 0.6750
0 0 0 0 0 1 1 1.4625 1 0 0 0 0 1 1 0.6625
0 0 0 0 1 0 0 1.4500 1 0 0 0 1 0 0 0.6500
0 0 0 0 1 0 1 1.4375 1 0 0 0 1 0 1 0.6375
0 0 0 0 1 1 0 1.4250 1 0 0 0 1 1 0 0.6250
0 0 0 0 1 1 1 1.4125 1 0 0 0 1 1 1 0.6125
0 0 0 1 0 0 0 1.4000 1 0 0 1 0 0 0 0.6000
0 0 0 1 0 0 1 1.3875 1 0 0 1 0 0 1 0.5875
0 0 0 1 0 1 0 1.3750 1 0 0 1 0 1 0 0.5750
0 0 0 1 0 1 1 1.3625 1 0 0 1 0 1 1 0.5625
0 0 0 1 1 0 0 1.3500 1 0 0 1 1 0 0 0.5500
0 0 0 1 1 0 1 1.3375 1 0 0 1 1 0 1 0.5375
0 0 0 1 1 1 0 1.3250 1 0 0 1 1 1 0 0.5250
0 0 0 1 1 1 1 1.3125 1 0 0 1 1 1 1 0.5125
0 0 1 0 0 0 0 1.3000 1 0 1 0 0 0 0 0.5000
0 0 1 0 0 0 1 1.2875 1 0 1 0 0 0 1 0.4875
0 0 1 0 0 1 0 1.2750 1 0 1 0 0 1 0 0.4750
0 0 1 0 0 1 1 1.2625 1 0 1 0 0 1 1 0.4625
0 0 1 0 1 0 0 1.2500 1 0 1 0 1 0 0 0.4500
0 0 1 0 1 0 1 1.2375 1 0 1 0 1 0 1 0.4375
0 0 1 0 1 1 0 1.2250 1 0 1 0 1 1 0 0.4250
0 0 1 0 1 1 1 1.2125 1 0 1 0 1 1 1 0.4125
0 0 1 1 0 0 0 1.2000 1 0 1 1 0 0 0 0.4000
0 0 1 1 0 0 1 1.1875 1 0 1 1 0 0 1 0.3875
0 0 1 1 0 1 0 1.1750 1 0 1 1 0 1 0 0.3750
0 0 1 1 0 1 1 1.1625 1 0 1 1 0 1 1 0.3625
0 0 1 1 1 0 0 1.1500 1 0 1 1 1 0 0 0.3500
0 0 1 1 1 0 1 1.1375 1 0 1 1 1 0 1 0.3375
0 0 1 1 1 1 0 1.1250 1 0 1 1 1 1 0 0.3250
0 0 1 1 1 1 1 1.1125 1 0 1 1 1 1 1 0.3125
0 1 0 0 0 0 0 1.1000 1 1 0 0 0 0 0 0.3000
0 1 0 0 0 0 1 1.0875 1 1 0 0 0 0 1 0.2875
0 1 0 0 0 1 0 1.0750 1 1 0 0 0 1 0 0.2750
0 1 0 0 0 1 1 1.0625 1 1 0 0 0 1 1 0.2625
0 1 0 0 1 0 0 1.0500 1 1 0 0 1 0 0 0.2500
0 1 0 0 1 0 1 1.0375 1 1 0 0 1 0 1 0.2375
0 1 0 0 1 1 0 1.0250 1 1 0 0 1 1 0 0.2250
0 1 0 0 1 1 1 1.0125 1 1 0 0 1 1 1 0.2125
0 1 0 1 0 0 0 1.0000 1 1 0 1 0 0 0 0.2000
0 1 0 1 0 0 1 0.9875 1 1 0 1 0 0 1 0.1875
0 1 0 1 0 1 0 0.9750 1 1 0 1 0 1 0 0.1750
0 1 0 1 0 1 1 0.9625 1 1 0 1 0 1 1 0.1625
0 1 0 1 1 0 0 0.9500 1 1 0 1 1 0 0 0.1500
0 1 0 1 1 0 1 0.9375 1 1 0 1 1 0 1 0.1375
0 1 0 1 1 1 0 0.9250 1 1 0 1 1 1 0 0.1250
0 1 0 1 1 1 1 0.9125 1 1 0 1 1 1 1 0.1125
0 1 1 0 0 0 0 0.9000 1 1 1 0 0 0 0 0.1000
0 1 1 0 0 0 1 0.8875 1 1 1 0 0 0 1 0.0875
0 1 1 0 0 1 0 0.8750 1 1 1 0 0 1 0 0.0750
0 1 1 0 0 1 1 0.8625 1 1 1 0 0 1 1 0.0625
0 1 1 0 1 0 0 0.8500 1 1 1 0 1 0 0 0.0500
0 1 1 0 1 0 1 0.8375 1 1 1 0 1 0 1 0.0375
0 1 1 0 1 1 0 0.8250 1 1 1 0 1 1 0 0.0250
0 1 1 0 1 1 1 0.8125 1 1 1 0 1 1 1 0.0125
0 1 1 1 0 0 0 0.8000 1 1 1 1 0 0 0 0.0000
0 1 1 1 0 0 1 0.7875 1 1 1 1 0 0 1 0.0000
0 1 1 1 0 1 0 0.7750 1 1 1 1 0 1 0 0.0000
0 1 1 1 0 1 1 0.7625 1 1 1 1 0 1 1 0.0000
0 1 1 1 1 0 0 0.7500 1 1 1 1 1 0 0 0.0000
0 1 1 1 1 0 1 0.7375 1 1 1 1 1 0 1 0.0000
0 1 1 1 1 1 0 0.7250 1 1 1 1 1 1 0 0.0000
0 1 1 1 1 1 1 0.7125 1 1 1 1 1 1 1 0.0000
3816f

15
LTC3816
OPERATION (Refer to Funtional Diagram)
The LTC3816 is a constant frequency, voltage mode DC/DC VCC(SEN) and VSS(SEN) pins. The AITC amplifier monitors
step-down controller that complies with the Intel IMVP‑6/ the inductor current and computes the load dependent
IMVP-6.5 specifications. The 7-bit VID code programs the output droop required to implement the active voltage
switcher output voltage as specified in Table 1. Figure 2 positioning features in IMVP-6/IMVP-6.5. The IC servos
shows the timing diagram. Upon start-up, the switcher the differential output voltage to the VID DAC voltage
output soft-start ramps to the VBOOT voltage. 75µs after minus the small load dependent AVP droop.
reaching the VBOOT power good threshold, which is about
The LTC3816 feedback loop is capable of dynamically
45mV below VBOOT , the controller forces the CLKEN# pin
changing the regulator output to different VID DAC voltages.
low and the VID code is loaded. Next, the output is servoed
Upon receiving a new VID code, the LTC3816 regulates to
to its VID DAC potential. 10ms after regulation, PWRGD
its new potential with a programmable slew rate which is
pulls high to indicate that the switcher is regulating and
selected to prevent the converter from generating audible
has completed its start-up phase.
noise. The switcher output load current can be monitored
The LTC3816 uses two external synchronous N-channel by measuring the IMON pin potential. The LTC3816 forces
MOSFETs. A floating topside driver and a simple external the IMON pin voltage to be proportional to the average
charge pump provide full gate drive to the upper MOSFET. load current with a gain configured by the RPREIMON and
The controller uses a leading edge modulation architec- RIMON resistors.
ture to allow extremely low duty cycles and fast load The LTC3816 includes an onboard current limit circuit that
step response. In a typical LTC3816 switching cycle, the senses the inductor current through an external sense
PWM comparator turns on the top MOSFET to charge the resistor or the inductor DCR. The peak inductor current
output capacitor. An internal clock resets the top MOSFET can be controlled by selecting the current limit RIMAX
and turns on the bottom MOSFET to reduce the output resistance. The LTC3816 current limit architecture allows
charging current. This switching cycle repeats itself at an momentary overcurrent events for a predefined duration
internally fixed frequency, or in synchronization with an (see the Current Sense and Current Limit sections). Upon
external oscillator. current limit, the top gate is shut off, the SS external
The top gate duty cycle is controlled by the voltage feed- capacitor is discharged to limit the top gate duty cycle,
back loop which includes an internal differential amplifier and the switcher output voltage is reduced until the load
that senses the differential output voltage between the fault is removed.

VRON

VID

DPRSLPVR

INTVCC NORMAL
45mV IMVP-6 SLEW RATE
SLOW SLEW RATE
VBOOT
VCC(CORE)

CLKEN# tCLKEN#

PWRGD tCLK(PWRGD)
3816 F02

Figure 2. LTC3816 Power-Up and Power-Down Timing Diagram

3816f

16
 LTC3816
Applications Information
LDO, INTVCC/EXTVCC Power Supply advisable to short EXTVCC to VIN. In this case, the INTVCC
output voltage becomes:
The LTC3816 is designed to operate with a wide range of
VIN input voltages. The IC includes a 5.2V LDO to power VINTVCC(EXTVCC) = VEXTVCC – IQ(TOT) • REXTVCC
the driver and control circuits. The LDO output, INTVCC where REXTVCC is the internal EXTVCC switch on-resistance.
should be bypassed with a minimum 4.7µF low ESR It has a typical value of 2Ω at 25°C and has a temperature
ceramic capacitor. The INTVCC regulator can supply up to coefficient of approximately 4000ppm/°C.
50mA of total LTC3816 quiescent current, IQ(TOT), which
consists of the static supply current, IQ, and the current
required to charge the gate capacitance, QG(TOT), of the Undervoltage LockOUT and Shutdown
top and bottom power MOSFETs. A precision undervoltage lockout (UVLO) comparator
IQ(TOT) = IQ + QG(TOT) • fOSC monitors the INTVCC voltage and enables soft-start opera-
tion once INTVCC is above 3.9V. For power supplies that
PDISS = VIN • (IQ + QG(TOT) • fOSC) start-up slowly, the gate drivers could begin switching
TJ = TA + PDISS • θJA when VIN is well below its steady-state value. The high
inrush current through the input power cable could cause
The value of QG(TOT) can be obtained from the MOSFET
the VIN supply to dip below the UVLO threshold and result
data sheets. For high VIN and high frequency operation, in hiccup operation at start-up. This problem can be eas-
care must be taken to ensure that the maximum junction
ily overcome by adding a VIN UVLO function as shown in
temperature TJMAX of the IC is never exceeded. Figure 3. Connect an external resistive divider from VIN to
When the EXTVCC pin is left open or tied to a voltage less VRON. Set the resistive divider according to the following
than 4.5V, the 5.2V LDO powers INTVCC. If EXTVCC is taken equation:
above 4.5V, the LDO is turned off and an internal switch
RON1
connects INTVCC to EXTVCC. Do not apply greater than 6V VUVLO = 1.2V = VIN(UVLO)
to the EXTVCC pin, and ensure that EXTVCC < VIN + 0.3V RON1 + RON2
unless EXTVCC is shorted to the VIN supply. Using the
where VIN(UVLO) is the desired VIN UVLO threshold. The
EXTVCC pin allows INTVCC to be powered from an external
resistances are normally chosen so that the error caused
source reducing LDO losses and improving the regulator
by the internal 1µA pull-up current has a negligible effect
efficiency, especially at high VIN. When the EXTVCC pin is
on the UVLO threshold. Be careful not to allow the resistive
used, the chip power dissipation reduces to:
divider output voltage to exceed the 6V maximum rating
PDISS = VEXTVCC • (IQ + QG(TOT) • fOSC) of the VRON pin.
If the VIN supply is low enough for the INTVCC LDO to enter If the external resistive divider is not used, upon power-
dropout, the output voltage of the LDO becomes: up, the VRON pin is pulled up by an internal 1µA pull-up
VINTVCC(DROPOUT) = VIN – VDROPOUT current. The LTC3816 can be put into a low power shut-

The LDO dropout voltage is a function of the total quies- VIN

LTC3816
cent current IQ(TOT), VIN voltage and junction temperature. RON2 1µA
VRON
The temperature coefficient of the LDO dropout voltage +
ON
is approximately 6400ppm/°C. To enable proper opera- SHUTDOWN RON1 1.2V –
tion, make sure that the LDO output voltage meets the 3816 F03

INTVCC undervoltage and minimum MOSFET gate driver

requirements. If VIN is connected to a fixed 5V supply, it is Figure 3. VIN UVLO Circuit

3816f

17
LTC3816
APPLICATIONS INFORMATION
down mode by pulling the VRON pin below 0.65V. In the pin to GND. An internal 1µA current source charges this
shutdown mode, the internal circuitry and the INTVCC capacitor, creating a voltage ramp on the SS pin. As the
regulator are off and the supply current drops well below SS pin voltage rises from 0V to 1.3V, the output voltage,
100µA. When the VRON pin voltage is between 0.65V and VOUT , rises smoothly from 0V to its VBOOT value. Once
1.2V, the INTVCC regulator and internal circuitry power up the soft-start interval is over, the internal current source
but the driver outputs remain low. continues charging the SS capacitor until the SS poten-
tial is internally clamped at about 2.7V. For the IMVP-6
Topside MOSFET Driver Supply configuration, a 1000pF SS capacitor generates roughly
a 1.6ms start-up time. With the IMVP-6.5 configuration,
An external bootstrap capacitor, CB, connected from the the start-up time is about 1.5ms.
BOOST pin to the SW pin supplies the topside gate driver
as shown in Figure 1. Capacitor CB is charged though the During severe overload conditions, the LTC3816 discharges
external diode, DB, from INTVCC when the SW pin is low. the SS capacitor to lower the switcher output voltage. If the
When the topside MOSFET is turned on, the top driver potential at SS is forced below 0.3V, the controller reduces
places the CB voltage across the gate source of the top its IMAX sourcing current from 10µA to 2.5µA and cuts the
MOSFET. This enhances the MOSFET and turns on the short-circuit current to about 25% of its nominal value.
top switch. The switch node voltage, SW, rises to VIN and
the BOOST pin follows. With the topside MOSFET on, the Current Sense and Current Limit
boost voltage is above the input supply: The LTC3816 features an onboard cycle-by-cycle user-
VBOOST = VIN + VINTVCC programmable current limit circuit that controls the peak
The value of the boost capacitor, CB, needs to be at least inductor current. The IMAX pin has an internal 10µA pull-
up current source, allowing the maximum load current
100 times that of the total input capacitance of the topside
ILOAD(MAX) to be programmed by a single external resistor
MOSFET. The reverse breakdown of the external Schottky
RIMAX connected between the IMAX and ISENN pins.
diode, DB, must be greater than VIN(MAX).
IIMAX • RIMAX
IL(PEAK ) =
IMVP-6/IMVP-6.5 Selection and VBOOT Voltage RSENSE
The LTC3816 can be configured to meet either IMVP‑6 ∆IL IIMAX • RIMAX ∆IL
ILOAD(MAX ) < ILIMIT = IL(PEAK ) – = –
or IMVP-6.5 requirements. To select IMVP-6 operation, 2 RSENSE 2
short both IMON and PREIMON to INTVCC. At start-up, when
VRON is asserted, the switcher output ramps to VBOOT = where IL(PEAK) is the peak inductor current, IIMAX is the IMAX
1.2V regardless of the VID code. To configure IMVP‑6.5 pin pull-up current, RSENSE is the current sense resistor
operation, connect a resistor from IMON to VSS(SEN) and value and ∆IL is the inductor ripple current.
another resistor from PREIMON to ITC. The IMON and 1  V 
PREIMON resistance set the IMON gain (see the IMON sec- ∆IL = VOUT  1– OUT 
fOSC • L  VIN 
tion). The VBOOT voltage for IMVP-6.5 is 1.1V.
Note that the output ripple current varies with the switch-
Soft-Start Operation ing frequency, inductor value and duty cycle. Hence, the
The start-up of VOUT is controlled by the LTC3816’s SS current limit value should be checked on the application
pin. When the voltage at the SS pin is less than 1.3V, the board to ensure that ILOAD(MAX) < ILIMIT under all operating
LTC3816 regulates the VFB voltage to the SS pin voltage conditions and temperature variations.
instead of 1.3V. This allows the user to program the soft- For current sensing using a low value sense resistor, the
start of the regulator output with a capacitor from the SS sense resistor parasitic inductance must be considered to
3816f

18
 LTC3816
APPLICATIONS INFORMATION
achieve accurate current sensing. Figure 4 shows a real VIN
IL
current sensing resistor, RSENSE, which can be modeled LTC3816
TG QT
with an ideal resistance, RSEN, in series with its parasitic L ESL RSEN
VOUT
SW
ESL. As shown in Figure 4, the voltage across the sense QB D
SENSE RESISTOR
+
BG
resistor includes the voltage across the parasitic induc- COUT
BSOURCE
tor which is a strong function of inductor ripple current RISR
and the switching frequency. This effectively reduces the ISENP
CISR VISR
current limit threshold, typically by more than 30%. The ISENN
RIMAX
voltage across the sense resistor can be extracted from IMAX

a lowpass filter placed close to the controller input sense

pins as shown in Figure 4. The voltage across the sensing VISR = VRSEN + VESL

capacitor, CISR, is: VESL(ON)

VRSEN = IL • RSEN

 sESL 
 1+ R 
VCISR = IL • RSEN  SEN 
 1+ sRISR • CISR 
 
VESL(OFF)

In the frequency domain, the second term in the above 3816 F04

equation must be equal to 1 to ensure that the voltage Figure 4. Current Limit Sensing Using
across the filter capacitor is independent of operating a Low Value Sense Resistor
frequency. To meet this requirement, the value of the RC
VIN
filter should fulfill the following condition: IL
LTC3816
ESL TG QT
L DCR
RISR • CISR = SW VOUT
RSEN INDUCTOR
BG QB D +
COUT
The ESL value can be obtained from the manufacturer ’s BSOURCE
RIDCR
data sheet or estimated with an oscilloscope, as shown in ISENP
the Figure 4 waveform, using the following equation: ISENN
CIDCR
3916 F05

RIMAX
VESL(ON) + VESL(OFF ) IMAX

ESL =
 1 1  Figure 5. Current Limit Sensing Using Inductor DCR
∆IL  +
 tON tOFF 
data sheet. Similar to the sense resistor application circuit,
where tON is the TG on time and tOFF is the TG off time. the voltage across the inductor DCR can be extracted from
a lowpass filter and the current limit threshold is given by
For high efficiency applications, the inductor DCR provides the following equation:
a method of sensing the inductor current without incurring
additional power loss from a sense resistor. The DCR of IIMAX • RIMAX
IL(PEAK ) =
the inductor represents the small amount of resistance RDCR
in the copper winding, which can be less than 1mΩ for ∆IL IIMAX • RIMAX ∆IL
today ’s low value, high current inductors. Figure 5 shows ILOAD(MAX ) < ILIMIT = IL(PEAK ) – = –
2 RDCR 2
a simplified inductor model, which can be modeled with an
ideal inductor, L, in series with its parasitic DCR. The DCR L
if RIDCR • CIDCR =
value can be obtained from the inductor manufacturer ’s RDCR
3816f

19
LTC3816
APPLICATIONS INFORMATION
Note that the value of RDCR must account for its temperature another cycle. After 90µs, the IMAX current returns to 10µA,
coefficient, which is approximately 0.39%/°C. and the output load is limited to 1× for the next 630µs as
shown in Figure 6c. Figure 6d shows the condition when
The current limit architecture of the LTC3816 allows short
a repetitive overload event triggers current limit.
durations of instantaneous overload. Upon power-up, the
current limit threshold is set to 1×, equal to ILIMIT . The Figure 6e shows that at any instant, if the load current
load is limited to ILIMIT until the switcher output reaches is above 1× for more than 90µs, or higher than 2×, the
its VBOOT potential. Beyond this point, during the VID DAC controller enters current limit. Under this condition, the TG
slewing interval, the IMAX sourcing current automatically duty cycle is reduced and the SS capacitor is discharged
switches from 10µA to 20µA and the current limit threshold CURRENT LIMITED
increases to 2× to enable the output capacitor voltage to 20µA
track the DAC transition. If the controller detects that there IIMAX
10µA
is an overload condition when the DAC is not slewing, the
90µs 45µs
current limit threshold increases to 2× for a duration of 2s
45µs. If the overload interval is shorter than 45µs, the IC 1s
allows another overcurrent event within the next 630µs,
ILOAD
as shown in Figure 6a. However, if an overload occurs
45µs < t < 90µs <45µs
within the 630µs following the second event, the controller >630µs 3816 F06c

current limits, as shown in Figure 6b.

Figure 6c. Allowable Longer Overload Condition
If the overload condition persists for more than 45µs,
the LTC3816 allows the 2× current limit to continue for
CURRENT LIMITED
20µA
CURRENT LIMITED
IIMAX
20µA 10µA
IIMAX 90µs
10µA
2s
45µs 45µs 45µs
1s
2s
1s ILOAD

ILOAD 45µs < t < 90µs <45µs

<630µs 3816 F06d

<45µs <45µs <45µs

>630µs
<630µs 3816 F06a Figure 6d. Allowable Longer Overload Condition,
Followed by Repeated Overload Triggers Current Limit
Figure 6a. Permissible Overload

CURRENT LIMITED
CURRENT LIMITED
20µA
20µA IIMAX
IIMAX 10µA
10µA
90µs 45µs
45µs 45µs
2s
2s
1s
1s
ILOAD
ILOAD
>90µs <45µs
<45µs <45µs <45µs >630µs 3816 F06e

<630µs <630µs 3816 F06b

Figure 6e. Long Overload or Excessive Loading

Figure 6b. Repeated Overload Triggers Current Limit Triggers Current Limit Condition
3816f

20
 LTC3816
APPLICATIONS INFORMATION
to lower the regulator output voltage. This current limit 1.03 3

condition persists until the fault condition disappears or

% FROM IDEAL NO-LOAD VALUE

the controller detects a low output voltage fault and forces 1.00 0

the switcher output to latch off. Once the output voltage PROGRAMMABLE
is lower than the power good threshold, the controller 0.97 AVP SLOPE –3

VOUT (V)
limits the maximum load to 1× to reduce the short-circuit
0.94 –6
current.
0.91 –9
Active Voltage PositioNing (AVP)
0.88 –12
In a conventional buck converter, the feedback control 0 5 10 15 20 25 30

regulates the output voltage to the same level for the ILOAD (A)

entire load range as shown in Figure 7a. The peak-to-peak

3816 F07b

Figure 7b. AVP DC Transfer Curve

output voltage spikes resulting from the load step must
be smaller than the voltage tolerance window.
To reduce the regulator output voltage peak-to-peak
perturbation resulting from a load transient, the LTC3816
VOUT
modulates the output voltage based on the output loading 50mV/DIV
current. The built-in AVP circuit lowers the output voltage
proportional to the load current as shown in Figure 7b.
Figure 7c shows the transient response with the AVP ILOAD
10A/DIV
function. The AVP voltage droop reduces the peak-to-peak
output voltage perturbation. As a result, the AVP topology VSW
20V/DIV
requires fewer capacitors at the regulator output to achieve VIN = 12V 20µs/DIV
3816 F07c

the same voltage tolerance window. VOUT = 1V

ILOAD = 0A TO 20A

The AVP circuit obtains the load current information from

the sense resistor or the inductor DCR as shown in Figure 8. Figure 7c. Transient Waveform with AVP Slope = –3mV/A, Using
The voltage drop across the sense resistor is extracted The Same Inductor and Output Capacitor as Figure 7a. The
Transient Peak-to-Peak Perturbation is Reduced to About 85mV

by the AITC amplifier and summed with the differential

amplifier output voltage. The resulting output is servoed
VOUT
to the VID DAC voltage. At higher load current, the volt-
50mV/DIV age drop across the sense resistor increases, resulting
in a lower switcher output voltage. Typically, the system
requirement defines the amount of AVP gain ensuring
ILOAD that the output voltage remains within the regulator sup-
10A/DIV
ply tolerance band over the full range of load conditions.
VSW
20V/DIV
Figure 8 includes the components required to compensate
VIN = 12V 20µs/DIV 3816 F07a
for the sense resistor parasitic inductance. The AVP DC
VOUT = 1V
ILOAD = 0A TO 20A transfer function is:
VOUT = VDAC – AAVP(SR) • IL = VDAC – AG(SR) • IL • RSEN
Figure 7a. Transient Waveform Without AVP. The Transient
Peak-to-Peak Spike ≈ 130mV. The AITC Amplifier is
Configured as a Unity-Gain Amplifier
3816f

21
LTC3816
APPLICATIONS INFORMATION
where AAVP(SR) is the AVP gain with sense resistor con- VIN
IL
figuration and AG(SR) is the sense resistor gain: TG QT
L ESL RSEN
R SW VOUT
A AVP(SR) = A G(SR) • RSEN and A G(SR) = VSR tt SENSE RESISTOR
+
R AVPSR BG QB D
COUT
LTC3816 RAVPSR
ESL BSOURCE
R VSR • C VSR = ITCFB
RSEN – ITC
CVSR RVSR
AITC
+ ISENN
Figure 9 shows the AVP configuration with current sense 3916 F08

implemented using the inductor DCR. The AVP DC transfer

function is: Figure 8. AVP Configuration with a Sense Resistor
VOUT = VDAC – AAVP(DCR) • IL = VDAC – AG(DCR) • IL • RDCR
where: VIN
IL
R
and A G(DCR) = VDCR TG QT
A AVP(DCR) = A G(DCR) • RDCR L DCR
R AVPDCR SW VOUT
INDUCTOR
QB D +
L BG
R VDCR • C VDCR = LTC3816 RAVPDCR COUT
RDCR BSOURCE
ITCFB
CVDCR RVDCR
– ITC
AITC
Temperature Compensated Active Voltage + ISENN
PositionING (AVP) With Inductor DCR 3916 F09

The inductor DCR AVP configuration improves the regula- Figure 9. AVP Configuration with Inductor DCR Current Sense
tor efficiency by eliminating the power losses associated
with a sense resistor. However, without proper temperature
VIN
compensation, the positive temperature coefficient of the IL
inductor DCR, 0.39%/°C, may compromise the output volt- TG QT
L DCR
age accuracy. As the temperature of the inductor rises, its SW VOUT
INDUCTOR
DCR value increases, resulting in a greater VOUT droop rate BG QB D +
RAVPDCRN NTC COUT
(higher AVP gain). To compensate for the DCR temperature LTC3816
shift, replace the resistor RVDCR in Figure 9 with an NTC BSOURCE
RPAR
resistor placed as close as possible to the inductor. Ideally, ITCFB

the NTC resistor should have the same temperature as the – ITC
CVDCRN RSER
inductor. As temperature increases, the NTC resistance AITC
+
drops, resulting in a reduction in the AITC amplifier voltage ISENN
3916 F10

gain. This compensates for the increase in DCR resistance

and maintains the AVP gain. The NTC resistor, however, is Figure 10. AVP with Inductor DCR Current Sense
highly nonlinear and must be linearized. Figure 10 shows and NTC Temperature Compensation

3816f

22
 LTC3816
APPLICATIONS INFORMATION
the NTC compensation network. To determine the compo- 1.02
TA = 25°C
nent values, first, select the NTC with room temperature 1.01

resistance approximately equal to RVDCR that has the 1.00

IDEAL + 1.5%
smallest temperature coefficient (β constant in the NTC 0.99
data sheet. Using an NTC with a higher β constant gen-

VOUT (V)
IDEAL
0.98
erates a less optimal temperature compensation). Next,
0.97
calculate the resistances RPAR and RSER from the following IDEAL – 1.5%
equations where the NTC resistances at different tempera- 0.96

tures is obtained from the manufacturer’s data sheet. 0.95 WITH NTC
WITHOUT NTC
RPAR = RNTC at 25°C 0.94
0 5 10 15 20 25 30
10
( ) (
RSER ≈  RPAR || (RNTC at 0°C) – RPAR || (RNTC at 75°C) )
ILOAD (A)

3
3816 F11a

(
– RPAR || (RNTC at 25°C) ) Figure 11a. AVP Transfer Curve Using Vishay
IHLP-5050CE-01 0.33µH (DCR = 1.3mΩ) Inductor
DCR Current Sense with AG(DCRN) = 1 at TA = 25°C
Note that the above equations optimize temperature
compensation at hot. At extreme cold temperature, the 1.02
TA = 125°C
temperature compensation is less effective. 1.01

With the NTC resistor network, the temperature compen- 1.00

IDEAL + 1.5%
sated AVP transfer function becomes: 0.99
VOUT (V)

IDEAL
0.98
VOUT = VDAC – AAVP(DCRN) • IL = VDAC – AG(DCRN) • IL • RDCR
0.97
where AAVP(DCRN) and AG(DCRN) are the AVP and DCR gain IDEAL – 1.5%
0.96
using the inductor DCR current sense with NTC temperature
compensation configuration. 0.95 WITH NTC
WITHOUT NTC
0.94
RNTCNET 0 5 10 15 20 25 30
A AVP(DCRN) = A G(DCRN) • RDCR and A G(DCRN) = ILOAD (A)
R AVPDCRN 3816 F11b

L Figure 11b. Same Setup as Figure 11a. Improvement

C VDCRN =
RNTCNET • RDCR in AVP Accuracy with NTC Temperature Compensation
Network at TA = 125°C
RNTCNET = RSER + (RPAR || RNTC ) 
VIN
IL
Figure 11a shows the room temperature AVP DC transfer TG QT
curves obtained using inductor DCR current sense with and SW
L DCR
VOUT
without NTC temperature compensation. There is only a BG QB D
INDUCTOR
+
slight difference in the transfer curve at heavy load. Figure LTC3816
LPTC COUT

11b shows the AVP transfer curve obtained at 125°C, it

BSOURCE
shows the improvement in AVP accuracy with the NTC ITCFB
resistor network. CVDCRP RVDCRP
– ITC
Figure 12 shows another easy way to compensate for the AITC
+
ISENN
inductor DCR temperature coefficient. In this configura- LPTC: VISHAY TPFT1206 SERIES, 4110ppm/°C
3916 F12

tion, a linear PTC resistor is connected from the SW node

to the ITCFB pin. The PTC thermistor ’s temperature coef- Figure 12. AVP Using Inductor DCR Current Sense
with Linear PTC Temperature Compensation
ficient of 0.411%/°C compensates for the change in DCR
3816f

23
LTC3816
APPLICATIONS INFORMATION
resistance (0.39%/°C) and produces a near perfect AVP the negative terminal of the resistor RIMON should be
slope across temperature. connected directly to the CPU VSS(SEN) pin. Depending
on the output load requirements, the IMON voltage gain
VOUT = VDAC – AAVP(DCRP) • IL = VDAC – AG(DCRP) • IL • RDCR
can be programmed by changing the ratio of the RIMON
where: and RPREIMON resistances. A capacitor should be added
R VDCRP in parallel with the resistor RIMON to remove the switching
A AVP(DCRP) = A G(DCRP) • RDCR and A G(DCRP) =
RLPTC ripple. The value of the capacitor CIMON is determined by
L the following equation:
C VDCRP =
R VDCRP • RDCR tIMON
CIMON =
RIMON
IMON
To facilitate CPU monitoring of load current in an IMVP‑6.5 where tIMON is the IMON time constant and must be larger
application, the LTC3816 forces the IMON pin voltage to than 300µs.
be proportional to the average load current. As shown in In the IMVP-6.5 configuration, the IMON pin potential is
Figure 13, the AITC and the unity-gain amplifiers force internally clamped to 1.1V with respect to the VSS(SEN) pin
the voltage across the resistor RPREIMON to be equal to voltage. Forcing the PREIMON pin to INTVCC configures the
the voltage drop across the sense resistor. A current is LTC3816 as an IMVP-6 regulator.
supplied to RIMON that is three times greater than the cur-
rent in RPREIMON. The voltage across the RIMON resistor Feedback Control
is equal to:
The LTC3816 feedback loop consists of the line feed-
R R
VIMON = 3 • (IL • RSEN ) VSR • IMON forward circuit, the modulator, the external inductor, the
R AVPSR RPREIMON output capacitor, the AITC and differential amplifier, and
the feedback amplifier with its compensation network. All
To prevent the ground difference between the CPU and of these components affect loop behavior and need to be
the regulator from affecting the IMON voltage accuracy, accounted for in the loop compensation.

VIN Line Feedforward and Modulator

IL

TG QT
The modulator consists of the PWM generator, the output
SW
L ESL RSEN
VOUT
MOSFET drivers and the external MOSFETs themselves.
BG QB D
SENSE RESISTOR
+ The modulator gain varies linearly with the input voltage.
LTC3816 RAVPSR COUT The line feedforward circuit compensates for this change in
BSOURCE
gain and provides a constant gain from the error amplifier
ITCFB
CVSR RVSR output to the SW node regardless of input voltage. From
– ITC
AITC
+
a feedback loop point of view, the combination of the line
INTVCC ISENN
feedforward circuit and the modulator looks like a linear
voltage transfer function from COMP to the SW node and
3816 F13
1X RPREIMON
PREIMON
has a gain roughly equal to:
IMON
IMON AMOD ≈ 25V/V ≈ 28dB
RIMON CIMON
VSS(SEN)
It has a fairly benign AC behavior at typical loop compen-
sation frequencies with significant phase shift appearing
Figure 13. IMON Configuration at half the switching frequency.
3816f

24
 LTC3816
APPLICATIONS INFORMATION
LC Filter where:
The external inductor and output capacitor combination A(SR) = RESR • CBULK + AG(SR) • RSEN • COUT
causes a second order LC roll-off at the output with 180° B(SR) = AG(SR) • RSEN • RESR • CBULK • CCER
of phase shift. At higher frequencies, the reactance of the
output capacitor approaches its ESR, and the roll-off due to Similarly, for the DCR configuration with NTC compen-
the capacitor stops, leaving –20dB/decade and 90° of phase sation, the simplified low frequency transfer function is
shift. Beyond the ESR zero, the ceramic capacitor creates a given by:
high frequency pole. The LC filter transfer function, poles 2
and zero locations are given by the following equations: VSERVO 1+ sA(DCR) + s B(DCR)
≈
VOUT 1+ sRESR • CBULK
VOUT 1+ sRESR • CBULK
ALC = ≈
VSW 2
(
s LLCOUT + SRLCOUT + 1 ) where:

1 A(DCR) = RESR • CBULK + AG(DCR) • RDCR • COUT

•
C •C B(DCR) = AG(DCRN) • RDCR • RESR • CBULK • CCER
1+ sRESR BULK CER
COUT Note that with either the sense resistor or the DCR current
1 sense configuration, the AVP circuitry introduces a pole at
fLC(DOUBLE _ POLE) = the same location as the LC lowpass filter ESR zero. This
2π LLCOUT
cancels the increase in gain and phase caused by the ESR
1 zero. Fortunately, the zero in the AVP transfer function is
fESR(ZERO) =
2π • RESR • CBULK typically within the closed-loop bandwidth and provides a
1 beneficial phase boost at the crossover frequency.
fCER(POLE) =
CBULK • CCER
2π • RESR Error Amplifier
COUT
where: The error amplifier provides most of the low frequency
loop gain and servos the switcher output voltage to the
RL includes DCR, sense resistance, PCB trace resistance VID DAC potential minus the AVP droop. After selecting
and the turn-on resistance of the power MOSFET. the inductor, the output capacitor and the AVP component
LL includes the inductor inductance, PCB trace induc- values, the control loop is compensated by tailoring the
tance and sense resistor ESL. frequency response of the error amplifier. A typical LTC3816
application uses Type 3 compensation to frequency com-
COUT = CBULK + CCER pensate the feedback loop. Figure 14a and Figure 14b
show the LTC3816 error amplifier Type 3 configuration.
AITC and Differential Amplifiers
The transfer function of this amplifier is given by the fol-
With the sense resistor configuration, the AITC and the lowing equation:
differential amplifiers add a double zero and a pole in the
vicinity of the feedback loop crossover frequency, fC, and VCOMP
=–
(1+ sRC • CC )(1+ sR1• CFF )
multiple poles at higher frequencies. The simplified low VSERVO  C •C 
frequency transfer function from the regulator output node sR1(CC + CC1)  1+ sRC C C1 
 C +C 
C C1
to the SERVO pin, as shown in Figure 14a, is given by the
following equation: The error amplifier component values can be obtained
2 using the following guidelines.
VSERVO 1+ sA(SR) + s B(SR)
≈
VOUT 1+ sRESR • CBULK
3816f

25
LTC3816
APPLICATIONS INFORMATION
CFF CC
RC

CC1
R1
VIN
IL
SERVO VFB – COMP TG
L ESL RSEN
SW
+EA SW VOUT
1.3V SENSE RESISTOR
BG RESR
CCER
LTC3816 RAVPSR +
CBULK
BSOURCE
+
DAMP
– ITCFB

– CVSR RVSR
ITC
+AITC
ISENN
VSS(SEN)
VCC(SEN)
3816 F14a

Figure 14a. LTC3816 Frequency Compensation with Sense Resistor Configuration

CFF CC
RC

CC1
R1
VIN
IL
SERVO VFB – COMP TG
L DCR
SW
+EA SW VOUT
1.3V INDUCTOR
BG RESR
RAVPDCRN NTC CCER
LTC3816 +
CBULK
BSOURCE
+
DAMP RPAR
– ITCFB

– CVDCRN RSER
ITC
+AITC
ISENN
VSS(SEN)
VCC(SEN)
3816 F14b

Figure 14b. LTC3816 Frequency Compensation with DCR Configuration

3816f

26
 LTC3816
APPLICATIONS INFORMATION
fOSC Line Feedforward (LFF)
1. Select fC = feedback crossover frequency =
N The LTC3816 incorporates a line feedforward function to
where N is between 5 and 10. compensate for changes in the line voltage and to simplify
2. At the feedback loop crossover frequency, fC, the loop the frequency compensation. On the other hand, with
gain is unity, therefore the error amplifier gain is: the line feedforward enabled, the feedback loop has high
modulator gain and is more sensitive to noise pickup.
VCOMP 1 If the input supply voltage is low (e.g., around 5V) and
=
VSERVO VSERVO well regulated, it is better to disable the LFF function by
AMOD • ALC •
VOUT shorting the LFF pin to GND. Without LFF , the modulator
gain AMOD(WOLFF) is reduced and the control loop is less
3. Place the error amplifier zero near the LC filter double- sensitive to noise injection.
pole frequency: AMOD(WOLFF) ≈ 0.85 • VIN
1 1 If line feedforward is disabled, the control loop needs to
fEA(ZERO) = ≈
2π • RC • CC 2π LLCOUT be recompensated in order to account for the reduction
in modulator gain.
4. The feedforward zero is positioned to give the required
phase boost at the crossover frequency:
DPRSLPVR and VID DAC Slew Rate Control
1 The LTC3816 allows the user to program the VID DAC
fFF (ZERO) =
2π • R1• CFF voltage transition slew rate by adding a capacitor at the

CSLEW pin. In the IMVP-6.5 mode, CSLEW is internally
5. Place the error amplifier pole at 5fC to suppress the pulled up by a 40µA current source. Upon a code transition
switching noise. command, CSLEW is ramped up by the internal current
1 source. When the capacitor, CSLEW , potential reaches 1V,
fEA(POLE) = = 5fC the VID DAC output voltage jumps by 1 LSB (12.5mV) and
 CC • CC1 
2π • RC  the controller resets the CSLEW capacitor. This operation
 CC + CC1  repeats until the DAC reaches its target value. The DAC

voltage slew rate is given by the following equation:
Compensating the switching power supply voltage feed-
back loop is a complex task. The frequency compensation dVDAC I
= 12.5mV • CSLEW
equations shown in this data sheet were obtained using dt CSLEW
some approximations to simplify the calculations. The
compensation values shown in this data sheet are typi- where ICSLEW = 40µA.
cal values, optimized for the power components shown
When the IMVP-6 configuration is selected, the LTC3816
in the circuit. Though similar power components should
allows two different slew rates as shown in Figure 15.
suffice, substantially changing even one major power
To configure the normal slew rate, short the pin DPRSLPVR
component or circuit layout may degrade performance
to ground. To configure for a slower slew rate, force the
significantly. To verify the calculated component values,
DPRSLPVR pin potential above 1.6V.   25µs after the control-
all new circuit designs should be prototyped and tested
ler detects a low-to-high transition at the DPRSLPVR pin,
for stability.

3816f

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LTC3816
APPLICATIONS INFORMATION
drops, which further improves efficiency by minimizing
gate charge losses.
VOUT
Forcing the MODE/SYNC pin low enables forced continuous
100mV/DIV mode operation. In forced continuous mode, the bottom
MOSFET is always on when the top MOSFET is off, allowing
the inductor current to reverse at low currents. This mode
VID5
1V/DIV is less efficient due to conduction and switching losses,
DPRSLPVR but has the advantage of better transient response at low
5V/DIV
3816 F15
currents, constant frequency operation, and the ability to
VIN = 12V
VOUT = 0.75V TO 1.15V
0.1ms/DIV maintain regulation when sinking current.
CSLEW = 47pF
IMVP-6 CONFIGURATION During soft-start, the LTC3816 forces the controller to
operate in pulse-skipping mode until the switcher output
Figure 15. Programmable VID Slew Rate voltage reaches its VBOOT power good threshold. During
VID code transitions, however, the controller always oper-
the controller reduces the ICSLEW pull-up current from 40µA ates in forced continuous mode to allow the switcher to
to 10µA (deeper sleep mode). This effectively reduces the sink current.
VID DAC slew rate to 1/4 of its original value. If IMVP-6.5
is selected, the slow slew rate function is disabled.
Operating Frequency/Frequency
Synchronization
Pulse-Skipping and Forced Continuous Mode
Operation The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
The LTC3816 can operate in one of two modes select- increases efficiency by reducing MOSFET switching losses,
able with the MODE/SYNC pin: pulse-skipping mode but requires a larger inductance and/or capacitance to
or forced continuous mode. Shorting the MODE/SYNC maintain low output voltage ripple. For converters with
pin to INTVCC selects pulse-skipping mode. Pulse-skip- high step-down VIN-to-VOUT ratios, another consideration
ping mode is selected when high efficiency at very light is the minimum on-time of the converter.
loads is desired. In this mode, when the inductor current
reverses, the bottom MOSFET turns off to minimize the VOUT
tON(MIN) =
efficiency loss due to reverse current flow. This reduces VIN(MAX ) • fOSC
the conduction loss and slightly improves the efficiency.
As the load reduces, the top gate duty cycle shrinks to If the MODE/SYNC pin is not driven by an external clock,
maintain regulation. The LTC3816 is capable of operating the RFREQ pin voltage configures the LTC3816 free-run-
at extremely low duty cycles; hence, TG will continue to ning switching frequency. Floating or shorting the RFREQ
run at a constant switching frequency until the top gate pin to INTVCC allows the controller to run at the nominal
on-time is less than 40ns to 50ns. When the load decreases 400kHz frequency. Connecting the RFREQ pin to GND
beyond this point, the LTC3816 TG begins to skip cycles selects 210kHz. Tying RFREQ to a potential between 2.5V
to maintain regulation. The driver switching frequency and 3.5V selects 580kHz. The RFREQ pin has an internal

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 LTC3816
APPLICATIONS INFORMATION
10µA current source pull-up. Placing a resistor between CLKEN#, OVF and PWRGD
RFREQ and GND creates a potential given by the follow- CLKEN# is an open-drain output used to enable the CPU’s
ing equation: PLL. Upon power-up, this open-drain pull-down is disabled,
VRFREQ = IRFREQ • RRFREQ and CLKEN# is pulled high by an external resistor. During
where IRFREQ = 10µA and allows the oscillator free-running the soft-start ramp, when the switcher output is 45mV
frequency to be programmed between 210kHz to 580kHz from the VBOOT voltage, the controller completes its soft-
start cycle and 75µs later, CLKEN# pulls low to enable the
as shown in Figure 16.
processor PLL as shown in Figure 2.
An internal phase-locked loop (PLL) allows the LTC3816
At any instant, if the switcher output voltage rises above
to synchronize the internal oscillator to an external clock.
the OVF threshold, the PWRGD pulls low, the regulator
When there is a clocking signal at the MODE/SYNC pin, the
output voltage is actively ramped to 0V and PWRGD
LTC3816 phase detector adjusts the internal PLL VCO input,
remains latched low until either the power is cycled or
synchronizing the switching frequency to the external clock
VRON toggles. In the IMVP-6 configuration, the maximum
frequency, and aligning the TG falling edge to the external
OVF threshold is 1.7V. In the IMVP-6.5 configuration, the
clock’s falling edge. During synchronization, the oscillator
maximum threshold reduces to 1.55V.
frequency range widens to 120kHz to 650kHz.
The PWRGD pin is an open-drain output that indicates the
For rapid frequency lock-in, the VCO input voltage can be
regulator output voltage has stabilized. At start-up, once
pre-biased to the desired operating frequency before the
the switcher output has settled to its VID potential for more
external clock is applied. A resistor connected between
than 10ms, this open-drain releases and is pulled high by
the RFREQ pin and GND can pre-bias the VCO’s input
the external pull-up resistor. It pulls low again if the switcher
voltage to the desired potential. Once pre-biased, the PLL
output voltage remains outside of the +175mV/–270mV
loop only needs to make slight changes to the VCO input
window around its nominal VID set point for more than
voltage in order to synchronize. The ability to pre-bias the
750µs. Once pulled low, the PWRGD state is latched and
loop filter allows the PLL to lock-in rapidly.
the control logic initiates a shutdown sequence. After the

700

600
SYNCHRONIZATION

500
fOSC (kHz)

400

300
FREE
RUNNING
200

100
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4
VRFREQ (V)
3816 F16

Figure 16. VCO Transfer Curve

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LTC3816
APPLICATIONS INFORMATION
output voltage is ramped down, the controller continues event. The controller continues its normal operation with
to hold the regulator output and PWRGD low until the no disruption to the output voltage. To reset this thermal
VRON pin toggles or the input supply resets. comparator, the voltage at the RPTC pin must drop below
During a VID transition, the power good comparators 0.1V. To accurately reflect the system temperature, the
are masked for 100µs. In deeper sleep mode (25µs after nonlinear PTC thermistor should be mounted as close as
DPRSLPVR pin transitions high), the power good com- thermally possible to the hottest device, e.g., the inductor
parators are disabled and PWRGD stays high unless the or the MOSFET. To prevent the switching noise from af-
switcher output voltage rises above its overvoltage fault fecting the thermal sensing circuit, add a small capacitor
threshold OVF or the controller detects that the regulator near the RPTC pin.
output voltage is 370mV lower than its nominal value. Figure 17 shows the Murata PTC PRF18 series typical re-
The LTC3816 PWRGD pin can be configured for wire-OR sistance-temperature characteristics. At room temperature,
operation. Shorting PWRGD to ground externally triggers all parts have about 470Ω nominal resistance. At higher
a latchoff function. The regulator forces the output to a temperatures, the resistance increases exponentially. An
zero voltage condition and stays in this state until either overtemperature event is detected by the LTC3816 when
the VRON pin or the input supply resets. the PTC thermistor ’s resistance exceeds 4.7k. By selecting
the appropriate thermistor from the series, this thermal
monitoring threshold can be set anywhere from 65°C to
VRTT# and Thermal Shutdown 145°C with 10°C resolution.
The LTC3816 includes a thermal monitoring circuit that The LTC3816 includes a second thermal protection feature.
senses the potential at the RPTC pin. An internal 100µA If the LTC3816 die temperature is higher than 150°C, the
pull-up current source connects to an external nonlinear controller pulls down the VRTT# pin. Under this condition
PTC thermistor through this pin. At room temperature, the the CPU should initiate its thermal management opera-
low resistance PTC creates a low voltage at the RPTC pin. tion. To untrip the VRTT# flag, the die temperature must
At high temperatures, the PTC resistance increases expo- be dropped below 130°C. If the LTC3816 die temperature
nentially. If the resulting RPTC voltage is higher than 0.47V, exceeds 165°C, the driver is disabled and the controller is
it trips the thermal monitor comparator, causing the open- latched in a thermal shutdown state until the power supply
drain pin VRTT# to pull low signaling an overtemperature is cycled or the VRON input toggles.
1000
BG
BF
BE
RESISTANCE CHANGE (R/R25)

100 BD
BC
BB
BA
10 AR
AS

0
–20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
3816 F17

Figure 17. Murata Nonlinear PTC PRF18 Series Typical

Resistance-Temperature Characteristics. Extracted From
Murata PTC PRF18**471QB1RB Data Sheet

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 LTC3816
APPLICATIONS INFORMATION
Power MOSFET and Schottky Diode Selection estimate the CMILLER term is to take the change in gate
charge from points A and B on a manufacturers data sheet
The LTC3816 requires two external N-channel power
and divide by the stated VDS voltage specified. CMILLER is
MOSFETs: One for the top (main) switch and one (or more)
the most important selection criteria for determining the
for the bottom (synchronous) switch.
transition loss term in the top MOSFET but is not directly
The peak-to-peak MOSFET gate drive levels are set by the specified on MOSFET data sheets. CRSS and COSS are
5.2V INTVCC supply, requiring the use of logic-level thresh- specified sometimes but definitions of these parameters
old MOSFETs in most applications. Pay close attention to are not included.
the BVDSS specification for the MOSFETs as well; many
logic-level MOSFETs are limited to 30V or less. When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given
Selection criteria for the power MOSFETs includes the by:
input capacitance, the on-resistance RDS(ON), the input
voltage and the maximum output current. MOSFET input VOUT
Main Switch Duty Cycle =
capacitance is a combination of several components VIN
but can be derived from the typical gate-charge   curve VIN – VOUT
included on most data sheets as shown in Figure 18. The Synchronous Switch Duty Cycle =
VIN
curve is generated by forcing a constant input current
into the gate of a common source, current source loaded The power dissipation for the main and synchronous
stage and then plotting the gate voltage versus time. The MOSFETs at maximum output current are given by:
initial slope is the effect of the gate-to-source and the
( )
VOUT 2
gate-to-drain capacitances. The flat portion of the curve PMAIN = ILOAD(MAX ) (1+ δ )RDS(ON) +
is the result of the Miller multiplication effect of the drain- VIN
to-gate capacitance as the drain drops the voltage across I
the current source load. The upper sloping line is due to ( VIN )2 LOAD2(MAX) (RDR )(CMILLER ) •
the drain-to-gate accumulation capacitance and the gate-
to-source capacitance.  1 1 
 +  ( fOSC )
The Miller charge (the increase in coulombs on the hori-  VINTVCC – VGS(MIL) VGS(MIL) 
zontal axis from A to B while the curve is flat) is specified
for a given VDS drain voltage, but can be adjusted for
V –V
VIN
( 2
)
PSYNC = IN OUT ILOAD(MAX ) (1+ δ )RDS(ON)
different VDS voltages by multiplying the ratio of the ap-
plication VDS to the curve specified VDS values. A way to where δ is the temperature dependency of RDS(ON) and
VIN
RDR is the effective top driver resistance (approximately
2.6Ω). VGS(MIL) is the MOSFET VGS at the Miller effect
VGS
MILLER EFFECT
V transition. CMILLER is the calculated capacitance using
VGS(MIL)
A B
the gate-charge curve from the MOSFET data sheet as
+
+V
DS
described above. The term (1 + δ) is generally given for
QIN VGS – a MOSFET in the form of a normalized RDS(ON) versus
–
CMILLER = (QB – QA)/VDS
3816 F18
temperature curve, but δ = 0.005/°C can be used as an
approximation for low voltage MOSFETs.
Figure 18. MOSFET Miller Capacitance

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LTC3816
APPLICATIONS INFORMATION
Both MOSFETs have I2R losses while the topside N-channel This equation has a maximum RMS current at VIN = 2VOUT ,
equation includes an additional term for transition losses, where IRMS(MAX) = ILOAD(MAX)/2. This simple worst-case
which are highest at the highest input voltage. The number, condition is commonly used for design because even
type and on-resistance of all MOSFETs selected take into significant deviations do not offer much relief. A typical
account the voltage step-down ratio as well as the actual LTC3816 application operates at low duty cycle, hence,
position (main or synchronous) in which the MOSFET is the maximum input supply ripple current occurs at
used. A much smaller, lower input capacitance MOSFET VIN = VIN(MIN), and typically IRMS(MAX) < ILOAD(MAX)/2.5.
should be used for the top MOSFET in applications where Note that capacitor manufacturers’ ripple current ratings
VIN >> VOUT . The top MOSFET ’s on-resistance is normally are often based on only 2000 hours of life. This makes
less important for overall efficiency than its input capaci-
it advisable to further derate the capacitor or to choose
tance at operating frequencies above 300kHz. MOSFET
a capacitor rated at a higher temperature than required.
manufacturers have designed special purpose devices that
Several capacitors may also be paralleled to meet size or
provide reasonably low on-resistance with significantly
height requirements in the design. Sanyo OS-CON SVP,
reduced input capacitance for the main switch in switching
SVPD series or aluminum electrolytic capacitors from
regulators. The synchronous MOSFET losses are greatest
Panasonic WA series in parallel with a couple of high
at high input voltages when the top switch duty cycle is
performance ceramic capacitors should be used as the
low or during a short circuit when the synchronous switch
input supply bypass. Ceramic capacitors placed next to
is on close to 100% of the period.
the top MOSFET drain helps to reduce the input supply
The Schottky diode, D, shown in Figure 1 conducts during voltage ripple.
the dead-time between the conduction of the two large
power MOSFETs. This prevents the body diode of the bot- COUT Selection
tom MOSFET from turning on, storing charge during the
dead time and requiring a reverse-recovery period which The output capacitor choice is primarily determined by the
could cost as much as several percent in efficiency. Due voltage tolerance specifications due to large load current
to the relatively small average current, a 2A to 8A Schottky transients encountered in typical LTC3816 applications.
is generally acceptable while offering a good compromise The capacitance must be sufficient to absorb the change
between series resistance and capacitance. Larger diodes in inductor current when a high current to low current
result in additional transition loss due to their larger junc- transition occurs. The opposite load current transition is
tion capacitance. generally determined by the control loop compensation
components, so make sure not to overcompensate and
slow down the response. The minimum capacitance to
CIN Selection assure the inductor ’s energy is adequately absorbed is:
In continuous mode, the source current of the top N-chan-
L ( ∆ILOAD )
2
nel MOSFET is a square wave of duty cycle VOUT/VIN. To
CBULK + CCER =
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
(
2VOUT ∆VOUT(LOAD) )
maximum RMS capacitor current is given by: where CBULK is the amount of bulk capacitance and CCER
VOUT ( VIN – VOUT ) is the total amount of ceramic capacitance. To minimize
IRMS(MAX ) ≈ ILOAD(MAX ) the output voltage overshoot during a load step, set:
VIN
∆VOUT(LOAD) = ∆VOUT(AVP)

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 LTC3816
APPLICATIONS INFORMATION
The resistive component of the bulk capacitor ESR must The Sanyo OS-CON semiconductor electrolyte capacitor
be small enough that under a load release, ESR multiplied is one possible choice for high performance through-hole
by the change in load current must meet the following capacitors. In surface mount applications, multiple paral-
criteria: lel capacitors are required to meet the ESR or transient
∆VOUT(LOAD) > ∆ILOAD • RESR current handling requirements. Aluminum electrolytic
and dry tantalum capacitors are both available in surface
The ceramic capacitors at the regulator output help to mount configurations. New special polymer surface mount
absorb some of the change in the load current and reduce capacitors offer very low ESR but have much lower ca-
the ESR voltage step predicted by the above equation. High pacitive density per unit volume. In the case of tantalum,
performance ceramic capacitors also help to lower the it is critical that the capacitors are surge tested for use in
regulator output voltage perturbation caused by the high switching power supplies. Several excellent output capaci-
slew rate change in the inductor current flowing through tor choices are the Sanyo POSCAP TPF, TPL and TPLF, or
the bulk capacitor parasitic ESL. the Panasonic SP series. Consult the manufacturer for
The total amount of output capacitance required is also other specific recommendations.
restricted by the steady-state output voltage ripple. The
output ripple, ∆VOUT , in continuous mode is determined Inductor Selection
by: The inductor in a typical LTC3816 circuit is chosen primarily
 1  for its saturation current and inductance value. The induc-
∆VOUT ≈ ∆IL  RESR + tor DC rated current should be larger than the expected
 8 • fOSC • (CBULK + CCER ) 
peak current which is equal to:
where fOSC = operating frequency and ∆IL = ripple current ∆IL(MAX )
in the inductor. The output ripple is highest at maximum IL(PEAK ) = ILOAD(MAX ) +
2
input voltage since ∆IL increases with input voltage. The
first term in the ripple voltage equation relates to the In addition, the selected inductor must be able to withstand
ripple current into the ESR of the output capacitor, which 2 × ILOAD(MAX) for a short duration without saturation (see
dominates the output ripple voltage. The second term the Current Limit section).
guarantees that the output capacitance does not signifi- The inductor value sets the ripple current, which is com-
cantly discharge during the operating frequency period monly chosen at around 20% to 30% of the anticipated
due to ripple current. full load current. Higher inductance reduces ripple cur-
Note that the IMVP-6 or IMVP-6.5 application specifies rent, core losses in the inductor, ESR losses in the output
extremely low output voltage deviations. Therefore, the capacitors and output voltage ripple. But, under rapid
output capacitor selection should be carefully considered. loading conditions, higher inductance results in higher
The regulator should be located in close proximity to the peak-to-peak transient deviations. A lower value inductor
CPU. The bulk capacitor needs to be as close as possible reduces the number of output capacitors and requires a
to the power supply pins of the processor to minimize the smaller PCB footprint for the LC filter. Highest efficiency
parasitic inductance between the decoupling capacitor and operation is obtained at low frequency with small ripple
the load. In addition, multiple high performance ceramic current. However, achieving this requires a large induc-
capacitors are normally placed in the processor socket tor and higher output ripple under transient conditions.
cavity to compensate for the PCB parasitic resistance There is a trade-off between component size, efficiency
and inductance.

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LTC3816
APPLICATIONS INFORMATION
and operating frequency. Given a specified limit for ripple VIN VBAT
12V
current, the inductor value can be obtained using the fol-
LTC3816
lowing equation: TG QT
L

VOUT  VOUT 
SW
+
VOUT

L=  1 –  BG QB D
COUT
fOSC • ∆IL(MAX )  VIN(MAX ) 
BSOURCE
3816 F19

Once the value for L is known, the type of inductor must

Figure 19. Automotive Application Protection
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores, transient suppressor clamps the input voltage during
forcing the use of more expensive ferrite cores. Ferrite load dump. Note that the transient suppressor should not
designs have very low core loss and are thus preferred conduct during double-battery operation, but must still
at high switching frequencies. Ferrite core materials clamp the input voltage below breakdown of the converter.
saturate hard, which means that inductance collapses Although the IC has a maximum input voltage of 40V on
abruptly when the peak design current is exceeded. This the SW pins, most applications will be limited to 30V by
results in an abrupt increase in inductor ripple current and the MOSFET BVDSS.
consequent output voltage ripple. Do not allow the core to
saturate! A variety of inductors designed for high current,
low voltage applications are available from manufacturers Checking Transient Response
such as Vishay, Sumida, Pulse, Wurth Elektronik, Vitec For all new LTC3816 PCB circuits, transient tests need to
and Toko. be performed to verify the proper feedback loop operation.
The regulator loop response can be checked by looking at
Automotive Considerations the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
Before you connect an LTC3816 converter to an automo- load current. When a load step occurs, VOUT shifts by an
tive cigarette lighter supply, be advised: you are plugging amount equal to ∆VAVP . ∆ILOAD also begins to charge or
into the supply from hell. The main battery line in an discharge COUT generating the feedback error signal that
automobile is the source of a number of nasty potential forces the regulator to adapt to the current change and
transients, including load dump, reverse battery and return VOUT to its steady-state value. During this recovery
double battery. time VOUT can be monitored for excessive overshoot or
Load dump is the result of a loose battery cable. When the ringing, which would indicate a stability problem.
cable breaks connection, the field collapse in the alterna- Measuring transient response presents challenges in two
tor can cause a positive spike as high as 60V which takes respects: obtaining an accurate measurement and generat-
several hundred milliseconds to decay. Reverse battery is ing a suitable transient to use to test the circuit. Output
just what it says, while double battery is a consequence of measurements should be taken with a scope probe directly
tow truck operators finding that a 24V jump start cranks across the output capacitor. Proper high frequency probing
cold engines faster than 12V. techniques should be used. In particular, don’t use the 6"
The network shown in Figure 19 is the most straightforward ground lead that comes with the probe! Use an adapter that
approach to protect a DC/DC converter from the ravages fits on the tip of the probe and has a short ground clip to
of an automotive battery line. The series diode prevents ensure that inductance in the ground path doesn’t cause
current from flowing during reverse battery, while the a bigger spike than the transient signal being measured.

3816f

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 LTC3816
APPLICATIONS INFORMATION
Conveniently, the typical probe tip ground clip is spaced A Design Example
just right to span the leads of a typical output capacitor. In As a design example, consider an IMVP-6.5 application
general, it is best to take this measurement with the 20MHz with inductor DCR current sense (see the last page
bandwidth limit on the oscilloscope turned on to limit high schematic) and the following requirements: assume VIN
frequency noise. Note that microprocessor manufacturers = 12V (nominal), VIN = 24V (maximum), VOUT = 0.75V,
typically specify ripple ≤20MHz, as energy above 20MHz VOUT (minimum) = 0.725V, ILOAD(MAX) = 27A, ILOAD(MIN)
is generally radiated and not conducted and will not affect = 1.5A, AVP = –3mV/A, fOSC = 400kHz, VIMON = 1.0V.
the load even if it appears at the output capacitor.
For the input and output conditions given above, the
Now that we know how to measure the signal, we need to steady-state minimum on-time for this application at
have something to measure. The ideal situation is to use VIN = 24V is approximately:
the actual load for the test, and switch it on and off while
watching the output. If this isn’t convenient, a current VOUT(MIN) 0.725V
step generator is needed. This generator needs to be able tON(MIN) = = = 75.5ns
VIN(MAX ) • fOSC 24V • 400kHz
to turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip This is much longer than the LTC3816 minimum on-time.
leads between the LTC3816 and the transient generator
must be minimized. To program the 400kHz operation, float the RFREQ pin.
The inductance value is chosen first based on a 20% ripple
Figure 20 shows an example of a simple transient gen- current assumption. The highest value of ripple current
erator. Be sure to use a noninductive resistor as the load occurs at the maximum input voltage:
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution VOUT  VOUT 
is to take ten 1/4W film resistors and wire them in parallel L=  1 – 
fOUT • ∆IL(MAX )  VIN(MAX ) 
to get the desired value. This gives a noninductive resis-
tive load which can dissipate 2.5W continuously or 50W 0.75V  0.75V 
= 1– = 0.33µH
if pulsed with a 5% duty cycle, enough for most LTC3816 4000kHz • 0.2 • 27 A  24V 
circuits. Solder the MOSFET and the resistor(s) as close
to the output of the LTC3816 circuit as possible and set A commonly available 0.33µH inductor is chosen. This
up the signal generator to pulse at a 100Hz rate with a 5% results in 5.5A of ripple current. The peak inductor cur-
duty cycle. This pulses the LTC3816 with 500µs transients rent is the maximum DC load current plus one-half the
10ms apart, adequate for viewing the entire transient ripple current, or:
recovery time for both positive and negative transitions 1
while keeping the load resistor cool. IL(PEAK ) = 27 A + • 5.5A = 29.75A
2

LTC3816 VOUT
RLOAD

PULSE 50Ω
RENESAS RJK0305DPB
GENERATOR OR EQUIVALENT
10k

0V TO 10V
100Hz, 1% TO 5%
3816 F20
DUTY CYCLE LOCATE CLOSE TO THE OUTPUT

Figure 20. Transient Load Generator PC Board

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LTC3816
APPLICATIONS INFORMATION
For this example, a Vishay IHLP-5050CE-01 0.33µH induc- To derive the voltage drop across the inductor DCR (typically
tor is chosen. According to the inductor data sheet, it has 1.3mΩ), place a 0.1µF capacitor across the current sense
a maximum DC current rating of 36.5A and a saturation input pins, ISENP and ISENN. The current sense filter resistor
current of 62A. At room temperature, the typical DCR is value RIDCR can be calculated from the equation:
1.3mΩ and the maximum DCR is 1.5mΩ. At 125°C, the
L 0.33µH
DCR increases to approximately 2.085mΩ. The RIMAX RIDCR = = = 2.538k
resistor value can be calculated. RDCR • CIDCR 1.3mΩ • 0.1µF

 ∆I  RDCR Select RIDCR = 2.55k.

RIMAX =  ILIMIT + L 
 2  IIMAX(MIN) For the AVP section (refer to Figure 10), first select a 10k
2.0085mΩ NTC thermistor. In this example, the Murata NCP18XH103
= 29.75A • = 6.89k is chosen. Next, select:
9µA
RPAR = RNTC at 25°C = 10k
Choose 1% resistor RIMAX = 6.98k to ensure that the
regulator can supply the maximum load current under The RSER resistor value can be obtained from the follow-
the worst-case conditions. ing equation:
10 
If this large DCR variation is a problem, replace this induc- RSER ≈ ( ) ( )
R || (RNTC at 0°C ) – RPAR || (RNTC at 75°C ) 
3  PAR
tor with another inductor with a smaller DCR variation or
use an NTC temperature compensation circuit as shown in (
– RPAR || (RNTC at 25°C ) )
Figure 21. Please refer to the Temperature Compensated
Active Voltage Positioning with Inductor DCR section. From the NTC data sheet:
Note that Figure 21 uses a resistive divider and requires RNTC at 0°C = 27.2k
different component values for optimal temperature
compensation. RNTC at 75°C = 1.925k

VIN
IL
LTC3816
TG QT
L DCR
SW VOUT
INDUCTOR
BG QB D +
NTC COUT
RS
BSOURCE
RSER RPAR
ISENP 3816 F21

CIDCR
ISENN
RIMAX
IMAX

Figure 21. Inductor DCR Current Sense Using

NTC Temperature Compensation

3816f

36
 LTC3816
APPLICATIONS INFORMATION
Therefore RSER is calculated to be 13.99k and standard Select RIMON = 21k. The value of CIMON is selected to
value RSER = 14k is used. Next, the resistor RAVPDCRN value satisfy the desired IMON time constant:
is obtained from the AVP slope requirement:
tIMON 300µs
CIMON = = = 14.28nF
RSER + (RPAR || RNTC )  RIMON 21k
A AVP= = 3mV/A =  • RDCR
R AVPDCRN
Select CIMON = 15nF.
14k + (10k || 10k ) 
⇒ R AVPDCRN =  • 1.3mΩ = 8.233k The power MOSFETs chosen for this application are the
3mV/A Renesas RJK0305DPB (top) and 2 × RJK0330DPB (bot-
tom). The upper MOSFET, which is optimized for low
Select the standard value 8.25k. The capacitor value CVDCRN switching losses, has a typical RDS(ON) of 10mΩ at VGS
is given by the following equation: = 4.5V, a total gate charge of 8nC, and a minimum BVDSS
L of 30V. The bottom MOSFET which is optimized for low
C VDCRN =
RSER + (RPAR || RNTC )  • RDCR on-resistance, has a typical RDS(ON) of 2.8mΩ at VGS =
4.5V, a total gate charge of 27nC, and a minimum BVDSS
0.33µH of 30V.
= = 13.36nF
14k + (10kk || 10k )  • 1.3mΩ From the RJK0305DPB upper MOSFET data sheet, the
Miller capacitance is calculated to be:
Use the standard value CVDCRN = 15nF.
∆QG 2nC
To program the IMON voltage, first select the resistor CMILLER ≈ = = 167pF
RPREIMON such that IPREIMON bias current is around 10µA ∆VDS 12V
to 20µA:
Assuming a top MOSFET junction temperature of 75°C,
ILOAD(MAX ) • RDCR R δ = 0.25 and the power dissipation in this MOSFET is:
RPREIMON = • NTCNET
IPREIMON R AVPDCRN
27 A • 1.3mΩ 14k + (10k || 10k ) 
PMAIN =
VOUT
VIN
( ) 2
ILOAD(MAX ) (1+ δ )RDS(ON) + t
= •
15µA 8.25k I
= 5.389k
( VIN )2 LOAD2(MAX) (RDR )(CMILLER ) •
 1 1 
Select a standard value RPREIMON = 5.1k. Once the resistor  +  ( fOSC )
RPREIMON value is chosen, the RIMON resistor value can  VINTVCC – VGS(MIL) VGS(MIL) 
be obtained from the following equation:
0.75V
VIMON • RPREIMON R AVPDCRN
PMAIN =
12V
( 27 A ) (1+ 0.25) 10mΩ +
2

RIMON = •
(
3 • ILOAD(MAX ) • RDCR ) RNTCNET
(12V )2 272A (2.6Ω)(167pF ) •
1.0 V • 5.1k 8.25k
= •  1 1
3 • ( 27 A • 1.3mΩ ) 14k + (10k || 10k )   5.2V – 3V + 3V  ( 400kHz )
 
= 21.03k
PMAIN = 0.57 W + 0.266 W ≈ 0.836 W

3816f

37
LTC3816
APPLICATIONS INFORMATION
For the synchronous MOSFETs, assume that the two Most regulator designs allow a slight transient overshoot
bottom MOSFETs share the inductor current equally. The for a short duration. If this is limited to 40mV, we have:
power dissipation for one MOSFET is:
(
∆VOUT( AVP) = AVP • ILOAD(MAX ) – ILOAD(MIN) )
V –V
( 2
)
PSYNC = IN OUT ILOAD(MAX ) (1+ δ )RDS(ON)
VIN
mV
=3 • ( 27 A – 1.5A ) = 76.5mV
A
12V – 0.75V
PSYNC =
12V
( 13.5A ) (1+ 0.25) 2.8mΩ
2 ∆VOUT(LOAD) = ∆VOUT( AVP) + ∆VOVERSHOOT

= 0.598 W = 76.5mV + 40mV = 116.5mV

0.33µH ( 27 A – 1.5A )
2
The total power dissipation of the bottom MOSFETs is CBULK + CCER = = 1228µF
2 × 0.598W = 1.196W. 2 ( 0.75V )(116.5mV )
For this application, the maximum input RMS current The ESR of the output capacitor is determined by the load
happens when VIN = VIN(MIN) and can be determined from transient requirement. If the output voltage jump due to
the formula: the capacitor ESR is limited to ∆VOUT(AVP):

IRMS(MAX ) ≈ ILOAD(MAX )
(
VOUT VIN(MIN) – VOUT ) RESR <
∆VOUT( AVP)
=
75mV
= 2.94mΩ
VIN(MIN) ∆ILOAD (27A – 1.5A )
0.75V ( 5V – 0.75V ) The above requirements are easily satisfied by three
IRMS(MAX ) ≈ 27 A ≈ 9.64A Sanyo POSCAP 2TPF330M6 330µF (ESR = 6mΩ) bulk
5V
capacitors in parallel, twenty 10µF and some 1µF high
The minimum RMS current rating of the input capacitor performance ceramic capacitors in the processor socket
must exceed 9.64A. To meet this ripple current requirement cavity. With three bulk capacitors in parallel, the effective
with VIN(MAX) = 24V, select two Sanyo OS-CON 25SVP56 ESR is 2mΩ, and the maximum steady-state output ripple
capacitors or higher voltage rating capacitor as the input voltage is given by:
supply bulk capacitance. In addition, place a couple of
high performance ceramic capacitors in parallel with the  1 
∆VOUT ≈ ∆IL RESR + 
bulk capacitors.  8 • fOSC • (CBULK + CCER ) 
The output capacitor value is determined by:  1 
= 5.5A 2mΩ + 
8 • 400kHz • ( 3 • 330µF + 20 • 10µF ) 
L ( ∆ILOAD )
2 
CBULK + CCER =
(
2VOUT ∆VOUT(LOAD) ) = 11mV + 1.44mV = 12.44mV

3816f

38
 LTC3816
APPLICATIONS INFORMATION
As can be seen from the above equation, the biggest portion 6. The AITC amplifier external components should be
of the output ripple comes from the ESR of the capacitor. placed close to the LTC3816. Only the NTC or PTC
This is why low ESR capacitors are so important in low thermistor should be placed near the inductor.
voltage, high current applications.
7. Are the VCC(SEN) and VSS(SEN), ISENP and ISENN leads
routed together with minimum PC trace spacing? The
PC Board Layout Checklist filter capacitor between VCC(SEN) and VSS(SEN) and the
When laying out the printed circuit board, start with the filter capacitor between ISENP and ISENN should be as
power devices. Be sure to orient the power circuitry so close as possible to the LTC3816. Ensure accurate
that a clean flow of the power path is achieved. Conductor current sensing with Kelvin connections as shown in
widths should be maximized and lengths minimized. After Figure 22.
you are satisfied with the power path, the control circuitry 8. To prevent IMON current from affecting the output
should be laid out. It is much easier to find routes for the voltage kelvin sense accuracy, the IMON resistor and
relatively small traces in the control circuits than it is to VSS(SEN) should be connected to the CPU VSS(SEN) pin
find circuitous routes for high current paths. After the using separate PCB traces.
layout, the following checklist should be used to ensure
9. Since the IC ground will normally return to the ground
proper operation of the LTC3816.
planes on the PCB through an array of vias, be sure
1. Keep the GND and BSOURCE traces separate. The signal to avoid having any high di/dt power path currents
ground consists of the LTC3816 GND pin and the (–) flowing under the IC.
terminal of VOUT . The power ground consists of the
BSOURCE pin, the Schottky diode anode, the source 10. Any external small-signal components that are con-
nected to ground should be located as close as pos-
of the bottom side MOSFET, and the (–) terminal of the
sible to the IC, with local connections to GND or the
input capacitor. Also, try to connect the (–) terminal
ground plane using vias.
of the output capacitor as close as possible to the (–)
terminals of the input capacitor. Place the LDO ceramic INDUCTOR
capacitor CINTVCC next to the IC, between INTVCC and
GND. The negative terminals of CIN, COUT and CINTVCC
LTC3816 RISR
should be as close as possible to one another. ISENP
CISR SENSE
2. The high di/dt loop formed by the top MOSFET, the ISENN RESISTOR

bottom MOSFET and the CIN capacitor should have

short leads and PC trace lengths to minimize high
frequency noise and voltage stress from inductive OUTPUT CAPACITOR
ringing.
SW
3. Connect the drain of the topside MOSFET directly to the
(+) plate of CIN, and connect the source of the bottom LTC3816 RISR
side MOSFET directly to the (–) terminal of CIN. This ISENP
CISR INDUCTOR
capacitor provides the AC current to the MOSFETs. ISENN

4. The charge pump capacitor, CB, should also be next 3816 F22

to the IC between BOOST and SW. OUTPUT CAPACITOR

5. Place the small-signal components away from high Figure 22. Sense Resistor and Inductor DCR
frequency switching nodes (BOOST, SW, TG and Kelvin Current Sensing
BG).
3816f

39
LTC3816
Typical Applications
An IMVP-6 Converter Using Current Sense Resistor with –5.7mV/A AVP Slope

4.75k 3.32k

33pF
1000pF 124Ω
2.37k
1.1V
3.3V
INTVCC
GND ITC ITCFB SGND ISENN IMAX ISENP LFF 56Ω 1.9k 1.9k
PREIMON VRTT# VRTT#
IMON CLKEN# CLKEN# PTC
RPTC PWRGD 4.5V TO 25V
1000pF VIN
VRON VRON 8 +
SW CIN
VSS(SEN) 1
TG
0.1µF 6, 7 L RSEN
VCC(SEN) 5
BOOST VCC(CORE)
SERVO 4 CBULK + CCER
ILOAD(MAX)
LTC3816 VIN 330µF 10µF
22pF 1µF s2 s6 4A
10k EXTVCC DB 2, 3
VSS(CORE)
VFB INTVCC
INTVCC Si4816BDY 100Ω 100Ω
20k 10pF
COMP BG 4.7µF

1500pF BSOURCE
SS
MODE/SYNC
DPRSLPVR DPRSLPVR fSYNC
RFREQ
CSLEW
470pF 22pF CBULK: SANYO POSCAP 2TPF330M6
VID0 VID1 VID2 VID3 VID4 VID5 VID6 L: VISHAY IHLP2525CZ-06 (1µH, DCR = 8.44mΩ)
PTC: MURATA PRF18BC471QB1RB
VID0 VID1 VID2 VID3 VID4 VID5 VID6 RSEN: PANASONIC ERJM1WTF4M0U

3816 TA02

Efficiency Transient Waveform

100
VCC(CORE) = 1V
90 fOSC = 400kHz
VEXTVCC = 0V
80
70 VCC(CORE)
20mV/DIV
EFFICIENCY (%)

60
VIN = 5V
50
VIN = 12V
40
30 ILOAD
20 2A/DIV

10 CONTINUOUS MODE
PULSE-SKIPPING MODE
0 3816 TA02b
0.01 0.1 1 20µs/DIV
LOAD CURRENT (A)
3816 TA02b

3816f

40
 A Dual Channel IMVP-6 Converter Using Sense Resistor with –2.1mV/A AVP Slope

VIN
4.5V TO 24V
100Ω 100Ω

1000pF 10.2k 2.43k 2.43k 10.2k 1000pF

22pF ISENN ISENN 22pF

3k 1.1V 3.3V 3k
ITCFB IMAX 1000pF 1000pF IMAX ITCFB
511Ω 511Ω
typical Applications

ITC ISENP 56Ω ISENP ITC

LFF 1.9k LFF
PREIMON VRTT# PREIMON
INTVCC IMON VRTT# VRTT# IMON INTVCC
LT3816 LT3816
CLKEN# 1.9k
RPTC CLKEN# 3.3V CLKEN# RPTC
VRON VRON PWRGD VRON
PWRGD PWRGD
VSS(SEN) + VSS(SEN)
VCC(SEN) SW CVIN SW VCC(SEN)
SERVO TG QT QT TG SERVO
0.1µF L RSENSE RSENSE L 0.1µF
10k 10k
VFB BOOST BOOST VFB
12k 10pF VIN
+ VIN 10pF 12k
QB QB
COMP DB CBULK DB COMP
EXTVCC 5V PTC CCER PTC 5V EXTVCC
22pF 6800pF INTVCC INTVCC 6800pF 22pF
SS SS
BG – + BG
470pF 22pF DPRSLPVR VCC_CORE DPRSLPVR 22pF 470pF
BSOURCE BSOURCE
ILOAD(MAX) = 54A
CSLEW MODE/SYNC 4.7µF 4.7µF MODE/SYNC CSLEW
VID0 RFREQ RFREQ VID0
VID1 VID6 400kHz VID6 VID1
VID5 SQUARE WAVE VID5
VID2 VID2
VID3 VID4 VID4 VID3
GND GND

3816 TA04

VID6
VID5
VID4
VID3
VID2
VID1
VID0

CBULK: 4 s SANYO 2TPF330M6 (330µF) PTC: MURATA PRF18BC471QB1RB

CCER: 32 s 10µF + 2 s 1µF QT: RENESAS RJK0305DPB
CIN: 3 s SANYO OS-CON 35SVPD47M + 2 s 10µF QB: 2 s RENESAS RJK0330DPB
DB: CMDSH-4E RSENSE: PANASONIC ERJM1WTF1M0U (1mΩ)
L: IHLP-5050CE-01 (0.33µH, DCR = 1.3mΩ)

41
3816f
LTC3816
LTC3816
Package Description
FE Package
38-Lead Plastic eTSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev B)
Exposed Pad Variation AA

4.75 REF 9.60 – 9.80*

(.378 – .386)
4.75 REF
(.187)
38 20

6.60 ±0.10
2.74 REF
4.50 REF
SEE NOTE 4 6.40
2.74
0.315 ±0.05 REF (.252)
(.108)
BSC
1.05 ±0.10

0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 19
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0o – 8o

0.50
0.09 – 0.20 0.50 – 0.75 (.0196) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.17 – 0.27
FE38 (AA) eTSSOP REV B 0510
(.0067 – .0106)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN MILLIMETERS FOR EXPOSED PAD ATTACHMENT
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3816f

42
 LTC3816
Package Description
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)

0.70 p 0.05

5.50 p 0.05
5.15 ± 0.05

4.10 p 0.05

3.00 REF 3.15 ± 0.05

PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
5.5 REF
6.10 p 0.05
7.50 p 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30 TYP OR
0.75 p 0.05 3.00 REF 0.35 s 45o CHAMFER
5.00 p 0.10
0.00 – 0.05 37 38

0.40 p0.10
PIN 1
TOP MARK 1
(SEE NOTE 6)
2

5.15 ± 0.10
7.00 p 0.10 5.50 REF

3.15 ± 0.10

(UH) QFN REF C 1107

0.200 REF 0.25 p 0.05 R = 0.125 R = 0.10

0.50 BSC TYP TYP
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
OUTLINE M0-220 VARIATION WHKD MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3816f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 43
LTC3816
Typical Application
An IMVP-6.5 Converter Using Temperature Compensated Inductor DCR Sensing with –3mV/A AVP Slope

10k

14k
8.25k

15nF ISENN
6.98k
ITCFB IMAX 0.1µF
2.55k
ITC ISENP
5.1k
15nF 21k PREIMON LFF 56Ω
VRTT#
IMON IMON VRTT# 1.1V
LT3816 CLKEN# 1.9k
RPTC CLKEN# 3.3V VIN
1000pF VRON VRON PWRGD 1.9k 4.5V TO 24V
PWRGD
VSS(SEN) NTC +
SW CVIN 100Ω
VCC(SEN)
SERVO TG QT 100Ω
0.1µF L
10k
VFB BOOST
12k 10pF VIN DB + VCC(CORE)
QB CBULK CCER
COMP ILOAD(MAX) = 27A
EXTVCC 5V PTC
22pF 2.2nF INTVCC
SS
BG
470pF 22pF DPRSLPVR 4.7µF
BSOURCE
CBULK: 3 s SANYO 2TPF330M6 (330µF)
CSLEW MODE/SYNC CCER: 20 s 10µF + 2 s 1µF
VID0 RFREQ CIN: 2 s SANYO OS-CON 35SVPD47M + 2 s 10µF
VID6 DB: CMDSH-4E
VID1
L: IHLP-5050CE-01 (0.33µH, DCR = 1.3mΩ)
VID2 VID5 NTC: MURATA NCP18XH103
VID0 VID3 VID4 PTC: MURATA PRF18BC471QB1RB
VID1 GND QB: 2 s RENESAS RJK0330DPB
VID2 QT: RENESAS RJK0305DPB
VID3
VID4
VID5
VID6

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6mm × 6mm QFN Package

3816f

44 Linear Technology Corporation

LT 0710 • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

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