LTM8023

2A, 36V DC/DC

Step-Down µModule
Regulator
FEATURES DESCRIPTION
n Complete Step-Down Switch Mode Power Supply The LTM®8023 is a complete 2A, DC/DC step-down power
n Wide Input Voltage Range: 3.6V to 36V supply. Included in the package are the switching controller,
n 2A Output Current power switches, inductor, and all support components.
n 0.8V to 10V Output Voltage Operating over an input voltage range of 3.6V to 36V, the
n Selectable Switching Frequency: 200kHz to 2.4MHz LTM8023 supports an output voltage range of 0.8V to 10V,
n Current Mode Control and a switching frequency range of 200kHz to 2.4MHz,
n Programmable Soft-Start each set by a single resistor. Only the bulk input and output
n SnPb (BGA) or RoHS Compliant (LGA and BGA) filter capacitors are needed to finish the design.
Finish
The low profile package enables utilization of unused
n Tiny, Low Profile, Surface Mount LGA (9mm ×
space on the bottom of PC boards for high density point
11.25mm × 2.82mm) and BGA (9mm × 11.25mm ×
of load regulation.
3.42mm) Packages
The LTM8023 is packaged in a thermally enhanced, com-
pact and low profile over-molded land grid array (LGA)
APPLICATIONS and ball grid array (BGA) packages suitable for automated
n Automotive Battery Regulation assembly by standard surface mount equipment. The
n Power for Portable Products LTM8023 is available with SnPb (BGA) or RoHS compli-
n Distributed Supply Regulation ant terminal finish.
n Industrial Supplies L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and µModule are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
n Wall Transformer Regulation respective owners.

TYPICAL APPLICATION
5.5VIN to 36VIN, 3.3V/2A DC/DC µModule® Converter Efficiency and Power Loss
90 1.8
VOUT
VIN* 85 1.6
VIN VOUT 3.3V
5.5V TO 36V
2A
2.2µF AUX 1.4
22µF 80
RUN/SS BIAS 1.2
POWER LOSS (W)
EFFICIENCY (%)

75
SHARE
1.0
LTM8023 70
0.8
PGOOD 65
0.6
60
ADJ 0.4
SELECTABLE 55 VIN = 12V
VOUT = 3.3V 0.2
OPERATING RT GND SYNC
FREQUENCY 8023 TA01
50 f = 650 kHz 0
49.9k 154k 0.01 0.1 1 10
LOAD CURRENT (A)
8023 TA01b
*RUNNING VOLTAGE RANGE. PLEASE
REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS

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LTM8023
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, RUN/SS Voltage..................................................40V VIN + BIAS..................................................................56V
ADJ, RT, SHARE Voltage..............................................5V Internal Operating Temperature
VOUT, AUX..................................................................10V (Note 2)................................................... –40°C to 125°C
PGOOD, SYNC...........................................................30V Storage Temperature.............................. –55°C to 125°C
BIAS...........................................................................16V Solder Temperature................................................ 250°C

PIN CONFIGURATION
GND (BANK 3) SHARE RT ADJ GND (BANK 3) SHARE RT ADJ

7 7
SYNC SYNC
6 PGOOD 6 PGOOD

5 RUN/SS 5 RUN/SS
BIAS BIAS
4 4
AUX AUX

3 3
VOUT VOUT
(BANK 2) 2 VIN (BANK 2) 2 VIN
(BANK 1) (BANK 1)
1 1

A B C D E F G H A B C D E F G H
LGA PACKAGE BGA PACKAGE
50-LEAD (11.25mm × 9mm × 2.82mm) 50-LEAD (11.25mm × 9mm × 3.42mm)

TJMAX = 125°C, θJA = 30.4°C/W, θJCbottom = 12.2°C/W, TJMAX = 125°C, θJA = 32.1°C/W, θJCbottom = 14.8°C/W,
θJCtop = 23.9°C/W, θJB = 12.1°C/W, WEIGHT = 0.9g θJCtop = 23.7°C/W, θJB = 14.6°C/W, WEIGHT = 0.9g
θ VALUES DETERMINED PER JEDEC 51-9, 51-12 θ VALUES DETERMINED PER JEDEC 51-9, 51-12

ORDER INFORMATION
PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE MSL TEMPERATURE RANGE
DEVICE FINISH CODE TYPE RATING (Note 2)
LTM8023EV#PBF Au (RoHS) LTM8023V e4 LGA 3 –40°C to 85°C
LTM8023IV#PBF Au (RoHS) LTM8023V e4 LGA 3 –40°C to 85°C
LTM8023MPV#PBF Au (RoHS) LTM8023MPV e4 LGA 3 –55°C to 125°C
LTM8023EY#PBF SAC305 (RoHS) LTM8023Y e1 BGA 3 –40°C to 85°C
LTM8023IY#PBF SAC305 (RoHS) LTM8023Y e1 BGA 3 –40°C to 85°C
LTM8023IY SnPb (63/37) LTM8023Y e0 BGA 3 –40°C to 85°C
LTM8023MPY#PBF SAC305 (RoHS) LTM8023Y e1 BGA 3 –55°C to 125°C
LTM8023MPY SnPb (63/37) LTM8023Y e0 BGA 3 –55°C to 125°C
Consult Marketing for parts specified with wider operating temperature • Recommended LGA and BGA PCB Assembly and Manufacturing
ranges. *Device temperature grade is indicated by a label on the shipping Procedures:
container. Pad or ball finish code is per IPC/JEDEC J-STD-609. www.linear.com/umodule/pcbassembly
• Terminal Finish Part Marking: • LGA and BGA Package and Tray Drawings:
www.linear.com/leadfree www.linear.com/packaging

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 LTM8023
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 10V, VRUN/SS = 10V, VBIAS = 3V, RT = 60.4k, COUT = 4.7µF unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input DC Voltage l 3.6 36 V
VOUT Output DC Voltage 0A < IOUT ≤ 2A, RADJ Open, COUT = 51µF (Note 3) 0.8 V
0A < IOUT ≤ 2A, RADJ = 43.2k, COUT = 51µF (Note 3) 10 V
RADJ(MIN) Minimum Allowable RADJ (Note 4) 42.2 kΩ
IOUT Continuous Output DC Current 4 ≤ VIN ≤ 36, COUT = 51µF 0 2 A
IQVIN VIN Quiescent Current VRUN/SS = 0.2V, RT = 174k 0.1 0.5 µA
VBIAS = 3V, Not Switching, RT = 174k (E, I) l 25 60 µA
VBIAS = 3V, Not Switching, RT = 174k (MP) l 25 350 µA
VBIAS = 0V, Not Switching, RT = 174k 85 120 µA
IQBIAS BIAS Quiescent Current VRUN/SS = 0.2V, RT = 174k 0.03 0.5 µA
VBIAS = 3V, Not Switching, RT = 174k (E, I) l 50 120 µA
VBIAS = 3V, Not Switching, RT = 174k (MP) l 50 200 µA
VBIAS = 0V, Not Switching, RT = 174k 1 5 µA
ΔVOUT/VOUT Line Regulation 5 ≤ VIN ≤ 36, IOUT = 1A, VOUT = 3.3V, COUT = 51µF 0.1 %
ΔVOUT/VOUT Load Regulation VIN = 24V, 0 ≤ IOUT ≤ 2A, VOUT = 3.3V, COUT = 51µF 0.4 %
VOUT(AC_RMS) Output Ripple (RMS) VIN = 24V, IOUT = 2A, VOUT = 3.3V, COUT = 51µF 10 mV
fSW Switching Frequency RT = 113k, COUT = 51µF 325 kHz
ISC(OUT) Output Short Circuit Current VIN = 36V, VOUT = 0V (Note 5) 2.9 A
VADJ Voltage at ADJ Pin COUT = 51µF l 765 790 805 mV
VBIAS(MIN) Minimum BIAS Voltage for Proper 2.3 2.8 V
Operation
IADJ Current Out of ADJ Pin ADJ = 1V, COUT = 51µF 2 µA
IRUN/SS RUN/SS Pin Current VRUN/SS = 2.5V 5 10 µA
VIH(RUN/SS) RUN/SS Input High Voltage COUT = 51µF 2.5 V
VIL(RUN/SS) RUN/SS Input Low Voltage COUT = 51µF 0.2 V
VPGOOD(TH) PGOOD Threshold VOUT Rising 730 mV
IPGOOD(O) PGOOD Leakage VPGOOD = 30V 0.1 1 µA
IPGOOD(SINK) PGOOD Sink Current VPGOOD = 0.4V 200 800 µA
VSYNCIL SYNC Input Low Threshold fSYNC = 550kHz, COUT = 51µF 0.5 V
VSYNCIH SYNC Input High Threshold fSYNC = 550kHz, COUT = 51µF 0.7 V
ISYNCBIAS SYNC Pin Bias Current VSYNC = 0V 0.1 µA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings meet specifications over the full –55°C to 125°C temperature range. Note
may cause permanent damage to the device. Exposure to any Absolute that the maximum internal temperature is determined by specific operating
Maximum Rating condition for extended periods may affect device conditions in conjunction with board layout, the rated package thermal
reliability and lifetime. resistance and other environmental factors.
Note 2: The LTM8023E is guaranteed to meet performance specifications Note 3: COUT = 51µF is composed of a 4.7µF ceramic capacitor in parallel
from 0°C to 85°C ambient. Specifications over the full –40°C to with a 47µF electrolytic.
85°C ambient operating temperature range are assured by design, Note 4: Guaranteed by design.
characterization and correlation with statistical process controls. The Note 5: Short circuit current at VIN = 36V is guaranteed by characterization
LTM8023I is guaranteed to meet specifications over the full –40°C to 85°C and correlation. 100% tested at VIN = 10V
ambient operating temperature range. The LTM8023MP is guaranteed to

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LTM8023
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted

Efficiency (8VOUT) Efficiency (5VOUT) Efficiency (3.3VOUT)

100 90 90
VOUT = 8V VOUT = 5V VOUT = 3.3V
90 85 85

80 80 80
EFFICIENCY (%)

EFFICIENCY (%)

EFFICIENCY (%)
70 75 75

60 70 70

50 65 65

40 60 60
5VIN
12VIN 12VIN 12VIN
30 55 55
24VIN 24VIN 24VIN
36VIN 36VIN 36VIN
20 50 50
0.01 0.1 1 0.01 0.1 1 0.01 0.1 1
OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A)
8023 G01 8023 G02 8023 G03

Minimum Required Input Voltage 36VIN Start-Up Waveforms 36VIN Start-Up Waveforms
vs Output Voltage (5VOUT) (3.3VOUT)
20
IOUT = 2A
18
VOUT VOUT
16
2V/DIV 2V/DIV
IIN
INPUT VOLTAGE (V)

14 OPERATING FREQUENCY IIN

AS RECOMMENDED 0.2A/DIV 0.2A/DIV
12 IN TABLE 1 RUN/SS RUN/SS
10 5V/DIV 5V/DIV
8023 G05 8023 G06
VIN = 36V 50µs/DIV VIN = 36V 50µs/DIV
8 IOUT = 2A IOUT = 2A
6 VBIAS = 3V VBIAS = 3V

2
0 2 4 6 8 10
OUTPUT VOLTAGE (V)
8023 G04

Input Current vs Output Current Input Current vs Output Current Input Current vs Output Current
1600 1200 2000
VOUT = 8V VOUT = 5V VOUT = 3.3V
1800
1400
1000
1600
1200
INPUT CURRENT (mA)

INPUT CURRENT (mA)

1400
INPUT CURRENT (mA)

800
1000 1200
12VIN 5VIN
600 24VIN 1000 12VIN
800
36VIN 24VIN
800 36VIN
600
400
600
400
400
12VIN 200
200 24VIN 200
36VIN
0 0 0
0 500 1000 1500 2000 0 500 1000 1500 2000 0 500 1000 1500 2000
OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)
8023 G07 8023 G08 8023 G09

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 LTM8023
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted

Output Short-Circuit Current Maximum Load Current

vs Input Voltage BIAS Current vs Load Current vs Input Voltage (8VOUT, LGA)
3200 30 2500

3000
25
2000
2800
OUTPUT CURRENT (mA)

LOAD CURRENT (mA)

BIAS CURRENT (mA)
20
2600 1500
3.3VOUT
2400 15 5VOUT
8VOUT
1000
2200
10
2000
500
5 25°C
1800 40°C
85°C
1600 0 0
0 10 20 30 40 0 500 1000 1500 2000 0 10 20 30 40
INPUT VOLTAGE (V) LOAD CURRENT (mA) INPUT VOLTAGE (V)
8023 G10 8023 G11 8023 G13

Load Current Load Current

vs Input Voltage (5VOUT, LGA) vs Input Voltage (3.3VOUT, LGA)
2500 2500

2000 2000
LOAD CURRENT (mA)

LOAD CURRENT (mA)

1500 1500

1000 1000

500 500
25°C 25°C
40°C 40°C
85°C 85°C
0 0
0 10 20 30 40 0 10 20 30 40
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
8023 G14 8023 G15

3.3VOUT Junction Temperature 5VOUT Junction Temperature 8VOUT Junction Temperature

vs Load (LGA) vs Load (LGA) vs Load (LGA)
50 60 80
45 70
50
40
60
TEMPERATURE RISE (°C)

TEMPERATURE RISE (°C)

TEMPERATURE RISE (°C)

35
40
30 50

25 30 40
20 30
20
15
20
10
12VIN 10 12VIN 16VIN
5 24VIN 24VIN 10 24VIN
36VIN 36VIN 36VIN
0 0 0
0 500 1000 1500 2000 2500 0 500 1000 1500 2000 2500 0 500 1000 1500 2000 2500
CURRENT (mA) CURRENT (mA) CURRENT (mA)
8023 G16 8023 G17 8023 G18

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LTM8023
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted

3.3VOUT Temperature Rise vs 5VOUT Temperature Rise vs 8VOUT Temperature Rise vs

Load Current (BGA) Load Current (BGA) Load Current (BGA)
60 60 90

80
50 50
70
TEMPERATURE RISE (°C)

TEMPERATURE RISE (°C)

TEMPERATURE RISE (°C)

40 40 60

50
30 30
40

20 20 30

20
10 12VIN 10 12VIN 18VIN
24VIN 24VIN 10 24VIN
36VIN 36VIN 36VIN
0 0 0
0 500 1000 1500 2000 2500 0 500 1000 1500 2000 2500 0 500 1000 1500 2000 2500
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
8023 G19 8023 G20 8023 G21

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 LTM8023
PIN FUNCTIONS
VIN (Bank 1): The VIN pin supplies current to the LTM8023’s large impact on the thermal performance of the part. See
internal regulator and to the internal power switch. This the PCB Layout and Thermal Consideration sections for
pin must be locally bypassed with an external, low ESR more details. Return the feedback divider (RADJ) to this net.
capacitor of at least 2.2µF. RT (Pin G7): The RT pin is used to program the switching
VOUT (Bank 2): Power Output Pins. Apply the output filter frequency of the LTM8023 by connecting a resistor from
capacitor and the output load between these pins and this pin to ground. The Applications Information section of
GND pins. the data sheet includes a table to determine the resistance
value based on the desired switching frequency. Minimize
AUX (Pin F5): Low Current Voltage Source for BIAS. The
capacitance at this pin.
VAUX pin is internally connected to VOUT and is placed
adjacent to the BIAS pin to ease printed circuit board SHARE (Pin F7): Tie this to the SHARE pin of another
routing. Although this pin is internally connected to VOUT, LTM8023 when paralleling the outputs. Otherwise, do not
do NOT connect this pin to the load. If this pin is not tied connect (leave floating).
to BIAS, leave it floating. SYNC (Pin G6): This is the external clock synchronization
BIAS (Pin G5): The BIAS pin connects to the internal power input. Ground this pin for low ripple Burst Mode® operation
bus. Connect to a power source greater than 2.8V. If the at low output loads. Tie to a stable voltage source greater
output is greater than 2.8V, connect this pin there. If the than 0.7V to disable Burst Mode operation. Do not leave
output voltage is less, connect this to a voltage source this pin floating. Tie to a clock source for synchronization.
between 2.8V and 16V. Also, make sure that BIAS + VIN Clock edges should have rise and fall times faster than 1µs.
is less than 56V. See synchronizing section in Applications Information.
RUN/SS (Pin H5): Tie RUN/SS pin to ground to shut down PGOOD (Pin H6): The PGOOD pin is the open-collector
the LTM8023. Tie to 2.5V or more for normal operation. output of an internal comparator. PG remains low until
If the shutdown feature is not used, tie this pin to the VIN the ADJ pin is within 10% of the final regulation voltage.
pin. RUN/SS also provides a soft-start function; see the PG output is valid when VIN is above 3.6V and RUN/SS is
Applications Information section. high. If this function is not used, leave this pin floating.
GND (Bank 3): Tie these GND pins to a local ground plane ADJ (Pin H7): The LTM8023 regulates its ADJ pin to 0.79V.
below the LTM8023 and the circuit components. In most Connect the adjust resistor from this pin to ground. The
applications, the bulk of the heat flow out of the LTM8023 value of RADJ is given by the equation RADJ = 394.21/
is through these pads, so the printed circuit design has a (VOUT – 0.79), where RADJ is in kΩ.

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LTM8023
BLOCK DIAGRAM

VIN 4.7µH VOUT

0.1µF 4.7pF 499k 10µF AUX

BIAS

SHARE
CURRENT MODE PGOOD
CONTROLLER
RUN/SS

SYNC

GND RT ADJ
8023 BD

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 LTM8023
OPERATION
The LTM8023 is a standalone nonisolated step-down voltage higher than 2.8V, bias power will be drawn from
switching DC/DC power supply. It can deliver up to 2A of the external source (typically the regulated output volt-
DC output current with only bulk external input and output age). This improves efficiency. The RUN/SS pin is used
capacitors. This module provides a precisely regulated to place the LTM8023 in shutdown, disconnecting the
output voltage programmable via one external resistor output and reducing the input current to less than 1µA.
from 0.8VDC to 10VDC. The input voltage range is 3.6V to To further optimize efficiency, the LTM8023 automatically
36V. Given that the LTM8023 is a step-down converter, switches to Burst Mode operation in light load situations.
make sure that the input voltage is high enough to support Between bursts, all circuitry associated with controlling
the desired output voltage and load current. A simplified the output switch is shut down reducing the input supply
Block Diagram is given on the previous page. current to 50µA in a typical application. The oscillator
The LTM8023 contains a current mode controller, power reduces the LTM8023’s operating frequency when the
switching element, power inductor, power Schottky diode voltage at the ADJ pin is low. This frequency foldback helps
and a modest amount of input and output capacitance. to control the output current during start-up and overload.
The LTM8023 is a fixed frequency PWM regulator. The The LTM8023 contains a power good comparator which
switching frequency is set by simply connecting the trips when the ADJ pin is at 92% of its regulated value.
appropriate resistor value from the RT pin to GND. The PGOOD output is an open-collector transistor that is
An internal regulator provides power to the control cir- off when the output is in regulation, allowing an external
cuitry. The bias regulator normally draws power from the resistor to pull the PGOOD pin high. Power good is valid
VIN pin, but if the BIAS pin is connected to an external when the LTM8023 is enabled and VIN is above 3.6V.

APPLICATIONS INFORMATION
For most applications, the design process is straight indicated in Table 1 is not recommended, and may result
forward, summarized as follows: in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
1. Look at Table 1 and find the row that has the desired
input range and output voltage. it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
2. Apply the recommended CIN, COUT, RADJ and RT values. load and environmental conditions.
3. Connect BIAS as indicated. Ceramic capacitors are small, robust and have very low
While these component combinations have been tested ESR. However, not all ceramic capacitors are suitable.
for proper operation, it is incumbent upon the user to X5R and X7R types are stable over temperature and ap-
verify proper operation over the intended system’s line, plied voltage and give dependable service. Other types,
load and environmental conditions. including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application cir-
Capacitor Selection Considerations cuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
The CIN and COUT capacitor values in Table 1 are the
than expected.
minimum recommended values for the associated oper-
ating conditions. Applying capacitor values below those

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LTM8023
APPLICATIONS INFORMATION
Table 1. Recommended Component Values and Configuration (TA = 25°C)
VIN VOUT CIN COUT RADJ BIAS fOPTIMAL (kHz) RT(OPTIMAL) fMAX (kHz) RT(MIN)
3.6V to 36V 0.82V 10µF 200µF 1206 13M ≥2.8V, <16V 250 150k 250 150k
3.6V to 36V 1.00V 10µF 147µF 1206 1.87M ≥2.8V, <16V 300 124k 300 124k
3.6V to 36V 1.20V 10µF 100µF 1206 953k ≥2.8V, <16V 350 105k 350 105k
3.6V to 36V 1.50V 10µF 100µF 1206 549k ≥2.8V, <16V 400 88.7k 400 88.7k
3.6V to 36V 1.80V 4.7µF 100µF 1206 383k ≥2.8V, <16V 450 79k 450 79k
3.6V to 36V 2.00V 2.2µF 68µF 1206 324k ≥2.8V, <16V 450 79k 500 69.8k
3.6V to 36V 2.20V 2.2µF 47µF 1206 274k ≥2.8V, <16V 500 69.8k 550 61.9k
4.1V to 36V 2.50V 2.2µF 47µF 1206 226k ≥2.8V, <16V 550 61.9k 615 54.9k
5.5V to 36V 3.30V 2.2µF 22µF 1206 154k AUX 650 49.9k 750 42.2k
7.5V to 36V 5.00V 2.2µF 10µF 0805 93.1k AUX 650 49.9k 890 34.8k
3.6V to 15V 0.82V 10µF 200µF 1206 13M VIN 350 105k 650 49.9k
3.6V to 15V 1.00V 10µF 147µF 1206 1.87M VIN 400 88.7k 725 43.2k
3.6V to 15V 1.20V 10µF 100µF 1206 953k VIN 450 79k 800 39.2k
3.6V to 15V 1.50V 10µF 100µF 1206 549k VIN 450 79k 1000 29.4k
3.6V to 15V 1.80V 4.7µF 100µF 1206 383k VIN 450 79k 1100 26.7k
3.6V to 15V 2.00V 2.2µF 68µF 1206 324k VIN 450 79k 1200 23.7k
3.6V to 15V 2.20V 2.2µF 47µF 1206 274k VIN 500 69.8k 1300 21.0k
3.6V to 15V 2.50V 2.2µF 47µF 1206 226k VIN 550 61.9k 1450 18.2k
5.5V to 15V 3.30V 2.2µF 22µF 1206 154k AUX 650 49.9k 1400 19.6k
7.5V to 15V 5.00V 2.2µF 10µF 0805 93.1k AUX 650 49.9k 1200 23.7k
9V to 24V 0.82V 10µF 200µF 1206 13M ≥2.8V, <16V 250 150k 250 150k
9V to 24V 1.00V 10µF 147µF 1206 1.87M ≥2.8V, <16V 300 124k 450 79k
9V to 24V 1.20V 2.2µF 100µF 1206 953k ≥2.8V, <16V 450 79k 500 69.8k
9V to 24V 1.50V 2.2µF 100µF 1206 549k ≥2.8V, <16V 450 79k 615 54.9k
9V to 24V 1.80V 2.2µF 100µF 1206 383k ≥2.8V, <16V 450 79k 700 44.2k
9V to 24V 2.00V 2.2µF 68µF 1206 324k ≥2.8V, <16V 450 79k 750 42.2k
9V to 24V 2.20V 2.2µF 47µF 1206 274k ≥2.8V, <16V 500 69.8k 800 39.2k
9V to 24V 2.50V 2.2µF 47µF 1206 226k ≥2.8V, <16V 550 61.9k 890 34.8k
9V to 24V 3.30V 2.2µF 22µF 1206 154k AUX 650 49.9k 1150 25.5k
9V to 24V 5.00V 2.2µF 10µF 0805 93.1k AUX 650 49.9k 1000 29.4k
14.5V to 24V 8.00V 2.2µF 10µF 0805 53.6k AUX 650 49.9k 800 39.2k
18V to 36V 0.82V 10µF 200µF 1206 13M ≥2.8V, <16V 250 150k 250 150k
18V to 36V 1.00V 10µF 147µF 1206 1.87M ≥2.8V, <16V 300 124k 300 124k
18V to 36V 1.20V 2.2µF 100µF 1206 953k ≥2.8V, <16V 350 105k 350 105k
18V to 36V 1.50V 2.2µF 100µF 1206 549k ≥2.8V, <16V 400 88.7k 400 88.7k
18V to 36V 1.80V 2.2µF 100µF 1206 383k ≥2.8V, <16V 450 79k 450 79k
18V to 36V 2.00V 2.2µF 68µF 1206 324k ≥2.8V, <16V 450 79k 500 69.8k
18V to 36V 2.20V 2.2µF 47µF 1206 274k ≥2.8V, <16V 450 79k 550 61.9k
18V to 36V 2.50V 2.2µF 47µF 1206 226k ≥2.8V, <16V 500 69.8k 615 54.9k
18V to 36V 3.30V 2.2µF 22µF 1206 154k AUX 650 49.9k 750 42.2k
18V to 36V 5.00V 2.2µF 10µF 0805 93.1k AUX 800 39.2k 890 34.8k
18V to 36V 8.00V 2.2µF 10µF 0805 53.6k AUX 650 49.9k 800 39.2k
20V to 36V 10.00V 2.2µF 10µF 0805 42.2k AUX 615 54.9k 750 42.2k
4.75V to 32V –3.30V 2.2µF 22µF 1206 154k AUX 550 61.9k 800 39.2k
7V to 31V –5.00V 2.2µF 10µF 0805 93.1k AUX 800 39.2k 1100 26.7k
15V to 28V –8.00V 2.2µF 10µF 0805 53.6k AUX 800 39.2k 1600 15.8k
A bulk input capacitor is required.
8023fj

10 For more information www.linear.com/LTM8023

 LTM8023
APPLICATIONS INFORMATION
Ceramic capacitors are also piezoelectric. In Burst Mode Operating Frequency Trade-Offs
operation, the LTM8023’s switching frequency depends It is recommended that the user apply the optimal RT
on the load current, and can excite a ceramic capacitor value given in Table 1 for the input and output operating
at audio frequencies, generating audible noise. Since the condition. System level or other considerations, however,
LTM8023 operates at a lower current limit during Burst may necessitate another operating frequency. While the
Mode operation, the noise is typically very quiet to a LTM8023 is flexible enough to accommodate a wide range
casual ear. of operating frequencies, a haphazardly chosen one may
If this audible noise is unacceptable, use a high performance result in undesirable operation under certain operating or
electrolytic capacitor at the output. The input capacitor can fault conditions. A frequency that is too high can reduce
be a parallel combination of a 2.2µF ceramic capacitor and efficiency, generate excessive heat or even damage the
a low cost electrolytic capacitor. LTM8023 if the output is overloaded or short circuited. A
frequency that is too low can result in a final design that has
A final precaution regarding ceramic capacitors concerns
too much output ripple or too large of an output capacitor.
the maximum input voltage rating of the LTM8023. A
ceramic input capacitor combined with trace or cable The maximum frequency (and attendant RT value) at which
inductance forms a high Q (under damped) tank circuit. the LTM8023 should be allowed to switch is given in Table 1
If the LTM8023 circuit is plugged into a live supply, the in the f(MAX) column, while the recommended frequency
input voltage can ring to twice its nominal value, possi- (and RT value) for optimal efficiency over the given input
bly exceeding the device’s rating. This situation is easily condition is given in the fOPTIMAL column.
avoided; see the Hot-Plugging Safely section. There are additional conditions that must be satisfied if
the synchronization function is used. Please refer to the
Frequency Selection
Synchronization section for details.
The LTM8023 uses a constant frequency PWM architecture
that can be programmed to switch from 200kHz to 2.4MHz BIAS Pin Considerations
by using a resistor tied from the RT pin to ground. Table 2 The BIAS pin is used to provide drive power for the internal
provides a list of RT resistor values and their resultant power switching stage and operate internal circuitry. For
frequencies. proper operation, it must be powered by at least 2.8V. If
Table 2. Switching Frequency vs RT Value the output voltage is programmed to be 2.8V or higher,
SWITCHING FREQUENCY (MHz) RT VALUE (kΩ) simply tie BIAS to VOUT. If VOUT is less than 2.8V, BIAS
0.2 187 can be tied to VIN or some other voltage source. In all
0.3 124 cases, ensure that the maximum voltage at the BIAS pin
0.4 88.7
0.5 69.8 is both less than 16V and the sum of VIN and BIAS is less
0.6 56.2 than 56V. If BIAS power is applied from a remote or noisy
0.7 46.4 voltage source, it may be necessary to apply a decoupling
0.8 39.2
0.9 34.6 capacitor locally to the LTM8023.
1.0 29.4
1.2 23.7
1.4 19.6
1.6 15.8
1.8 13.3
2.0 11.5
2.2 9.76
2.4 8.66

8023fj

For more information www.linear.com/LTM8023 11

LTM8023
APPLICATIONS INFORMATION
Load Sharing Minimum Input Voltage
Two or more LTM8023’s may be paralleled to produce The LTM8023 is a step-down converter, so a minimum
higher currents. To do this, tie the VIN, ADJ, VOUT and amount of headroom is required to keep the output in
SHARE pins of all the paralleled LTM8023’s together. To regulation. In addition, the input voltage required to turn
ensure that paralleled modules start up together, the RUN/ on is higher than that required to run, and depends upon
SS pins may be tied together, as well. If the RUN/SS pins whether the RUN/SS is used. As shown in Figure 2, it
are not tied together, make sure that the same valued soft- takes only about 3.5VIN for the LTM8023 to run a 3.3V
start capacitors are used for each module. An example output at light load. If RUN/SS is tied to VIN, a 5.5V input
of two LTM8023 modules configured for load sharing is voltage is required to start. If VIN is allowed to settle in
given in the Typical Applications section. the operating region first then the RUN/SS pin is enabled,
For current sharing applications using multiple LTM8023s, the minimum input voltage to start at light load is lower,
the ADJ pins for all regulators may be combined using about 4.2V. A similar curve for 5VOUT operation is also
one resistor to ground as determined by: provided in Figure 2.
6.0
394.21
R ADJ = N 5.5

VOUT – 0.79 TO START

INPUT VOLTAGE (V) 5.0

where N is the number of paralleled modules and RADJ 4.5

is in kΩ. RUN/SS ENABLED
4.0

Burst Mode Operation 3.5 VOUT = 3.3V

TO RUN
TA = 25°C
To enhance efficiency at light loads, the LTM8023 auto- 3.0
f = 650kHz
matically switches to Burst Mode operation which keeps 0 500 1000 1500 2000
the output capacitor charged to the proper voltage while LOAD CURRENT (mA)

minimizing the input quiescent current. During Burst Mode 7.5

operation, the LTM8023 delivers single cycle bursts of
current to the output capacitor followed by sleep periods 7.0

where the output power is delivered to the load by the output

INPUT VOLTAGE (V)

capacitor. In addition, VIN and BIAS quiescent currents are 6.5 TO START

reduced to typically 25µA and 50µA respectively during

6.0
the sleep time. As the load current decreases towards a no RUN/SS ENABLED

load condition, the percentage of time that the LTM8023 5.5

operates in sleep mode increases and the average input VOUT = 5V
TA = 25°C
current is greatly reduced, resulting in higher efficiency. 5.0
TO RUN f = 650kHz
0 500 1000 1500 2000
Burst Mode operation is enabled by tying SYNC to GND. LOAD CURRENT (mA)
To disable Burst Mode operation, tie SYNC to a stable 8023 F02

voltage above 0.7V or synchronize to an external clock. Figure 2. The LTM8023 Needs More Voltage to Start Than to Run
Do not leave the SYNC pin floating.

8023fj

12 For more information www.linear.com/LTM8023

 LTM8023
APPLICATIONS INFORMATION
Soft-Start Shorted Input Protection
The RUN/SS pin can be used to soft-start the LTM8023, Care needs to be taken in systems where the output will be
reducing the maximum input current during start-up. held high when the input to the LTM8023 is absent. This
The RUN/SS pin is driven through an external RC filter may occur in battery charging applications or in battery
to create a voltage ramp at this pin. Figure 3 shows the backup systems where a battery or some other supply is
start-up and shutdown waveforms with the soft-start diode OR-ed with the LTM8023’s output. If the VIN pin is
circuit. By choosing an appropriate RC time constant, allowed to float and the RUN/SS pin is held high (either
the peak start-up current can be reduced to the current by a logic signal or because it is tied to VIN), then the
that is required to regulate the output, with no overshoot. LTM8023’s internal circuitry will pull its quiescent cur-
Choose the value of the resistor so that it can supply at rent through its internal power switch. This is fine if your
least 20µA when the RUN/SS pin reaches 2.5V. system can tolerate a few milliamps in this state. If you
ground the RUN/SS pin, the internal power switch cur-
rent will drop to essentially zero. However, if the VIN pin
is grounded while the output is held high, then parasitic
IL diodes inside the LTM8023 can pull large currents from
RUN 1A/DIV the output through the VIN pin. Figure 4 shows a circuit
15k
that will run only when the input voltage is present and
RUN/SS VRUN/SS that protects against a shorted or reversed input.
2V/DIV
0.22µF GND

VOUT
2V/DIV VIN VIN VOUT VOUT

RUN/SS AUX
2ms/DIV 8023 F03
BIAS
LTM8023

Figure 3. To Soft-Start the LTM8023, Add a

Resistor and Capacitor to the RUN/SS Pin ADJ
RT SYNC GND
8023 F04

Synchronization
The internal oscillator of the LTM8023 can be synchronized
by applying an external 250kHz to 2MHz clock to the SYNC Figure 4. The Input Diode Prevents a Shorted Input from
pin. Do not leave this pin floating. The resistor tied from the Discharging a Backup Battery Tied to the Output. It Also Protects
RT pin to ground should be chosen such that the LTM8023 the Circuit from a Reversed Input. The LTM8023 Runs Only
When the Input is Present.
oscillates 20% lower than the intended synchronization
frequency (see the Frequency Selection section).
The LTM8023 will not enter Burst Mode operation while
synchronized to an external clock, but will instead skip
pulses to maintain regulation.

8023fj

For more information www.linear.com/LTM8023 13

LTM8023
APPLICATIONS INFORMATION
PCB Layout 4. Place the CIN and COUT capacitors such that their
ground current flow directly adjacent or underneath
Most of the headaches associated with PCB layout have
the LTM8023.
been alleviated or even eliminated by the high level of
integration of the LTM8023. The LTM8023 is neverthe- 5. Connect all of the GND connections to as large a copper
less a switching power supply, and care must be taken to pour or plane area as possible on the top layer. Avoid
minimize EMI and ensure proper operation. Even with the breaking the ground connection between the external
high level of integration, you may fail to achieve specified components and the LTM8023.
operation with a haphazard or poor layout. See Figure 5 6. Use vias to connect the GND copper area to the boards
for a suggested layout. internal ground plane. Liberally distribute these GND vias
to provide both a good ground connection and thermal
GND path to the internal planes of the printed circuit board.
RT RADJ
SHARE
Hot-Plugging Safely
SYNC
PGOOD The small size, robustness and low impedance of ceramic
RUN/SS
capacitors make them an attractive option for the input
AUX BIAS bypass capacitor of LTM8023. However, these capacitors
can cause problems if the LTM8023 is plugged into a live
supply (see Linear Technology Application Note 88 for a
complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt-
VOUT
COUT CIN
VIN
age at the VIN pin of the LTM8023 can ring to twice the
8023 F05
nominal input voltage, possibly exceeding the LTM8023’s
rating and damaging the part. If the input supply is poorly
Figure 5. Layout Showing Suggested External Components, GND
Plane and Thermal Vias controlled or the user will be plugging the LTM8023 into
an energized supply, the input network should be designed
to prevent this overshoot. Figure 6 shows the waveforms
Ensure that the grounding and heatsinking are acceptable. that result when an LTM8023 circuit is connected to a 24V
A few rules to keep in mind are: supply through six feet of 24-gauge twisted pair. The first
1. Place the RADJ and RT resistors as close as possible to plot is the response with a 2.2µF ceramic capacitor at the
their respective pins. input. The input voltage rings as high as 35V and the input
current peaks at 20A. One method of damping the tank
2. Place the CIN capacitor as close as possible to the VIN
circuit is to add another capacitor with a series resistor to
and GND connection of the LTM8023.
the circuit. In Figure 6c an aluminum electrolytic capacitor
3. Place the COUT capacitor as close as possible to the has been added. This capacitor’s high equivalent series
VOUT and GND connection of the LTM8023. resistance damps the circuit and eliminates the voltage
overshoot. The extra capacitor improves low frequency

8023fj

14 For more information www.linear.com/LTM8023

 LTM8023
APPLICATIONS INFORMATION
CLOSING SWITCH DANGER
SIMULATES HOT PLUG VIN
IIN VIN 20V/DIV
LTM8023 RINGING VIN MAY EXCEED
ABSOLUTE MAXIMUM RATING
+
4.7µF

IIN
LOW STRAY
10A/DIV
IMPEDANCE INDUCTANCE
ENERGIZED DUE TO 6 FEET
24V SUPPLY (2 METERS) OF
20µs/DIV
TWISTED PAIR
(6a)

0.7Ω VIN
LTM8023 20V/DIV
+
0.1µF 4.7µF

IIN
10A/DIV

(6b) 20µs/DIV

VIN
LTM8023 20V/DIV
+ 22µF +
35V 4.7µF
AI.EI.
IIN
10A/DIV

(6c) 20µs/DIV
8023 F06

Figure 6. A Well Chosen Input Network Prevents Input Voltage Overshoot and Ensures Reliable
Operation When the LTM8023 is Connected to a Live Supply

ripple filtering and can slightly improve the efficiency of the A 0.1µF capacitor improves high frequency filtering. This
circuit, though it is likely to be the largest component in the solution is smaller and less expensive than the electrolytic
circuit. An alternative solution is shown in Figure 6b. A 0.7Ω capacitor. For high input voltages its impact on efficiency
resistor is added in series with the input to eliminate the is minor, reducing efficiency less than one-half percent
voltage overshoot (it also reduces the peak input current). for a 5V output at full load operating from 24V.

8023fj

For more information www.linear.com/LTM8023 15

LTM8023
APPLICATIONS INFORMATION
Thermal Considerations “still air” although natural convection causes the air to
move. This value is determined with the part mounted to
The LTM8023 output current may need to be derated if
a JESD 51-9 defined test board, which does not reflect
it is required to operate in a high ambient temperature or
an actual application or viable operating condition.
deliver a large amount of continuous power. The amount
of current derating is dependent upon the input voltage, • θJCbottom is the junction-to-board thermal resistance
output power and ambient temperature. The temperature with all of the component power dissipation flowing
rise curves given in the Typical Performance Character- through the bottom of the package. In the typical
istics section can be used as a guide. These curves were µModule regulator, the bulk of the heat flows out the
generated by an LTM8023 mounted to a 33cm2 4-layer FR4 bottom of the package, but there is always heat flow out
printed circuit board. Boards of other sizes and layer count into the ambient environment. As a result, this thermal
can exhibit different thermal behavior, so it is incumbent resistance value may be useful for comparing packages
upon the user to verify proper operation over the intended but the test conditions don’t generally match the user’s
system’s line, load and environmental operating conditions. application.
The thermal resistance numbers listed in the Pin Con- • θJCtop is determined with nearly all of the component
figuration are based on modeling the µModule package power dissipation flowing through the top of the pack-
mounted on a test board specified per JESD51-9 “Test age. As the electrical connections of the typical µModule
Boards for Area Array Surface Mount Package Thermal regulator are on the bottom of the package, it is rare
Measurements.” The thermal coefficients provided in this for an application to operate such that most of the heat
page are based on JESD 51-12 “Guidelines for Reporting flows from the junction to the top of the part. As in the
and Using Electronic Package Thermal Information.” case of θJCbottom, this value may be useful for comparing
packages but the test conditions don’t generally match
For increased accuracy and fidelity to the actual application, the user’s application.
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration typically gives four • θJB is the junction-to-board thermal resistance where
thermal coefficients: almost all of the heat flows through the bottom of the
µModule regulator and into the board, and is really the
• θJA – Thermal resistance from junction to ambient. sum of the θJCbottom and the thermal resistance of the
• θJCbottom – Thermal resistance from junction to the bottom of the part through the solder joints and through
bottom of the product case. a portion of the board. The board temperature is mea-
sured a specified distance from the package, using a
• θJCtop – Thermal resistance from junction to top of
two sided, two layer board. This board is described in
the product case.
JESD 51-9.
• θJB – Thermal resistance from junction to the printed
The most appropriate way to use the coefficients is when
circuit board.
running a detailed thermal analysis, such as FEA, which
While the meaning of each of these coefficients may seem considers all of the thermal resistances simultaneously.
to be intuitive, JEDEC has defined each to avoid confu- None of them can be individually used to accurately pre-
sion and inconsistency. These definitions are given in dict the thermal performance of the product, so it would
JESD 51-12, and are quoted or paraphrased in the following: be inappropriate to attempt to use any one coefficient to
• θJA is the natural convection junction-to-ambient air correlate to the junction temperature versus load graphs
thermal resistance measured in a one cubic foot sealed given in the LTM8023 data sheet.
enclosure. This environment is sometimes referred to as

8023fj

16 For more information www.linear.com/LTM8023

 LTM8023
APPLICATIONS INFORMATION
A graphical representation of these thermal resistances pads into the printed circuit board. Consequently a poor
is given in Figure 7. printed circuit board design can cause excessive heating,
The blue resistances are contained within the µModule resulting in impaired performance or reliability. Please
regulator, and the green are outside. refer to the PCB Layout section for printed circuit board
design suggestions.
The die temperature of the LTM8023 must be lower than
the maximum rating of 125°C, so care should be taken Finally, be aware that at high ambient temperatures the
in the layout of the circuit to ensure good heat sinking internal Schottky diode will have significant leakage current
of the LTM8023. The bulk of the heat flow out of the increasing the quiescent current of the LTM8023.
LTM8023 is through the bottom of the module and the LGA

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT

RESISTANCE RESISTANCE

JUNCTION-TO-BOARD RESISTANCE
JUNCTION At

JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT

(BOTTOM) RESISTANCE RESISTANCE RESISTANCE

8023 F07
µMODULE REGULATOR

Figure 7

8023fj

For more information www.linear.com/LTM8023 17

LTM8023
TYPICAL APPLICATIONS
0.82V Step-Down Converter 1.8V Step-Down Converter
VOUT VOUT
VIN* VIN*
VIN VOUT 0.82V VIN VOUT 1.8V
3.6V TO 15V 3.6V TO 15V
2A 2A
10µF BIAS 200µF 4.7µF BIAS 100µF
RUN/SS RUN/SS
AUX AUX

LTM8023 LTM8023

SHARE PGOOD SHARE PGOOD

ADJ ADJ

RT GND SYNC RT GND SYNC

8023 TA02 8023 TA03

105k 13M 79k 383k

*RUNNING VOLTAGE RANGE. PLEASE *RUNNING VOLTAGE RANGE. PLEASE

REFER TO APPLICATIONS INFORMATION REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS FOR START-UP DETAILS

2.5V Step-Down Converter 5V Step-Down Converter

VIN* VOUT VOUT
VIN*
4.5V TO 36VDC VIN VOUT 2.5V VIN VOUT 5V
7.5V TO 36VDC
2A 2A
2.2µF 47µF 2.2µF AUX 10µF
RUN/SS RUN/SS BIAS
SHARE AUX

LTM8023 LTM8023

3.3V BIAS PGOOD SHARE PGOOD

ADJ ADJ

RT GND SYNC RT GND SYNC

8023 TA04 8023 TA05

61.9k 226k 49.9k 93.1k

*RUNNING VOLTAGE RANGE. PLEASE *RUNNING VOLTAGE RANGE. PLEASE

REFER TO APPLICATIONS INFORMATION REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS FOR START-UP DETAILS

VOUT
VIN*
VIN VOUT 3.3V
5.5V TO 36V
2A
AUX
RUN/SS BIAS

LTM8023
2.2µF 22µF
SHARE PGOOD

ADJ

RT GND SYNC
8023 TA07

49.9k 154k

*RUNNING VOLTAGE RANGE. PLEASE

REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS
8023fj

18 For more information www.linear.com/LTM8023

 LTM8023
TYPICAL APPLICATIONS
–5V Positive to Negative Converter –5V Positive to Negative Converter
Load Current vs Input Voltage
VIN* VIN VOUT
7V TO 31V 2500
AUX
RUN/SS BIAS
2000

LOAD CURRENT (mA)

LTM8023 1500

2.2µF SHARE PGOOD 10µF

1000
ADJ

RT GND SYNC 500

8023 TA06

39.2k 93.1k
0
–5V 0 10 20 30 40
*RUNNING VOLTAGE RANGE. PLEASE INPUT VOLTAGE (V)
REFER TO APPLICATIONS INFORMATION 8023 TA06b

FOR START-UP DETAILS

Two LTM8023’s in Parallel, 3.3V at 4A

VIN* VOUT
VIN VOUT 3.3V
6.5V TO 36V
4A
AUX

RUN/SS BIAS

LTM8023

SHARE PGOOD
2.2µF ADJ

RT SYNC GND

49.9k 76.8k

VIN VOUT
2.2k AUX 47µF
RUN/SS BIAS

LTM8023

SHARE PGOOD
2.2µF 0.22µF ADJ

RT SYNC GND
8023 TA08

49.9k

*RUNNING VOLTAGE RANGE. PLEASE

REFER TO APPLICATIONS INFORMATION
FOR START-UP DETAILS

8023fj

For more information www.linear.com/LTM8023 19

 LGA Package
50-Lead (11.25mm × 9.00mm × 2.82mm)
(Reference LTC DWG # 05-08-1804 Rev C)

20
aaa Z
8.89 SEE NOTES
11.25 BSC
X 2.72 – 2.92 7
BSC Y 0.605 – 0.665

7
LTM8023

0.605 – 0.665 5

MOLD
CAP SUBSTRATE 7.62
9.00
BSC BSC 4

0.27 – 0.37
2.45 – 2.55 3

Z
PAD 1
CORNER 2
DETAIL A

bbb Z
4 1.27
PACKAGE DESCRIPTION

BSC
1
aaa Z C(0.30)
H G F E D C B A PAD 1
PACKAGE TOP VIEW PADS
SEE NOTES
DETAIL A PACKAGE BOTTOM VIEW
3
PACKAGE SIDE VIEW

NOTES:

4.445
3.175
1.905
0.635
0.000
0.635
1.905
3.175
4.445
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
3.810 3 LAND DESIGNATION PER JESD MO-222, SPP-010 AND SPP-020
4 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
2.540 BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR A
MARKED FEATURE
1.270
5. PRIMARY DATUM -Z- IS SEATING PLANE
0.3175
0.000 6. THE TOTAL NUMBER OF PADS: 50 LTMXXXXXX
0.3175 µModule
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
!

For more information www.linear.com/LTM8023

1.270 AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY

2.540
SYMBOL TOLERANCE TRAY PIN 1
BEVEL
aaa 0.15 PACKAGE IN TRAY LOADING ORIENTATION
3.810 bbb 0.10 LGA 50 0113 REV C
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

0.9525
0.3175
0.635
SUGGESTED PCB LAYOUT
TOP VIEW

8023fj
 BGA Package
50-Lead (11.25mm × 9.00mm × 3.42mm)
(Reference LTC DWG # 05-08-1883 Rev A)

Z SEE NOTES
A DETAIL A
aaa Z 7
E Y G
X A1 A2 SEE NOTES
PIN 1
3
ccc Z
A

PIN “A1” B
CORNER
4 b C
MOLD b1
CAP
D
D F
SUBSTRATE
E
H1
H2
F

Z
e

DETAIL B G

// bbb Z
PACKAGE DESCRIPTION

H
aaa Z Øb (50 PLACES)
7 6 5 4 3 2 1
PACKAGE TOP VIEW ddd M Z X Y
eee M Z PACKAGE BOTTOM VIEW
DETAIL B
PACKAGE SIDE VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
3 BALL DESIGNATION PER JESD MS-028 AND JEP95

0.000
DETAIL A 4 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,

3.810
2.540
1.270
0.3175
0.3175
1.270
2.540
3.810
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
DIMENSIONS MARKED FEATURE
0.630 ±0.025 Ø 50x 4.445
SYMBOL MIN NOM MAX NOTES
3.175
5. PRIMARY DATUM -Z- IS SEATING PLANE
A 3.22 3.42 3.62
A1 0.50 0.60 0.70 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu
1.905
OR Sn Pb EUTECTIC
A2 2.72 2.82 2.92
0.635 7 PACKAGE ROW AND COLUMN LABELING MAY VARY

For more information www.linear.com/LTM8023

b 0.71 0.78 0.85
0.000 ! AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
0.635 b1 0.60 0.63 0.66 LAYOUT CAREFULLY
D 11.25
1.905
E 9.0
3.175 e 1.27
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

4.13 F 8.89
4.445
4.76 G 7.62
H1 0.27 0.32
0.37
SUGGESTED PCB LAYOUT LTMXXXXXX
H2 2.45 2.50
2.55
TOP VIEW µModule
aaa 0.15
COMPONENT
bbb 0.10 PIN “A1”
ccc 0.20
ddd 0.30
TRAY PIN 1
eee 0.15 BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
TOTAL NUMBER OF BALLS: 50
BGA 50 1212 REV A

21
8023fj
LTM8023
LTM8023
PACKAGE DESCRIPTION
Table 3. Pin Assignment (Sorted by Pin Number)
PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION
A1 VOUT D5 GND
A2 VOUT D6 GND
A3 VOUT D7 GND
A4 VOUT E1 GND
A5 GND E2 GND
A6 GND E3 GND
A7 GND E4 GND
B1 VOUT E5 GND
B2 VOUT E6 GND
B3 VOUT E7 GND
B4 VOUT F5 AUX
B5 GND F6 GND
B6 GND F7 SHARE
B7 GND G1 VIN
C1 VOUT G2 VIN
C2 VOUT G3 VIN
C3 VOUT G5 BIAS
C4 VOUT G6 SYNC
C5 GND G7 RT
C6 GND H1 VIN
C7 GND H2 VIN
D1 GND H3 VIN
D2 GND H5 RUN/SS
D3 GND H6 PGOOD
D4 GND H7 ADJ

8023fj

22 For more information www.linear.com/LTM8023

 LTM8023
REVISION HISTORY (Revision history begins at Rev F)

REV DATE DESCRIPTION PAGE NUMBER

F 8/10 Added Note 5 3
G 8/11 Added BGA package. Changes reflected throughout the data sheet. 1 to 24
H 8/13 Changed output capacitor from 2.2µF to 22µF 1
I 2/14 Added SnPb BGA package option 1, 2
J 8/15 Updated thermal impedance values 2

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
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tion that the interconnection information
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circuits as described herein will not infringe on existing patent rights. 23
LTM8023
PACKAGE PHOTOGRAPHS
LGA

BGA

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LTM8025 36V, 3A Step-Down µModule Regulator 0.8V ≤ VOUT ≤ 24V, Synchronizable, 9mm × 15mm × 4.3mm LGA
LTM8027 60V, 4A Step-Down µModule Regulator 2.5V ≤ VOUT ≤ 24V, Synchronizable, 15mm × 15mm × 4.3mm LGA
LTM4612 EN55022B Certified 36V, 5A Step-Down 3.3V ≤ VOUT ≤ 15V, Synchronizable, 15mm × 15mm × 2.8mm LGA
µModule Regulator
LTM4613 EN55022B Certified 36V, 8A Step-Down 3.3V ≤ VOUT ≤ 15V, Synchronizable, 15mm × 15mm × 4.3mm LGA
µModule Regulator
LTM8061 32V, 2A Li-Ion/Li-Polymer µModule Battery C/10 or Timer Termination, Auto-Recharge, Programmable Charge Current,
Charger 9mm × 15mm × 4.3mm LGA

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24 Linear Technology Corporation

LT 0815 REV J • PRINTED IN USA

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(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM8023  LINEAR TECHNOLOGY CORPORATION 2007