Quad 12-Bit Serial Voltage Output DAC

Data Sheet DAC8420

FEATURES FUNCTIONAL BLOCK DIAGRAM
VREFHI VDD
Guaranteed monotonic over temperature 5 1
Excellent matching between DACs DAC8420
Unipolar or bipolar operation SDI 10
REG
DAC A 7 VOUTA
Buffered voltage outputs A
12
High speed serial digital interface
Reset-to-zero scale or midscale CS 12
Wide supply range, +5 V only to ±15 V CLK 11 REG
SHIFT DAC B 6 VOUTB
B
REGISTER
Low power consumption (35 mW maximum)
Available in 16-Lead PDIP, SOIC, and CERDIP packages
NC 13
APPLICATIONS 4
REG
C
DAC C 3 VOUTC

Software controlled calibration

Servo controls LD 14 DECODE
Process control and automation REG
DAC D 2 VOUTD
2 D
ATE

00275-001
9 16 15 4 8

GND CLSEL CLR VREFLO VSS

Figure 1.

GENERAL DESCRIPTION
The DAC8420 is a quad, 12-bit voltage-output DAC with serial The user-programmable reset control CLR forces all four DAC
digital interface in a 16-lead package. Utilizing BiCMOS tech- outputs to either zero scale or midscale, asynchronously overriding
nology, this monolithic device features unusually high circuit the current DAC register values. The output voltage range,
density and low power consumption. The simple, easy-to-use determined by the inputs VREFHI and VREFLO, is set by the
serial digital input and fully buffered analog voltage outputs user for positive or negative unipolar or bipolar signal swings
require no external components to achieve a specified per- within the supplies, allowing considerable design flexibility.
formance.
The DAC8420 is available in 16-lead PDIP, SOIC, and CERDIP
The 3-wire serial digital input is easily interfaced to micro- packages. Operation is specified with supplies ranging from +5 V
processors running at 10 MHz with minimal additional only to ±15 V, with references of +2.5 V to ±10 V, respectively.
circuitry. Each DAC is addressed individually by a 16-bit serial Power dissipation when operating from ±15 V supplies is less than
word consisting of a 12-bit data word and an address header. 255 mW (maximum) and only 35 mW (maximum) with a +5 V
supply.

Rev. C Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
DAC8420 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Correct Operation of CS and CLK........................................... 13
Applications ....................................................................................... 1 Using CLR and CLSEL............................................................... 13
Functional Block Diagram .............................................................. 1 Programming the Analog Outputs .......................................... 13
General Description ......................................................................... 1 VREFHI Input Requirements ................................................... 15
Revision History ............................................................................... 2 Power-Up Sequence ................................................................... 15
Specifications..................................................................................... 3 Applications..................................................................................... 16
Electrical Characteristics ............................................................. 3 Power Supply Bypassing and Grounding ................................ 16
Absolute Maximum Ratings ............................................................ 6 Analog Outputs .......................................................................... 16
Thermal Resistance ...................................................................... 6 Reference Configuration ........................................................... 17
ESD Caution .................................................................................. 6 Isolated Digital Interface ........................................................... 18
Pin Configurations and Function Descriptions ........................... 8 Dual Window Comparator ....................................................... 19
Typical Performance Characteristics ............................................. 9 MC68HC11 Microcontroller Interfacing ................................ 19
Theory of Operation ...................................................................... 13 DAC8420 to M68HC11 Interface Assembly Program .......... 20
Introduction ................................................................................ 13 Outline Dimensions ....................................................................... 21
Digital Interface Operation ....................................................... 13 Ordering Guide .......................................................................... 22

REVISION HISTORY
9/2016—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22

5/2007—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Endnote 3 ...................................................................... 4
Changes to Table 3 ............................................................................ 6
Changes to Table 4 ............................................................................ 2
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 23

9/2003—Rev. 0 to Rev. A
Changes to General Description .................................................... 1
Deleted Wafer Test Limits table ...................................................... 4
Deleted Dice Characteristics ........................................................... 4
Updated Ordering Guide ................................................................. 4
Added Power-Up Sequence section ............................................. 12
Updated Outline Dimensions ....................................................... 17

Rev. C | Page 2 of 23
Data Sheet DAC8420

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 1
At VDD = +5.0 V ± 5%, VSS = 0 V, VVREFHI = +2.5 V, VVREFLD = 0 V, and VSS = −5.0 V ± 5%, VVREFLO = −2.5 V, −40°C ≤ TA ≤ +85°C unless
otherwise noted. 2

Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
STATIC ACCURACY
Integral Linearity E Grade INL ±¼ ±1 LSB
Integral Linearity E Grade INL VSS = 0 V 3 ±½ ±3 LSB
Integral Linearity F Grade INL ±¾ ±2 LSB
Integral Linearity F Grade INL VSS = 0 V3 ±1 ±4 LSB
Differential Linearity DNL Monotonic over temperature ±¼ ±1 LSB
Zero-Scale Error ZSE RL = 2 kΩ, VSS = −5 V ±4 LSB
Full-Scale Error FSE RL = 2 kΩ, VSS = −5 V ±4 LSB
Zero-Scale Error ZSE RL = 2 kΩ, VSS = 0 V3 ±8 LSB
Full-Scale Error FSE RL = 2 kΩ, VSS = 0 V3 ±8 LSB
Zero-Scale Temperature Coefficient TCZSE RL = 2 kΩ, VSS = −5 V 4 ±10 ppm/°C
Full-Scale Temperature Coefficient TCFSE RL = 2 kΩ, VSS = −5 V4 ±10 ppm/°C
MATCHING PERFORMANCE
Linearity Matching ±1 LSB
REFERENCE
Positive Reference Input Range 5 VVREFHI VVREFLO + 2.5 VDD − 2.5 V
Negative Reference Input Range5 VVREFLO VSS VVREFHI − 2.5 V
Negative Reference Input Range VVREFLO VSS = 0 V5 0 VVREFHI − 2.5 V
Reference High Input Current IVREFHI Code 0x000, Code 0x555 −0.75 ±0.25 +0.75 mA
Reference Low Input Current IVREFLO Code 0x000, Code 0x555, VSS = −5 V −1.0 −0.6 mA
AMPLIFIER CHARACTERISTICS
Output Current IOUT VSS = −5 V −1.25 +1.25 mA
Settling Time tS To 0.01% 6 8 μs
Slew Rate SR 10% to 90%6 1.5 V/μs
LOGIC CHARACTERISTICS
Logic Input High Voltage VINH 2.4 V
Logic Input Low Voltage VINL 0.8 V
Logic Input Current IIN 10 μA
Input Capacitance4 CIN 13 pF
LOGIC TIMING CHARACTERISTICS4, 7
Data Setup Time tDS 25 ns
Data Hold tDH 55 ns
Clock Pulse Width High tCH 90 ns
Clock Pulse Width Low tCL 120 ns
Select Time tCSS 90 ns
Deselect Delay tCSH 5 ns
Load Disable Time tLD1 130 ns
Load Delay tLD2 35 ns
Load Pulse Width tLDW 80 ns
Clear Pulse Width tCLRW 150 ns

Rev. C | Page 3 of 23
DAC8420 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSRR 0.002 0.01 %/%
Positive Supply Current IDD 4 7 mA
Negative Supply Current ISS −6 −3 mA
Power Dissipation PDISS VSS = 0 V 20 35 mW
1
Typical values indicate performance measured at 25°C.
2
All supplies can be varied ±5% and operation is guaranteed. Device is tested with VDD = 4.75 V.
3
For single-supply operation (VVREFLO = 0 V, VSS = 0 V), due to internal offset errors INL and DNL are measured beginning at Code 0x005.
4
Guaranteed, but not tested.
5
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
6
VOUT swing between +2.5 V and −2.5 V with VDD = 5.0 V.
7
All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

Rev. C | Page 4 of 23
Data Sheet DAC8420
At VDD = +15.0 V ± 5%, VSS = −15.0 V ± 5%, VVREFHI = +10.0 V, VVREFLO = −10.0 V, −40°C ≤ TA ≤ +85°C unless otherwise noted. 1, 2

Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
STATIC ACCURACY
Integral Linearity E Grade INL ±¼ ±½ LSB
Integral Linearity F Grade INL ±½ ±1 LSB
Differential Linearity DNL Monotonic over temperature ±¼ ±1 LSB
Zero-Scale Error ZSE RL = 2 kΩ ±2 LSB
Full-Scale Error FSE RL = 2 kΩ ±2 LSB
Zero-Scale Temperature Coefficient TCZSE RL = 2 kΩ 3 ±4 ppm/°C
Full-Scale Temperature Coefficient TCFSE RL = 2 kΩ3 ±4 ppm/°C
MATCHING PERFORMANCE
Linearity Matching ±1 LSB
REFERENCE
Positive Reference Input Range 4 VVREFHI VVREFLO + 2.5 VDD − 2.5 V
Negative Reference Input Range4 VVREFLO −10 VVREFHI − 2.5 V
Reference High Input Current IVREFHI Code 0x000, Code 0x555 −2.0 ±1.0 +2.0 mA
Reference Low Input Current IVREFLO Code 0x000, Code 0x555 −3.5 −2.0 mA
AMPLIFIER CHARACTERISTICS
Output Current IOUT −5 +5 mA
Settling Time tS To 0.01% 5 13 μs
Slew Rate SR 10% to 90%5 2 V/μs
DYNAMIC PERFORMANCE
Analog Crosstalk3 >64 dB
Digital Feedthrough3 >72 dB
Large Signal Bandwidth 3 dB, VVREFHI = 5 V + 10 V p-p, VVREFLO = −10 V3 90 kHz
Glitch Impulse Code Transition = 0x7FF to 0x8003 6 μV-s
LOGIC CHARACTERISTICS
Logic Input High Voltage VINH 2.4 V
Logic Input Low Voltage VINL 0.8 V
Logic Input Current IIN 10 μA
Input Capacitance3 CIN 13 pF
LOGIC TIMING CHARACTERISTICS3, 6
Data Setup Time tDS 25 ns
Data Hold tDH 20 ns
Clock Pulse Width High tCH 30 ns
Clock Pulse Width Low tCL 50 ns
Select Time tCSS 55 ns
Deselect Delay tCSH 15 ns
Load Disable Time tLD1 40 ns
Load Delay tLD2 15 ns
Load Pulse Width tLDW 45 ns
Clear Pulse Width tCLRW 70 ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSRR 0.002 0.01 %/%
Positive Supply Current IDD 6 9 mA
Negative Supply Current ISS −8 −5 mA
Power Dissipation PDISS 255 mW
1
Typical values indicate performance measured at 25°C.
2
All supplies can be varied ±5% and operation is guaranteed.
3
Guaranteed, but not tested.
4
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
5
VOUT swing between +10 V and −10 V.
6
All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

Rev. C | Page 5 of 23
DAC8420 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. THERMAL RESISTANCE
Table 3. Table 4.
Parameter Rating Package Type θJA θJC Unit
VDD to GND −0.3 V, +18.0 V 16-Lead PDIP (N) 701 27 °C/W
VSS to GND +0.3 V, −18.0 V 16-Lead CERDIP (Q) 821 9 °C/W
VSS to VDD −0.3 V, +36.0 V 16-Lead SOIC (RW) 862 22 °C/W
VSS to VVREFLO −0.3 V, VSS − 2.0 V
1
θJA is specified for worst case mounting conditions, that is, θJA is specified for
VVREFHI to VVREFLO +2.0 V, VDD − VSS device in socket.
VVREFHI to VDD +2.0 V, +33.0 V 2
θJA is specified for device on board.
IVREFHI, IVREFLO 10 mA
Digital Input Voltage to GND −0.3 V, VDD + 0.3 V ESD CAUTION
Output Short-Circuit Duration Indefinite
Operating Temperature Range
EP, FP, ES, FS, EQ, FQ –40°C to +85°C
Dice Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Power Dissipation 1000 mW
Lead Temperature JEDEC Industry Standard
Soldering J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. C | Page 6 of 23
Data Sheet DAC8420
DATA LOAD SEQUENCE
tCSH

CS
tCSS

SDI A1 A0 X X D11 D10 D9 D8 D4 D3 D2 D1 D0

CLK

tLD1 tLD2
LD

DATA LOAD TIMING tDS tDH CLEAR TIMING

SDI CLSEL

tCLRW
CLK CLR
tCH
tCL
tCSH tS
CS VOUT
tLD2
tLDW
±1LSB
LD
tS

00275-002
VOUTx ±1LSB

Figure 2. Timing Diagram

5kΩ
10kΩ
+15V 1 16
+
1N4001 10µF 0.1µF
NC 2 15

NC 3 14
10kΩ
–10V 4 13 NC
DUT
1N4001 10µF 0.1µF
+ 5 12
5kΩ
NC 6 11
10kΩ
+10V NC 7 10
+
1N4001 10µF 0.1µF
8 9

10kΩ
10kΩ
–15V
1N4001 10µF 0.1µF NC = NO CONNECT
00275-003

Figure 3. Burn-In Diagram

Rev. C | Page 7 of 23
DAC8420 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VDD 1 16 CLSEL VDD 1 16 CLSEL
VOUTD 2 15 CLR VOUTD 2 15 CLR
VOUTC 3 DAC8420 14 LD VOUTC 3 14 LD
VREFLO 4 TOP VIEW 13 NC
DAC8420
VREFLO 4 TOP VIEW 13 NC
VREFHI 5 (Not to Scale) 12 CS
VREFHI 5 (Not to Scale) 12 CS
VOUTB 6 11 CLK
VOUTB 6 11 CLK
VOUTA 7 10 SDI
VOUTA 7 10 SDI

00275-004
VSS 8 9 GND

00275-005
VSS 8 9 GND
NC = NO CONNECT
NC = NO CONNECT

Figure 4. PDIP and CERDIP Figure 5. SOIC

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD Positive Power Supply, 5 V to 15 V.
4 VREFLO Reference Input. Lower DAC ladder reference voltage input, equal to zero-scale output. Allowable
range is VSS to (VVREFHI − 2.5 V).
5 VREFHI Reference Input. Upper DAC ladder reference voltage input. Allowable range is (VDD − 2.5 V) to
(VVREFLO + 2.5 V).
7, 6, 3, 2 VOUTA through VOUTD Buffered DAC Analog Voltage Outputs.
8 VSS Negative Power Supply, 0 V to −15 V.
9 GND Power Supply, Digital Ground.
10 SDI Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register,
which shifts data in, beginning with DAC Address Bit A1. This input is ignored when CS is high. SDI
is CMOS/TTL compatible. The format of the 16-bit serial word is shown in Table 8.
11 CLK System Serial Data Clock Input, TTL/CMOS Levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically OR’ed
with CS.
12 CS Control Input, Device Chip Select, Active Low. This input is logically OR’ed with the clock and
disables the serial data register input when high. When low, data input clocking is enabled (see
Table 6). CS is CMOS/TTL compatible.
13 NC No Connect = Don’t Care.
14 LD Control Input, Asynchronous DAC Register Load Control, Active Low. The data currently contained
in the serial input shift register is shifted out to the DAC data registers on the falling edge of LD,
independent of CS. Input data must remain stable while LD is low. LD is CMOS/TTL compatible.
15 CLR Control Input, Asynchronous Clear, Active Low. Sets internal data Register A through Register D to
zero or midscale, depending on current state of CLSEL. The data in the serial input shift register is
unaffected by this control. CLR is CMOS/TTL compatible.
16 CLSEL Control Input, Determines action of CLR. If high, a clear command sets the internal DAC Register A
through Register D to midscale (0x800). If low, the registers are set to zero (0x000). CLSEL is CMOS/
TTL compatible.

Table 6. Control Function Logic Table

CLK1 CS1 LD CLR CLSEL Serial Input Shift Register DAC Register A to DAC Register D
2
NC High High Low High No change Loads midscale value (0x800)
NC2 High High Low Low No change Loads zero-scale value (0x000)
NC2 High High ↑ High /Low No change Latches value
↑ Low High High NC2 Shifts register one bit No change
Low ↑ High High NC2 Shifts register one bit No change
High NC (↑)2 ↓ High NC2 No change Loads the serial data-word3
High NC2 Low High NC2 No change Transparent4
NC2 High High High NC2 No change No change
1
CLK and CS are interchangeable.
2
NC = Don’t Care.
3
Returning CS high while CLK is high avoids an additional false clock of serial input data. CLK and CS are interchangeable.
4
Do not clock in serial data while LD is low.

Rev. C | Page 8 of 23
Data Sheet DAC8420

TYPICAL PERFORMANCE CHARACTERISTICS

0.3 0.4
TA = +25°C TA = +25°C
VDD = +15V 0.3 VDD = +5V
0.2 VSS = 0V
VSS = –15V
VVREFLO = –10V 0.2 VVREFLO = 0V

0.1
0.1
DNL (LSB)

INL (LSB)
0 0

–0.1
–0.1
–0.2
–0.2
–0.3

–0.3

00275-010
00275-007
–0.4
–6 –4 –2 0 2 4 6 8 10 12 14 1.5 2.0 2.5 3.0 3.5
VVREFHI (V) VVREFHI (V)

Figure 6. DNL vs. VVREFHI (±15 V) Figure 9. INL vs. VVREFHI (+5 V)

0.7
0.10
x + 3σ

FULL-SCALE ERROR WITH RL = 2kΩ (LSB)

TA = +25°C
0.05 VDD = +5V 0.5 VDD = +15V
VSS = 0V VSS = –15V
0 VVREFLO = 0V VVREFHI = +10V
0.3
VVREFLO = –10V
–0.05
x
DNL (LSB)

0.1
–0.10

–0.15 –0.1

–0.20
–0.3
x – 3σ
–0.25
–0.5
0 200 400 600 800 1000

00275-011
00275-008

–0.30
1.5 2.0 2.5 3.0 3.5 t = HOURS OF OPERATION AT 125°C
VVREFHI (V) CURVES NOT NORMALIZED

Figure 7. DNL vs. VVREFHI (+5 V) Figure 10. Full-Scale Error vs. Time Accelerated by Burn-In

1.2
0.3
x + 3σ
FULL-SCALE ERROR WITH RL = 2kΩ (LSB)

1.0
0.2
VDD = +15V
0.8 VSS = –15V
0.1 VVREFHI = +10V
VVREFLO = –10V
INL (LSB)

x
0.6
0

0.4
–0.1 TA = +25°C
VDD = +15V
VSS = –15V 0.2
–0.2 VVREFLO = –10V x – 3σ

0
–0.3 0 200 400 600 800 1000
00275-012
00275-009

–6 –4 –2 0 2 4 6 8 10 12 14 t = HOURS OF OPERATION AT 125°C

VVREFHI (V) CURVES NOT NORMALIZED

Figure 8. INL vs. VREFHI (±15 V) Figure 11. Zero-Scale Error vs. Time Accelerated by Burn-In

Rev. C | Page 9 of 23
DAC8420 Data Sheet
0.2 1.5
VDD = +15V TA = +25°C
VSS = –15V VDD = +5V
0.1 1.0
VVREFHI = +10V VSS = 0V
VVREFLO = –10V VVREFHI = +2.5V
FULL-SCALE ERROR (LSB)

0 VVREFLO = 0V
0.5

ERROR (LSB)
–0.1
DAC C DAC D 0
–0.2
DAC A
–0.5
–0.3

DAC B –1.0
–0.4

–1.5
–0.5

00275-016
–0.6

00275-013
–75 –50 –25 0 25 50 75 100 125 0 500 1000 1500 2000 2500 3000 3500 4000 4500
TEMPERATURE (°C) DIGITAL INPUT CODE

Figure 12. Full-Scale Error vs. Temperature Figure 15. Channel-to-Channel Matching

1.2 13
VDD = +15V TA = +25°C
VSS = –15V 12 VDD = +15V
1.0
VVREFHI = +10V VSS = –15V
VVREFLO = –10V 11 VVREFLO = –10V
ZERO-SCALE ERROR (LSB)

0.8
DAC B 10
0.6
DAC C IDD (mA)
9
0.4
DAC A 8
0.2
DAC D 7

0 6

–0.2 5

00275-017
–0.4
00275-014

–75 –50 –25 0 25 50 75 100 125 –7 –5 –3 –1 0 1 3 5 7 9 11 13

TEMPERATURE (°C) VVREFHI (V)

Figure 13. Zero-Scale Error vs. Temperature Figure 16. IDD vs. VVREFHI, All DACs High

0.9 0.8
TA = +25°C TA = +25°C, –55°C, 125°C
0.7
0.7 VDD = +15V VDD = +15V
VSS = –15V 0.6 VSS = –15V
0.5 VVREFHI = +10V 0.5 VVREFHI = +10V
VVREFLO = –10V VVREFLO = –10V
0.4
0.3
ERROR (±LSB)

0.3
INL (LSB)

0.1 0.2

–0.1 0.1
0
–0.3
–0.1
–0.5 –0.2
–0.3
–0.7
–0.4
00275-015

00275-018

–0.9
0 500 1000 1500 2000 2500 3000 3500 4000 4500 0 500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL INPUT CODE DIGITAL INPUT CODE

Figure 14. Channel-to-Channel Matching Figure 17. INL vs. Code

Rev. C | Page 10 of 23
Data Sheet DAC8420
1.5 31.25mV
LD

1.0 TA = +25°C
VDD = +15V
VSS = –15V
VVREFHI = +10V
IVREFHI (mA)

0.5 VVREFLO = –10V

TA = +25°C 4.88mV
VDD = +15V 1 LSB
–0.5 0mV
VSS = –15V
VVREFHI = +10V
VVREFLO = –10V

00275-019
–1.0
–18.75mV

00275-022
0 500 1000 1500 2000 2500 3000 3500 4000 4500
–9.8µs 10µs/DIV 90.2µs
DIGITAL INPUT CODE
tSETT 13µs

Figure 18. IVREFHI vs. Code Figure 21. Positive Settling Time (±15 V)

–2.50µV 43.75mV
CLR
LD
TA = +25°C TA = +25°C
VDD = +5V VDD = +15V
VSS = –5V VSS = –15V
VVREFHI = +2.5V VVREFHI = +10V
1.22mV VVREFLO = –2.5V VVREFLO = –10V
1 LSB
0mV

0mV
1 LSB
–4.88mV

–10.25mV
00275-020

–6.25mV

00275-023
–4.9µs 5µs/DIV 45.1µs –9.8µs 10µs/DIV 90.2µs
tSETT 8µs tSETT 13µs

Figure 19. Positive Settling Time (±5 V) Figure 22. Negative Settling Time (±15 V)

6.5mV 5V
CLR
TA = +25°C
VDD = +5V
TA = +25°C VSS = –5V
VDD = +5V VVREFHI = +2.5V
VSS = –5V VVREFLO = –2.5V
VVREFHI = +2.5V
VVREFLO = –2.5V
+1V/DIV
0

0mV
1 LSB
1.22mV

–5V
00275-024

3.5mV
00275-021

–4.9µs 5µs/DIV 45.1µs –47.6µs V 20µs/DIV V 152.4µs

SRRISE = 1.65 SRFALL = 1.17
tSETT 8µs µs µs

Figure 20. Negative Settling Time (±5 V) Figure 23. Slew Rate (±5 V)

Rev. C | Page 11 of 23
DAC8420 Data Sheet
25V 6
LD
IDD

POWER SUPPLY CURRENT (mA)

CLR

2 VDD = +15V
VSS = –15V
+5V/DIV
VVREFHI = +10V
0 0 VVREFLO = –10V
TA = +25°C ALL DACS HIGH (FULL SCALE)
VDD = +15V –2
VSS = –15V
VVREFHI = +10V
VVREFLO = –10V –4

ISS
–25V –6

00275-028
00275-025
–33.6µs V 20µs/DIV V 166.4µs –75 0 75 150
SRRISE = 1.9 SRFALL = 2.02 TEMPERATURE (°C)
µs µs

Figure 24. Slew Rate (±15 V) Figure 27. Power Supply Current vs. Temperature

VOUTA THROUGH VOUTD

TA = +25°C
10 VDD = +15V
VSS = –15V
0 VVREFHI = +10V
GAIN (dB)

VVREFLO = –10V
–10 10mA/DIV DATA = 0x800

–20

–30
TA = +25°C
VDD = +15V
VSS = –15V
VVREFHI = 0 ±100mV
VVREFLO = –10V

00275-029
ALL BITS HIGH 200mV p-p
00275-026

10 100 1k 10k 100k 1M 10M 5V/DIV

FREQUENCY (Hz)

Figure 25. Small-Signal Response Figure 28. DAC Output Current vs. VOUTx

100 10

90

80 8

70
|VOUT PEAK| (V)

60 6
PSRR (dB)

50

40 4
TA = +25°C TA = +25°C
30 DATA = 0x000 VDD = +15V
VDD = +15V ±1V VSS = –15V
20 2
VSS = –15V VVREFHI = +10V
10 VVREFHI = +10V VVREFLO = –10V
VVREFLO = –10V DATA = 0xFFF OR 0x000
0 0
00275-027

00275-030

10 100 1k 10k 100k 1M 10 100 1k 10k

FREQUENCY (Hz) LOAD RESISTANCE (Ω)

Figure 26. PSRR vs. Frequency Figure 29. Output Swing vs. Load Resistance

Rev. C | Page 12 of 23
Data Sheet DAC8420

THEORY OF OPERATION
INTRODUCTION USING CLR AND CLSEL
The DAC8420 is a quad, voltage-output 12-bit DAC with a serial The clear (CLR) control allows the user to perform an asyn-
digital input capable of operating from a single 5 V supply. The chronous reset function. Asserting CLR loads all four DAC
straightforward serial interface can be connected directly to data-word registers, forcing the DAC outputs to either zero
most popular microprocessors and microcontrollers, and can scale (0x000) or midscale (0x800), depending on the state of
accept data at a 10 MHz clock rate when operating from ±15 V CLSEL as shown in Table 6. The clear function is asynchronous
supplies. A unique voltage reference structure ensures maximum and totally independent of CS. When CLR returns high, the
utilization of the DAC output resolution by allowing the user to DAC outputs remain latched at the reset value until LD is
set the zero-scale and full-scale output levels within the supply
strobed, reloading the individual DAC data-word registers
rails. The analog voltage outputs are fully buffered, and are
with either the data held in the serial input register prior to the
capable of driving a 2 kΩ load. Output glitch impulse during
reset or with new data loaded through the serial interface.
major code transitions is a very low 64 nV-s (typ).
DIGITAL INTERFACE OPERATION Table 7. DAC Address Word Decode Table
A1 A0 DAC Addressed
The serial input of the DAC8420, consisting of CS, SDI, and LD,
0 0 DAC A
is easily interfaced to a wide variety of microprocessor serial ports.
0 1 DAC B
While CS is low, the data presented to the input SDI is shifted 1 0 DAC C
into the internal serial-to-parallel shift register on the rising 1 1 DAC D
edge of the clock, with the address MSB first, data LSB last, as
shown in Table 6 and in the timing diagram (Figure 2). The
PROGRAMMING THE ANALOG OUTPUTS
data format, shown in Table 8, is two bits of DAC address and
two don’t care fill bits, followed by the 12-bit DAC data-word. The unique differential reference structure of the DAC8420
Once all 16 bits of the serial data-word have been input, the allows the user to tailor the output voltage range precisely to
load control LD is strobed and the word is parallel-shifted out the needs of the application. Instead of spending DAC resolu-
tion on an unused region near the positive or negative rail, the
onto the internal data bus. The two address bits are decoded
DAC8420 allows the user to determine both the upper and
and used to route the 12-bit data-word to the appropriate DAC
lower limits of the analog output voltage range. Thus, as shown
data register (see the Applications section).
in Table 9 and Figure 30, the outputs of DAC A through DAC D
CORRECT OPERATION OF CS AND CLK range between VREFHI and VREFLO, within the limits specified
In Table 6, the control pins CLK and CS require some attention in the Specifications section. Note also that VREFHI must be
during a data load cycle. Since these two inputs are fed to the greater than VREFLO.
same logical OR gate, the operation is in fact identical. The user VDD

must take care to operate them accordingly to avoid clocking in 2.5V MIN
VVREFHI
false data bits. In the timing diagram, CLK must be halted high
or CS must be brought high during the last high portion of the
0xFFF

CLK following the rising edge that latched in the last data bit.
Otherwise, an additional rising edge is generated by CS rising 1 LSB
2.5V MIN
while CLK is low, causing CS to act as the clock and allowing a
false data bit into the serial input register. The same issue must
also be considered in the beginning of the data load sequence.
0x000
–10V MIN
VVREFLO

0V MIN
00275-006

VSS

Figure 30. Output Voltage Range Programming

Table 8.
(FIRST) (LAST)
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
A1 A0 NC NC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
—Address Word— (MSB) —DAC Data-Word— (LSB)

Rev. C | Page 13 of 23
DAC8420 Data Sheet

Table 9. Analog Output Code

DAC Data-Word (Hex) VOUT Note
0xFFF (VREFHI − VREFLO) Full-scale output
VREFLO + × 4095
4096
0x801 (VREFHI − VREFLO) Midscale + 1
VREFLO + × 2049
4096
0x800 (VREFHI − VREFLO) Midscale
VREFLO + × 2048
4096
0x7FF (VREFHI − VREFLO) Midscale − 1
VREFLO + × 2047
4096
0x000 (VREFHI − VREFLO) Zero scale
VREFLO + ×0
4096

Rev. C | Page 14 of 23
Data Sheet DAC8420
VREFHI INPUT REQUIREMENTS POWER-UP SEQUENCE
The DAC8420 utilizes a unique, patented DAC switch driver To prevent a CMOS latch-up condition, power up VDD, VSS,
circuit that compensates for different supply, reference voltage, and GND prior to any reference voltages. The ideal power-up
and digital code inputs. This ensures that all DAC ladder switches sequence is GND, VSS, VDD, VREFHI, VREFLO, and digital
are always biased equally, ensuring excellent linearity under all inputs. Noncompliance with the power-up sequence over an
conditions. Thus, as shown in Table 1, the VREFHI input of the extended period can elevate the reference currents and eventually
DAC8420 requires both sourcing and sinking current capabili- damage the device. On the other hand, if the noncompliant
ties from the reference voltage source. Many positive voltage power-up sequence condition is as short as a few milliseconds,
references are intended as current sources only and offer little the device can resume normal operation without being damaged
sinking capability. The user must consider references such as once VDD/VSS is powered.
the AD584, AD586, AD587, AD588, AD780, and REF43 for
such an application.

Rev. C | Page 15 of 23
DAC8420 Data Sheet

APPLICATIONS
POWER SUPPLY BYPASSING AND GROUNDING In the case of 5 V only systems, it is desirable to use the same 5 V
In any circuit where accuracy is important, careful consid- supply for both the analog circuitry and the digital portion of
eration of the power supply and ground return layout helps to the circuit. Unfortunately, the typical 5 V supply is extremely
ensure the rated performance. The DAC8420 has a single ground noisy due to the fast edge rates of the popular CMOS logic families,
pin that is internally connected to the digital section as the logic which induce large inductive voltage spikes, and busy micro-
reference level. The first thought may be to connect this pin to controller or microprocessor buses, and therefore commonly have
digital ground; however, in large systems digital ground is often large current spikes during bus activity. However, by properly
noisy because of the switching currents of other digital circuitry. filtering the supply as shown in Figure 32, the digital 5 V supply
Any noise that is introduced at the ground pin can couple into can be used. The inductors and capacitors generate a filter that
the analog output. Thus, to avoid error-causing digital noise in the not only rejects noise due to the digital circuitry, but also filters
sensitive analog circuitry, the ground pin must be connected to out the lower frequency noise of switch mode power supplies.
the system analog ground. The ground path (circuit board trace) The analog supply must be connected as close as possible to the
must be as wide as possible to reduce any effects of parasitic origin of the digital supply to minimize noise pickup from the
inductance and ohmic drops. A ground plane is recommended digital section.
FERRITE BEADS:
if possible. The noise immunity of the on-board digital circuitry, 2 TURNS, FAIR-RITE
typically in the hundreds of millivolts, is well able to reject the #2677006301
TTL/CMOS +5V
common-mode noise typically seen between system analog and LOGIC
+ 100µF + 10µF TO 22µF
digital grounds. Finally, the analog and digital ground must be CIRCUITS
ELECT.
0.1µF
CER.
TANT.
connected to each other at a single point in the system to provide a +5V
common reference. This is preferably done at the power supply. RETURN

Good grounding practice is also essential to maintaining analog

performance in the surrounding analog support circuitry. With

00275-032
+5V
two reference inputs and four analog outputs capable of moderate POWER SUPPLY

bandwidth and output current, there is a significant potential Figure 32. Single-Supply Analog Supply Filter
for ground loops. Again, a ground plane is recommended as the
most effective solution to minimizing errors due to noise and
ANALOG OUTPUTS
ground offsets. The DAC8420 features buffered analog voltage outputs capable
of sourcing and sinking up to 5 mA when operating from ±15 V
+VS 1 V
DD supplies, eliminating the need for external buffer amplifiers in most
10µF 0.1µF applications while maintaining specified accuracy over the rated
operating conditions. The buffered outputs are simply an
operational amplifier connected as a voltage follower, and thus
have output characteristics very similar to the typical operational
amplifier. These amplifiers are short-circuit protected. The user
must verify that the output load meets the capabilities of the device,
in terms of both output current and load capacitance. The
–VS
8
VSS GND
9 DAC8420 is stable with capacitive loads up to 2 nF typically.
10µF 0.1µF However, any capacitive load increases the settling time, and
must be minimized if speed is a concern.
00275-031

10µF = TANTALUM
0.1µF = CERAMIC The output stage includes a P-channel MOSFET to pull the output
Figure 31. Recommended Supply Bypassing Scheme voltage down to the negative supply. This is very important in
single-supply systems where VREFLO usually has the same
The DAC8420 must have ample supply bypassing, located as
potential as the negative supply. With no load, the zero-scale output
close to the package as possible. Figure 31 shows the recom-
voltage in these applications is less than 500 μV typically, or less
mended capacitor values of 10 μF in parallel with 0.1 μF. The
than 1 LSB when VVREFHI = 2.5 V. However, when sinking current,
0.1 μF capacitor must have low effective series resistance (ESR) and
this voltage does increase because of the finite impedance of the
effective series inductance (ESI) (such as any common ceramic
output stage. The effective value of the pull-down resistor in the
type capacitor), which provide a low impedance path to ground
output stage is typically 320 Ω. With a 100 kΩ resistor connected to
at high frequencies to handle transient currents due to internal
5 V, the resulting zero-scale output voltage is 16 mV. Thus, the best
logic switching. To preserve the specified analog performance of
single-supply operation is obtained with the output load connected
the device, the supply must be as noise free as possible.
to ground, so the output stage does not have to sink current.

Rev. C | Page 16 of 23
Data Sheet DAC8420
Like all amplifiers, the DAC8420 output buffers do generate The AD588 provides both voltages and needs no external
voltage noise, 52 nV/√Hz typically. This is easily reduced by components. Additionally, the device is trimmed in production
adding a simple RC low-pass filter on each output. for 12-bit accuracy over the full temperature range without user
calibration. Performing a clear with the reset select CLSEL high
REFERENCE CONFIGURATION
allows the user to easily reset the DAC outputs to midscale, or
The two reference inputs of the DAC8420 allow a great deal 0 V in these applications.
of flexibility in circuit design. The user must take care, however,
to observe the minimum voltage input levels on VREFHI and When driving the reference inputs VREFHI and VREFLO, it is
VREFLO to maintain the accuracy shown in the data sheet. important to note that VREFHI both sinks and sources current,
These input voltages can be set anywhere across a wide range and that the input currents of both are code dependent. Many
within the supplies, but must be a minimum of 2.5 V apart in voltage reference products have a limited current sinking capability
any case (see Figure 30). A wide output voltage range can be and must be buffered with an amplifier to drive VREFHI in order
obtained with ±5 V references, which can be provided by the to maintain overall system accuracy. The input VREFLO, however,
AD588 as shown in Figure 33. Many applications utilize the has no such requirement.
DACs to synthesize symmetric bipolar waveforms, which
require an accurate, low drift bipolar reference.
1µF +15V SUPPLY

VREFHI
7 6 4 3 +5V 0.1µF
5 1
AD588

RB +5V DAC8420 DAC A 7 VOUTA

A3 1
A1

R4 14
R1 DAC B 6 VOUTB
–5V
A4 15
R2 R5
DAC C 3 VOUTC
+VS 2 +15V
SUPPLY DIGITAL
R3 R6 CONTROLS
0.1µF
A2
–VS 16 SYSTEM DAC D 2 VOUTD
GROUND
5 9 10 8 12 11 13 0.1µF
10 11 12 14 15 16 9 4 8
–15V
SUPPLY GND VREFLO
DIGITAL INPUTS –5V
0.1µF

00275-033
–15V SUPPLY

Figure 33. ±10 V Bipolar Reference Configuration Using the AD588

Rev. C | Page 17 of 23
DAC8420 Data Sheet
For a single 5 V supply, VVREFHI is limited to at most 2.5 V, and One opto-isolated line (LD) can be eliminated from this circuit
must always be at least 2.5 V less than the positive supply to ensure by adding an inexpensive 4-bit TTL counter to generate the load
linearity of the device. For these applications, the REF43 is an pulse for the DAC8420 after 16 clock cycles. The counter is used
excellent low drift 2.5 V reference that consumes only 450 μA to count the number of clock cycles loading serial data to the
(max). It works well with the DAC8420 in a single 5 V system as DAC8420. After all 16 bits have been clocked into the converter,
shown in Figure 34. the counter resets, and a load pulse is generated on Clock 17. In
+5V SUPPLY either circuit, the serial interface of the DAC8420 provides a simple,
REF43
2 VIN
low cost method of isolating the digital control.
+5V SUPPLY
0.1µF HIGH VOLTAGE
2.5V ISOLATION
4 GND VOUT 6
5V
VREFHI 0.1µF 5V
REG
5 1
POWER

DAC8420 DAC A 7 VOUTA

5V +5V
REF43
10kΩ 2 VIN
DAC B 6 VOUTB
VOUT 6
LD 5V
4 GND
2.5V
DAC C 3 VOUTC
5V 0.1µF
DIGITAL 5 1
CONTROLS 5V
10kΩ VREFHI VDD
DAC D 2 VOUTD 10kΩ 15 CLR
0.1µF 7 VOUTA
SCLK 16 CLSEL
10 11 12 14 15 16 9 4 8
00275-034

6 VOUTB
GND VREFLO 14 LD
DIGITAL INPUTS DAC8420
12 CS 3 VOUTC
5V
Figure 34. 5 V Single-Supply Operation Using REF43
11 CLK
10kΩ
ISOLATED DIGITAL INTERFACE SDI 10 SDI
2 VOUTD

Because the DAC8420 is ideal for generating accurate voltages VREFLO VSS GND
4 8 9
in process control and industrial applications, due to noise, from

00275-035
the central controller; it can be necessary to isolate it from the
central controller. This can be easily achieved by using opto-
Figure 35. Opto-lsolated 3-Wire Interface
isolators, which are commonly used to provide electrical isolation
in excess of 3 kV. Figure 35 shows a simple 3-wire interface scheme
for controlling the clock, data, and load pulse. For normal
operation, CS is tied permanently low so that the DAC8420 is
always selected. The resistor and capacitor on the CLR pin provide
a power-on reset with 10 ms time constant. The three opto-
isolators are used for the SDI, CLK, and LD lines.

Rev. C | Page 18 of 23
Data Sheet DAC8420
5V SUPPLY
REF43 VINA 5V
2 VIN
5V SUPPLY
0.1µF
2.5V 0.1µF
4 GND VOUT 6 5V
0.1µF
VREFHI 3
5 1 604Ω
CMP04
DAC8420 DAC A 7
VOUTA
5 RED LED
C1 2 OUT A
4
VOUTB 5V
DAC B 6 7
C2 1 604Ω
6
VOUTC
DAC C 3
9 RED LED
DIGITAL C3 14 OUT B
CONTROLS 8
VOUTD
DAC D 2
11
C4 13
10 11 12 14 15 16 9 4 8 10
GND VREFLO VSS
DIGITAL INPUTS 12

00275-036
VINB

Figure 36. Dual Programmable Window Comparator

DUAL WINDOW COMPARATOR PC2 CLSEL

Often a comparator is needed to signal an out-of-range warning. PC1 CLR

PC0 CS
Combining the DAC8420 with a quad comparator such as the
MC68HC11* DAC8420*
CMP04 provides a simple dual window comparator with adjustable (PD5) SS LD
trip points as shown in Figure 36. This circuit can be operated with SCK CLK

00275-037
either a dual supply or a single supply. For the A input channel, MOSI SDI

DAC B sets the low trip point, and DAC A sets the upper trip
*ADDITIONAL PINS OMITTED FOR CLARITY.
point. The CMP04 has open-collector outputs that are connected
Figure 37. MC68HC11 Microcontroller Interface
together in a wire-OR’ed configuration to generate an out-of-
range signal. For example, when VINA goes below the trip point For correct operation, the MC68HC11 must be configured
set by DAC B, Comparator C2 pulls the output down, turning such that the CPOL bit and CPHA bit are both set to 1. In this
on the red LED. The output can also be used as a logic signal for configuration, serial data on MOSI of the MC68HC11 is valid
further processing. on the rising edge of the clock, which is the required timing for
the DAC8420. Data is transmitted in 8-bit bytes (MSB first), with
MC68HC11 MICROCONTROLLER INTERFACING only eight rising clock edges occurring in the transmit cycle. To
Figure 37 shows a serial interface between the DAC8420 and load data to the input register of the DAC8420, PC0 is taken low
the MC68HC11 8-bit microcontroller. The SCK output of the and held low during the entire loading cycle. The first eight bits
port outputs the serial data to load into the SDI input of the are shifted in address first, immediately followed by another eight
DAC. The port lines (PD5, PC0, PC1, and PC2) provide the bits in the second least-significant byte to load the complete 16-
controls to the DAC as shown. bit word. At the end of the second byte load, PC0 is then taken
high. To prevent an additional advancing of the internal shift
register, SCK must already be asserted before PC0 is taken high.
To transfer the contents of the input shift register to the DAC
register, PD5 is then taken low, asserting the LD input of the DAC
and completing the loading process. PD5 must return high before
the next load cycle begins. The CLR input of the DAC8420
(controlled by the output PC1) provides an asynchronous clear
function.

Rev. C | Page 19 of 23
DAC8420 Data Sheet
DAC8420 TO M68HC11 INTERFACE ASSEMBLY PROGRAM
* M68HC11 Register Definitions * Initialize SPI Interface
PORTC EQU $1003 Port C control register LDAA #$5F
* “0,0,0,0;0,CLSEL,CLR,CS” STAA SPCR SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32
DDRC EQU $1007 Port C data direction * Call update subroutine
PORTD EQU $1008 Port D data register BSR UPDATE Xfer 2 8-bit words to DAC-8420
* “0,0,LD,SCLK;SDI,0,0,0” JMP $E000 Restart BUFFALO
DDRD EQU $1009 Port D data direction * Subroutine UPDATE
SPCR EQU $1028 SPI control register UPDATE PSHX Save registers X, Y, and A
* “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0” PSHY
SPSR EQU $1029 SPI status register PSHA
* “SPIF,WCOL,0,MODF;0,0,0,0” * Enter Contents of SDI1 Data Register (DAC# and 4 MSBs)
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter LDAA #$80 1,0,0,0;0,0,0,0
* STAA SDI1 SDI1 is set to 80 (Hex)
* SDI RAM variables: SDI1 is encoded from 0 (Hex) to CF (Hex) * Enter Contents of SDI2 Data Register
* To select: DAC A – Set SDI1 to $0X LDAA #$00 0,0,0,0;0,0,0,0
DAC B – Set SDI1 to $4X STAA SDI2 SDI2 is set to 00 (Hex)
DAC C – Set SDI1 to $8X LDX #SDI1 Stack pointer at 1st byte to send via SDI
DAC D – Set SDI1 to $CX LDY #$1000 Stack pointer at on-chip registers
SDI2 is encoded from 00 (Hex) to FF (Hex) * Clear DAC output to zero
* DAC requires two 8-bit loads – Address + 12 bits BCLR PORTC,Y $02 Assert CLR
SDI1 EQU $00 SDI packed byte 1 “A1,A0,0,0;MSB,DB10,DB9,DB8” BSET PORTC,Y $02 Deassert CLR
SDI2 EQU $01 SDI packed byte 2 * Get DAC ready for data input
“DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0” BCLR PORTC,Y $01 Assert CS
* Main Program TFRLP LDAA 0,X Get a byte to transfer via SPI
ORG $C000 Start of user’s RAM in EVB STAA SPDR Write SDI data reg to start xfer
INIT LDS #$CFFF Top of C page RAM WAIT LDAA SPSR Loop to wait for SPIF
* Initialize Port C Outputs BPL WAIT SPIF is the MSB of SPSR
LDAA #$07 0,0,0,0;0,1,1,1 * (when SPIF is set, SPSR is negated)
* CLSEL-Hi, CLR-Hi, CS-Hi INX Increment counter to next byte for xfer
* To reset DAC to ZERO-SCALE, set CLSEL-Lo ($03) CPX #SDI2+ 1 Are we done yet ?
* To reset DAC to MID-SCALE, set CLSEL-Hi ($07) BNE TFRLP If not, xfer the second byte
STAA PORTC Initialize Port C Outputs * Update DAC output with contents of DAC register
LDAA #$07 0,0,0,0;0,1,1,1 BCLR PORTD,Y 520 Assert LD
STAA DDRC CLSEL, CLR, and CS are now enabled as outputs BSET PORTD,Y $20 Latch DAC register
* Initialize Port D Outputs BSET PORTC,Y $01 De-assert CS
LDAA #$30 0,0,1,1;0,0,0,0 PULA When done, restore registers X, Y & A
* LD-Hi,SCLK-Hi,SDI-Lo PULY
STAA PORTD Initialize Port D Outputs PULX
LDAA #$38 0,0,1,1;1,0,0,0 RTS ** Return to Main Program **
STAA DDRD LD,SCLK, and SDI are now enabled as outputs

Rev. C | Page 20 of 23
Data Sheet DAC8420

OUTLINE DIMENSIONS
0.775
0.755
0.735

16 9
0.280
PIN 1 0.250
INDICATOR 1
8
0.240

TOP VIEW
0.100 0.325
BSC 0.195 0.310
0.210 0.130 0.300
MAX SIDE VIEW 0.115
0.015
0.150 MIN 0.015
0.130 GAUGE END VIEW
PLANE 0.012
0.115 SEATING 0.010
PLANE
0.022 0.008
0.021 0.430
0.018 0.070 0.016 MAX
0.015 0.045 0.060 0.011
0.039 0.055

03-07-2014-D
0.030

COMPLIANT TO JEDEC STANDARDS MS-001-BB

Figure 38. 16-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body
(N-16)
Dimensions shown in inches
10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)

BSC 45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013- AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
032707-B

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 39. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)

Rev. C | Page 21 of 23
DAC8420 Data Sheet
0.005 (0.13) MIN 0.098 (2.49) MAX

16 9
0.310 (7.87)
1 0.220 (5.59)
8

PIN 1
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.060 (1.52)
0.200 (5.08) 0.015 (0.38)
MAX
0.150
0.200 (5.08) (3.81)
0.125 (3.18) MIN
SEATING 0.015 (0.38)
0.023 (0.58) 0.070 (1.78) PLANE 15°
0.008 (0.20)
0.014 (0.36) 0.030 (0.76) 0°

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 40. 16-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-16)
Dimensions shown in inches and (millimeters)

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option INL 2 (±LSB)
DAC8420EPZ −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 0.5
DAC8420ES −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 0.5
DAC8420ESZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 0.5
DAC8420ESZ-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 0.5
DAC8420FPZ −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 1.0
DAC8420FQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 1.0
DAC8420FS −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 1.0
DAC8420FSZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 1.0
DAC8420FSZ-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 1.0
1
Z = RoHS Compliant Part.
2
INL measured at VDD = +15 V and VSS = −15 V.

Rev. C | Page 22 of 23
Data Sheet DAC8420

NOTES

©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D00275-0-9/16(C)

Rev. C | Page 23 of 23