CD40160BMS, CD40161BMS, CD40162BMS,

CD40163BMS
December 1992 File Number 3358

CMOS Synchronous Programmable 4-Bit Features

Counters • High-Voltage Types (20V Rating)

CD40160BMS, CD40161BMS, CD40162BMS and • CD40160BMS Decade with Asynchronous Clear

CD40163BMS are 4-bit synchronous programmable • CD40161BMS Binary with Asynchronous Clear
counters. The CLEAR function of the CD40162BMS and • CD40162BMS Decade with Synchronous Clear
CD40163BMS is synchronous and a low level at the CLEAR
• CD40163BMS Binary with Synchronous Clear
input sets all four outputs low on the next positive CLOCK
edge. The CLEAR function of the CD40160BMS and • Internal Look-Ahead for Fast Counting
CD40161BMS is asychronous and a low level at the CLEAR • Carry Output for Cascading
input sets all four outputs low regardless of the state of the • Synchronously Programmable
CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD
input disables the counter and causes the output to agree • Clear Asynchronous Input (CD40160BMS, CD40161BMS)
with the setup data after the next CLOCK pulse regardless of • Clear Synchronous Input (CD40162BMS, CD40163BMS)
the conditions of the ENABLE inputs. • Synchronous Load Control Input
The carry look-ahead circuitry provides for cascading counters • Low Power TTL Compatibility
for n-bit synchronous applications without additional gating. • Standardized Symmetrical Output Characteristics
Instrumental in accomplishing this function are two count-enable
• 100% Tested for Quiescent Current at 20V
inputs and a carry output (COUT). Counting is enabled when
both PE and TE inputs are high. The TE input is fed forward to • Maximum Input Current of 1µA at 18V Over Full Package
enable COUT. This enabled output produces a positive output Temperature Range; 100nA at 18V and +25oC
pulses with a duration approximately equal to the positive portion • Noise Margin (Over Full Package Temperature Range):
of the Q1 output. This positive overflow carry pulse can be used - 1V at VDD = 5V
to enable successive cascaded stages. Logic transitions at the - 2V at VDD = 10V
PE or TE inputs may occur when the clock is either high or low. - 2.5V at VDD = 15V
The CD40160BMS through CD40163BMS types are functionally • 5V, 10V and 15V Parametric Ratings
equivalent to and pin-compatible with the TTL counter series • Meets All Requirements of JEDEC Tentative Standard No. 13B,
74LS160 through 74LS163 respectively. “Standard Specifications for Description of ‘B’ Series CMOS
Devices”
The CD40160BMS, CD40161BMS, CD40162BMS and
CD40163BMS are supplied in these 16 lead outline packages: Applications
CD40160 CD40161 CD40162 CD40163 • Programmable Binary and Decade Counting
Braze Seal DIP H4W H4X H4X H4W • Counter Control/Timers
Frit Seal DIP H1F H1F H1L H1F • Frequency Dividing
Ceramic Flatpack H6P H6W H6P H6W

Pinout Functional Diagram

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TOP VIEW 7 14
PE Q1
10
TE
CLEAR 1 16 VDD 13
1
CLEAR Q2
CLOCK 2 15 CARRY OUT
9
P1 3 14 Q1 LOAD
2 12
CLOCK Q3
P2 4 13 Q2
3
P3 5 12 Q3 P1
4 11
P4 6 11 Q4 P2 Q4
5
PE 7 10 TE P3
6 15
VDD = 16 P4 CARRY
VSS 8 9 LOAD
VSS = 8 OUT

4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance. . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125oC
Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K). . . . . . .500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being im- 3. For accuracy, voltage is measured differentially to VDD. Limit is
plemented. 0.050V max.
2. Go/No Go test with limits applied to inputs.

4-2
 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns
Clock to Q TPLH1 10, 11 +125oC, -55oC - 540 ns
Propagation Delay TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 450 ns
Clock to COut TPLH2 10, 11 +125oC, -55oC - 608 ns
Propagation Delay TPHL3 VDD = 5V, VIN = VDD or GND 9 +25oC - 250 ns
TE to COut TPLH3 10, 11 +125oC, -55oC - 338 ns
Propagation Delay TPHL4 VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns
CD40160BMS, 10, 11 +125oC, -55oC - 675 ns
CD40161BMS Clear to Q
Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTLH 10, 11 +125oC, -55oC - 270 ns
Maximum Clock Input Fre- FCL VDD = 5V, VIN = VDD or GND 9 +25oC 2 - MHz
quency 10, 11 +125oC, -55oC 1.48 - MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, - - 50 mV
55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - - 50 mV
55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, - 4.95 - V
55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, - 9.95 - V
55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -1.6 mA

4-3
 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - - 3 V
55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - 7 - V
55oC
Propagation Delay TPHL1 VDD = 10V 1, 2, 3 +25oC - 160 ns
Clock to Q TPLH1 VDD = 15V 1, 2, 3 +25oC - 120 ns
Propagation Delay TPHL2 VDD = 10V 1, 2, 3 +25oC - 190 ns
Clock to C Out TPLH2 VDD = 15V 1, 2, 3 +25oC - 140 ns
Propagation Delay TPHL3 VDD = 10V 1, 2, 3 +25oC - 110 ns
TE to C Out TPLH3 VDD = 15V 1, 2, 3 +25oC - 80 ns
Propagation Delay TPHL4 VDD = 10V 1, 2, 3 +25oC - 220 ns
CD40160BMS, VDD = 15V 1, 2, 3 +25oC - 160 ns
CD40161BMS Clear to Q
Transition Time TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns
TTLH VDD = 15V 1, 2, 3 +25oC - 80 ns
Maximum Clock Input Fre- FCL VDD = 10V 1, 2, 3 +25oC 5.5 - MHz
quency VDD = 15V 1, 2, 3 +25oC 8 - MHz
Maximum Clock Rise or TRCL VDD = 5V 1, 2, 3, 4 +25oC - 200 µs
Fall Time TFCL VDD = 10V 1, 2, 3, 4 +25oC - 70 µs
VDD = 15V 1, 2, 3, 4 +25oC - 15 µs
Minimum Data Hold Time TH VDD = 5V 1, 2, 3 +25oC - 0 ns
Clock Operation VDD = 10V 1, 2, 3 +25oC - 0 ns
VDD = 15V 1, 2, 3 +25oC - 0 ns
Minimum Clock Pulse TW VDD = 5V 1, 2, 3 +25oC - 170 ns
Width VDD = 10V 1, 2, 3 +25oC - 70 ns
Clock Operation
VDD = 15V 1, 2, 3 +25oC - 50 ns
Minimum Setup Time TS VDD = 5V 1, 2, 3 +25oC - 240 ns
Data to Clock VDD = 10V 1, 2, 3 +25oC - 90 ns
VDD = 15V 1, 2, 3 +25oC - 60 ns
Minimum Setup Time TS VDD = 5V 1, 2, 3 +25oC - 240 ns
Load to Clock VDD = 10V 1, 2, 3 +25oC - 90 ns
VDD = 15V 1, 2, 3 +25oC - 60 ns
Minimum Setup Time PE TS VDD = 5V 1, 2, 3 +25oC - 340 ns
to TE to Clock VDD = 10V 1, 2, 3 +25oC - 140 ns
VDD = 15V 1, 2, 3 +25oC - 100 ns
Minimum Clear Pulse TW VDD = 5V 1, 2, 3 +25oC - 170 ns
Width (CD40160BMS, VDD = 10V 1, 2, 3 +25oC - 70 ns
CD40161BMS)
VDD = 15V 1, 2, 3 +25oC - 50 ns
Minimum Setup Time TS VDD = 5V 1, 2, 3 +25oC - 340 ns
Clear to Clock VDD = 10V 1, 2, 3 +25oC - 140 ns
(CD40162BMS,
CD40163BMS) VDD = 15V 1, 2, 3 +25oC - 100 ns

Minimum Hold Time TH VDD = 5V 1, 2, 3 +25oC - 0 ns

Clear to Clock VDD = 10V 1, 2, 3 +25oC - 0 ns
(CD40162BMS,
CD40163BMS) VDD = 15V 1, 2, 3 +25oC - 0 ns

4-4
 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Minimum Clear Removal TREM VDD = 5V 1, 2, 3 +25oC - 200 ns
Time VDD = 10V 1, 2, 3 +25oC - 100 ns
(CD40160BMS,
CD40161BMS) VDD = 15V 1, 2, 3 +25oC - 70 ns

NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of
the output of the driving stage for the estimated capacitive load.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

4-5
 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
Static Burn-In 1 Note 1 11 - 15 1 - 10 16
Static Burn-In 2 Note 1 11 - 15 8 1 - 7, 9, 10, 16
Dynamic Burn-In Note 1 - 8 1, 7, 9, 10, 16 11 - 15 2-6 -
Irradiation Note 2 11 - 15 8 1 - 7, 9, 10, 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

Logic Diagrams
CD40160BMS AND CD40162BMS BCD DECADE COUNTERS

* * * * * * *
CD40160BMS 7 10 3 4 5 16 6
ASYNCHRONOUS PE TE P1 P2 P3 VDD P4
CLEAR Q1 Q1
Q4 Q4 Q1
LOAD*
9

CLOCK*
2

CLEAR*

Q1
CD40162BMS
SYNCHRONOUS
LOAD* CLEAR
LD PI Q1 LD PI Q2 LD PI Q3 LD PI Q4
9
T T T T
CLOCK* CL Q1 CL Q2 CL CL
CLR CLR CLR CLR
2 Q3 Q4

CLEAR*
1

*INPUTS PROTECTED BY VDD

CMOS PROTECTION NETWORK

14 Q1 13 Q2 12 Q3 11 Q4 15 COUT

VSS

FIGURE 1. LOGIC DIAGRAM FOR CD40160BMS AND CD40162BMS BCD DECADE COUNTERS

4-6
 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

Logic Diagrams (Continued)

CD40161BMS AND CD40163BMS BINARY COUNTERS

* * * * * *
CD40161BMS 7 10 3 16 4 5 6
ASYNCHRONOUS PE TE P1 VDD P2 P3 P4
CLEAR
Q1 Q1
Q1 Q2 Q2
LOAD* Q2
9

CLOCK* Q4
2 Q3
Q2

CLEAR*

CD40163BMS
SYNCHRONOUS Q1
CLEAR
LOAD*
9

LD PI Q1 LD PI Q2 LD PI Q3 LD PI Q4

CLOCK* T T T T
CL CL CL CL
2 CLR CLR CLR CLR
Q1 Q2 Q3 Q4
CLEAR*
1

*INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VDD

14 Q1 13 Q2 12 Q3 11 Q4 15 COUT

VSS

FIGURE 2. LOGIC DIAGRAM FOR CD40161BMS AND CD40163BMS BINARY COUNTERS

TRUTH TABLE

CLOCK CLR LOAD PE TE OPERATION

1 0 X X Preset
1 1 0 X NC
1 1 X 0 NC
1 1 1 1 Count
X 0 X X X Reset (CD40160BMS, CD40161BMS)
0 X X X Reset (CD40162BMS, CD40163BMS)
1 X X X NC (CD40162BMS, CD40163BMS)
1 = High Level X = Don’t Care
0 = Low Level NC = No Change

4-7
 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 4. MIMIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15 -10 -5 0 -15 -10 -5 0
0 0
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-5 -5

-10V -10V
-10 -10

-15V -15V
-15 -15

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

AMBIENT TEMPERATURE (TA) = +25oC

AMBIENT TEMPERATURE (TA) = +25oC
TRANSITION TIME (tTHL, tTLH) (ns)

300

200
SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 5V
200 150

10V 100
100 10V
15V
15V 50

0
0 20 40 60 80 100 0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNC- FIGURE 8. TYPICAL TRANSISTION TIME AS A FUNCTION OF
TION OF LOAD CAPACITANCE (CLOCK TO Q) LOAD CAPACITANCE

4-8
 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

Typical Performance Characteristics (Continued)

105 8
6
AMBIENT TEMPERATURE (TA)
o
4 = +25 C

POWER DISSIPATION (PD) (µW)

2
104 SUPPLY VOLTAGE (VDD)
8 = 15V
6
4
2
10V
103
8 10V
6
4
5V
2
102
8
6 CL = 50pF
4
CL = 15pF
2
10
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
1 10 102 103 104
CLOCK FREQUENCY (fCL) (kHz)
FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY

CLEAR (CD40160BMS)
ASYNCHRONOUS
CLEAR (CD40162BMS)

SYNCHRONOUS
LOAD

P1

P2
DATA INPUTS
P3

P4

CLOCK (CD40160BMS)

CLOCK (CD40162BMS)

PE
ENABLES
TE

Q1

Q2
OUTPUTS
Q3

Q4

CARRY OUT
0 7 8 9 0 1 2 3

COUNT INHIBIT
CLEAR PRESET

FIGURE 10. TIMING DIAGRAM FOR CD40160BMS, CD40162BMS

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 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

CLEAR (CD40161BMS)
ASYNCHRONOUS
CLEAR (CD40163BMS)

SYNCHRONOUS
LOAD

P1

P2
DATA INPUTS
P3

P4

CLOCK (CD40161BMS)

CLOCK (CD40163BMS)

PE
ENABLES
TE

Q1

Q2
OUTPUTS
Q3

Q4

CARRY OUT
0 12 13 14 15 0 1 2

COUNT INHIBIT
CLEAR PRESET

FIGURE 11. TIMING DIAGRAM FOR CD40161BMS AND CD40163BMS

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 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TN PN LD CL CLR

p CL
n

CL

p
n CL CL

p p
n n

p CL CL
p p QN
n
n n

CL CL
QN

FIGURE 12. DETAIL OF FLIP-FLOPS OF CD40160BMS AND CD40161BMS (ASYNCHRONOUS CLEAR)

TN CLR PN LD CL

p CL
n

CL
CL CL
p
n p p
n n

CL CL
p QN
p p
n
n n

CL CL
QN

FIGURE 13. DETAIL OF FLIP-FLOPS OF CD40162BMS AND CD40163BMS (SYNCHRONOUS CLEAR)

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 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

LOAD
VDD

P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 P3 P4

VDD
PE LD PE LD PE LD

TE CD TE CD TE CD

CLK CLR CLK CLR CLK CLR

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLOCK

CLEAR

FIGURE 14. CASCADED COUNTER PACKAGES IN THE PARALLEL-CLOCKED MODE

LOAD
VDD VDD VDD

P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 P3 P4

PE LD PE LD PE LD

TE CD TE CD TE CD

CLK CLR CLK CLR CLK CLR

CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLEAR

FIGURE 15. CASCADED COUNTER PACKAGES IN THE RIPPLE-CLOCKED MODE

Chip Dimensions and Pad Layout

Dimensions and pad layout for CD40160BMSH.
Dimensions and pad layout for CD40161BMS,
CD40162BMSH, and CD40163BMSH are identical.

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

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 CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com

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