CD4067BMS

CD4097BMS
CMOS Analog
December 1992 Multiplexers/Demultiplexers

Features Pinout
• High Voltage Types (20V Rating) CD4067BMS
• CD4067BMS Single 16 Channel Multiplexer/Demultiplexer TOP VIEW

• CD4097BMS Differential 8 Channel Multiplexer/Demulti-

plexer
COMMON OUT/IN 1 24 VDD
• Low ON Resistance: 125Ω (typ) Over 15Vp-p Signal
Input Range for VDD - VSS = 15V 7 2 23 8

• High OFF Resistance: Channel Leakage of ±10pA (typ) 6 3 22 9

at VDD - VSS = 18V 5 4 21 10

4 5 20 11
• Matched Switch Characteristics: RON = 5Ω (typ) for
* 19 12
*
VDD - VSS = 15V 3 6

• Very Low Quiescent Power Dissipation Under All Digi- 2 7 18 13

tal Control Input and Supply Conditions: 0.2µW (typ) 1 8 17 14

at VDD - VSS = 10V 0 9 16 15
• Binary Address Decoding on Chip A 10 15 INHIBIT

• 5V, 10V and 15V Parametric Ratings B 11 14 C

* CHANNEL VSS 12 13 D
• 100% Tested for Quiescent Current at 20V IN/OUT
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Standardized Symmetrical Output Characteristics

Applications
CD4097BMS
• Analog and Digital Multiplexing and Demultiplexing
TOP VIEW
• A/D and D/A Conversion
• Signal Gating
COMMON X
* When these devices are used as demultiplexers the “CHANNEL OUT/IN 1 24 VDD
IN/OUT” terminals are the outputs and the “COMMON OUT/IN” ter- 23 0
7 2
minals are the inputs.
6 3 22 1
Description 5 4 21 2
Y CHANNEL
4 5 20 3 IN/OUT
CD4067BMS and CD4097BMS CMOS analog multiplexers/ CHANNEL X
demultiplexers* are digitally controlled analog switches having IN/OUT 3 6 19 4
low ON Impedance, low OFF leakage current, and internal 2 7 18 5
address decoding. In addition, the ON resistance is relatively 1 8 17 COMMON Y
constant over the full input-signal range. OUT/IN
0 9 16 6 Y CHANNEL
The CD4067BMS is a 16 channel multiplexer with four binary A 10 15 7 IN/OUT
control inputs, A, B, C, D and an inhibit input, arranged so that B 11 14 C
any combination of the inputs selects one switch.
VSS 12 13 INHIBIT
The CD4097BMS is a differential 8 channel multiplexer having
three binary control inputs A, B, C and an inhibit input. The inputs
permit selection of one of eight pairs of switches. A logic “1”
present at the inhibit input turns all channels off.
The CD4067BMS and CD4097BMS are supplied in these 24
lead outline packages:
Braze Seal DIP *H4V †H6M
Frit Seal DIP *H1Z †HFN
Ceramic Flatpack *H4P †H4P
*CD4067B Only †CD4097B

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3190
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1
 Specifications CD4067BMS, CD4097BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125 C o

Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25 oC - 10 µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25o C -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
ON-State Resistance RON VDD = 5V 1 +25oC - 1050 Ω
RL = 10K Returned to VIS = VSS to VDD
2 +125oC - 1300 Ω
VDD - VSS/2
3 -55oC - 800 Ω
VDD = 10V 1 +25oC - 400 Ω
VIS = VSS to VDD
2 +125oC - 500 Ω
3 -55oC - 310 Ω
VDD = 15V 1 +25oC - 240 Ω
VIS = VSS to VDD
2 +125oC - 320 Ω
3 -55oC - 220 Ω
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional (Note 4) F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V = VIS Thru 1K 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2) VEE = VSS
RL = 1K to VSS
Input Voltage High VIH 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
|ISS| < 2µA on all
(Note 2)
OFF Channels
Input Voltage Low VIL VDD = 15V = VIS Thru 1K 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VEE = VSS
RL = 1K to VSS
Input Voltage High VIH 1, 2, 3 +25oC, +125oC, -55oC 11 - V
|ISS| < 2µA on all
(Note 2)
OFF Channels

7-2
 Specifications CD4067BMS, CD4097BMS

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
OFF Channel Leakage IOZL VOUT = 0V VDD = 20V 1 +25oC -0.1 - µA
Any Channel OFF or All
2 +125oC -1.0 - µA
Channels OFF
(Common OUT/IN) VDD = 18V 3 -55oC -0.1 - µA
IOZH VOUT = VDD VDD = 20V 1 +25oC - 0.1 µA
2 +125oC - 1.0 µA
VDD = 18V 3 -55oC - 0.1 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs. 4. VDD = 2.8/3.0V, RL = 200K
VDD = 20V/18V, RL = 10K - 25K

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL VDD = 5V, VIN = VDD or GND 9 +25oC - 60 ns
(Signal In to Output) TPLH (Notes 1, 2)
10, 11 +125oC, -55oC - 81 ns
Propagation Delay TPZH VDD = 5V, VIN = VDD or GND 9 +25oC - 650 ns
Address or Inhibit to TPZL (Notes 2, 3)
10, 11 +125oC, -55oC - 878 ns
Signal Out.
(Channel Turning On)
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 10K, Input TR, TF < 20ns.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 600 µA
Input Voltage Low VIL VDD = VIS = 10V 1, 2 +25oC, +125oC, - 3 V
VEE = VSS -55oC
RL = 1K to VSS
Input Voltage High VIH 1, 2 +25oC, +125oC, +7 - V
IIS < 2µA
-55oC
ON OFF Channel
Propagation Delay TPZH VDD = 10V 1, 2, 4 +25oC - 270 ns
Address or Inhibit to TPZL
VDD = 15V 1, 2, 4 +25oC - 190 ns
Signal Out.
(Channel Turning On)
Propagation Delay TPHL VDD = 10V VIS = VDD or 1, 2, 3 +25oC - 30 ns
Signal In to Output TPLH GND
VDD = 15V 1, 2, 3 +25oC - 20 ns

7-3
 Specifications CD4067BMS, CD4097BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Propagation Delay TPHZ VDD = 5V 1, 2, 5 +25oC - 440 ns
Address or Inhibit to TPLZ o
VDD = 10V 1, 2, 5 +25 C - 180 ns
Signal Out
(Channel Turning Off) VDD = 15V 1, 2, 5 +25oC - 130 ns
o
Input Capacitance CIN Any Address or Inhibit 1, 2 +25 C - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 10K, Input TR, TF < 20ns.
5. CL = 50pF, RL = 300Ω, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 o
+25 C - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 o
+25 C - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
ON Resistance RONDEL10 ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A, RONDEL10
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11

7-4
 Specifications CD4067BMS, CD4097BMS

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
PART NUMBER CD4067BMS
Static Burn-In 1 Note 1 1 2 - 23 24
Static Burn-In 2 Note 1 1 12 2 - 11, 13 - 24
Dynamic Burn-In Note 1 - 12, 15 24 1 2 - 9, 16 - 23 10, 11, 13, 14
(Note 3)
Irradiation Note 2 1 12 2 - 11, 13 - 24
PART NUMBER CD4097BMS
Static Burn-In 1 Note 1 1, 17 2 - 16, 18 - 23 24
Static Burn-In 2 Note 1 1, 17 12 2 - 11, 13 - 16,
18 - 24
Dynamic Burn-In Note 1 - 12, 13 24 1, 17 2 - 9, 15, 16, 10, 11, 14
18 - 23 (Note 4)
Irradiation Note 2 1, 17 12 2 - 11, 13 - 16,
18 - 24
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
3. Pin 10 is at 14kHz, Pin 11 is at 7kHz, Pin 13 is at 1.7kHz, Pin 14 is at 3.5kHz
4. Pin 10 is at 14kHz, Pin 11 is at 7kHz, Pin 14 is at 3.5kHZ

7-5
 CD4067BMS, CD4097BMS

Functional Diagram

INHIBIT
1 of 8 DECODERS
3

INHIBIT
1 of 16 DECODERS 0
4 X
1 OUT/IN
X
IN/OUT
0
1 OUT/IN 7
VDD = 24
VSS = 12 0
IN/OUT Y
15 1 OUT/IN
Y
VDD = 24 VSS = 12 IN/OUT

CD4067 CD4097

CD4067 TRUTH TABLE CD4097 TRUTH TABLE

SELECTED SELECTED
A B C D Inh CHANNEL A B C Inh CHANNEL
X X X X 1 None X X X 1 None
0 0 0 0 0 0 0 0 0 0 0X, 0Y
1 0 0 0 0 1 1 0 0 0 1X, 1Y
0 1 0 0 0 2 0 1 0 0 2X, 2Y
1 1 0 0 0 3 1 1 0 0 3X, 3Y
0 0 1 0 0 4 0 0 1 0 4X, 4Y
1 0 1 0 0 5 1 0 1 0 5X, 5Y
0 1 1 0 0 6 0 1 1 0 6X, 6Y
1 1 1 0 0 7 1 1 1 0 7X, 7Y
0 0 0 1 0 8
tr = 20ns tf = 20ns
1 0 0 1 0 9
90% 90%
0 1 0 1 0 10
50% 50%
1 1 0 1 0 11 10% 10%

tPZL TURN-ON
0 0 1 1 0 12
TIME
90%
1 0 1 1 0 13
50%
0 1 1 1 0 14 10% 10%
1 1 1 1 0 15 TURN-OFF TIME tPLZ

FIGURE 1. WAVEFORM CHANNEL BEING TURNED ON, OFF

tr = 20ns tf = 20ns

90% 90%
50% 50%
10%
10%

90%

10%
TURN-ON
tPHZ TURN-OFF TIME
TIME tPZH

FIGURE 2. PROPAGATION DELAY WAVEFORM, CHANNEL

BEING TURNED OFF, ON

7-6
 CD4067BMS, CD4097BMS

16
CHANNEL IN/OUT
VDD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

24 16 17 18 19 20 21 22 23 2 3 4 5 6 7 8 9

TG

TG

TG

TG

TG

TG
BINARY 1 OF 16 DECODERS WITH INHIBIT

* 10
A TG

* 11
B TG

* 14 1
C TG COMMON
OUT/IN
* 13
D TG

* 15

INHIBIT TG

TG

TG

TG

TG

TG

VDD
*ALL INPUTS PROTECTED BY
12 CMOS PROTECTION NETWORK

VSS

VSS

FIGURE 3. CD4067BMS LOGIC DIAGRAM

7-7
 CD4067BMS, CD4097BMS

8 8
CHANNEL CHANNEL
IN/OUT Y IN/OUT X
VDD 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

24 15 16 18 19 20 21 22 23 2 3 4 5 6 7 8 9

TG

TG

TG

TG

1
TG COMMON
X OUT/IN

TG
BINARY 1 OF 8 DECODERS WITH INHIBIT

* 10
A TG

* 11
B TG

* 14
C TG

* 13

INHIBIT TG

TG

TG

17
TG COMMON
Y OUT/IN

TG

TG

TG

VDD
*ALL INPUTS PROTECTED BY
12 CMOS PROTECTION NETWORK

VSS

VSS

FIGURE 4. CD4097BMS LOGIC DIAGRAM

7-8
 CD4067BMS, CD4097BMS

Typical Performance Characteristics

SUPPLY VOLTAGE (VDD - VSS) = 5V SUPPLY VOLTAGE (VDD - VSS) = 10V

CHANNEL ON RESISTANCE (RON) (Ω)

CHANNEL ON RESISTANCE (RON) (Ω)

600 300
AMBIENT TEMPERATURE
(TA) = +125oC AMBIENT TEMPERATURE
500 250 (TA) = +125oC

400 200

+25oC
300 150

+25oC -55oC
200 100

-55oC
100 50

0 0
-4 -3 -2 -1 0 1 2 3 4 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V) INPUT SIGNAL VOLTAGE (VIS) (V)

FIGURE 5. TYPICAL ON RESISTANCE vs INPUT SIGNAL FIGURE 6. TYPICAL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES) VOLTAGE (ALL TYPES)

AMBIENT TEMPERATURE SUPPLY VOLTAGE (VDD - VSS) = 15V

CHANNEL ON RESISTANCE (RON) (Ω)

CHANNEL ON RESISTANCE (RON) (Ω)

(TA) = +25oC
600 300

500 SUPPLY VOLTAGE (VDD - VSS) = 5V 250

400 200
AMBIENT TEMPERATURE
(TA) = +125oC
300 150

200 100 +25oC

10V
100 50 -55oC
15V

0 0
-10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0
INPUT SIGNAL VOLTAGE (VIS) (V) INPUT SIGNAL VOLTAGE (VIS) (V)

FIGURE 7. TYPICAL ON RESISTANCE vs INPUT SIGNAL FIGURE 8. TYPICAL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES) VOLTAGE (ALL TYPES)

7-9
 CD4067BMS, CD4097BMS

Chip Dimensions and Pad Layouts

CD4067BMSH CD4097BMSH
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)

Special Considerations
In applications where separate power sources are used to channel will lose 3 to 4% of its voltage at the moment the
drive VDD and the signal inputs, the VDD current capability channel turns on or off. This loss of voltage is essentially
should exceed VDD/RL (RL = effective external load). This independent of the address or inhibit signal transition time, if
provision avoids permanent current flow or clamp action on the transition time is less than 1 - 2µs. When the inhibit sig-
the VDD supply when power is applied or removed from the nal turns a channel off, there is no charge dumping to VSS.
CD4067BMS or CD4097BMS. Rather, there is a slight rise in the channel voltage level
(65mV typ.) due to capacitive coupling from inhibit input to
When switching from one address to another, some of the
channel input or output. Address inputs also couple some
ON periods of the channels of the multiplexers will overlap
voltage steps onto the channel signal levels.
momentarily, which may be objectionable in certain applica-
tions. Also when a channel is turned on or off by an address In certain applications, the external load resistor current may
input, there is a momentary conductive path from the chan- include both VDD and signal-line components. To avoid
nel to VSS, which will dump some charge from any capacitor drawing VDD current when switch current flows into the
connected to the input or output of the channel. The inhibit transmission gate inputs, the voltage drop across the bidi-
input turning on a channel will similarly dump some charge rectional switch must not exceed 0.8 volt (calculated from
to VSS. RON values shown in ELECTRICAL CHARACTERISTICS
CHART - Table 1). no VDD current will flow through RL if the
The amount of charge dumped is mostly a function of the
switch current flows into terminal 1 on the CD4067BMS, ter-
signal level above VSS. Typically, at VDD - VSS = 10V, a
minals 1 and 17 on the CD4097BMS.
100pF capacitor connected to the input or output of the
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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