CD4027BMS

CMOS Dual J-K

December 1992
Master-Slave Flip-Flop

Features Pinout
• High Voltage Type (20V Rating) CD4027BMS
TOP VIEW
• Set - Reset Capability
• Static Flip-Flop Operation - Retains State Indefinitely
Q2 1 16 VDD
with Clock Level Either “High” or “Low”
Q2 2 15 Q1
• Medium Speed Operation - 16MHz (typ.) Clock Toggle
CLOCK 2 3 14 Q1
Rate at 10V
RESET 2 4 13 CLOCK 1
• Standardized Symmetrical Output Characteristics
K2 5 12 RESET 1
• 100% Tested For Quiescent Current at 20V J2 6 11 K1

• Maximum Input Current of 1µA at 18V Over Full SET 2 7 10 J1

Package-Temperature Range; VSS 8 9 SET 1
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V Functional Diagram
- 2.5V at VDD = 15V
VDD
• 5V, 10V and 15V Parametric Ratings SET 1 9 16
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of J1 10 15 Q1
‘B’ Series CMOS Devices” K1 11
F/F1
CLOCK1 13 14 Q1
Applications
RESET1 12
• Registers, Counters, Control Circuits SET2 7

J2 6
Description 1 Q2
K2 5
CD4027BMS is a single monolithic chip integrated circuit con- F/F2
CLOCK2 3 2 Q2
taining two identical complementary-symmetry J-K master-
slave flip-flops. Each flip-flop has provisions for individual J, K,
Set Reset, and Clock input signals. Buffered Q and Q signals 4
RESET 2 8
are provided as outputs. This input-output arrangement pro-
VSS
vides for compatible operation with the Intersil CD4013B dual D
type flip-flop.
The CD4027BMS is useful in performing control, register, and
toggle functions. Logic levels present at the J and K inputs
along with internal self-steering control the state of each flip-
flop; changes in the flip-flop state are synchronous with the pos-
itive-going transition of the clock pulse. Set and reset functions
are independent of the clock and are initiated when a high level
signal is present at either the Set or Reset input.
The CD4027BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP H4T
Frit Seal DIP H1E
Ceramic Flatpack H6W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3302
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-780
 Specifications CD4027BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125 C o

Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25 oC - 2 µA
2 +125oC - 200 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 2 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125o C -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs.

7-781
 Specifications CD4027BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +25oC - 300 ns
Clock To Q, Q TPLH1 10, 11 +125oC, -55oC - 405 ns
Propagation Delay TPLH2 VDD = 5V, VIN = VDD or GND 9 +25oC - 300 ns
Set To Q Reset To Q 10, 11 +125oC, -55oC - 405 ns
o
Propagation Delay TPHL3 VDD = 5V, VIN = VDD or GND 9 +25 C - 400 ns
Set To Q, Reset To Q 10, 11 +125oC, -55oC - 540 ns
Transition Time TTLH VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTHL 10, 11 +125oC, -55oC - 270 ns
Maximum Clock Input FCL VDD = 5V, VIN = VDD or GND 9 +25oC 3.5 - MHz
Frequency 10, 11 +125oC, -55oC 3.5/1.35 - MHz
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 1 µA
+125oC - 30 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 2 µA
+125oC - 60 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 2 µA
+125oC - 120 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 4.95 - V
-55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 9.95 - V
-55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -1.6 mA

7-782
 Specifications CD4027BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - 3 V
-55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, 7 - V
-55oC
Propagation Delay TPHL1 VDD = 10V 1, 2, 3 +25oC - 130 ns
Clock To Q, Q TPLH1 o
VDD = 15V 1, 2, 3 +25 C - 90 ns
o
Propagation Delay TPLH2 VDD = 10V 1, 2, 3 +25 C - 130 ns
Set To Q, Reset To Q o
VDD = 15V 1, 2, 3 +25 C - 90 ns
Propagation Delay TPHL3 VDD = 10V 1, 2, 3 +25oC - 170 ns
Set To Q, Reset To Q
VDD = 15V 1, 2, 3 +25oC - 120 ns
o
Transition Time TTHL VDD = 10V 1, 2, 3 +25 C - 100 ns
TTLH
VDD = 15V 1, 2, 3 +25oC - 80 ns
Maximum Clock Input FCL VDD = 10V 1, 2, 3 +25oC 8 - MHz
Frequency Toggle Mode
VDD = 15V 1, 2, 3 +25oC 12 - MHz
Input TR, TF = 5ns
Minimum Data Setup TS VDD = 5V 1, 2, 3 +25oC - 200 ns
Time
VDD = 10V 1, 2, 3 +25oC - 75 ns
VDD = 15V 1, 2, 3 +25oC - 50 ns
Minimum Set or Reset TW VDD = 5V 1, 2, 3 +25oC - 180 ns
Pulse Width
VDD = 10V 1, 2, 3 +25oC - 80 ns
VDD = 15V 1, 2, 3 +25oC - 50 ns
Minimum Clock Pulse TW VDD = 5V 1, 2, 3 +25oC - 140 ns
Width
VDD = 10V 1, 2, 3 +25oC - 60 ns
VDD = 15V 1, 2, 3 +25oC - 40 ns
Clock Input Rise Or Fall TRCL VDD = 5V 1, 2, 3, 4 +25oC - 45 µs
Time (Note 5) TFCL
VDD = 10V 1, 2, 3, 4 +25oC - 5 µs
VDD = 15V 1, 2, 3, 4 +25oC - 2 µs
Input Capacitance CIN 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded in a parallel clocked operation, trCL should be made less than or equal to the sum of the fixed propa-
gation delay time at 15pF and the transition time of the output driving stage for the estimated capacitive load.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 µA

7-783
 Specifications CD4027BMS

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT
Supply Current - MSI-1 IDD ± 0.2µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD
MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

7-784
 CD4027BMS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
Static Burn-In 1 1, 2, 14, 15 3 - 13 16
Note 1
Static Burn-In 2 1, 2, 14, 15 8 3 - 7, 9 - 13, 16
Note 1
Dynamic Burn- - 4, 7 - 9, 12 5, 6, 10, 11, 16 12, 14, 15 3, 13
In Note 2
Irradiation 1, 2, 14, 15 8 3 - 7, 9 - 13, 16
Note 3
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 4.75K ± 5%, VDD = 18V ± 0.5V
3. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

Logic Diagram
RESET
*4(12)
Q
CL CL 2(14)
J
*6(10) MASTER
p p
SLAVE Q
TG TG 1(15)
n n
K
*5(11) CL CL
CL CL

p p
TG TG
n n

SET CL CL VDD
*7(9)

CL CL * ALL INPUTS ARE

PROTECTED BY
*3(13) CMOS PROTECTION VSS
CLOCK NETWORK

LOGIC DIAGRAM AND TRUTH TABLE FOR CD4027BMS (ONE OF TWO IDENTICAL J-K FLIP-FLOPS)

TRUTH TABLE

PRESENT STATE NEXT STATE

INPUTS OUTPUT OUTPUTS
J K S R Q CL* Q Q
1 X 0 0 0 1 0
X 0 0 0 1 1 0
0 X 0 0 0 0 1
X 1 0 0 1 0 1
X X 0 0 X No Change
X X 1 0 X X 1 0
X X 0 1 X X 0 1
X X 1 1 X X 1 1
Logic 1 = High Level * = Level change
Logic 0 = Low Level X = Don’t care

7-785
 CD4027BMS

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 2. MINIMUM N OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15 -10 -5 0 -15 -10 -5 0
0 0
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10 -5

-15

-10V -10V
-20 -10

-25

-15V -15V
-30 -15

FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS

104 8 CD = 15pF
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

6
CL = 50pF AMBIENT TEMPERATURE (TA) = +25oC
4
DISSIPATION PER DEVICE (PD) (µW)

250
2

10 3 SUPPLY VOLTAGE
8 (VDD) = 15V
6
4
200
10V SUPPLY VOLTAGE (VDD) = 5V
2

102 10V 150

8
6
4 5V
2 100
10V
10
8
6
4 50
AMBIENT TEMPERATURE (TA) = +25oC 15V
2
INPUT tr = tf = 20ns
1
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
0 20 40 60 80 100
102 103 104 105 106 107
INPUT FREQUENCY (fI) (Hz) LOAD CAPACITANCE (CL) (pF)
FIGURE 5. TYPICAL POWER DISSIPATION vs FREQUENCY FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE (CLOCK OR SET TO Q, CLOCK OR
RESET TO Q)

7-786
 CD4027BMS

Typical Performance Characteristics (Continued)

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

trl tf = 5ns
250 CL = 50pF

CLOCK FREQUENCY (fCL) (MHz)

30
200
25
SUPPLY VOLTAGE (VDD) = 5V
150 20

15
100
10V
10
50 15V
5

0 20 40 60 80 100 0 5 10 15 20
LOAD CAPACITANCE (CL) (pF) SUPPLY VOLTAGE (VDD) (V)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD FIGURE 8. TYPICAL MAXIMUM CLOCK FREQUENCY vs
CAPACITANCE (SET TO Q, OR RESET TO Q) SUPPLY VOLTAGE (TOGGLE MODE)

Chip Dimensions and Pad Layout

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

787