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Automotive PMIC for Safety Systems

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Automotive PMIC for Safety Systems

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TPS6593-Q1

SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023

TPS6593-Q1 Power Management IC (PMIC) with 5 BUCKs and 4 LDOs for Safety-
Relevant Automotive Applications
• One low-dropout (LDO) linear regulator with low-
1 Features noise performance
• Qualified for automotive applications – 1.2 V to 3.3 V output voltage range in 25-mV
• AEC-Q100 qualified with the following results: steps
– Device operates from 3 V to 5.5 V input supply – 300 mA output current capability with short-
– Device temperature grade 1: –40°C to +125°C circuit and over-current protection
ambient operating temperature range • Configurable power sequence control in non-
– Device HBM classification level 2 volatile memory (NVM):
– Device CDM classification level C4A – Configurable power-up and power-down
• Functional Safety-Compliant sequences between power states
– Developed for functional safety applications – Digital output signals can be included in the
– Documentation to aid ISO26262 and IEC61508 power sequences
system design available upon product release – Digital input signals can be used to trigger
– Systematic capability up to ASIL-D and SIL-3 power sequence transitions
– Hardware integrity up to ASIL-B and SIL-2 – Configurable handling of safety-relevant errors
– Input supply voltage monitor • 32-kHz crystal oscillator with option to output a
– Under/overvoltage monitors and over-current buffered 32-kHz clock output
monitors on all output supply rails • Real-time clock (RTC) with alarm and periodic
– Watchdog with selectable trigger / Q&A mode wake-up mechanism
– Two error signal monitors (ESMs) with • One SPI or two I2C control interfaces, with
selectable level / PWM mode second I2C interface dedicated for Q&A watchdog
– Thermal monitoring with high temperature communication
warning and thermal shutdown • Package option:
– Bit-integrity (CRC) error detection on internal – 8-mm × 8-mm 56-pin VQFNP with 0.5-mm pitch
configuration registers and non-volatile memory
(NVM) 2 Applications
• Low-power consumption • Automotive infotainment and digital cluster,
– 2 μA typical shutdown current navigation systems, telematics, body electronics
– 7 μA typical in back up supply only mode and lighting
– 20 μA typical in low power standby mode • Advanced driver assistance system (ADAS)
• Five step-down switched-mode power supply • Industrial control and automation
(BUCK) regulators:
3 Description
– 0.3 V to 3.34 V output voltage range in 5, 10, or
20-mV steps The TPS6593-Q1 device provides four flexible multi-
– One with 4 A, three with 3.5 A, and one with 2 phase configurable BUCK regulators with 3.5 A output
A output current capability current per phase, and one additional BUCK regulator
– Flexible multi-phase capability for four BUCKs: with 2 A output current.
up to 14 A output current from a single rail Table 3-1. Device Information Table
– Short-circuit and over-current protection
PART NUMBER(1) PACKAGE BODY SIZE (NOM)
– Internal soft-start for in-rush current limitation
TPS6593-Q1 VQFNP (56) 8.00 mm × 8.00 mm
– 2.2 MHz / 4.4 MHz switching frequency
– Ability to synchronize to external clock input (1) See the orderable addendum at the end of the data sheet for
• Three low-dropout (LDO) linear regulators with all available packages.
configurable bypass mode
– 0.6 V to 3.3 V output voltage range with 50-mV
steps in linear regulation mode
– 1.7 V to 3.3 V output voltage range in bypass
mode
– 500 mA output current capability with short-
circuit and over-current protection

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS6593-Q1
SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023 www.ti.com

nINT
I2C and SPI
128-kHz RC Oscillator
OSC32KCAP
nPWRON/ENABLE
Interrupt Handler OSC32KIN
VBACKUP 32-kHz Crystal Oscillator OSC32KOUT
Backup Supply
VCCA Management WAKEn Real-Time Clock SYNCCLKOUT/CLK32KOUT
nSLEEPn (RTC) With Calendar
VOUT_LDOVRTC LDO Bandgap 20-MHz Monitor Oscillator
Clock Controller
RTC VRTC
Fixed & Monitor
20-MHz RC Oscillator
State Machine
VOUT_LDOVINT LDO Bandgap (FFSM) Trigger Mode or
FSD
INT VINT Question and Answer Clock
Pre- (Q&A) Watchdog DPLL with SYNCCLKIN
Dividers and
Configurable nERR_MCU, SSM (GPIO10)
VIN Monitor Mux
State nERR_SoC Level or PWM Mode
OVP Machine
Bandgap Error Signal Monitors
UVLO Single or Multiphase
(PFSM) (MCU, SoC)
BUCK1 PVIN_B1
Power-Good Monitor
Resource Controller
for Buck and LDO 3.5 A SW_B1
Regulators SRAM Over-Current Monitor,
PVIN_B5
Power Good Short Circuit Monitor, FB_B1
Controller & Monitor SW Short Monitor
VIN Monitor
OVP
Bandgap
UVLO
Registers BUCK2 PVIN_B2
CRC
Thermal Monitor Thermal I2C/SPI/ 3.5 A SW_B2
Controller GPIO/ Over-Current Monitor,
Register Map Short Circuit Monitor,
SPMI FB_B2
VOUT_LDO1 LDO1, Bypass SW Short Monitor
Non-Volatile Memory
LBIST (NVM)
PVIN_LDO12 Over-Current Monitor,
Short Circuit Monitor BUCK3 PVIN_B3

2
LDO2, Bypass SPMI I C and SPI 3.5 A SW_B3
Over-Current Monitor,
Over-Current Monitor, BIST and CRC CRC Short Circuit Monitor,
VOUT_LDO2 FB_B3
Short Circuit Monitor SW Short Monitor
Target Control I2C1 I2C2 SPI
PVIN_LDO3 LDO3, Bypass
BUCK4 PVIN_B4
VOUT_LDO3 Over-Current Monitor, 4 A (Single-Phase)
Short Circuit Monitor or 3.5 A SW_B4
nERR_MCU (GPIO7)

SDA_I2C2 (GPIO2)
SCL_I2C2 (GPIO1)

Over-Current Monitor,
nERR_SoC (GPIO3)

SDO_SPI (GPIO2)
(GPIO2 or GPIO11)

PGOOD (GPIO9)

CS_SPI (GPIO1)
SDATA (GPIO6)

PVIN_LDO4 LDO4 Short Circuit Monitor,

SCLK (GPIO5)

FB_B4
(Low Noise) SW Short Monitor
TRIG_WDOG

SDA_I2C1
SCL_I2C1

Over-Current Monitor,
CLK_SPI
SDI_SPI

VOUT_LDO4
Short Circuit Monitor
BUCK5 PVIN_B5

GPIO Control 2A SW_B5

Over-Current Monitor,
Short Circuit Monitor, FB_B5
SW Short Monitor
SCL_I2C1/CLK_SPI

VIO_IN Safety
SDA_I2C1/SDI_SPI

AMUXOUT
Bandgap

nRST_OUT
GPIO10

GPIO11
GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

EN_DRV

VCCA

Copyright © 2019, Texas Instruments Incorporated

Functional Diagram

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Table of Contents
1 Features............................................................................1 7.18 I/O Pullup and Pulldown Resistance.......................37
2 Applications..................................................................... 1 7.19 I2C Interface............................................................37
3 Description.......................................................................1 7.20 Serial Peripheral Interface (SPI)............................. 39
4 Revision History.............................................................. 3 7.21 Typical Characteristics............................................ 40
5 Description (continued).................................................. 4 8 Detailed Description......................................................43
6 Pin Configuration and Functions...................................5 8.1 Overview................................................................... 43
6.1 Digital Signal Descriptions........................................ 10 8.2 Functional Block Diagram......................................... 44
7 Specifications................................................................ 17 8.3 Feature Description...................................................45
7.1 Absolute Maximum Ratings...................................... 17 8.4 Device Functional Modes........................................118
7.2 ESD Ratings............................................................. 18 8.5 Control Interfaces....................................................151
7.3 Recommended Operating Conditions.......................18 8.6 Configurable Registers........................................... 158
7.4 Thermal Information..................................................18 8.7 Register Maps.........................................................160
7.5 General Purpose Low Drop-Out Regulators 9 Application and Implementation................................ 358
(LDO1, LDO2, LDO3)..................................................20 9.1 Application Information........................................... 358
7.6 Low Noise Low Drop-Out Regulator (LDO4)............ 21 9.2 Typical Application.................................................. 358
7.7 Internal Low Drop-Out Regulators (LDOVRTC, 9.3 Power Supply Recommendations...........................378
LDOVINT)....................................................................22 9.4 Layout..................................................................... 378
7.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 10 Device and Documentation Support........................381
Regulators................................................................... 23 10.1 Device Support..................................................... 381
7.9 Reference Generator (BandGap)..............................29 10.2 Device Nomenclature............................................381
7.10 Monitoring Functions ..............................................30 10.3 Documentation Support........................................ 382
7.11 Clocks, Oscillators, and PLL................................... 32 10.4 Receiving Notification of Documentation Updates382
7.12 Thermal Monitoring and Shutdown......................... 33 10.5 Support Resources............................................... 382
7.13 System Control Thresholds.....................................34 10.6 Trademarks........................................................... 382
7.14 Current Consumption..............................................34 10.7 Electrostatic Discharge Caution............................382
7.15 Backup Battery Charger..........................................35 10.8 Glossary................................................................382
7.16 Digital Input Signal Parameters.............................. 35 11 Mechanical, Packaging, and Orderable
7.17 Digital Output Signal Parameters ...........................36 Information.................................................................. 382

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2022) to Revision B (September 2023) Page
• Changed the device status from Advance Information to Production Data ....................................................... 1

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5 Description (continued)
All of the BUCK regulators can be synchronized to an internal 2.2-MHz or 4.4-MHz or an external 1-MHz, 2-MHz,
or 4-MHz clock signal. To improve the EMC performance, an integrated spread-spectrum modulation can be
added to the synchronized BUCK switching clock signal. This clock signal can also be made available to external
devices through a GPIO output pin. The device provides four LDOs: three with 500-mA capability, which can be
configured as load switches; one with 300-mA capability and low-noise performance.
Non-volatile memory (NVM) is used to control the default power sequences and default configurations, such
as output voltage and GPIO configurations. The NVM is pre-programmed to allow start-up without external
programming. Most static configurations, stored in the register map of the device, can be changed from the
default through SPI or I2C interfaces to configure the device to meet many different system needs. The NVM
contains a bit-integrity-error detection feature (CRC) to stop the power-up sequence if an error is detected,
preventing the system from starting in an unknown state.
The TPS6593-Q1 includes a 32-kHz crystal oscillator, which generates an accurate 32-kHz clock for the
integrated RTC module. A backup-battery management provides power to the crystal oscillator and the real-time
clock (RTC) module from a coin cell battery or a super-cap in the event of power loss from the main supply.
The TPS6593-Q1 device includes protection and diagnostic mechanisms such as voltage monitoring on the
input supply, voltage monitoring on all BUCK and LDO regulator outputs, register and interface CRC, current-
limit, short-circuit protection, thermal pre-warning, and over-temperature shutdown. The device also includes a
Q&A or trigger mode watchdog to monitor for MCU software lockup, and two error signal monitor (ESM) inputs
with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can
notify the processor of these events through the interrupt handler, allowing the MCU to take action in response.

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6 Pin Configuration and Functions

Figure 6-1 shows the 56-pin RWE plastic quad-flatpack no-lead (VQFNP) pin assignments and thermal pad.

PVIN_B4

PVIN_B3
GPIO11
SW_B4

SW_B4

SW_B3

SW_B3
VIO_IN
FB_B4

FB_B3

GPIO4

GPIO3
GND

GND
56

43
AMUXOUT 1 42 GPIO10

VOUT_LDOVINT 2 41 GPIO8

VOUT_LDOVRTC 3 40 OSC32KCAP

VCCA 4 39 OSC32KOUT

REFGND1 5 38 OSC32KIN

REFGND2 6 37 FB_B5

VOUT_LDO4 7 Thermal 36 VBACKUP

Pad
PVIN_LDO4 8 (GND) 35 PVIN_B5

VOUT_LDO3 9 34 SW_B5

PVIN_LDO3 10 33 GPIO2

VOUT_LDO2 11 32 GPIO1

PVIN_LDO12 12 31 SCL_I2C1/SCK_SPI

VOUT_LDO1 13 30 SDA_I2C1/SDI_SPI

nINT 14 29 EN_DRV
15

28
GPIO7

nRSTOUT
PVIN_B2

nPWRON/ENABLE

PVIN_B1
SW_B2

SW_B2

GPIO9

FB_B2

FB_B1

GPIO5

GPIO6

SW_B1

Not to scale

Figure 6-1. 56-Pin RWE (VQFNP) Package, 0.5-mm Pitch, With Thermal Pad (Top View)

Table 6-1. Pin Attributes

PIN CONNECTION IF
I/O DESCRIPTION
NAME NO. NOT USED

STEP-DOWN CONVERTERS (BUCKs)

Output voltage-sense (feedback) input for BUCK1 or differential voltage-
FB_B1 22 I sense (feedback) positive input for BUCK12/123/1234 in multi-phase Ground
configuration.
Output voltage-sense (feedback) input for BUCK2 or differential voltage-
FB_B2 21 I sense (feedback) negative input for BUCK12/123/1234 in multi-phase Ground
configuration.
Output voltage-sense (feedback) input for BUCK3 or differential voltage-
FB_B3 49 I Ground
sense (feedback) positive input for BUCK34 in dual-phase configuration.
Output voltage-sense (feedback) input for BUCK4 or differential voltage-
FB_B4 50 I Ground
sense (feedback) negative input for BUCK34 in dual-phase configuration.
FB_B5 37 I Output voltage-sense (feedback) input for BUCK5 Ground
PVIN_B1 26 I Power input for BUCK1 VCCA
PVIN_B2 17 I Power input for BUCK2 VCCA
PVIN_B3 45 I Power input for BUCK3 VCCA
PVIN_B4 54 I Power input for BUCK4 VCCA
PVIN_B5 35 I Power input for BUCK5 VCCA

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Table 6-1. Pin Attributes (continued)

PIN CONNECTION IF
I/O DESCRIPTION
NAME NO. NOT USED

SW_B1 27 O Switch node of BUCK1 Floating

SW_B1 28 O Switch node of BUCK1 Floating
SW_B2 15 O Switch node of BUCK2 Floating
SW_B2 16 O Switch node of BUCK2 Floating
SW_B3 43 O Switch node of BUCK3 Floating
SW_B3 44 O Switch node of BUCK3 Floating
SW_B4 55 O Switch node of BUCK4 Floating
SW_B4 56 O Switch node of BUCK4 Floating
SW_B5 34 O Switch node of BUCK5 Floating
LOW-DROPOUT REGULATORS
PVIN_LDO3 10 I Power input voltage for LDO3 regulator VCCA
PVIN_LDO4 8 I Power input voltage for LDO4 regulator VCCA
PVIN_LDO12 12 I Power input voltage for LDO1 and LDO2 regulator VCCA
VOUT_LDO1 13 O LDO1 output voltage Floating
VOUT_LDO2 11 O LDO2 output voltage Floating
VOUT_LDO3 9 O LDO3 output voltage Floating
VOUT_LDO4 7 O LDO4 output voltage Floating
LOW-DROPOUT REGULATORS (INTERNAL)
LDOVINT output for connecting to the filtering capacitor. Not for external
VOUT_LDOVINT 2 O —
loading.
LDOVRTC output for connecting to the filtering capacitor. Not for external
VOUT_LDOVRTC 3 O —
loading.
CRYSTAL OSCILLATOR
Filtering capacitor for the 32 KHz crystal Oscillator, connected to VRTC
OSC32KCAP 40 O Floating
through an internal 100 Ω resistor.
OSC32KIN 38 I 32-KHz crystal oscillator input Ground
OSC32KOUT 39 O 32-KHz crystal oscillator output Floating
SYSTEM CONTROL
AMUXOUT 1 O Buffered bandgap output Floating
Enable Drive output pin to indicate the device entering safe state (set low
EN_DRV 29 O Floating
when ENABLE_DRV bit is '0').
Primary function: General-purpose input(1) and output
Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: SCL_I2C2, which is the Q&A WatchDog I2C serial
I Ground
clock (external pull-up).
I Alternative function: CS_SPI, which is the SPI chip enable signal. Ground
GPIO1 32
Alternative function: nRSTOUT_SoC, which is the SoC reset or power on
O Floating
output (Active Low).
Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: WKUP1 or WKUP2, which are the wake-up request
I Ground
signals for the device to go to higher power states.

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Table 6-1. Pin Attributes (continued)

PIN CONNECTION IF
I/O DESCRIPTION
NAME NO. NOT USED

Primary function: General-purpose input(1) and output

Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: SDA_I2C2, which is the Q&A WatchDog I2C serial
I/O Ground
bidirectional data (external pull-up).
O Alternative function: SDO_SPI, which is the SPI output data signal. Floating
GPIO2 33
Alternative function: TRIG_WDOG, which is the watchdog trigger input
I Ground
signal for Watchdog Trigger mode.
Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: WKUP1 or WKUP2, which are the wake-up request
I Ground
signals for the device to go to higher power states.
Primary function: General-purpose input(1) and output.
Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: nERR_SoC, which is the system error count down
I Floating
input signal from the SoC (Active Low).
Alternative function: CLK32KOUT, which is the output of the 32 KHz
O Floating
GPIO3 46 crystal oscillator clock.
Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of
processing a wake-up request for the device to go to higher power states
I Ground
while the device is in LP STANDBY state. They can also be used as
regular WKUP1 or WKUP2 pins while the device is in mission states.
Primary function: General-purpose input(1) and output.
Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: CLK32KOUT, which is the output of the 32 KHz
O Floating
crystal oscillator clock.
GPIO4 47 Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of
processing a wake-up request for the device to go to higher power states
I Ground
while the device is in LP STANDBY state. They can also be used as
regular WKUP1 or WKUP2 pins while the device is in mission states.
Primary function: General-purpose input(1) and output.
Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial
I/O interface clock signal. The SCLK_SPMI is an output pin for the SPMI Floating
GPIO5 23 controller device, and an input pin for the SPMI peripheral device.
Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: WKUP1 or WKUP2, which are the wake-up request
I Ground
signals for the device to go to higher power states.

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Table 6-1. Pin Attributes (continued)

PIN CONNECTION IF
I/O DESCRIPTION
NAME NO. NOT USED

Primary function: General-purpose input(1) and output.

Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial
I/O Floating
GPIO6 24 interface bidirectional data signal.
Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: WKUP1 or WKUP2, which are the wake-up request
I Ground
signals for the device to go to higher power states.
Primary function: General-purpose input(1) and output.
Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: nERR_MCU, which is the system error count down
I Floating
GPIO7 18 input signal from the MCU (Active Low).
Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: WKUP1 or WKUP2, which are the wake-up request
I Ground
signals for the device to go to higher power states.
Primary function: General-purpose input(1) and output.
Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: SYNCCLKOUT, which is a clock output synchronized
O Floating
to the switching clock signals for the bucks in the device.
Alternative function: DISABLE_WDOG, which is the input to disable the
I Floating
GPIO8 41 watchdog monitoring function.
Alternative function: CLK32KOUT, which is the output of the 32 KHz
O Floating
crystal oscillator clock.
Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: WKUP1 or WKUP2, which are the wake-up request
I Ground
signals for the device to go to higher power states.
Primary function: General-purpose input(1) and output.
Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: PGOOD, which is the indication signal for valid
O Floating
regulator output voltages and currents
Alternative function: SYNCCLKOUT, which is the internal fallback
O Floating
GPIO9 19 switching clock for BUCK.
Alternative function: DISABLE_WDOG, which is the input to disable the
I Floating
watchdog monitoring function.
Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: WKUP1 or WKUP2, which are the wake-up request
I Ground
signals for the device to go to higher power states.

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Table 6-1. Pin Attributes (continued)

PIN CONNECTION IF
I/O DESCRIPTION
NAME NO. NOT USED

Primary function: General-purpose input(1) and output.

Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: SYNCCLKIN, which is the external switching clock
I Floating
input for BUCK.
Alternative function: SYNCCLKOUT, which is the internal fallback
O Floating
GPIO10 42 switching clock for BUCK.
Alternative function: CLK32KOUT, which is the output of the 32 KHz
O Floating
crystal oscillator clock.
Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: WKUP1 or WKUP2, which are the wake-up request
I Ground
signals for the device to go to higher power states.
Primary function: General-purpose input(1) and output.
Input: Ground
I/O When configured as an output pin, it can be included as part of the power
Output: Floating
sequencer output signal to enable an external regulator.
Alternative function: TRIG_WDOG, which is the watchdog trigger input
I Ground
signal for Watchdog Trigger mode.
GPIO11 53 Alternative function: nRSTOUT_SoC, which is the SoC reset or power on
O Floating
output (Active Low).
Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request
I Ground
signals for the device to go to lower power states (Active Low).
Alternative function: WKUP1 or WKUP2, which are the wake-up request
I Ground
signals for the device to go to higher power states.
GND 52 — Analog ground —
nINT 14 O Maskable interrupt output request to the host processor (Active Low) Floating
NPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the
I Floating
device, with configurable polarity
nPWRON/ENABLE 20
NPWRON_SEL = '1': nPWRON - Active low edge sensitive button press
I Ground
pin to power up the device
nRSTOUT 25 O MCU reset or power on reset output (Active Low) Floating
I If SPI is the default interface: SCL_I2C1 - I2C serial clock (external pullup) Ground
SCL_I2C1/SCK_SPI 31
I If I2C is the default interface: CLK_SPI - SPI clock signal Ground
If SPI is the default interface: SDA_I2C1 - I2C serial bidirectional data
I/O Ground
SDA_I2C1/SDI_SPI 30 (external pullup)
I If I2C is the default interface: SDI_SPI - SPI input data signal Ground
POWER SUPPLIES AND REFERENCE GROUNDS
GND 51 I Analog ground —
Power Ground, which is also the thermal pad of the package. Connect to
PGND/ThermalPad — — —
PCB ground planes with multiple vias.
REFGND1 5 — System reference ground —
REFGND2 6 — System reference ground —
VBACKUP 36 I Backup power source input pin Ground
VCCA 4 I Analog input voltage for the internal LDOs and other internal blocks —
VIO_IN 48 I Digital supply input for GPIOs and I/O supply voltage —

(1) Default option before NVM settings are loaded into the device.

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6.1 Digital Signal Descriptions

Table 6-2. Signal Descriptions
INPUT TYPE SELECTION OUTPUT TYPE SELECTION
Internal PU/ RECOMMENDED Control Register
SIGNAL NAME I/O Threshold Level Power Power Push-pull/
DEGLITCH TIME(5) PD(2) EXTERNAL PU/PD(2) Bits
Domain Domain Open-drain(4)
nPWRON
(Selectable
VIL(VCCA), 400 kΩ PU to
function of Input VRTC 50 ms None NPWRON_SEL
VIH(VCCA) VCCA
nPWRON/
ENABLE pin)(1)
NPWRON_SEL
ENABLE ENABLE_POL
400 kΩ SPU to
(Selectable ENABLE_DEGLITCH
VIL(VCCA), VCCA, or
function of Input VRTC 8 µs None _EN
VIH(VCCA) 400 kΩ SPD to
nPWRON/ ENABLE_PU_PD_E
GND
ENABLE pin)(1) N
ENABLE_PU_SEL
VCCA/ 10 kΩ High-side
EN_DRV Output VOL(EN_DRV) PP None ENABLE_DRV
PVIN_B1 to VCCA
SCL_I2C1
High-speed mode: I2C or SPI
(Selectable
VIL(DIG), 10 ns selection from NVM-
function of Input VINT None PU to VIO
VIH(DIG) All other modes: configuration (6)
SCL_I2C1/
50 ns I2C1_HS
SCK_SPI pin)(1)
SDA_I2C1
High-speed mode: I2C or SPI
(Selectable VIL(DIG),
10 ns selection from NVM-
function of Input/output VIH(DIG), VINT VIO OD None PU to VIO
All other modes: configuration(6)
SDA_I2C1/ VOL(VIO)_20mA
50 ns I2C1_HS
SDI_SPI pin)(1)
I2C or SPI
SCL_I2C2 High-speed mode:
selection from NVM-
(Selectable VIL(DIG), 10 ns
Input VINT None PU to VIO configuration(6)
function of VIH(DIG) All other modes:
I2C2_HS
GPIO1)(1) 50 ns
GPIO1_SEL
I2C or SPI
SDA_I2C2 High-speed mode:
VIL(DIG), selection from NVM-
(Selectable 10 ns
Input/output VIH(DIG), VINT VIO OD None PU to VIO configuration(6)
function of All other modes:
VOL(VIO)_20mA I2C2_HS
GPIO2)(1) 50 ns
GPIO2_SEL
SCK_SPI
(Selectable I2C or SPI
VIL(DIG),
function of Input VINT None None None selection from NVM-
VIH(DIG)
SCL_I2C1/ configuration(6)
SCK_SPI pin)(1)

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Table 6-2. Signal Descriptions (continued)

INPUT TYPE SELECTION OUTPUT TYPE SELECTION
Internal PU/ RECOMMENDED Control Register
SIGNAL NAME I/O Threshold Level Power Power Push-pull/
DEGLITCH TIME(5) PD(2) EXTERNAL PU/PD(2) Bits
Domain Domain Open-drain(4)
SDI_SPI
(Selectable I2C or SPI
VIL(DIG),
function of Input VINT None None None selection from NVM-
VIH(DIG)
SDA_I2C1/ configuration(6)
SDI_SPI pin)(1)
CS_SPI I2C or SPI
(Selectable VIL(DIG), selection from NVM-
Input VINT None None None
function of VIH(DIG) configuration(6)
GPIO1)(1) GPIO1_SEL
SDO_SPI I2C or SPI
(Selectable VOL(VIO)_20mA, selection from NVM-
Output VIO PP(3) / HiZ None None
function of VOH(VIO) configuration(6)
GPIO2)(1) GPIO2_SEL
Output for
SCLK_SPMI SPMI controller VIL(DIG),
NVM-configuration(6)
(Configurable device, input VIH(DIG), 400 kΩ PD to
VINT None VINT PP None GPIO5_SEL
function of for SPMI VOL(DIG)_20mA, GND
GPIO5_PU_PD_EN
GPIO5)(1) peripheral VOH(DIG)
device
SDATA_SPMI VIL(DIG),
NVM-configuration(6)
(Configurable VIH(DIG), 400 kΩ PD to
Input/output VINT None VINT PP / HiZ None GPIO6_SEL
function of VOL(DIG)_20mA, GND
GPIO6_PU_PD_EN
GPIO6)(1) VOH(DIG)
nINT Output VOL(nINT) VCCA OD None PU to VCCA
10 kΩ Pull-Up to
VCCA/ PU to VIO if Open-drain
nRSTOUT Output VOL(nRSTOUT) PP(3) or OD VIO if configured NRSTOUT_OD
VIO (driven low if no VINT)
as Push-Pull
nRSTOUT_SoC
GPIO1_SEL
(Configurable 10 kΩ Pull-Up to
VCCA/ PU to VIO if Open-drain GPIO1_OD
function of Output VOL(nRSTOUT) PP(3) or OD VIO if configured
VIO (driven low if no VINT) GPIO11_SEL
GPIO1 and as Push-Pull
GPIO11_OD
GPIO11)(1)
GPIO9_SEL
PGOOD
GPIO9_OD
(Configurable VOL(VIO),
Output VIO PP(3) or OD None PU to VIO if Open-drain PGOOD_POL
function of VOH(VIO)
PGOOD_WINDOW
GPIO9)(1)
PGOOD_SEL_x

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Table 6-2. Signal Descriptions (continued)

INPUT TYPE SELECTION OUTPUT TYPE SELECTION
Internal PU/ RECOMMENDED Control Register
SIGNAL NAME I/O Threshold Level Power Power Push-pull/
DEGLITCH TIME(5) PD(2) EXTERNAL PU/PD(2) Bits
Domain Domain Open-drain(4)
nERR_MCU
(Configurable VIL(DIG), 400 kΩ PD to
Input VINT 8 µs None GPIO7_SEL
function of VIH(DIG) GND
GPIO7)(1)
nERR_SoC
(Configurable VIL(DIG), 400 kΩ PD to
Input VRTC 15 µs None GPIO3_SEL
function of VIH(DIG) GND
GPIO3)(1)
DISABLE_WDO
G
(Configurable VIL(DIG), 400 kΩ PD to GPIO8_SEL
Input VINT 30 µs PU to VIO
function of VIH(DIG) GND GPIO9_SEL
GPIO8 and
GPIO9)(1)
TRIG_WDOG
GPIO2_SEL
(Configurable
VIL(DIG), 400 kΩ SPD to GPIO2_PU_PD_EN
function of Input VINT 30 µs None
VIH(DIG) GND GPIO11_SEL
GPIO2 and
GPIO11_PU_PD_EN
GPIO11)(1)
GPIO3 or 4:
400 kΩ SPU to
GPIO3 or
VRTC
nSLEEP1 4:
GPIO5 or 6: GPIOn_SEL
(Configurable VIL(DIG), VRTC
Input 8 µs 400 kΩ SPU to None GPIOn_PU_PD_EN
function of all VIH(DIG) other
VINT NSLEEP1B
GPIO pins)(1) GPIOs:
all other GPIOs:
VINT
400 kΩ SPU to
VIO
GPIO3 or 4:
400 kΩ SPU to
GPIO3 or
VRTC
nSLEEP2 4:
GPIO5 or 6: GPIOn_SEL
(Configurable VIL(DIG), VRTC
Input 8 µs 400 kΩ SPU to None GPIOn_PU_PD_EN
function of all VIH(DIG) other
VINT NSLEEP2B
GPIO pins)(1) GPIOs:
all other GPIOs:
VINT
400 kΩ SPU to
VIO

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Table 6-2. Signal Descriptions (continued)

INPUT TYPE SELECTION OUTPUT TYPE SELECTION
Internal PU/ RECOMMENDED Control Register
SIGNAL NAME I/O Threshold Level Power Power Push-pull/
DEGLITCH TIME(5) PD(2) EXTERNAL PU/PD(2) Bits
Domain Domain Open-drain(4)
GPIO5 or 6:
400 kΩ SPU to
WKUP1 VINT or
GPIOn_SEL
(Configurable 400 kΩ SPD to
GPIOn_DEGLITCH_
function of all VIL(DIG), GND
Input VINT 8 µs None EN
GPIO pins except VIH(DIG) all other GPIOs:
GPIOn_PU_PD_EN
GPIO3 and 400 kΩ SPU to
GPIOn_PU_SEL
GPIO4)(1) VIO or
400 kΩ SPD to
GND
GPIO5 or 6:
400 kΩ SPU to
WKUP2 VINT or
GPIOn_SEL
(Configurable 400 kΩ SPD to
GPIOn_DEGLITCH_
function of all VIL(DIG), GND
Input VINT 8 µs None EN
GPIO pins except VIH(DIG) all other GPIOs:
GPIOn_PU_PD_EN
GPIO3 and 400 kΩ SPU to
GPIOn_PU_SEL
GPIO4)(1) VIO or
400 kΩ SPD to
GND
GPIO3,4_SEL
LP_WKUP1
400 kΩ SPU to GPIO3,4_DEGLITCH
(Configurable 8 µs,
VIL(DIG), VRTC, or _EN
function of Input VRTC no deglitch in None
VIH(DIG) 400 kΩ SPD to GPIO3,4_PU_PD_E
GPIO3 and LP_STANDBY state
GND N
GPIO4)(1)
GPIO3,4_PU_SEL
GPIO3,4_SEL
LP_WKUP2
400 kΩ SPU to GPIO3,4_DEGLITCH
(Configurable 8 µs,
VIL(DIG), VRTC, or _EN
function of Input VRTC no deglitch in None
VIH(DIG) 400 kΩ SPD to GPIO3,4_PU_PD_E
GPIO3 and LP_STANDBY state
GND N
GPIO4)(1)
GPIO3,4_PU_SEL
GPIO1_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO1_DEGLITCH_
VIH(DIG), VIO, or PU to VIO EN
GPIO1 Input/output VINT 8 µs VIO PP(3) or OD
VOL(VIO)_20mA, 400 kΩ SPD to if Open-drain GPIO1_PU_PD_EN
VOH(VIO) GND GPIO1_PU_SEL
Output:
GPIO1_OD

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Table 6-2. Signal Descriptions (continued)

INPUT TYPE SELECTION OUTPUT TYPE SELECTION
Internal PU/ RECOMMENDED Control Register
SIGNAL NAME I/O Threshold Level Power Power Push-pull/
DEGLITCH TIME(5) PD(2) EXTERNAL PU/PD(2) Bits
Domain Domain Open-drain(4)
GPIO2_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO2_DEGLITCH_
VIH(DIG), VIO, or PU to VIO EN
GPIO2 Input/output VINT 8 µs VIO PP(3) or OD
VOL(VIO)_20mA, 400 kΩ SPD to if Open-drain GPIO2_PU_PD_EN
VOH(VIO) GND GPIO2_PU_SEL
Output:
GPIO2_OD
GPIO3_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO3_DEGLITCH_
VIH(DIG), VINT, or PU to VIO EN
GPIO3 Input/output VRTC 8 µs VINT PP or OD
VOL(DIG), 400 kΩ SPD to if Open-drain GPIO3_PU_PD_EN
VOH(DIG) GND GPIO3_PU_SEL
Output:
GPIO3_OD
GPIO4_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO4_DEGLITCH_
VIH(DIG), VINT, or PU to VIO EN
GPIO4 Input/output VRTC 8 µs VINT PP or OD
VOL(DIG), 400 kΩ SPD to if Open-drain GPIO4_PU_PD_EN
VOH(DIG) GND GPIO4_PU_SEL
Output:
GPIO4_OD
GPIO5_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO5_DEGLITCH_
VIH(DIG), VINT, or PU to VIO EN
GPIO5 Input/output VINT 8 µs VINT PP or OD
VOL(DIG)_20mA, 400 kΩ SPD to if Open-drain GPIO5_PU_PD_EN
VOH(DIG) GND GPIO5_PU_SEL
Output:
GPIO5_OD
GPIO6_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO6_DEGLITCH_
VIH(DIG), VINT, or PU to VIO EN
GPIO6 Input/output VINT 8 µs VINT PP or OD
VOL(DIG)_20mA, 400 kΩ SPD to if Open-drain GPIO6_PU_PD_EN
VOH(DIG) GND GPIO6_PU_SEL
Output:
GPIO6_OD

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Table 6-2. Signal Descriptions (continued)

INPUT TYPE SELECTION OUTPUT TYPE SELECTION
Internal PU/ RECOMMENDED Control Register
SIGNAL NAME I/O Threshold Level Power Power Push-pull/
DEGLITCH TIME(5) PD(2) EXTERNAL PU/PD(2) Bits
Domain Domain Open-drain(4)
GPIO7_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO7_DEGLITCH_
VIH(DIG), VIO, or PU to VIO EN
GPIO7 Input/output VINT 8 µs VIO PP(3) or OD
VOL(VIO), 400 kΩ SPD to if Open-drain GPIO7_PU_PD_EN
VOH(VIO) GND GPIO7_PU_SEL
Output:
GPIO7_OD
GPIO8_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO8_DEGLITCH_
VIH(DIG), VIO, or PU to VIO EN
GPIO8 Input/output VINT 8 µs VIO PP(3) or OD
VOL(VIO), 400 kΩ SPD to if Open-drain GPIO8_PU_PD_EN
VOH(VIO) GND GPIO8_PU_SEL
Output:
GPIO8_OD
GPIO9_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO9_DEGLITCH_
VIH(DIG), VIO, or PU to VIO EN
GPIO9 Input/output VINT 8 µs VIO P(3)P or OD
VOL(VIO), 400 kΩ SPD to if Open-drain GPIO9_PU_PD_EN
VOH(VIO) GND GPIO9_PU_SEL
Output:
GPIO9_OD
GPIO10_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO10_DEGLITCH
VIH(DIG), VIO, or PU to VIO _EN
GPIO10 Input/output VINT 8 µs VIO PP(3) or OD
VOL(VIO), 400 kΩ SPD to if Open-drain GPIO10_PU_PD_EN
VOH(VIO) GND GPIO10_PU_SEL
Output:
GPIO10_OD
GPIO11_DIR
Input:
VIL(DIG), 400 kΩ SPU to GPIO11_DEGLITCH_
VIH(DIG), VIO, or PU to VIO EN
GPIO11 Input/output VINT 8 µs VIO PP(3) or OD
VOL(VIO), 400 kΩ SPD to if Open-drain GPIO11_PU_PD_EN
VOH(VIO) GND GPIO11_PU_SEL
Output:
GPIO11_OD

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Table 6-2. Signal Descriptions (continued)

INPUT TYPE SELECTION OUTPUT TYPE SELECTION
Internal PU/ RECOMMENDED Control Register
SIGNAL NAME I/O Threshold Level Power Power Push-pull/
DEGLITCH TIME(5) PD(2) EXTERNAL PU/PD(2) Bits
Domain Domain Open-drain(4)
SYNCCLKIN
(Configurable VIL(DIG), 400 kΩ SPD to GPIO10_SEL
Input VINT None None
function of VIH(DIG) GND GPIO10_PU_PD_EN
GPIO10)(1)
SYNCCLKOUT
(Configurable GPIO8_SEL
VOL(VIO),
function of Output VIO PP(3) None None GPIO9_SEL
VOH(VIO)
GPIO8, GPIO9, GPIO10_SEL
and GPIO10)(1)
CLK32KOUT GPIO3 or 4:
(Configurable VOL(DIG), GPIO3 or 4: GPIO3_SEL
function of VOH(DIG) VRTC GPIO4_SEL
Output PP(3) None None
GPIO3, GPIO4, GPIO8 or 10: GPIO8 or 10: GPIO8_SEL
GPIO8, and VOL(VIO), VIO GPIO10_SEL
GPIO10)(1) VOH(VIO)

(1) Configurable function through NVM register setting.

(2) PU = Pullup, PD = Pulldown, SPU = Software-configurable pullup, SPD = Software-configurable pulldown.
(3) When VIO is not available, the push-pull pin must be configured as low output to minimize current leakage from the IO cell.
(4) PP = Push-pull, OD = Open-drain.
(5) Deglitch time is only applicable when option is enabled.
(6) NVM-configuration for I2C/SPI and SPMI cannot be overwritten during operation.

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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). Voltage level is with reference to the thermal/ground
pad of the device.(1)
POS MIN MAX UNIT
M1.3 Voltage on OV protected supply input pin VCCA(2) –0.3 6 V
Voltage on all buck supply voltage input
M1.4 PVIN_Bx(2) –0.3 6 V
pins
Voltage difference between supply input
M1.4a Between VCCA and each PVIN_Bx –0.5 0.5 V
pins
PVIN_Bx + 0.3
M1.5a SW_Bx pins –0.3 V
Voltage on all buck switch nodes V, up to 6 V
M1.5b SW_Bx pins, 10-ns transient –2 10 V
M1.6 Voltage on all buck voltage sense nodes FB_Bx –0.3 4 V
M1.7 Voltage on all LDO supply voltage input pins PVIN_LDOx(2) –0.3 6 V
PVIN_LDOx +
M1.8 Voltage on all LDO output pins VOUT_LDOx –0.3 V
0.3 V, up to 6 V
M1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC –0.3 2 V
VCCA + 0.3 V,
M1.10 Voltage on I/O supply pin VIO_IN with respect to ground pad –0.3 V
up to 6 V
Voltage on logic pins (input or output) in VIO I2C and SPI pins, nRSTOUT, and nINT pins, and all
M1.11 –0.3 6 V
domain GPIO output buffers except GPIO5 & GPIO6
Voltage on logic pins (input or output) in GPIO5 & GPIO6, and all GPIO input buffers except
M1.12 –0.3 6 V
LDOVINT domain GPIO3 & GPIO4
Voltage on logic pins (input) in LDOVRTC
M1.13 GPIO3 & GPIO4 –0.3 6 V
domain
Voltage on logic pins (input or output) in
M1.14 nPWRON/ENABLE & EN_DRV –0.3 6 V
VCCA domain
VCCA + 0.3 V,
M1.15 Voltage on analog mux output pin AMUXOUT –0.3 V
up to 6 V
M1.16 Voltage on back-up power supply input VBACKUP –0.3 6 V
M1.17 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, & OSC32KCAP –0.3 2 V
M1.18 Voltage on REFGND pins REFGND1 & REFGND2 –0.3 0.3 V
M2.1a VCCA, PVIN_Bx (voltage below 2.7 V) 60 mV/µs
Voltage rise slew-rate on input supply pins
M2.1b VIO (only when VCCA < 2 V) 60 mV/µs
M2.3a All pins other than power resources 20 mA
Buck1/2/3/4 regulators: PVIN_Bx and SW_Bx per
M2.3b Peak output current 5 A
phase
M2.3c Buck5 regulator: PVIN_B5 and SW_B5 3 A
M2.4a GPIOx pins, source current 3 mA
GPIO1/2/5/6, SDA_I2C1/SDI_SPI, EN_DRV, nINT,
M2.4b 8 mA
and nRSTOUT pins, sink current
Average output current, 100 k hour, TJ =
M2.4c 125℃ GPIO3/4/7/8/9/10/11 pins, sink current 3 mA
M2.4d LDO1/2/3 regulators 350 mA
M2.4e LDO4 regulators 210 mA
M3 Junction temperature, TJ –45 160 °C
M4 Storage temperature, Tstg –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The voltage at VCCA and PVIN pins can exceed the 6 V absolute max condition for a short period of time, but must remain less than 8
V. VCCA at 8 V for a 100 ms duration is equivalent to approximately 8 hours of aging for the device at room temperature.

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7.2 ESD Ratings

POS VALUE UNIT
Electrostatic
M5 V(ESD) Human-body model (HBM), per AEC Q100-002(1) ±2000 V
discharge
Electrostatic
M6 V(ESD) Charged-device model (CDM), per AEC Q100-011 ±500 V
discharge

(1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device.
POS MIN NOM MAX UNIT
R1.3 Voltage on OV protected supply input pin VCCA VCCA_UV 5.5 V
R1.4 Voltage on all buck supply input pins PVIN_Bx 2.8 5.5 V
R1.4a Voltage difference between supply input pins Between VCCA and each PVIN_Bx –0.2 0.2 V
R1.5 Voltage on all buck switch nodes SW_Bx pins 3.3 5.5 V
R1.6 Voltage on all buck voltage sense nodes(1) FB_Bx 0 VOUT_Bn,max V
R1.7a PVIN_LDO12, PVIN_LDO3 1.2 3.3 VCCA V
Voltage on all LDO supply voltage input pins
R1.7b PVIN_LDO4 2.2 3.3 VCCA V
R1.8 Voltage on all LDO output pins(1) VOUT_LDOx 0 3.3 V
R1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC 1.65 1.95 V
R1.10 Voltage on reference ground pins REFGNDx –0.3 0.3 V
R1.11 VVIO_IN = 1.8 V 1.7 1.8 1.9
Voltage on I/O supply pin VCCA, up to V
R1.12 VVIO_IN = 3.3 V 3.135 3.3
3.465V
I2C and SPI pins, nRSTOUT & nRSTOUT_SoC
Voltage on logic pins (input or output) in VIO
R1.13 pins, GPIO1, GPIO2, GPIO7, GPIO8, GPIO9, 0 VVIO_IN VVIO_IN,max V
domain
GPIO10, and GPIO11 pins
Full Battery, up
R1.14 Voltage on backup supply pin VBACKUP 0 V
to 5.5V
VOUT_LDOVRTC,
R1.15 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, OSC32KCAP 0 V
max

Voltage on logic pins (input or output) in VOUT_LDOVRTC,

R1.16 With fail-safe(3): GPIO3 & GPIO4 0 1.8 V
LDOVRTC domain max

Voltage on logic pins (input or output) in VOUT_LDOVINT,m

R1.17 With fail-safe(3): GPIO5 & GPIO6 0 1.8 V
LDOVINT domain ax

Voltage on logic pins (input or output) in VCCA

R1.18 nPWRON/ENABLE, EN_DRV 0 VVCCA V
domain
R1.19 Operating free-air temperature(2) –40 25 125 °C
R1.20 Junction temperature, TJ Operational –40 25 150 °C

(1) The maximum output voltage of BUCK1 to BUCK5 and LDO1 to LDO4 can be reduced by an NVM setting to adopt the maximum
voltage to the requirements (or maximum ratings) of the load. This reduction of the maximum output voltage protects the processor
from exceeding the maximum ratings of the core voltage. The default value is defined in the nonvolatile memory (NVM) and can be
updated by software through I2C/SPI interface after device start-up.
(2) Additional cooling strategies may be necessary to keep junction temperature at recommended limits.
(3) The input buffer of a fail-safe GPIO pin is isolated from its input signal. Therefore, the input voltage to a fail-safe pin can be as high as
5.5 V.

7.4 Thermal Information

TPS6593-Q1
THERMAL METRIC(1) RWE (VQFNP) UNIT
56 PINS
RθJA Junction-to-ambient thermal resistance 21.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W

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7.4 Thermal Information (continued)

TPS6593-Q1
THERMAL METRIC(1) RWE (VQFNP) UNIT
56 PINS
RθJB Junction-to-board thermal resistance 6.2 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 6.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics application
report.

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7.5 General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad
of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
Connected from PVIN_LDOn to GND, Shared input
1.1a CIN(LDOn) Input filtering capacitance(1) 1 2.2 µF
tank capacitance (depending on platform requirements)
Output filtering effective
1.1b COUT(LDOn) Connected from VOUT_LDOn to GND 1 2.2 4 µF
capacitance(2)
1.1c CESR (LDOn) Filtering capacitor ESR(3) 1 MHz ≤ f ≤ 10 MHz 20 mΩ
COUT_TOTAL (L Total capacitance at output
1.1d 1 MHz ≤ f ≤ 10 MHz 20 µF
DOn) (Local + POL)(5)
1.2a VIN(LDOn) LDO Input voltage LDO mode 1.2 VCCA V
VIN(LDOn)_bypas LDO Input voltage in bypass VCCA, up
1.2b Bypass mode 1.7 V
s mode to 3.6 V
LDO output voltage
1.3 VOUT(LDOn) LDO mode, with 50-mV steps 0.6 3.3 V
configurable range
Total DC output voltage LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV,
1.4a –1% 1%
accuracy, including voltage VOUT(LDOn) ≥ 1V
TDCOV(LDOn) references, DC load and
line regulations, process and LDO mode, VIN(LDOn) - VOUT(LDOn) > 300 mV, VOUT(LDOn)
1.4b –10 10 mV
temperature variations < 1V

1.6 IOUT(LDOn) Output current VIN(LDOn)min ≤ VIN(LDOn) ≤ VIN(LDOn)max 500 mA

1.7 ISHORT(LDOn) LDO current limitation LDO mode and bypass mode 700 1800 mA
LDOn_BYPASS = 0 1500
1.8a IIN_RUSH(LDOn) LDO inrush current LDOx_BYPASS = 1, with maximum 50-µF load mA
1500
connected to VOUT_LDOn
Pulldown discharge resistance Active only when converter is disabled. Also applies to
1.11a RDIS(LDOn) 35 50 65 kΩ
at LDO output bypass mode. LDOn_PLDN = '00'
Pulldown discharge resistance Active only when converter is disabled. Also applies to
1.11b RDIS(LDOn) 60 125 200 Ω
at LDO output bypass mode. LDOn_PLDN = '01'
Pulldown discharge resistance Active only when converter is disabled. Also applies to
1.11c RDIS(LDOn) 120 250 400 Ω
at LDO output bypass mode. LDOn_PLDN = '10'
Pulldown discharge resistance Active only when converter is disabled. Also applies to
1.11d RDIS(LDOn) 240 500 800 Ω
at LDO output bypass mode. LDOn_PLDN = '11'
f = 1 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500
1.12a 60
mA
f = 10 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500
1.12b 50
Power supply ripple rejection mA
PSRRVIN(LDOn) dB
from VIN(LDOn) f = 100 kHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500
1.12c 35
mA
f = 1 MHz, VIN(LDOx) = 3.3 V, VOUT = 2.8 V, IOUT = 500
1.12d 24
mA
For LDO1, LDO2, & LDO3, VCCA = VIN(LDOn) = 3.3 V,
1.13 IQoff(LDOn) Quiescent current, off mode 2 µA
TJ = 25°C
1.14a LDOn_BYPASS = 0, ILOAD = 0 mA , TJ = 25°C 78
IQon(LDOn) Quiescent current, on mode µA
1.14b LDOn_BYPASS = 1, ILOAD = 0 mA , TJ = 25°C 68
Transient load regulation, LDOn_BYPASS = 0, IOUT = 20% to 80% of IOUTmax, tr =
1.15 TLDR(LDOn) 25 mV
ΔVOUT (4) tf = 1 µs
Transient regulation due to
TBYPASS_to_LD VIN(LDOn) = 3.3V, IOUT=IOUT(LDOn)max, LDOn_BYPASS bit
1.16 Bypass Mode to Linear Mode -2 mV
O(LDOn) switches between 1 and 0
Transition
100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT =
1.17 VNOISE(LDOn) RMS Noise 250 µVRMS
300 mA
1.18 Ripple From the internal charge pump 5 mVPP
3.1 V ≤ VIN(LDOn) ≤ 3.5 V, PVIN_LDOx ≤ VCCA, IOUT =
1.19a 200
500 mA, LDOx_BYPASS = 1
RBYPASS(LDOn) Bypass resistance mΩ
1.7 V ≤ VIN(LDOn) ≤ 1.9 V, IOUT = 500 mA,
1.19c 250
LDOn_BYPASS = 1

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7.5 General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3) (continued)
Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad
of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VTH_RV_SC(LDO Threshold voltage for Short
1.20 LDOn_EN = 0 140 150 160 mV
n) Circuit
Timing Requirements
Time between enable of the LDOn to within OV/UV
19.1 ton(LDOn) Turn-on time 500 µs
monitor level
VOUT from 0.3 V to 90% of LDOn_VSET.
19.2a 25 mV/µs
LDOn_SLOW_RAMP = 0
tramp(LDOn) Ramp-up slew rate
VOUT from 0.3 V to 90% of LDOn_VSET.
19.2b 3 mV/µs
LDOn_SLOW_RAMP = 1
19.3a tdelay_OC(LDOn) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs
tdeglitch_OC(LDOn Over-current detection signal
19.3b Digital deglitch time for the over-current detection signal 38 44 µs
) deglitch time
tlatency_OC(LDOn Over-current signal total
19.4 Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs
) latency time

7.6 Low Noise Low Drop-Out Regulator (LDO4)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
Connected from PVIN_LDO4 to GND, Shared input
2.1a CIN(LDO4) Input filtering capacitance(1) 1 2.2 µF
tank capacitance (depending on platform requirements)
2.1b COUT(LDO4) Output filtering capacitance(2) Connected from VOUT_LDO4 to GND 1 2.2 4 µF
Input and output capacitor
2.1c CESR(LDO4) 1 MHz ≤ f ≤ 10 MHz 20 mΩ
ESR(3)
2.1d COUT_TOTAL Total capacitance at output 1 MHz ≤ f ≤ 10 MHz, fast ramp 15 µF
2.1e (LDO4) (Local + POL)(4) 1 MHz ≤ f ≤ 10 MHz, slow ramp 30 µF
2.2 VIN(LDO4) LDO Input voltage 2.2 5.5 V
LDO output voltage
2.3 VOUT(LDO4) with 25-mV steps 1.2 3.3 V
configurable range
Total DC output voltage
accuracy, including voltage
2.5 TDCOV(LDO4) references, DC load and VIN(LDO4) - VOUT(LDO4) > 300 mV –1% 1%
line regulations, process and
temperature
2.7 IOUT(LDO4) Output current VIN(LDO4)min ≤ VIN(LDO4) ≤ VIN(LDO4)max 300 mA
2.8 ISHORT(LDO4) LDO current limit 400 900 mA
2.9 IIN_RUSH(LDO4) LDO inrush current VIN = 3.3V when LDO is enabled 650 mA
f = 1 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300
2.13a 70
mA
f = 10 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300
2.13b 70
mA
PSRR(LDO4) Power supply ripple rejection dB
f = 100 kHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300
2.13c 62
mA
f = 1 MHz, VIN(LDO4) = 3.3 V, VOUT = 2.8 V, IOUT = 300
2.13d 15
mA

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7.6 Low Noise Low Drop-Out Regulator (LDO4) (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Active only when converter is disabled, LDO4_PLDN =
2.12a 35 50 65 kΩ
'00'
Active only when converter is disabled, LDO4_PLDN =
2.12b 60 125 200 Ω
Pulldown discharge resistance '01'
RDIS(LDO4)
at LDO output Active only when converter is disabled, LDO4_PLDN =
2.12c 120 250 400 Ω
'10'
Active only when converter is disabled, LDO4_PLDN=
2.12d 240 500 800 Ω
'11'
For all LDO regulators, VCCA = VIN(LDO4) = 3.8 V, TJ =
2.14 IQoff(LDO4) Leakage current in off mode 2 µA
25℃
ILOAD = 0 mA ,LDO4 under valid operating condition, TJ
2.15 IQon(LDO4) Quiescent current 40 µA
= 25℃
Transient load regulation, VIN(LDO4) = 3.3V, VOUT(LDO4) = 2.80V, IOUT = 20% of
2.16 TLDR(LDO4) –25 25 mV
ΔVOUT IOUT_MAX to 80% of IOUT_MAX in 1us, COUT(LDO4) = 2.2uF
Transient line regulation, On mode, not under dropout condition, VIN step = 600
2.17 TLNR(LDO4) -25 25 mV
ΔVOUT / VOUT mVPP, tr = tf = 10 µs
100 Hz < f ≤ 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, IOUT =
2.18 VNOISE(LDO4) RMS Noise 15 µVRMS
300 mA
VTH_SC_RV(LDO Threshold voltage for Short
2.19 LDO4_EN = 0 140 150 160 mV
4) Circuit
Timing Requirements
Time from completion of enable command to output
19.11a tSTART(LDO4) Start Time 150 µs
voltage at 0.5 V
19.12 Measured from 0.5 V to 90% of
350 µs
a1 LDO4_VSET. LDO4_SLOW_RAMP = 0
tRAMP(LDO4) Ramp Time
19.12 Measured from 0.5 V to 90% of
2.3 ms
a2 LDO4_VSET. LDO4_SLOW_RAMP = 1
19.12 VOUT from 0.5 V to 90% of LDO4_VSET.
27 mV/µs
b tRAMP_SLEW(LD LDO4_SLOW_RAMP = 0
Ramp up slew rate
O4) VOUT from 0.5 V to 90% of LDO4_VSET.
19.12c 3 mV/µs
LDO4_SLOW_RAMP = 1
19.13
tdelay_OC(LDO4) Over-current detection delay Detection signal delay when IOUT > ILIM 35 µs
a
19.13 tdeglitch_OC(LDO4 Over-current detection signal
Digital deglitch time for the over-current detection signal 38 44 µs
b ) deglitch time
tlatency_OC(LDO4 Over-current signal total
19.14 Total delay from Iout > ILIM to interrupt or PFSM trigger 79 µs
) latency time

7.7 Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)

3.3a VOUT(LDOVRTC) LDOVRTC 1.8 V

LDO output voltage
3.3b VOUT(LDOVINT) LDOVINT 1.8 V

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7.7 Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT) (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.7a LDOVRTC, VCCA = 3.3 V, TJ = 25℃ 2
IQoff(LDOinternal) Leakage current, off mode µA
3.7b LDOVINT, VCCA = 3.3 V, TJ = 25℃ 2
LDOVRTC under valid operating condition, ILOAD = 0
3.8a 3 10
IQon(LDOinternal) Quiescent current, on mode mA µA
3.8b LDOVINT under valid operating condition, ILOAD = 0 mA 3 10
Pulldown discharge resistance
3.9 RDIS(LDOinterna;) LDOx disabled 60 125 190 Ω
at LDO output
LDOVINT output step from 1.8 V → 1.6 V, tf = 100
3.10ai VUVLO(LDOVINT) LDOVINT UVLO threshold 1.62 1.64 1.665 V
mV/µs
VUVLO(LDOVRTC LDOVRTC output step from 1.8 V → 1.6 V, tf = 100
3.10bi LDOVRTC UVLO threshold 1.62 1.64 1.665 V
) mV/µs
LDOVINT output step from 1.8 V → 2.0 V, tr = 100
3.11ai VOVP(LDOVINT) LDOVINT OVP threshold 1.93 1.96 1.98 V
mV/µs

(1) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above
therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of
the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of
regulators.

7.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators

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7.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

ILIM_FWD_PEAK
4.10 Forward current limit step Size 1 A
_Step

ILIM_FWD = 2.5 A or 3.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5

4.11a -0.55 0.55 A
V
ILIM_FWD = 4.5 A, 3.0 V ≤ VPVIN_Bn ≤ 5.5 V,
4.11b -0.55 0.55 A
ILIM_FWD_PEAK BUCK1, BUCK2, BUCK3, BUCK4
Forward current limit accuracy
_Accuracy ILIM_FWD = 5.5 A, 3.0 V ≤ VPVIN_Bn ≤ 4.5 V,
4.11c –15% 10%
BUCK1, BUCK2, BUCK3, BUCK4
ILIM_FWD = 5.5 A, 4.5 V ≤ VPVIN_Bn ≤ 5.5 V,
4.11d –10% 10%
BUCK1, BUCK2, BUCK3, BUCK4
Negative current limit (peak during
4.12 ILIM_NEG 1.5 2 2.8 A
each switching cycle)
4.15a From 1-phase to 2-phase 2.0 A
4.15b IADD Phase adding level (multi-phase rails) From 2-phase to 3-phase 4.0 A
4.15c From 3-phase to 4-phase 6.0 A
4.16a From 2-phase to 1-phase 1.3 A
Phase shedding level (multi-phase
4.16b ISHED From 3-phase to 2-phase 2.7 A
rails)
4.16c From 4-phase to 3-phase 3.5 A
4.16d Hysteresis from 2-phase to 1-phase 0.7 A
Phase shedding hysteresis (multi-
4.16e ISHED_Hyst Hysteresis from 3-phase to 2-phase 1.3 A
phase rails)
4.16f Hysteresis from 4-phase to 3-phase 2.5 A
Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance
4.17 Ioff Shutdown current, BUCKn disabled VCCA = VPVIN_Bn = 3.3 V. TJ = 25°C 1 µA
IOUT_Bn = 0 mA, not switching, first single
4.18a phase or primary phase in multi-phase 80 µA
configuration, TJ = 25°C
IOUT_Bn = 0 mA, not switching, additional
4.18b IQ_AUTO Auto mode quiescent current single phase or primary phase in multi-phase 60 µA
configuration, TJ = 25°C
IOUT_Bn = 0 mA, not switching, secondary/
4.18c tertiary/quaternary phase in multi-phase 30 µA
configuration, TJ = 25°C
4.19a IOUT_Bn = 1 A, BUCK5 55 110 mΩ
RDS(ON) HS FET On-resistance, high-side FET IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3,
4.19b 52 100 mΩ
BUCK4
4.20a IOUT_Bn = 1 A, BUCK5 41 70 mΩ
RDS(ON) LS FET On-resistance, low-side FET IOUT_Bn = 1 A, BUCK1, BUCK2, BUCK3,
4.20b 30 55 mΩ
BUCK4
Regulator disabled, per phase, BUCKn_PLDN =
4.21 RDIS_Bn Output pulldown discharge resistance 50 100 150 Ω
1
Short circuit detection resistance
4.22 RSW_SC 2 4.5 20 Ω
threshold at the SW pin
Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Multiphase or High COUT Single Phase
4.31 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V
4.32 VVOUT_Bn Output voltage configurable range 0.3 1.9 V
4.33a CIN_Bn Input filtering capacitance(1) 3 22 µF
COUT-
4.33b Output capacitance, local(2) Per phase 10 22 µF
Local(Buckn)

Output capacitance, total (local and

4.33c COUT-TOTAL_Bn Per phase 70 250 µF
POL)(2)

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7.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level are referenced to the thermal/ground pad
of the device except for VOUT_Bn in multiphase configurations, in which case, the voltage level is referenced to the negative
FB_Bn pin of the differential pair.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4.34a Inductance 154 220 286 nH
LBn Power inductor
4.34b DCR 10 mΩ
4.35 IQ_PWM PWM mode Quiescent current Per phase, IOUT_Bn = 0 mA 19 mA
4.160a VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.160b DC output voltage accuracy, includes VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.160c VOUT_DC_Bx voltage reference, DC load and line VVOUT_Bx < 1 V, PFM mode –20 25 mV
regulations and temperature
-1% - 10 1% + 15
4.160d VVOUT_Bx ≥ 1 V, PFM mode
mV mV
0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400
4.37a 10 mV
mA / phase, tr = tf = 1 µs, PWM mode
0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA
4.37ba to 1.75A / phase, tr = tf = 1 µs, PWM mode, 15 mV
BUCK1, BUCK2, BUCK3, BUCK4
0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 1
4.37bb TLDSR_MP Transient load step response(7) 15 mV
A / phase, tr = tf = 1 µs, PWM mode, BUCK5
1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to
4.37ca 1.75 A / phase, tr = tf = 1 µs, PWM mode, 1.2%
BUCK1, BUCK2, BUCK3, BUCK4
1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 1
4.37cb 1.0%
A / phase, tr = tf = 1 µs, PWM mode, BUCK5
VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10
4.38 TLNSR Transient line response -20 ±5 20 mV
µs, IOUT_Bn = IOUT(max)
4.39a PWM mode, 1-phase 3 mVPP
VOUT_Ripple Ripple voltage(7)
4.39b PFM mode 15 25 mVPP
4.40 VTH_SC_RV(Bn) Threshold voltage for Short Circuit Bn_EN = 0 140 150 160 mV
PWM to PFM switch current
4.102 IPWM-PFM Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 400 mA
threshold(6)
PFM to PWM switch current
4.101 IPFM-PWM Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 500 mA
threshold(6)
PWM to PFM switch current
4.103 IPWM-PFM_HYST Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0 V 100 mA
hysteresis
Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only
4.41 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V
4.42 IOUT_Bn_SINK Current sink –1 A
4.43 VVOUT_Bn Output voltage programmable range 0.5 0.7 V
4.44a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.44b COUT-TOTAL_Bn Output capacitance, local(2) 10 22 µF
Output capacitance, total (local and
4.44c COUT-TOTAL_Bn 35 65 µF
POL)(2)
4.45a Inductance 329 470 611 nH
LBn Power inductor
4.45b DCR 10 mΩ
4.46a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA
4.161a DC output voltage accuracy, includes VVOUT_Bx < 1 V, PWM mode –10 10 mV
VOUT_DC_Bx voltage reference, DC load and line
4.161b regulations and temperature VVOUT_Bx ≥ 1 V, PWM mode –1% 1%

0.5 V ≤ VVOUT_Bn ≤ 0.7 V, IOUT_Bn = -1 mA to

4.48 TLDSR_MP Transient load step response(7) 15 mV
-1000 mA, tr = tf = 1 µs, PWM mode
VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10
4.49 TLNSR Transient line response -20 ±5 20 mV
µs, IOUT_Bn = IOUT_Bn(max)
4.50 VOUT_Ripple Ripple voltage(7) PWM mode 3 6 mVPP
Electrical Characteristics - 4.4 MHz VOUT Less than 1.9 V, Low COUT, Single Phase Only
4.51 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V
4.52 VVOUT_Bn Output voltage configurable range 0.3 1.9 V

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7.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

4.63 VVOUT_Bn Output voltage configurable range 1.7 3.34 V

4.64a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.64b COUT-Local_Bn Output capacitance, local(2) 10 22 µF
Output capacitance, total (local and
4.64c COUT-TOTAL_Bn 50 150 µF
POL)(2)
4.65a Inductance 329 470 611 nH
LBn Power inductor
4.65b DCR 10 mΩ
4.66a IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 19 mA
4.163a VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.163b DC output voltage accuracy, includes VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.163c VOUT_DC_Bx voltage reference, DC load and line VVOUT_Bx < 1 V, PFM mode –20 25 mV
regulations and temperature
-1% - 10 1% + 15
4.163d VVOUT_Bx ≥ 1 V, PFM mode
mV mV
1.7 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 1
4.68 TLDSR_SP Transient load step response(7) 1.5%
A/phase, tr = tf = 1 µs, PWM mode
VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10
4.69 TLNSR Transient line response -20 ±5 20 mV
µs, IOUT_Bn = IOUT_Bn(max)

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7.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level are referenced to the thermal/ground pad
of the device except for VOUT_Bn in multiphase configurations, in which case, the voltage level is referenced to the negative
FB_Bn pin of the differential pair.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4.70a PWM mode 3 7 mVPP
VOUT_Ripple Ripple voltage(7)
4.70b PFM mode 15 25 mVPP
PFM to PWM switch current
4.121 IPFM-PWM Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 400 mA
threshold(6)
PWM to PFM switch current
4.122 IPWM-PFM Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 370 mA
threshold(6)
PWM to PFM switch current
4.123 IPWM-PFM_HYST Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.8 V 30 mA
hysteresis
Electrical Characteristics - 2.2 MHz Full VOUT Range and VIN Greater than 4.5 V, Single Phase Only
4.71 VPVIN_Bn Input voltage range 4.5 5 5.5 V
4.72 VVOUT_Bn Output voltage configurable range 0.3 3.34 V
4.73a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.73b COUT-Local_Bn Output capacitance, local(2) 10 22 µF
Output capacitance, total (local and
4.73c COUT-TOTAL_Bn 100 1000 µF
POL)(2)
4.74a Inductance 700 1000 1300 nH
LBn Power inductor
4.74b DCR 10 mΩ
4.75 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA
4.164a VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.164b DC output voltage accuracy, includes VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.164c VOUT_DC_Bx voltage reference, DC load and line VVOUT_Bx < 1 V, PFM mode –20 25 mV
regulations and temperature
-1% - 10 1% + 15
4.164d VVOUT_Bx ≥ 1 V, PFM mode
mV mV
0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400
4.77a 15 mV
mA / phase, tr = tf = 1 µs, PWM mode
0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2
4.77b TLDSR_MP Transient load step response(7) 15 mV
A / phase, tr = tf = 1 µs, PWM mode
1.5 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2
4.77c 1.5%
A / phase, tr = tf = 1 µs, PWM mode
VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10
4.78 TLNSR Transient line response -20 ±5 20 mV
µs, IOUT_Bn= IOUT_Bn(max)
4.79a PWM mode 3 7.5 mVPP
VOUT_Ripple Ripple voltage(7)
4.79b PFM mode 15 25 mVPP
PFM to PWM switch current
4.131 IPFM-PWM Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 310 mA
threshold(6)
PWM to PFM switch current
4.132 IPWM-PFM Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 290 mA
threshold(6)
PWM to PFM switch current
4.133 IPWM-PFM_HYST Auto mode, VPVIN_Bn = 5 V, VVOUT_Bn = 1.0V 20 mA
hysteresis
Electrical Characteristics - 2.2 MHz VOUT Less than 1.9 V Multiphase or Single Phase
4.81 VPVIN_Bn Input voltage range 3.0 3.3 5.5 V
4.82 VVOUT_Bn Output voltage configurable range 0.3 1.9 V
4.83a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.83b COUT-Local_Bn Output capacitance, local(2) Per phase 10 22 µF
Output capacitance, total (local and
4.83c COUT-TOTAL_Bn Per phase 100 1000 µF
POL)(2)
4.84a Inductance 329 470 611 nH
LBn Power inductor
4.84b DCR 10 mΩ
4.85 IQ_PWM PWM mode Quiescent current IOUT_Bn = 0 mA 13 mA

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7.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level are referenced to the thermal/ground pad
of the device except for VOUT_Bn in multiphase configurations, in which case, the voltage level is referenced to the negative
FB_Bn pin of the differential pair.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4.165a VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.165b DC output voltage accuracy, includes VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
4.165c VOUT_DC_Bx voltage reference, DC load and line VVOUT_Bx < 1 V, PFM mode –20 25 mV
regulations and temperature
-1% - 10 1% + 15
4.165d VVOUT_Bx ≥ 1 V, PFM mode
mV mV
0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400
4.87a 5 mV
mA / phase, tr = tf = 1 µs, PWM mode
0.6 V ≤ VVOUT_Bn < 1.5 V, IOUT_Bn = 1 mA to 2
4.87b TLDSR_MP Transient load step response(7) 15 mV
A / phase, tr = tf = 1 µs, PWM mode
1.5 V ≤ VVOUT_Bn ≤ 1.9 V, IOUT_Bn = 1 mA to 2
4.87c 1.0%
A / phase, tr = tf = 1 µs, PWM mode
VPVIN_Bn stepping from 4.7 V to 5.2 V, tr = tf = 10
4.88 TLNSR Transient line response -20 ±5 20 mV
µs, IOUT_Bn= IOUT_Bn(max)
4.89a PWM mode, 1-phase 3 5 mVPP
VOUT_Ripple Ripple voltage(7)
4.89b PFM mode 15 25 mVPP
PFM to PWM switch current
4.141 IPFM-PWM Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 500 mA
threshold(6)
PWM to PFM switch current
4.142 IPWM-PFM Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 400 mA
threshold(6)
PWM to PFM switch current
4.143 IPWM-PFM_HYST Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 100 mA
hysteresis
Electrical Characteristics - 2.2 MHz Full VOUT and Full VIN Range, Single Phase Only
4.91 VPVIN_Bn Input voltage range 2.8 3.3 5.5 V
4.92 VVOUT_Bn Output voltage configurable range 0.3 3.34 V
4.93a CIN_Bn Input filtering capacitance(1) 3 22 µF
4.93b COUT-Local_Bn Output capacitance, local(2) 10 22 µF
Output capacitance, total (local and
4.93c COUT-TOTAL_Bn 100 500 µF
POL)(2)
4.94a Inductance 700 1000 1300 nH
LBn Power inductor
4.94b DCR 10 mΩ
IOUT_Bn = 0 mA, BUCK1, BUCK2, BUCK3,
4.95 IQ_PWM PWM mode Quiescent current 13 mA
BUCK4
4.166a VVOUT_Bx < 1 V, PWM mode –10 10 mV
4.166b DC output voltage accuracy, includes VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
VOUT_DC_Bx voltage reference, DC load and line -1% - 10 1% + 15
4.166d regulations and temperature VVOUT_Bx ≥ 1 V, PFM mode
mV mV
4.166c VVOUT_Bx < 1 V, PFM mode –20 25 mV
0.3 V ≤ VVOUT_Bn < 0.6 V, IOUT_Bn = 1 mA to 400
4.97a 35 mV
mA / phase, tr = tf = 1 µs, PWM mode
0.6 V ≤ VVOUT_Bn < 1.0 V, IOUT_Bn = 1 mA to 2
4.97b TLDSR_SP Transient load step response(7) 17 mV
A / phase, tr = tf = 1 µs, PWM mode
1.0 V ≤ VVOUT_Bn ≤ 3.34 V, IOUT_Bn = 1 mA to 2
4.97c 3.5%
A / phase, tr = tf = 1 µs, PWM mode
VPVIN_Bn stepping from 3 V to 3.5 V, tr = tf = 10
4.98 TLNSR Transient line response -20 ±5 20 mV
µs, IOUT_Bn = IOUT_Bn(max)
4.99a PWM mode 3 7.5 mVPP
VOUT_Ripple Ripple voltage(7)
4.99b PFM mode 15 25 mVPP
PFM to PWM switch current
4.151 IPFM-PWM Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 290 mA
threshold(6)
PWM to PFM switch current
4.152 IPWM-PFM Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 230 mA
threshold(6)
PWM to PFM switch current
4.153 IPWM-PFM_HYST Auto mode, VPVIN_Bn = 3.3 V, VVOUT_Bn = 1.0V 50 mA
hysteresis

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7.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

(1) Input capacitors must be placed as close as possible to the device pins.
(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above
therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of
the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of
regulators.
(3) The maximum output current can be limited by the forward current limit. The maximum output current is also limited by the junction
temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and
limits the maximum current depending on the length of the current pulse, efficiency, board and ambient temperature.
(4) Additional cooling strategies may be necessary to keep the device junction temperature at recommended limits with large output
current.
(5) SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-configured by the MCU. Output capacitance, forward and
negative current limits and load current may limit the maximum and minimum slew rates.
(6) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and
the inductor current level. The BUCK Regulator does not switch over from PWM to PFM for Fsw=2.2MHz and VOUT < 0.5V
(7) Please refer to the applications section of the data sheet regarding the power delivery network (PDN) used for the transient load step
and output ripple test conditions. All ripple specs are defined across POL capacitor in the described PDN.
(8) The 33.3 mV/µs slew-rate setting is not recommended for LBx ≥ 1 µH, as this can trigger OV detection due to larger overshoot at the
buck output.

7.9 Reference Generator (BandGap)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
Capacitance between AMUXOUT pin and thermal/
5.1 Max capacitance at AMUX pin 100 pF
ground pad
5.2 Output voltage Measured at the AMUXOUT pin 1.17 1.2 1.23 V
Timing Requirements
From AMUXOUT_EN=1 to the time bandgap voltage
21.1 tSU_REF Start-up time 30 µs
settles

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7.10 Monitoring Functions

Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/
ground pad of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics: BUCK REGULATORS OUTPUT
7.1a BUCKn_OV_THR = 0x0 2% 3% 4%
7.1b BUCKn_OV_THR = 0x1 2.5% 3.5% 4.5%
7.1c BUCKn_OV_THR = 0x2 3% 4% 5%
7.1d Overvoltage monitoring for BUCK BUCKn_OV_THR = 0x3 4% 5% 6%
VBUCK_OV_TH output, threshold accuracy,
7.1e VOUT_Bn ≥ 1 V(1) BUCKn_OV_THR = 0x4 5% 6% 7%
7.1f BUCKn_OV_THR = 0x5 6% 7% 8%
7.1g BUCKn_OV_THR = 0x6 7% 8% 9%
7.1h BUCKn_OV_THR = 0x7 9% 10% 11%
7.2a BUCKn_OV_THR = 0x0 20 30 40
7.2b BUCKn_OV_THR = 0x1 25 35 45
7.2c BUCKn_OV_THR = 0x2 30 40 50
7.2d Overvoltage monitoring for BUCK BUCKn_OV_THR = 0x3 40 50 60
VBUCK_OV_TH_mv
output, threshold accuracy, mV
7.2e VOUT_Bn < 1 V(1) BUCKn_OV_THR = 0x4 50 60 70
7.2f BUCKn_OV_THR = 0x5 60 70 80
7.2g BUCKn_OV_THR = 0x6 70 80 90
7.2h BUCKn_OV_THR = 0x7 90 100 110
7.3a BUCKn_UV_THR = 0x0 –4% –3% –2%
7.3b BUCKn_UV_THR = 0x1 –4.5% –3.5% –2.5%
7.3c BUCKn_UV_THR = 0x2 –5% –4% –3%
7.3d Undervoltage monitoring for BUCKn_UV_THR = 0x3 –6% –5% –4%
VBUCK_UV_TH buck output, threshold accuracy,
7.3e VOUT_Bn ≥ 1 V(1) BUCKn_UV_THR = 0x4 –7% –6% –5%
7.3f BUCKn_UV_THR = 0x5 –8% –7% –6%
7.3g BUCKn_UV_THR = 0x6 –9% –8% –7%
7.3h BUCKn_UV_THR = 0x7 –11% –10% –9%
7.4a BUCKn_UV_THR = 0x0 –40 –30 –20
7.4b BUCKn_UV_THR = 0x1 –45 –35 –25
7.4c BUCKn_UV_THR = 0x2 –50 –40 –30
7.4d Undervoltage monitoring for BUCKn_UV_THR = 0x3 –60 –50 –40
VBUCK_UV_TH_mv
buck output, threshold accuracy, mV
7.4e VOUT_Bn < 1 V(1) BUCKn_UV_THR = 0x4 –70 –60 –50
7.4f BUCKn_UV_THR = 0x5 –80 –70 –60
7.4g BUCKn_UV_THR = 0x6 –90 –80 –70
7.4h BUCKn_UV_THR = 0x7 –110 –100 –90
Electrical Characteristics: LDO REGULATOR OUTPUTS
7.5a LDOn_OV_THR = 0x0 2% 3% 4%
7.5b LDOn_OV_THR = 0x1 2.5% 3.5% 4.5%
7.5c LDOn_OV_THR = 0x2 3% 4% 5%
7.5d Overvoltage monitoring for LDO LDOn_OV_THR = 0x3 4% 5% 6%
VLDO_OV_TH output, threshold accuracy,
7.5e VOUT_LDOn ≥ 1 V(2) LDOn_OV_THR = 0x4 5% 6% 7%
7.5f LDOn_OV_THR = 0x5 6% 7% 8%
7.5g LDOn_OV_THR = 0x6 7% 8% 9%
7.5h LDOn_OV_THR = 0x7 9% 10% 11%

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7.10 Monitoring Functions (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/
ground pad of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
7.6a LDOn_OV_THR = 0x0 20 30 40
7.6b LDOn_OV_THR = 0x1 25 35 45
7.6c LDOn_OV_THR = 0x2 30 40 50
7.6d Overvoltage monitoring for LDO LDOn_OV_THR = 0x3 40 50 60
VLDO_OV_TH_mv output, threshold accuracy, mV
7.6e VOUT_LDOn < 1 V(2) LDOn_OV_THR = 0x4 50 60 70
7.6f LDOn_OV_THR = 0x5 60 70 80
7.6g LDOn_OV_THR = 0x6 70 80 90
7.6h LDOn_OV_THR = 0x7 90 100 110
7.7a LDOn_UV_THR = 0x0 –4% –3% –2%
7.7b LDOn_UV_THR = 0x1 –4.5% –3.5% –2.5%
7.7c LDOn_UV_THR = 0x2 –5% –4% –3%
7.7d Undervoltage monitoring for LDOn_UV_THR = 0x3 –6% –5% –4%
VLDO_UV_TH LDO output, threshold accuracy,
7.7e VOUT_LDOn ≥ 1 V(2) LDOn_UV_THR = 0x4 –7% –6% –5%
7.7f LDOn_UV_THR = 0x5 –8% –7% –6%
7.7g LDOn_UV_THR = 0x6 –9% –8% –7%
7.7h LDOn_UV_THR = 0x7 –11% –10% –9%
7.8a LDOn_UV_THR = 0x0 –40 –30 –20
7.8b LDOn_UV_THR = 0x1 –45 –35 –25
7.8c LDOn_UV_THR = 0x2 –50 –40 –30
7.8d Undervoltage monitoring for LDOn_UV_THR = 0x3 –60 –50 –40
VLDO_UV_TH_mv LDO output, threshold accuracy, mV
7.8e VOUT_LDOn < 1 V(2) LDOn_UV_THR = 0x4 –70 –60 –50
7.8f LDOn_UV_THR = 0x5 –80 –70 –60
7.8g LDOn_UV_THR = 0x6 –90 –80 –70
7.8h LDOn_UV_THR = 0x7 –110 –100 –90
Electrical Characteristics: VCCA INPUT
7.9a VCCA_OV_THR = 0x0 2% 3% 4%
7.9b VCCA_OV_THR = 0x1 2.5% 3.5% 4.5%
7.9c VCCA_OV_THR = 0x2 3% 4% 5%
7.9d Overvoltage monitoring for VCCA VCCA_OV_THR = 0x3 4% 5% 6%
VCCAOV_TH
7.9e input, threshold accuracy(3) VCCA_OV_THR = 0x4 5% 6% 7%
7.9f VCCA_OV_THR = 0x5 6% 7% 8%
7.9g VCCA_OV_THR = 0x6 7% 8% 9%
7.9h VCCA_OV_THR = 0x7 9% 10% 11%
7.10a VCCA_UV_THR = 0x0 -4% -3% -2%
7.10b VCCA_UV_THR = 0x1 -4.5% -3.5% -2.5%
7.10c VCCA_UV_THR = 0x2 -5% -4% -3%
7.10d Undervoltage monitoring for VCCA_UV_THR = 0x3 -6% -5% -4%
VCCAUV_TH
7.10e VCCA input, threshold accuracy(3) VCCA_UV_THR = 0x4 -7% -6% -5%
7.10f VCCA_UV_THR = 0x5 -8% -7% -6%
7.10g VCCA_UV_THR = 0x6 -9% -8% -7%
7.10h VCCA_UV_THR = 0x7 -11% -10% -9%
Timing Requirements
BUCK and LDO OV/UV detection Detection delay with 5 mV (Vin < 1 V) or 0.5% (Vin ≥ 1 V)
26.30a tdelay_OV_UV 8 µs
delay over/underdrive
26.30b tdelay_OV_UV VCCA OV/UV detection delay Detection delay with 30 mV over/underdrive 12 µs
VMON_DEGLITCH_SEL = 0: Digital deglitch time for
26.31a tdeglitch1_OV_UV 3.4 3.8 4.2 µs
VCCA, BUCK and LDO OV/UV detected signal
signal deglitch time VMON_DEGLITCH_SEL = 1: Digital deglitch time for
26.31b tdeglitch2_OV_UV 18 20 22 µs
detected signal

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7.10 Monitoring Functions (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/
ground pad of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VMON_DEGLITCH_SEL = 0: Total delay from 5mV (Vin < 1
26.32a tlatency1_OV_UV V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM 13 µs
BUCK and LDO OV/UV signal trigger
latency time VMON_DEGLITCH_SEL = 1: Total delay from 5mV (Vin < 1
26.32b tlatency2_OV_UV V) or 0.5% (Vin ≥ 1 V) over/underdrive to interrupt or PFSM 30 µs
trigger
tlatency1_VCCA_OV VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/
26.32b 13 µs
_UV underdrive to interrupt or PFSM trigger
VCCA OV/UV signal latency time
tlatency2_VCCA_OV VMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/
26.32b 30 µs
_UV underdrive to interrupt or PFSM trigger
tdeglitch_PGOOD_ris
26.33a Internal logic signal transitions from invalid to valid(4) 9.5 10.5 µs
e
PGOOD signal deglitch time
tdeglitch_PGOOD_fal
26.33b Internal logic signal transitions from valid to invalid(4) 0 µs
l

(1) The default values of BUCKn_OV_THR & BUCKn_UV_THR registers come from the NVM memory, and can be re-configured by
software.
(2) The default values of LDOn_OV_THR & LDOn_UV_THR registers come from the NVM memory, and can be re-configured by software.
(3) The default values of VCCA_OV_THR & VCCA_UV_THR registers come from the NVM memory, and can be re-configured by
software.
(4) Interrupt status signal is input signal for PGOOD deglitch logic.

7.11 Clocks, Oscillators, and PLL

Over operating free-air temperature range (unless otherwise noted).
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics: CRYSTAL
6.1 Crystal frequency 32768 Hz
6.2 Crystal frequency tolerance Parameter of crystal, TJ = 25°C –20 20 ppm
6.4 Crystal series resistance At fundamental frequency 90 kΩ
The power dissipated in the crystal during oscillator
6.5 Oscillator drive power 0.1 0.5 μW
operation
Corresponding to crystal frequency, including parasitic
6.6 Crystal Load capacitance(1) 6 12.5 pF
capacitances
6.7 Crystal shunt capacitance Parameter of crystal 1.4 2.6 pF
Electrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS
6.7a Load capacitance on External Capacitors 0 13 pF
OSC32KIN and OSC32KOUT
(parallel mode, including
6.7b parasitic of PCB for external Internal Capacitors 9.5 12 14.5 pF
capacitor)(2)
Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK
Crystal Oscillator output
23.1 Typical with specified load capacitors 32768 Hz
frequency
Crystal Oscillator Output duty
23.2 Parameter of crystal, TJ = 25°C 40% 50% 60%
cycle
Crystal Oscillator rise and fall
23.3 10% to 90%, with 10 pF load capacitance 10 20 ns
time
From Oscillator enable to reaching ±1% of final output
23.4 Crystal Oscillator Settling time 200 ms
frequency
Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK
20 MHz RC Oscillator output
23.10 19 20 21 MHz
frequency
128 kHz RC Oscillator output
23.12 121 128 135 kHz
frequency
Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT

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7.11 Clocks, Oscillators, and PLL (continued)

Over operating free-air temperature range (unless otherwise noted).
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
22.1a EXT_CLK_FREQ = 0x0 1.1
External input clock nominal
22.1b EXT_CLK_FREQ = 0x1 2.2 MHz
frequency
22.1c EXT_CLK_FREQ = 0x2 4.4
22.2a SS_DEPTH = 0x0 –18% 18%
External input clock required
22.2b accuracy from nominal SS_DEPTH = 0x1 –12% 12%
frequency
22.2c SS_DEPTH = 0x2 –10% 10%
22.13 Logic low time for SYNCCLKIN
40 ns
a clock
22.13 Logic high time for
40 ns
b SYNCCLKIN clock
External clock detection delay
22.3 1.8 µs
for missing clock detection
External clock input debounce
22.4 20 µs
time for clock detection
Clock change delay (internal to
22.5 From valid clock detection to use of external clock 600 µs
external)
22.7a SYNCCLKOUT_FREQ_SEL = 0x1 1.1 MHz
SYNCCLKOUT clock nominal
22.7b SYNCCLKOUT_FREQ_SEL = 0x2 2.2 MHz
frequency
22.7c SYNCCLKOUT_FREQ_SEL = 0x3 4.4 MHz
22.8 SYNCCLKOUT duty-cycle Cycle-to-cycle 40% 50% 60%
SYNCCLKOUT output buffer
22.9 5 35 50 pF
external load
22.11a Spread spectrum variation SS_DEPTH = 0x1 6.3%
for nominal switching
22.11b frequency SS_DEPTH = 0x2 8.4%

Timing Requirements: Clock Monitors

26.7a Clock Monitor Failure signal Failure on 20MHz system clock 10 µs
tlatency_CLKfail latency from occurrence of
26.7b error Failure on 128KHz monitoring clock 40 µs

Clock Monitor Drift signal

26.8 tlatency_CLKdrift 115 µs
latency from detection
26.9 fsysclk Internal system clock 19 20 21 MHz
Threshold for internal system
26.10 CLKdrift_TH -20% 20%
clock frequency drift detection
Threshold for internal system
26.11 CLKfail_TH clock stuck at high or stuck at 10 MHz
low detection

(1) Customer must use the XTAL_SEL bit to select the corresponding crystal based on its load capacitance.
(2) External capacitors must be used if crystal load capacitance > 6 pF.

7.12 Thermal Monitoring and Shutdown

Over operating free-air temperature range (unless otherwise noted).
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
8.1a TWARN_0 TWARN_INT thermal warning TWARN_LEVEL = 0 120 130 140 °C
8.1b TWARN_1 threshold (no hysteresis) TWARN_LEVEL = 1 130 140 150 °C
8.2a TSD_orderly_0 TSD_ORD_INT thermal TSD_ORD_LEVEL = 0 130 140 150 °C
8.2b TSD_orderly_1 shutdown rising threshold TSD_ORD_LEVEL = 1 135 145 155 °C
TSD_orderly_hys_
8.2c TSD_ORD_LEVEL = 0 10 °C
0 TSD_ORD_INT thermal
TSD_orderly_hys_ shutdown hysteresis
8.2d TSD_ORD_LEVEL = 1 5 °C
1

TSD_IMM_INT thermal
8.3a TSD_imm 140 150 160 °C
shutdown rising threshold

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7.12 Thermal Monitoring and Shutdown (continued)

Over operating free-air temperature range (unless otherwise noted).
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TSD_IMM_INT
8.3b TSD_imm_hys 5 °C
thermal shutdown hysteresis
Timing Requirements
TSD signal latency from
26.6 tlatency_TSD 425 µs
detection

7.13 System Control Thresholds

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
VCCA UVLO/POR falling
9.1 VPOR_Falling Measured on VCCA pin 2.7 2.75 2.8 V
threshold
VCCA UVLO/POR rising
9.2 VPOR_Rising Measured on VCCA pin 2.7 3 V
threshold
9.3 VPOR_Hyst VCCA UVLO/POR hysteresis 100 mV
9.5aa VVCCA_OVP_Risi Measured on VCCA pin. VCCA_PG_SET = 0b 3.9 4.0 4.1 V
VCCA OVP rising threshold
9.5ab ng Measured on VCCA pin. VCCA_PG_SET = 1b 5.6 5.7 5.8 V
VVCCA_OVP_Hys
9.5b VCCA OVP hysteresis 50 mV
t

Input slew rate of VCCA and Measured at VCCA and PVIN_x pins as voltage rises
9.15 VVCCA_PVIN_SR 60 mV/µs
PVIN_x supplies from 0V to VPOR_Rising
Measured at VIO pin as voltage rises from 0V
9.16 VVIO_SR Input slew rate of VIO supply 60 mV/µs
to VPOR_Rising
Input slew rate of VBACKUP
9.17 VVBACKUP_SR Measured at VBACKUP pin 60 mV/µs
supply
Timing Requirements
VCCA_PG_SEL = 0b. Total delay from detection of
26.3a 15 µs
tlatency_VCCAOV VCCA_OVP signal latency VCCA_OVP to the rise of VCCA_OVP_INT
P from detection VCCA_PG_SEL = 1b. Total delay from detection of
26.3b 15 µs
VCCA_OVP to the rise of VCCA_OVP_INT
Measured time between VVCCA falling from 3.3 V to
tlatency_VCCAUVL VCCA_UVLO signal latency
26.4 2.7 V with ≤ 100mv/µs slope, to the detection of 10 µs
O from detection
VCCA_UVLO signal
LDOVINT OVP and UVLO
26.5 tlatency_VINT With 25-mV overdrive 12 µs
signal latency from detection
26.15 tLBISTrun Run time for LBIST 1.8 ms
Device initialization time to
tINIT_NVM_ANAL load default values for NVM
26.16 2 ms
OG registers, and start-up analog
circuits
Device initialization time for
tINIT_REF_CLK_L
26.17 reference bandgaps, system 1 ms
DO
clock, and internal LDOs

7.14 Current Consumption

Over operating free-air temperature range (unless otherwise noted).
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
From VBACKUP pin. PWRON/ENABLE deactivated.
Backup current consumption, Device powered by the backup battery source. VCCA
10.2 IBACKUP_RTC 7 10 µA
regulators disabled = 0V. VIO = 0V. VBACKUP = 3.3V. Only 32-kHz crystal
oscillator and RTC counters are functioning. TJ = 25℃.

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7.14 Current Consumption (continued)

Over operating free-air temperature range (unless otherwise noted).
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Combined current from VCCA and PVIN_x pins. VCCA
Low Power Standby current = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. 32-kHz
10.3a ILP_STANDBY consumption, regulators crystal oscillator and RTC digital is functioning. GPIO 11 24 µA
disabled pins in LDOVRTC domain are active. All monitors are
off. TJ = 25℃.
Combined current from VCCA, and PVIN_x. VCCA =
10.5a ISTANDBY Standby current consumption PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ = 25℃. 50 62 µA
VCCA_VMON_EN=0.
Combined current from VCCA and PVIN_x pins. VCCA
= PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V. TJ =
10.6a ISLEEP_3V3 Sleep current consumption 290 363 µA
25℃. One buck regulator enabled in PFS/PWM mode,
no load. Buck and VCCA OV/UV monitoring enabled.
Combined current from VCCA and PVIN_x pins. VCCA
= PVIN_Bx = PVIN_LDOx = 5 V. VIO = 0V. TJ = 25℃.
10.6b ISLEEP_5V Sleep current consumption 300 375 µA
One buck regulator enabled in PFS/PWM mode, no
load. Buck and VCCA OV/UV monitoring enabled.

7.15 Backup Battery Charger

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
27.1a VBACKUP = 1 V, BB_ICHR = 0x0 100
Icharge Charging current µA
27.1b VBACKUP = 1 V, BB_ICHR = 0x1 500
27.2a BB_VEOC = 0x0 2.4 2.5 2.6
27.2b BB_VEOC = 0x1 2.7 2.8 2.9
VEOC End of charge voltage(1) V
27.2c BB_VEOC = 0x2 2.9 3 3.1
27.2d BB_VEOC = 0x3 3.2 3.3 3.4
End of charge, charger
27.3 Iq_CHGR Quiescent current of backup battery charger enabled, VCCA - VBACKUP > 200 5 9 µA
mV. Measured from VCCA pin
VCCA - VBACKUP > 200 mV. Charger
27.4a disabled. Device not in BACKUP state. 10 100
Iq_CHGR_ Tj < 125°C
Off current of backup battery charger nA
OFF VCCA - VBACKUP > 200 mV. Charger
27.4b disabled. Device not in BACKUP state. 250
125°C < Tj < 150°C
Additional capacitor added when
27.5 CBKUP Backup battery capacitance with additional capacitor 1 2.2 4 µF
backup battery ESR > 20 Ω
27.6a RBKUP_E Without additional capacitor in parallel 20
Backup battery series resistance Ω
27.6b SR With additional capacitor in parallel 1000

(1) End of charge (EOC) voltage measured when VCCA-VBACKUP > 200mV. When VCCA-VBACKUP is ≤ 200mV, the charger remains
fully functional, although the EOC voltage measurement is not based on final voltage, but on charger dropout.

7.16 Digital Input Signal Parameters

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics: nPWRON/ENABLE
11.1 VIL(VCCA) Low-level input voltage -0.3 0 0.54 V
11.2 VIH(VCCA) High-level input voltage 1.26 V
11.3 Hysteresis 150 mV
Electrical Characteristics: I2C/SPI Pins and Input Signals through all GPIO pins
11.4 VIL(DIG) Low-level input voltage -0.3 0 0.54 V

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7.16 Digital Input Signal Parameters (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
11.5 VIH(DIG) High-level input voltage 1.26 V
11.6 Hysteresis 150 mV
Timing Requirements: nPWRON/ENABLE
24.1a tLPK_TIME nPWRON Long Press Key time 8 s
24.1b tdegl_PWRON nPWRON button deglitch time ENABLE_DEGLITCH_EN = 1 48 50 52 ms
ENABLE_EGLITCH_EN = 1, exclude when activated
24.2 tdegl_ENABLE ENABLE signal deglitch time(1) under LP_STANDBY state while the system clock is not 6 8 10 µs
available
Timing Requirements: GPIx, nSLEEPx, nERRx, and other digital input signals
Time from valid GPIx assertion
until device wakes up from
24.3 tWKUP_LP 5 ms
LP_STANDBY state to ACTIVE
or MCU ONLY states
GPIx and nSLEEPx signal
25.1a tdegl_GPIx GPIOn_DEGLITCH_EN = 1 6 8 10 µs
deglitch time
Time from receiving nPWRON/
25.2a ENABLE trigger in STANDBY 5 ms
state to nRSTOUT assertion
tSTARTUP Time from a valid GPIx
assertion until device starts
25.2b LDOVINT = 1.8V 1.5 ms
power-up sequence from a low
power state
Time from nSLEEPx assertion
until device starts power-down
25.3 tSLEEP LDOVINT = 1.8V 1.5 ms
sequence to enter a low power
state
input through LP_WKUP1 and LP_WKUP2 (GPIO3 or
25.4a Minimum valid input pulse 40 ns
GPIO4) pins while the device is in LP_STANDBY state
tWK_PW_MIN width for the WKUP input
signals input through WKUP1, WKUP2, LP_WKUP1 and
25.4b 200 ns
LP_WKUP2 pins while the device is in mission states
DISABLE_WDOG input signal
25.5a tWD_DIS 24 30 36 µs
deglitch time
TRIG_WDOG input signal
25.5b tWD_pulse 24 30 36 µs
deglitch time

(1) ENABLE signal deglitch is not available when device is activated from the LP_STANDBY state while the deglitching clock is not
available.

7.17 Digital Output Signal Parameters

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics: SDA_I2C1, and Output Signals through GPO1 and GPO2 pins
Low-level output voltage, push-
12.11 VOL(VIO)_20mA IOL = 20 mA 0.4 V
pull and open-drain
High-level output voltage,
12.12 VOH(VIO) IOH = 3 mA VIO – 0.4 V
push-pull
Electrical Characteristics: Output Signals through GPO3 and GPO4 pins
Low-level output voltage, push-
12.13 VOL(DIG) IOL = 3 mA 0.4 V
pull
High-level output voltage,
12.14 VOH(DIG) IOH = 3 mA 1.4 V
push-pull
Electrical Characteristics: Output Signals through GPO5 and GPO6 pins
Low-level output voltage, push-
12.4 VOL(DIG)_20mA IOL = 20 mA 0.4 V
pull

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7.17 Digital Output Signal Parameters (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of
the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level output voltage,
12.5 VOH(DIG) IOH = 3 mA 1.4 V
push-pull
Electrical Characteristics: Output Signals through GPO7, GPO8, GPO9, GPO10, and GPO11 pins
Low-level output voltage, push-
12.1 VOL(VIO) IOL = 3 mA 0.4 V
pull and open-drain
High-level output voltage,
12.2 VOH(VIO) IOH = 3 mA VIO – 0.4 V
push-pull
Supply for external pullup
12.3 VIO V
resistor, open drain
Electrical Characteristics:nINT, nRSTOUT
Low-level output voltage for
12.7 VOL(nINT) IOL = 20 mA 0.4 V
nINT pin
Low-level output voltage
12.8 VOL(nRSTOUT) for nRSTOUT and IOL = 20 mA 0.4 V
nRSTOUT_SoC pin
Timing Requirements
Gating time for readback
12.10 tgate_readback Signal level change or GPIO selection (GPIOn_SEL) 8.8 9.6 µs
monitor

7.18 I/O Pullup and Pulldown Resistance

Over operating free-air temperature range, VIO refers to the VIO_IN pin, VCCA refers the VCCA pin.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
13.1a nPWRON pullup resistance nPWRON IO buffer internal pull up to VCCA supply 280 400 520 kΩ
ENABLE IO buffer internal pull up to VCCA supply and
13.1b ENABLE pullup and pulldown resistance 280 400 520 kΩ
pull down to ground
13.2 GPIO pullup resistance GPIO1 -11 pins configured as input with internal pullup 280 400 520 kΩ
GPIO1 - 11 pins configured as inputs with internal
13.3 GPIO pulldown resistance 280 400 520 kΩ
pulldown
nRSTOUT and nRSTOUT_SoC pullup
13.4 Internal pullup to VIO supply when output driven high 8 10 12 kΩ
resistance

7.19 I2C Interface

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7.19 I2C Interface (continued)

Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode
(400 kHz), and fast mode+ (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
16.3a Standard mode 4
16.3b Fast mode 0.6 µs
16.3c tHIGH SCL high time Fast mode+ 0.26
16.3d High-speed mode, Cb = 100 pF 60
ns
16.3e High-speed mode, Cb = 400 pF 120
16.4a Standard mode 250
16.4b Fast mode 100
tSU;DAT Data setup time ns
16.4c Fast mode+ 50
16.4d High-speed mode 10
16.5a Standard mode 10 3450
16.5b Fast mode 10 900 ns
16.5c tHD;DAT Data hold time Fast mode+ 10
16.5d High-speed mode, Cb = 100 pF 10 70
ns
16.5e High-speed mode, Cb = 400 pF 10 150
16.6a Standard mode 4.7
16.6b Setup time for a start Fast mode 0.6 µs
tSU;STA or a REPEATED START
16.6c condition Fast mode+ 0.26
16.6d High-speed mode 160 ns
16.7a Standard mode 4
16.7b Hold time for a start or Fast mode 0.6 µs
tHD;STA a REPEATED START
16.7c condition Fast mode+ 0.26
16.7d High-speed mode 160 ns
16.8a Standard mode 4.7
Bus free time between
16.8b tBUF a STOP and START Fast mode 1.3 µs
condition
16.8c Fast mode+ 0.5
16.9a Standard mode 4
16.9b Setup time for a STOP Fast mode 0.6 µs
tSU;STO
16.9c condition Fast mode+ 0.26
16.9d High-speed mode 160 ns
16.10a Standard mode 1000
16.10b Fast mode 20 300
16.10c trDA Rise time of SDA signal Fast mode+ 120 ns
16.10d High-speed mode, Cb = 100 pF 10 80
16.10e High-speed mode, Cb = 400 pF 20 160
16.11a Standard mode 300
16.11b Fast mode 6.5 300
16.11c tfDA Fall time of SDA signal Fast mode+ 6.5 120 ns
16.11d High-speed mode, Cb = 100 pF 10 80
16.11e High-speed mode, Cb = 400 pF 13 160
16.12a Standard mode 1000
16.12b Fast mode 20 300
16.12c trCL Rise time of SCL signal Fast mode+ 120 ns
16.12d High-speed mode, Cb = 100 pF 10 40
16.12e High-speed mode, Cb = 400 pF 20 80
16.13a Rise time of SCL signal High-speed mode, Cb = 100 pF 10 80
after a repeated start
trCL1 ns
16.13b condition and after an High-speed mode, Cb = 400 pF 20 160
acknowledge bit

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7.19 I2C Interface (continued)

7.20 Serial Peripheral Interface (SPI)

These specifications are ensured by design, VIO = 1.8 V or 3.3V (unless otherwise noted).
POS PARAMETERS TEST CONDITIONS MIN NOM MAX UNIT
Electrical Characteristics
15.1 Capacitive load on pin SDO 30 pF
Timing Requirements
17.1 1 Cycle time 200 ns
17.2 2 Enable lead time 150 ns
17.3 3 Enable lag time 150 ns
17.4 4 Clock low time 60 ns
17.5 5 Clock high time 60 ns
17.6 6 Data setup time 15 ns
17.7 7 Data hold time 15 ns
17.8 8 Output data valid after SCLK falling 4 ns
17.9 9 New output data valid after SCLK falling 60 ns
17.1
10 Disable time 30 ns
0
17.1
11 CS inactive time 100 ns
1

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7.21 Typical Characteristics

65 260
VCCA_PG_SET = 3.3 V
60
VCCA_PG_SET = 5 V
55 255

50 LP STANDBY, no OVP
Quiescent Current (µA)

Standby Current (µA)

250
45 LP STANDBY
STANDBY
40 245
35
30 240
25
235
20
15 230
10
5 225
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
VCCA (V) VCCA (V)

TA = 25°C TA = 25°C
Figure 7-1. Quiescent Current vs Input Voltage Figure 7-2. Standby Current with VCCA Monitor
4 1.5

1.3
3
Total Active Phases

VVOUT_Bn (V)
1.1

2 SR = 33.3 V/ms
0.9 SR = 20 V/ms
SR = 10 V/ms
SR = 5 V/ms
1 2.2 MHz, Adding SR = 2.5 V/ms
2.2 MHz, Shedding 0.7 SR = 1.25 V/ms
4.4 MHz, Adding SR = 0.625 V/ms
4.4 MHz, Shedding SR = 0.3125 V/ms
0 0.5
0 1 2 3 4 5 6 0.5 1 1.5 2 2.5 3 3.5 4
IOUT_Bn (A) Time (ms)

VPVIN_Bn = 3.3 V Buck VSET = 1.0 V TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 0.6 V TA = 25°C
to 1.4 V
Figure 7-3. Buck Phase Adding and Shedding
Figure 7-4. Buck Ramp-up Slew Rate
1.5 1.2
SR = 33.3 V/ms
SR = 20 V/ms
1
SR = 10 V/ms
1.3
SR = 5 V/ms
SR = 2.5 V/ms 0.8
SR = 1.25 V/ms
VVOUT_Bn (V)

VVOUT_Bn (V)

1.1 SR = 0.625 V/ms 0.6

SR = 0.3125 V/ms
2.2MHz, 1-phase
0.4 2.2MHz, 2-phase
0.9
2.2MHz, 3-phase
0.2 2.2MHz, 4-phase
4.4MHz, 1-phase
0.7 4.4MHz, 2-phase
0 4.4MHz, 3-phase
4.4MHz, 4-phase
0.5 -0.2
0.5 1 1.5 2 2.5 3 3.5 4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (ms) Time (ms)

VPVIN_Bn = 3.3 Buck VSET = 1.4 V to TA = 25°C VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms
V 0.6 V Figure 7-6. Buck Start-up with no Load, Auto Mode
Figure 7-5. Buck Ramp-down Slew Rate

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7.21 Typical Characteristics (continued)

1.2 1.2

1 1

0.8 0.8
VVOUT_Bn (V)

VVOUT_Bn (V)
0.6 0.6
2.2MHz, 1-phase 2.2MHz, 1-phase
0.4 2.2MHz, 2-phase 0.4 2.2MHz, 2-phase
2.2MHz, 3-phase 2.2MHz, 3-phase
0.2 2.2MHz, 4-phase 0.2 2.2MHz, 4-phase
4.4MHz, 1-phase 4.4MHz, 1-phase
4.4MHz, 2-phase 4.4MHz, 2-phase
0 4.4MHz, 3-phase 0 4.4MHz, 3-phase
4.4MHz, 4-phase 4.4MHz, 4-phase
-0.2 -0.2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (ms) Time (ms)

VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms
Figure 7-7. Buck Start-up with 1A Load, Auto Mode Figure 7-8. Buck Shutdown with no Load, Auto Mode
1.2 1.6

1
1.4
0.8
VVOUT_Bn (V)

VVOUT_Bn (V)
1.2
0.6
2.2MHz, 1-phase
0.4 2.2MHz, 2-phase 1
2.2MHz, 3-phase
0.2 2.2MHz, 4-phase
4.4MHz, 1-phase
4.4MHz, 2-phase 0.8
0 4.4MHz, 3-phase No Load
4.4MHz, 4-phase with 1A load
-0.2 0.6
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 5 10 15 20 25 30 35
Time (ms) Time (us)

VPVIN_Bn = 3.3 V Buck VSET = 1 V Slew Rate = 5 V/ms VPVIN_Bn = 3.3 V Buck VSET = 0.6 V Slew Rate = 33.3
Figure 7-9. Buck Shutdown with 1A Load, Auto Mode to 1.4 V V/ms
Figure 7-10. Buck Ramp-up with and without Load
1.5 3.5
No Load 3.3 V to 0.8 V
1.4 with 1A load 3 3.3 V to 1.8 V
5 V to 0.8 V
1.3 5 V to 1.8 V
2.5
5 V to 3.3 V
1.2 Bypass Mode
VOUT(LDOn) (V)
VVOUT_Bn (V)

2
1.1
1.5
1
1
0.9
0.5
0.8

0.7 0

0.6 -0.5
0 10 20 30 40 50 60 70 80 90 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Time (us) Time (ms)

VPVIN_Bn = 3.3 Buck VSET = 1.4 V to Slew Rate = 33.3 VIN(LDOn) = 3.3 V or 5 V TA = 25°C
V 0.6 V V/ms Figure 7-12. GPLDO Start-up with LDOn_SLOW_RAMP = 0
Figure 7-11. Buck Ramp-down with and without Load

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7.21 Typical Characteristics (continued)

3.5 3.5
3.3 V to 0.8 V 3.3 V to 0.8 V
3 3.3 V to 1.8 V 3.3 V to 1.8 V
3
5 V to 0.8 V 5 V to 0.8 V
2.5 5 V to 1.8 V 5 V to 1.8 V
5 V to 3.3 V 2.5 5 V to 3.3 V
Bypass Mode Bypass Mode
VOUT(LDOn) (V)

VOUT(LDOn) (V)
2
2
1.5
1.5
1
1
0.5

0 0.5

-0.5 0
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 0 2 4 6 8 10 12 14 16 18 20
Time (ms) Time (ms)

VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or LDOn_PLDN = 500 TA = 25°C

Figure 7-13. GPLDO Start-up with LDOn_SLOW_RAMP = 1 5V Ω
Figure 7-14. GPLDO Shutdown
3.5 3.5
3.3 V to 0.8 V 3.3 V to 0.8 V
3 3.3 V to 1.8 V 3 3.3 V to 1.8 V
5 V to 0.8 V 5 V to 0.8 V
2.5 5 V to 1.8 V 2.5 5 V to 1.8 V
5 V to 3.3 V 5 V to 3.3 V
VOUT(LDOn) (V)

VOUT(LDOn) (V)
2 2

1.5 1.5

1 1

0.5 0.5

0 0

-0.5 -0.5
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Time (ms) Time (ms)

VIN(LDOn) = 3.3 V or 5 V TA = 25°C VIN(LDOn) = 3.3 V or 5 V TA = 25°C

Figure 7-15. LNLDO Start-up with LDOn_SLOW_RAMP = 0 Figure 7-16. LNLDO Start-up with LDOn_SLOW_RAMP = 1
3.5
3.3 V to 0.8 V
3.3 V to 1.8 V
3
5 V to 0.8 V
5 V to 1.8 V
2.5 5 V to 3.3 V
VOUT(LDOn) (V)

1.5

0.5

0
0 2 4 6 8 10 12 14 16 18 20
Time (ms)

VIN(LDOn) = 3.3 V or 5 V LDOn_PLDN = 500 Ω TA = 25°C

Figure 7-17. LNLDO Shutdown

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8 Detailed Description
8.1 Overview
The TPS6593-Q1 device is a Power-Management Integrated Circuit (PMIC), available in a 56-pin, 0.5-mm pitch,
8-mm × 8-mm QFN package. The TPS6593-Q1 is designed for powering embedded systems or System on Chip
(SoC) in automotive or industrial applications. The TPS6593-Q1 provides five configurable BUCK regulators, of
which four rails have the ability to combine outputs in multi-phase mode. BUCK4 has the ability to supply up to
4 A output current in single-phase mode, while BUCK1, BUCK2, and BUCK3 have the ability to supply up to
3.5 A output current in single-phase mode. When working in multi-phase mode, each BUCK1, BUCK2, BUCK3,
and BUCK4 can supply up to 3.5 A output current per phase, adding up to 14 A output current in four-phase
configuration. BUCK5 is a single-phase only BUCK regulator, which supports up to 2 A output current. All five
of the BUCK regulators have the capability to sink a current up to 1 A, and support dynamic voltage scaling.
Double-buffered voltage scaling registers enable each BUCK regulator to transition to a different voltage during
operation by SPI or I2C. A digital PLL enables the BUCK regulators to synchronize to an external clock input,
with phase delays between the output rails.
The TPS6593-Q1 device also provides three LDO rails, which can supply up to 500 mA output current per rail
and can be configured in bypass mode and used as a load switch. One additional low-noise LDO rail can supply
up to 300 mA output current. The 500-mA LDOs support 0.6 V to 3.3 V output voltage with 50-mV step. The
300-mA low-noise LDO supports 1.2 V to 3.3 V output voltage with 25-mV step. The output voltages of the LDOs
can be pre-configured through the SPI or I2C interfaces, which are used to configure the power rails and the
power states of the TPS6593-Q1 device.
I2C channel 1 (I2C1) is the main channel with access to the registers, which control the configurable power
sequencer, the states and the outputs of power rails, the device operating states, the RTC registers and the
Error Signal Monitors. I2C channel 2 (I2C2), which is available through the GPIO1 and GPIO2 pins, is dedicated
for accessing the Q&A Watchdog communication registers. If GPIO1 and GPIO2 are not configured as I2C2
pins, I2C1 can access all of the registers, including the Q&A Watchdog registers. Alternatively, depending on the
NVM-configuration of the orderable part number, SPI is the selected interface for the device and can be used to
access all registers.
The TPS6593-Q1 device includes an internal RC-oscillator to sequence all resources during power up and
power down. Two internal LDOs (LDOVINT and LDOVRTC) generate the supply for the entire digital circuitry of
the device as soon as the external input supply is available through the VCCA input. A backup battery supply
input can also be used to power the RTC block and a 32-kHz Crystal Oscillator clock generator in the event of
main supply power loss.
TPS6593-Q1 device has eleven GPIO pins each with multiple functions and configurable features. All of the
GPIO pins, when configured as general-purpose output pins, can be included in the power-up and power-down
sequence and used as enable signals for external resources. In addition, each GPIO can be configured as a
wake-up input or a sleep-mode trigger. The default configuration of the GPIO pins comes from the non-volatile
memory (NVM), and can be re-programmed by system software if the external connection permits.
The TPS6593-Q1 device includes a watchdog with selectable trigger or Q&A modes to monitor MCU software
lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the lock-step
signal of the attached SoC or MCU. TPS6593-Q1 includes protection and diagnostic mechanisms such as
voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, CRC
on configuration registers, CRC on non-volatile memory, CRC on communication interfaces, current-limit and
short-circuit protection on all output rails, thermal pre-warning, and over-temperature shutdown. The device also
includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two Error Signal Monitor
inputs with selectable level mode or PWM mode, and with fault injection options to monitor the error signals
from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt
handler, allowing the MCU to take action in response.
An SPMI interface is included in the TPS6593-Q1 device to distribute power state information to at most five
satellite PMICs on the same network, thus enabling synchronous power state transition across multiple PMICs in
the application system. This feature allows the consolidation of IO control signals from up to six PMICs powering
the system into one primary TPS6593-Q1 PMIC.

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8.2 Functional Block Diagram

VSYS VIO

VCCA

VOUT_LDOVINT

VOUT_LDOVRTC
VBACKUP

VIO_IN
<PBKG>
<GND_DIG>
<GND_ANA>
nPWRON/ENABLE
Control
Interface

Grounds Windowed
PGOOD
SCL_I2C1/CLK_SPI Power-Good
LDOVINT BSM LDOVRTC Monitor
SDA_I2C1/SDI_SPI I2C CNTRL,
CS_SPI or SPI VINT VRTC SYNCCLKOUT
SDO_SPI Single or

Output Buffer
VCC internal Multi-Phase
nRSTOUT supply
Internal EN PVIN_B1 VCCA
nINT Interrupt BUCK1
VSEL 3.5 A SW_B1
events
RC DPLL RAMP FB_B1
GPIO1
Oscillator (Phase CLK1 (AVS)
synchronization <GND_B1>
SYNCCLKIN
GPIO2 and dither)

EN PVIN_B2 VCCA
Application Processor

GPIO3 BUCK2
DFT VSEL 3.5 A SW_B2
NVM Controller RAMP FB_B2
GPIO4 NVM Memory CLK2 (AVS)
<GND_B2>
Registers
GPIO5
VCCA Pre-Configurable PVIN_B3 VCCA
Interrupt handler

EN
VCCA_UVLO Power Sequencer BUCK3
GPIO6 VSEL 3.5 A SW_B3
Controller
GPIO

RAMP FB_B3
ECO CLK3 (AVS)
GPIO7 <GND_B3>
WAKEn PWM
NSLEEPn DVS
GPIO8 Default NVM Settings
EN BUCK4 PVIN_B4 VCCA
Thermal VSEL 4 A (1N) SW_B4
GPIO9 Monitoring and 3.5A (multiN)
RAMP FB_B4
Shutdown CLK4
(AVS) <GND_B4>
GPIO10 Hot die detection

GPIO11 EN PVIN_B5 VCCA

BUCK5
VSEL 2A SW_B5
OSC32KIN RAMP FB_B5
32-kHz Crystal CLK5 Single-Phase
OSC32KOUT RTC <GND_B5>
Oscillator
OSC32KCAP
100Ÿ
EN
VSEL

EN
VSEL
EN
VSEL

EN
VSEL

VRTC REFGND1
Bypass Bypass Bypass LDO4
LDO1 LDO2 LDO3 300 mA
Internal supply 500 mA 500 mA 500 mA Low Noise
Quiet Ground
PVIN_LDO12

VOUT_LDO2

VOUT_LDO3

VOUT_LDO4
VOUT_LDO1

AMUX_OUT Reference
PVIN_LDO3

PVIN_LDO4

and Bias
REFGND2

VCCA

* These red squares are internal pads for down-bonds to the package thermal/ground pad.

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8.3 Feature Description

8.3.1 System Supply Voltage Monitor
The comparator module in TPS6593-Q1, which monitors the voltage on the VCCA pins, controls the power state
machine of the device. VCCA voltage detection outputs determine the power states of the device as follows:
VCCA_UVLO The TPS6593-Q1 returns to the BACKUP state. LDOVRTC is powered by the output of the
Backup Supply Management (BSM) module during the BACKUP state. The device returns to the
NO SUPPLY state and is completely shut down when the input supply of the LDOVRTC falls
below the operating range. The device cannot return to the BACKUP state from the NO SUPPLY
state.
VCCA_UV The TPS6593-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on
the VCCA pin rises above VCCA_UV during initial power-up.
VCCA_OVP If the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6593-Q1 is in
operation, then the device clears the ENABLE_DRV bit and starts the immediate shutdown
sequence.

A separate voltage comparator monitors whether or not the VCCA voltage is within the expected PGOOD range
when VCCA is expected to be 5-V or 3.3-V. This voltage comparator checks at device power-up whether the
voltage on the VCCA supply pin is above the VCCA_UV threshold. Refer to Section 8.3.3 for additional detail on
the operation of the PGOOD monitor function.
LDOVINT, which is the internal supply to the digital core of the device, may attempt to restart the device when
the input voltage at VCCA pin falls or stays between VCCA_UVLO and VCCA_UV voltage levels; the voltage at
the VCCA pin, however, must be above the VCCA_UV voltage level for the device to power up properly.
Figure 8-1 shows a block diagram of the VCCA input voltage monitoring.

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VSYS VCCA
Preregulator

External Protection

VCCA
Safety
Band Gap

VCCA_UVLO +

VCCA_OVP ±

VCCA OVP and UVLO

Monitor

Figure 8-1. VCCA Monitor

8.3.2 Power Resources (Bucks and LDOs)

The power resources provided by the TPS6593-Q1 device includes synchronous, current mode control bucks
and linear LDOs. These supply resources provide power to the external processors, components, and modules
inside the TPS6593-Q1 device. The supply of the bucks, the PVIN_Bx pins, must connect to the VCCA pin
externally. The supply of the LDOs, the PVIN_LDOx pins, may connect to the VCCA pin or a buck output which
is at a lower voltage level than the VCCA.
The voltage output of each power resource is continuously monitored by a dedicated analog monitor on an
independent reference voltage domain. An unused regulator can also be used as a voltage monitor for an
external rail by connecting the external rail to the FB_Bn the VOUT_LDOn pin.
Table 8-1 lists the power resources provided by the TPS6593-Q1 device.
Table 8-1. Power Resources
RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS
0.3 V to 0.6 V, 20-mV steps
BUCK1, BUCK2, 0.6 V to 1.1 V, 5-mV steps Can be configured in multi-phase mode
BUCK 3.5 A
BUCK3 1.1 V to 1.66 V, 10-mV steps or stand-alone in single-phase mode
1.66 V to 3.34 V, 20-mV steps
0.3 V to 0.6 V, 20-mV steps
0.6 V to 1.1 V, 5-mV steps 4 A in single-phase mode Can be configured in multi-phase mode
BUCK4 BUCK
1.1 V to 1.66 V, 10 mV steps 3.5 A in multi-phase mode or stand-alone in single-phase mode
1.66 V to 3.34 V, 20-mV steps

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Table 8-1. Power Resources (continued)

RESOURCE TYPE VOLTAGE CURRENT CAPABILITY COMMENTS
0.3 to 0.6 V, 20-mV steps
0.6 V to 1.1 V, 5-mV steps
BUCK5 BUCK 2A Only in single-phase mode
1.1 V to 1.66 V, 10-mV steps
1.66 V to 3.34 V , 20-mV steps
LDO1, LDO2,
LDO 0.6 V to 3.3 V, 50-mV steps 500 mA Bypass mode configurable
LDO3
LDO4 LDO 1.2 V to 3.3 V, 25-mV steps 300 mA Low-noise

8.3.2.1 Buck Regulators

8.3.2.1.1 BUCK Regulator Overview
The TPS6593-Q1 includes five synchronous buck converters, of which four can be combined in multi-phase
configuration. All of the buck converters support the following features:
• Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation
• External clock synchronization option to minimize crosstalk
• Optional spread spectrum technique to reduce EMI
• Soft start
• AVS support with configurable slew-rate
• Windowed undervoltage and overvoltage monitors with configurable threshold
• Windowed voltage monitor for external supply when the buck converter is inactive
• Output Current Limit
• Short-to-Ground Detection on SW_Bx pins at start-up of the buck regulator
When the outputs of these buck converters are combined in multi-phase configuration, it also supports the
following features:
• Current balancing between the phases of the converter
• Differential voltage sensing from point of the load
• Phase shifted outputs for EMI reduction
• Optional dynamic phase shedding or adding
There are two modes of operation for the buck converter, depending on the required output current: pulse-width
modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load
currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically
switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy
filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM =
1). The forced-PWM mode is the recommended mode of operation for the buck converter to achieve better ripple
and transient performance. The drawback of this forced-PWM mode is the higher quiescent current at low output
current levels.
When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on
the load current level. The forced multi-phase mode can be enabled for lower ripple at the output.
Figure 8-2 shows a block diagram of a single core.
Figure 8-3 shows the interleaving switching action of the multi-phase converters.

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PVIN
High-Side
Current Limit
Loop
FBP Comparator
Feedback Network
FBN
PWM Gate PDN
± Generator Driver
Low-Side
DAC + Current Limit
Error
CLK
Amplifier

Figure 8-2. BUCK Core Block Diagram

IL_TOT_4PH

IL1
IL2

IL4

IL3

0 90 180 270 360 450 540 630 720

PWM1

PWM2

PWM4

PWM3

Switching Cycle 360º

0 90 180 270 360 450 540 630 720

Phase (Degrees)

Figure 8-3. Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase
Configuration. 1

8.3.2.1.2 Multi-Phase Operation and Phase-Adding or Shedding

The 4-phase converters (BUCK1, BUCK2, BUCK3, and BUCK4) switches each channel 90° apart under heavy
load conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the
switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency
three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching
frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions.
The TPS6593-Q1 can change the number of active phases to optimize efficiency for the variations of the load in
order to overcome this operational inefficiency. The process in which the multi-phase buck regulator in case of
increasing load current automatically increases the number of active phases is called phase adding. The process
in which the multi-phase buck regulator in case of decreasing load current automatically decreases the number
of active phases is called phase shedding. The concept is shown in Figure 8-4.

1 Graph is not in scale and is for illustrative purposes only.

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The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register.
If the regulator operates in forced multi-phase mode , each phase automatically operates in the forced-PWM
mode. If the multi-phase operation is not forced, the number of phases are added and shed automatically to
follow the required output current.
Best efficiency obtained with

Operation

Operation
1-Phase

2-Phase

3-Phase

4-Phase
N=1

N=2
Efficiency

N=3
N=4

Load Current

Figure 8-4. Multiphase BUCK Converter Efficiency vs Number of Phases (Converters in PWM Mode) 2

8.3.2.1.3 Transition Between PWM and PFM Modes

The forced-PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load.
TheTPS6593-Q1 converter operates in PWM mode at load current of approximately 600 mA or higher. The
device automatically switches into PFM mode for reduced current consumption when forced-PWM mode is
not enabled (BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide
output-load-current range by combining the PFM and the PWM modes.
8.3.2.1.4 Multi-Phase BUCK Regulator Configurations
The control of the multi-phase regulator settings is done using the control registers of the primary BUCK
regulator in the multi-phase configuration. The TPS6593-Q1 ignores settings in the following registers of the
secondary and, if used, the tertiary and quaternary BUCK regulators :
• BUCKn_CTRL register, except BUCKn_VMON_EN
• BUCKn_CONF register
• BUCKn_VOUT_1 and BUCKn_VOUT_2 registers
• BUCKn_PG_WINDOW register
• Interrupt bits related to the secondary and, if sued, the tertiary and quaternary BUCK regulator, except
BUCKn_ILIM_INT, BUCKn_ILIM_MASK and BUCKn_ILIM_STAT
Table 8-2 shows the supported Multi-Phase BUCK regulator configurations and the assigned primary BUCK
regulator in each configuration.
Table 8-2. Primary BUCK Assignment for Supported Multi-phase Configuration
Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment
4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4 BUCK1
3-Phase: BUCK1 + BUCK2 + BUCK3 BUCK1

2 Graph is not in scale and is for illustrative purposes only.

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Table 8-2. Primary BUCK Assignment for Supported Multi-phase Configuration (continued)
Supported Multi-Phase BUCK Regulator Configuration Primary BUCK Assignment
2-Phase: BUCK1 + BUCK2 BUCK1
2-Phase: BUCK3 + BUCK4 BUCK3

When the BUCK regulators are configured in 3-phase or 4-phase configurations, there are exceptions to the
above list of registers that the TPS6593-Q1 ignores. The configuration registers are user-configurable for
the voltage monitor function on BUCK3 and BUCK4 in a 4-phase configuration and BUCK3 in a 3-phase
configuration. The UV/OV voltage monitors of these BUCK3 and BUCK4 regulators can be used to monitor
external supply rails, by connecting these external rails to the FB_Bn pins of these BUCK3 and BUCK4
regulators. The following list of registers and register bits for BUCK3 and BUCK4 can be used to enable and set
the target voltage for the external voltage monitoring function under such configuration:
• BUCKn_VMON_EN bit
• BUCKn_VSEL bit
• BUCKn_SLEW_RATE
• BUCKn_VOUT_1 and BUCKn_VOUT_2 registers
• BUCKn_PG_WINDOW register
Customers are responsible for the values set in these registers when using BUCK3 or BUCK4 to monitor an
external supply under the 3-phase or 4-phase configuration. If the voltage monitor function is not used under
such a scenario, the FB_Bn pins must be connected to the reference ground, and the BUCKn_VMON_EN bits
must be set to '0'.
8.3.2.1.5 Spread-Spectrum Mode
The TPS6593-Q1 device supports spread-spectrum modulation of the switching clock signal used by the BUCK
regulators. Three factory-selectable modulation modes are available: the first mode is modulation from external
input clock at the SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using
the DPLL; the third mode is modulating the internal 20-MHz RC-Oscillator clock using the DPLL.
The spread-spectrum modulation mode is pre-configured in NVM. Changing this modulation mode during
operation is not supported.
The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock
to the DPLL is ±18% to secure parametric compliance of the BUCK output performance.
The internal modulation is inactive by default and can be enabled and configured after power up. Internal
modulation is activated by setting the SS_EN control bit. The internal modulation must be inactive (SS_EN = 0)
when changing the following parameter:
• SS_DEPTH[1:0] – Spread Spectrum modulation depth
When internal modulation is enabled and configured, it can be made inactive by the system MCU during
operation. The device transition to different mission states does not impact internal modulation when it is
enabled and configured.
8.3.2.1.6 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered
up to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The
purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance
of the attached SoC.
All of BUCK regulators in the TPS6593-Q1 device support AVS and DVS voltage scaling changes. Once
the AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets
the BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the
AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur:
• Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY
state
• Error that causes the device to execute warm reset

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• MCU configures the device to enter the LP STANDBY state

Figure 8-5 shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register
using the BUCKn_VSET control registers.
I2C/SPI

BUCK ENABLE *)
I2C/SPI

BUCK VOLTAGE SELECT *)

BUCKn_VSEL BUCKn_EN

I2C/SPI BUCKn_VSET1
DCDC
MUX Regulator
I2C/SPI BUCKn_VSET2

*) BUCK ENABLE and BUCK VOLTAGE SELECT bits

are located in BUCKx_CTRL register

Figure 8-5. AVS/DVS Configuration Register Arbitration Diagram

The digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor
during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at
the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a
delay calculated by Equation 1.
When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is
updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by Equation 1.

tPG_OV_UV_DELAY = (dV / BUCKn_SLEW_RATE) + tsettle_Bx (1)

In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV
and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the
BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK
OV monitor output is masked for a fixed delay time of tPG_OV_GATE, that is approximately 115 µs – 128 µs. The
UV monitor output is masked for the time duration calculated by Equation 2. The 370-µs additional delay time in
the formula includes the start-up delay of the BUCK regulator, and the fixed delay after the ramp.

tPG_UV_GATE = (BUCKn_VSET / BUCKn_SLEW_RATE) + 370 µs (2)

Note
Because output capacitance, forward and negative current limits and load current of the BUCK
regulator may affect the slew rate of the BUCK regulator output voltage, the delay time of tPG_UV_GATE
may not be sufficient long for the slower slew rate setting when the target BUCK regulator output
voltage is higher. Please refer to the PMIC user's guide for detail information about the supported
voltage level and slew rate setting combinations of a particular orderable part number.

Figure 8-6 and Figure 8-7 are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK
regulators and the corresponding OV and UV monitor threshold changes.

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OV limit Inial voltage AVS_VNOM

OV limit OV limit
Default from NVM UV limit
UV limit

BUCKn VOUT
I2C/SPI write
State control (or State control (or State control (or
I2C/SPI write) I2C/SPI write) I2C/SPI write)

BUCKn_VSET1 0x00 0x5F 0x5A

Automac control
by digital
BUCKn_VSET2 0x00 0x5F

BUCKn_EN 0 1 0 1
0 us
Register bits BUCKn_OV_SET
(internal register, not 0x00 0x5F 0x5A
accessible by user)
tPG_OV_UV_DELAY
BUCKn_UV_SET 0x00 0x5F 0x5A
(internal register, not
accessible by user)

BUCKn_VSEL 0

BUCKn_OV_UV_EN 0 1 0 1

Automac control Automac control

0 us
by digital Automac control by digital
by digital
BUCKn_OV Monitor Output

BUCKn_OV Gang tPG_OV_GATE tPG_OV_GATE

Automac control
0 us by digital
BUCKn_UV Monitor Output

BUCKn_UV Ga ng tPG_UV_GATE
tPG_UV_GATE

Figure 8-6. AVS Voltage and OV UV Threshold Level Change Timing Diagram

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OPP_OD OPP_OD
(or OPP_TURBO) (or OPP_TURBO)
OPP_NOM
OV limit
OV limit
UV limit
UV limit
BUCKn VOUT

I2C/SPI write
(DVFS control) State control (or State control (or
I2C/SPI write) I2C/SPI write)

BUCKn_VSET1 0x5F 0x73

BUCKn_VSET2 0x5F
Automac control
by digital
BUCKn_EN 1 0 1
0 us
BUCKn_OV_SET
Register bits (internal register, not 0x5F 0x73
accessible by user)
tPG_OV_UV_DELAY
BUCKn_UV_SET
(internal register, not
0x5F 0x73
accessible by user)

BUCKn_VSEL 0

BUCKn_OV_UV_EN 1 0 1

0 us Automac control
Automac control by digital
by digital
BUCKn_OV Monitor Output

BUCKn_OV Gang tPG_OV_GATE

0 us
BUCKn_UV Monitor Output

BUCKn_UV Ga ng
tPG_UV_GATE

Figure 8-7. DVS Voltage and OV UV Threshold Level Change Timing Diagram

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8.3.2.1.7 BUCK Output Voltage Setting

Table 8-3 shows the coding used to select the BUCK regulator output voltage.
Table 8-3. Output Voltage Selection for BUCK Regulators
Output Output Output Output Output Output
BUCKn_VSE BUCKn_VSE BUCKn_VSE BUCKn_VSE BUCKn_VSE BUCKn_VSE
Voltage [V] Voltage [V] Voltage [V] Voltage [V] Voltage [V] Voltage [V]
Tn Tn Tn Tn Tn Tn
20 mV steps 5 mV steps 5 mV steps 10 mV steps 20 mV steps 20 mV steps
0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52
0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54
0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56
0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58
0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6
0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62
0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64
0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66
0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68
0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7
0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72
0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74
0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76
0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78
0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8
0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82
0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84
0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86
0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88
0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9
0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92
0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94
0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96
0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98
0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0
0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02
0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04
0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06

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Table 8-3. Output Voltage Selection for BUCK Regulators (continued)

Output Output Output Output Output Output
BUCKn_VSE BUCKn_VSE BUCKn_VSE BUCKn_VSE BUCKn_VSE BUCKn_VSE
Voltage [V] Voltage [V] Voltage [V] Voltage [V] Voltage [V] Voltage [V]
Tn Tn Tn Tn Tn Tn
20 mV steps 5 mV steps 5 mV steps 10 mV steps 20 mV steps 20 mV steps
0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08
0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1
0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12
0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14
0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16
0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18
0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2
0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22
0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24
0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26
0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28
0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3
0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32
0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34
0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5
0x3A 0.815 0x6C 1.065 0x9E 1.53
0x3B 0.82 0x6D 1.07 0x9F 1.54
0x3C 0.825 0x6E 1.075 0xA0 1.55
0x3D 0.83 0x6F 1.08 0xA1 1.56
0x3E 0.835 0x70 1.085 0xA2 1.57
0x3F 0.84 0x71 1.09 0xA3 1.58
0x40 0.845 0x72 1.095 0xA4 1.59
0xA5 1.6
0xA6 1.61
0xA7 1.62
0xA8 1.63
0xA9 1.64
0xAA 1.65

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8.3.2.1.8 BUCK Regulator Current Limit

Each BUCK regulator includes a Current Limit to protect the internal High-Side and Low-Side Power-FETs
against over-current. The High-Side Current Limit, also referred to as Forward Current Limit, is for BUCK1..4
adjustable between 2.5 A and 5.5 A with 1-A steps with register bits BUCKx_ILIM[3:0]. For BUCK5, this Forward
Current Limit has selectable levels 2.5 A and 3.5 A with register bits BUCK5_ILIM[3:0].
The Low-Side Current Limit, also referred to as Negative Current Limit, has a fixed value of typical 2 A.
8.3.2.1.9 SW_Bx Short-to-Ground Detection
Each BUCK regulator includes a SW_Bx Short-to-Ground Detection. This SW_Bx Short-to-Ground Detection
monitors whether the SW_B1...SW_B5 pins have a short-to-ground condition, either caused by external short
on these pins or caused by a short in the low-side power-FET of the BUCK regulator. This SW_Bx Short
to Ground Detection is activated before the power-up of the BUCK regulator. When this function detects a
short-to-ground condition on the SW_B1...SW_B5 pins, the TPS6593-Q1 aborts the power-up sequence and
sets the corresponding interrupt bits BUCKx_SC_INT (x=1...5). After this, the TPS6593-Q1 transitions to the
SAFE RECOVERY state, after which it performs an attempt to restart as described in Section 8.4.1.1.
8.3.2.1.10 Sync Clock Functionality
The TPS6593-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the BUCK
regulator with the external clock. The block diagram of the clocking and PLL module is shown in Figure 8-8. The
external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency
of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, or 4.4
MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical input frequency
for valid clock detection.
The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is
not available or the clock frequency is not within the valid range.
The TPS6593-Q1 device can also generate a clock signal, SYNCCLKOUT, for external device
use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note:
SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output
frequency selection can cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8,
GPIO9, or GPIO10.

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20 MHz
RC
Main CLK
Oscillator RESET
Detector

Main Digital Clock

Buck1

20 MHz
RC ÷ 18 Buck2
Oscillator
Phase and
DPLL
52.8MHz +/- 20% freq control
SYNCCLKIN /N
Detector
Divider
SYNCCLKOUT SYNCCLKOUT
_FREQ_SEL
Divider Clock Select
Spread-spec
SYNCCLKIN ´(;7_CLK_ Logic
Control
)5(4´

SEL_EXT_CLK

Figure 8-8. Sync Clock and DPLL Module

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8.3.2.2 Low Dropout Regulators (LDOs)

All of the LDO regulators in the TPS6593-Q1 device can be supplied by the system supply or another pre-
regulated voltage source which are within the specified VIN range. The PVIN_LDOn voltage level must be equal
or less than the VCCA voltage level to ensure proper operation of the LDOs. The default output voltages of all
LDOs are loaded from the NVM memory and can be configured by the LDOn_VSET[7:0]. There is no hardware
protection to prevent software from selecting an improper output voltage if the minimum level of PVIN_LDOn is
lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage. In such
conditions, the output voltage droops to near the PVIN_LDOn level.

Note
Writing a RESERVED value to the LDOn_VSET[7:0] register bits causes a LDOn_OV_INT or
LDOn_UV_INT interrupt.

The LDO regulators do not have slew rate control for voltage ramp; by setting the LDOn_SLOW_RAMP bit to '1',
however, the ramp up speed of the regulator output voltage is < 3 V/ms.
If an LDO is not needed, its associated UV/OV Voltage Monitor can be used to monitor an external voltage rail
by connecting the external rail to the VOUT_LDOn pin. The voltage level of the monitored external rail must be
within the PGOOD monitor range of the LDOn_VSET[7:0] of the LDO. If an external resistor divider is necessary
in this case, the user must take into account the input impedance at the VOUT_LDOn pin (as shown in Figure
8-9), and adjust the resistor values to compensate for the voltage shift.
External Supply
Output

PVIN_LDOn

VOUT_LDOn
LDO
50 kŸ
Pull-Down resistor 512 kŸ
when LDOs are
Disabled
LDOn_UV_THR
+
UV
±

DAC
±
LDOnOV_THR OV
+

Figure 8-9. Impedance at the VOUT_LDOn Pins

8.3.2.2.1 LDOVINT
The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the TPS6593-Q1
device, which are not required to be always-on and can be turned-off when the device is in low power states.
The LDOVINT voltage regulator is automatically turned on and off as needed if LP_STANDBY_SEL = '1'. The
automatic control optimizes the overall current consumption when the device is in low power LP_STANDBY
state.
The LDOVINT voltage regulator is dedicated for internal use only, and cannot be used to support external
loads. An output filtering capacitor must be connected at the VOUT_LDOVINT pin. Do not connect any other
components or external loads to this VOUT_LDOVINT pin.
8.3.2.2.2 LDOVRTC
The LDOVRTC voltage regulator supplies always-on functions, such as wake-up functions. This power resource
is active as soon as a valid VCCA is present. The LDOVRTC voltage regulator is dedicated for internal use

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only, and cannot be used to support external loads. An output filtering capacitor must be connected at the
VOUT_LDOVRTC pin. Do not connect any other components or external loads to this VOUT_LDOVRTC pin.
This voltage regulator is enabled in normal mode or backup mode. The LDOVRTC voltage regulator functions in
normal mode when supplied from the main system power rail and is able to supply the input buffers of GPIO3
and GPIO4, the digital components, the crystal, and the RTC calendar module of the TPS6593-Q1 device. The
LDOVRTC voltage regulator remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the
backup power source is above the LDOVRTC_UVLO level.
Only the 32 kHz crystal and the RTC counter are activated in the BACKUP state. The RTC calendar function
remains active in the LP_STANDBY state, but the interrupt functions are reduced to maintaining the wake up
functions only. The RTC calendar and interrupt functions are fully activated in the mission states.
The customer has the option to enable the shelf mode by setting the LDORTC_DIS bit to 1 while the device is in
the MISSION state and the I2C bus is in operation and ramp down VCCA to 0 V immediately after the I2C write
has completed. This shelf mode forces the device to skip the BACKUP state and enters the NO SUPPLY state
under VCCA_UVLO condition. This mode is useful to prevent the continual draining of the backup power source
when the 32 KHz crystal and RTC counter functions are no longer needed.
8.3.2.2.3 LDO1, LDO2, and LDO3
The LDO1, LDO2 and LDO3 regulators can deliver up to 500 mA of current, with a configurable output range
of 0.6 V to 3.3 V in 50-mV steps. These 3 LDO regulators also support bypass mode, which allows an input
voltage at the PVIN_LDOn to show up at the VOUT_LDOn pin. This feature allows the LDOs to be configured
as load switches with power sequencing control. Similar to the buck regulators mentioned in Section 8.3.2.1.4,
the UV/OV Voltage Monitor of an un-used LDO regulator can also be used to monitor an external voltage rail by
connecting the external rail to the VOUT_LDOn pin.
The bypass capability to connect the input voltage to the output in bypass mode is supported when the input
voltage is within the 1.7 V to 3.5 V range. This bypass capability also allows the LDO to switch from 3.3 V in
bypass mode to 1.8 V in LDO mode or from 1.8 V in LDO mode to 3.3 V in bypass mode for an SD card I/O
supply.
The LDO1, LDO2 and LDO3 regulator include a Current-Limit to protect the internal Power-FET against
overcurrent. This Current-Limit has a fixed value between 700 mA and 1800 mA.
It is important to wait until the LDO has settled on the target voltage from the previous change when changing
the LDO output voltage setting. The worst-case voltage scaling time for LDO1, LDO2, and LDO3 is 63 µs x (7 +
the number of 50-mV steps to the new target voltage).
Table 8-4 shows the coding used to select the output voltage for LDO1, LDO2, and LDO3.
Table 8-4. Output Voltage Selection for LDO1, LDO2, and LDO3
Output Voltage Output Voltage Output Voltage Output Voltage
LDOx_VSET LDOx_VSET LDOx_VSET LDOx_VSET
[V] [V] [V] [V]
0x00 Reserved 0x10 1.20 0x20 2.00 0x30 2.80
0x01 Reserved 0x11 1.25 0x21 2.05 0x31 2.85
0x02 Reserved 0x12 1.30 0x22 2.10 0x32 2.90
0x03 Reserved 0x13 1.35 0x23 2.15 0x33 2.95
0x04 0.60 0x14 1.40 0x24 2.20 0x34 3.00
0x05 0.65 0x15 1.45 0x25 2.25 0x35 3.05
0x06 0.70 0x16 1.50 0x26 2.30 0x36 3.10
0x07 0.75 0x17 1.55 0x27 2.35 0x37 3.15
0x08 0.80 0x18 1.60 0x28 2.40 0x38 3.20
0x09 0.85 0x19 1.65 0x29 2.45 0x39 3.25
0x0A 0.90 0x1A 1.70 0x2A 2.50 0x3A 3.30
0x0B 0.95 0x1B 1.75 0x2B 2.55 0x3B Reserved
0x0C 1.00 0x1C 1.80 0x2C 2.60 0x3C Reserved

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Table 8-4. Output Voltage Selection for LDO1, LDO2, and LDO3 (continued)
Output Voltage Output Voltage Output Voltage Output Voltage
LDOx_VSET LDOx_VSET LDOx_VSET LDOx_VSET
[V] [V] [V] [V]
0x0D 1.05 0x1D 1.85 0x2D 2.65 0x3D Reserved
0x0E 1.10 0x1E 1.90 0x2E 2.70 0x3E Reserved
0x0F 1.15 0x1F 1.95 0x2F 2.75 0x3F Reserved

8.3.2.2.4 Low-Noise LDO (LDO4)

The LDO4 regulator can deliver up to 300 mA of current, with a configurable output range of 1.2 V to 3.3 V in
25-mV steps. This LDO is specifically designed to supply noise sensitive circuits. This supply can be used to
power circuits such as PLLs, oscillators, or other analog modules that require low noise on the supply. LDO4
does not support bypass mode. However, if the LDO4 output voltage is not used, the associated UV/OV Voltage
Monitor of this regulator can be used as to monitor an external voltage rail by connecting this external voltage rail
to the VOUT_LDO4 pin.
The LDO4 regulator includes a Current-Limit to protect the internal Power-FET against overcurrent. This
Current-Limit has a fixed value between 400 mA and 900 mA.
Table 8-5 shows the coding used to select the output voltage for LDO4.
Table 8-5. Output Voltage Selection for LDO4
Output Voltage Output Voltage Output Voltage Output Voltage
LDO4_VSET LDO4_VSET LDO4_VSET LDO4_VSET
[V] [V] [V] [V]
0x00 Reserved 0x20 1.200 0x40 2.000 0x60 2.800
0x01 Reserved 0x21 1.225 0x41 2.025 0x61 2.825
0x02 Reserved 0x22 1.250 0x42 2.050 0x62 2.850
0x03 Reserved 0x23 1.275 0x43 2.075 0x63 2.875
0x04 Reserved 0x24 1.300 0x44 2.100 0x64 2.900
0x05 Reserved 0x25 1.325 0x45 2.125 0x65 2.925
0x06 Reserved 0x26 1.350 0x46 2.150 0x66 2.950
0x07 Reserved 0x27 1.375 0x47 2.175 0x67 2.975
0x08 Reserved 0x28 1.400 0x48 2.200 0x68 3.000
0x09 Reserved 0x29 1.425 0x49 2.225 0x69 3.025
0x0A Reserved 0x2A 1.450 0x4A 2.250 0x6A 3.050
0x0B Reserved 0x2B 1.475 0x4B 2.275 0x6B 3.075
0x0C Reserved 0x2C 1.500 0x4C 2.300 0x6C 3.100
0x0D Reserved 0x2D 1.525 0x4D 2.325 0x6D 3.125
0x0E Reserved 0x2E 1.550 0x4E 2.350 0x6E 3.150
0x0F Reserved 0x2F 1.575 0x4F 2.375 0x6F 3.175
0x10 Reserved 0x30 1.600 0x50 2.400 0x70 3.200
0x11 Reserved 0x31 1.625 0x51 2.425 0x71 3.225
0x12 Reserved 0x32 1.650 0x52 2.450 0x72 3.250
0x13 Reserved 0x33 1.675 0x53 2.475 0x73 3.275
0x14 Reserved 0x34 1.700 0x54 2.500 0x74 3.300
0x15 Reserved 0x35 1.725 0x55 2.525 0x75 Reserved
0x16 Reserved 0x36 1.750 0x56 2.550 0x76 Reserved
0x17 Reserved 0x37 1.775 0x57 2.575 0x77 Reserved
0x18 Reserved 0x38 1.800 0x58 2.600 0x78 Reserved
0x19 Reserved 0x39 1.825 0x59 2.625 0x79 Reserved
0x1A Reserved 0x3A 1.850 0x5A 2.650 0x7A Reserved
0x1B Reserved 0x3B 1.875 0x5B 2.675 0x7B Reserved

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Table 8-5. Output Voltage Selection for LDO4 (continued)

Output Voltage Output Voltage Output Voltage Output Voltage
LDO4_VSET LDO4_VSET LDO4_VSET LDO4_VSET
[V] [V] [V] [V]
0x1C Reserved 0x3C 1.900 0x5C 2.700 0x7C Reserved
0x1D Reserved 0x3D 1.925 0x5D 2.725 0x7D Reserved
0x1E Reserved 0x3E 1.950 0x5E 2.750 0x7E Reserved
0x1F Reserved 0x3F 1.975 0x5F 2.775 0x7F Reserved

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8.3.3 Output Voltage Monitor and PGOOD Generation

The TPS6593-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages
of the BUCK and LDO, regulators and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to
indicate the result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD
monitor if it is not masked. Either voltage and current monitoring or only voltage monitoring can be selected
for PGOOD indication. This selection is set by the PGOOD_SEL_BUCKn register bits for each BUCK regulator
(select primary phase for multi-phase regulator), and is set by the PGOOD_SEL_LDOn register bits for each
LDO regulator. When voltage and current are monitored, an active PGOOD signal active indicates that the
regulator output is inside the Power-Good voltage window and that load current is below the current limit. If only
voltage is monitored, then the current monitoring is ignored for the PGOOD signal.
The PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD
signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when
the previous indicated warning or error condition is no longer present.
The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC)
comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the
corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to
the PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. For LDO
regulators, the LDOn_VMON_EN bit enables the OV and UV, short-circuit (SC) comparators. The current limit
(ILIM) comparator of each LDO regulator is activated as soon as the corresponding LDO regulator is enabled.
In order to add the current limit indication of an LDO to the PGOOD signal, the LDOn_VMON_EN bit of the
corresponding LDO regulator must be set. When a BUCK or an LDO is not needed as a regulated output, it can
be used as a voltage monitor for an external rail. For BUCK converters, if the BUCKn_VMON_EN bit remains
'1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for an external rail that is connected
to the FB_Bn pin of the BUCK regulator. For LDO regulators, if the LDOn_VMON_EN bit remains '1' while
the LDOn_EN bit is '0', it can be used as a voltage monitor for an external rail which is connected to the
VOUT_LDOn pin.
When the voltage monitor for a BUCK or LDO regulator is inactive, the output of the corresponding monitor is
automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected
to other open-drain power good signals in the system.
The VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by
an NVM default setting, that starts the monitoring of the VCCA voltage after the device passes the BOOT BIST
state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit to either 3.3 V or 5 V.
The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA monitor is included in the
PGOOD monitor output signal.
An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the
intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the
PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is
gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for
external peripherals.
The outputs of the voltage monitors from all the output rails are combined, and PGOOD is active only if all the
sources shows active status.
The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only
undervoltage is monitored; if the bit is 1, then undervoltage and overvoltage are monitored.
The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits.
Figure 8-10 shows the Power-Good generation block diagram, and Figure 8-11 shows the Power-Good
waveforms.

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Die TJ < TWARN

TWARN_LEVEL Temperature
Monitor

PGOOD_SEL_TDIE_WARN

VMON
VMON
BUCKn
VMON
BUCKn
VMON
BUCKn
BUCKn PGOOD_BUCKn
PGOOD_WINDOW BUCKn
Monitor

BUCKn_ILIM
BUCKn_VSETn
BUCKn_UV_THR
BUCKn_OV_THR
BUCKn_VMON_EN
PGOOD_SEL_BUCKn

VMON
VMON
BUCKn
VMON
BUCKn
LDOn PGOOD_LDOn
PGOOD_WINDOW BUCKn
Monitor
PGOOD (GPIO9)

LDOn_VSET
LDOn_UV_THR
LDOn_OV_THR
PGOOD_POL
LDOn_VMON_EN
PGOOD_SEL_LDOn

VCCA PGOOD_VCCA
PGOOD_WINDOW
Monitor

VCCA_PG_SET
VCCA_UV_THR
VCCA_OV_THR
VCCA_VMON_EN
PGOOD_SEL_VCCA

NRSTOUT
PGOOD_SEL_NRSTOUT

NRSTOUT_SoC
PGOOD_SEL_NRSTOUT_SOC

Figure 8-10. PGOOD Block Diagram

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Voltage
Powergood window
BUCKn_VSETn or
LDOn_VSET (1)

BUCKn_VSETn or Power-good
LDOn_VSET (2) window

Time
On Request

VIO

BUCKn_VMON_EN
or LDOn_VMON_EN

NRSTOUT
or NRSTOUT_SoC
tlatency tlatency
_PGOOD _PGOOD

PGOOD
(PGOOD_SEL_NRSTOUT =1
or PGOOD_SEL_NRSTOUT_SOC = 1) tlatency tlatency
_PGOOD _PGOOD
PGOOD
(PGOOD_SEL_NRSTOUT = 0
and PGOOD_SEL_NRSTOUT_SOC = 0)

Regulator VSET BUCKn_VSETn or LDOn_VSET (1) BUCKn_VSETn or LDOn_VSET (2)

Figure 8-11. PGOOD Waveforms

The OV and UV threshold of the voltage monitors of the BUCK regulators and the LDO regulators are updated
automatically by the digital control block when the output voltage setting changes. When the output voltage of
the regulator is increased, the OV threshold is updated at the same time the _VSET of the regulator is changed.
The UV threshold is updated after a delay calculated by the delta voltage change and the slew rate setting.
When the output voltage is decreased, the UV threshold is updated at the same time the _VSET of the regulator
is changed. The OV threshold is updated after a delay calculated by the delta voltage change and the slew rate
setting. The OV and UV threshold of the BUCK and LDO output voltage monitors are calculated based on the
target output voltage set by the corresponding BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and
the deviation from the target output voltage set (the voltage window) by the corresponding BUCKn_UV_THR,
BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers. For the OV and UV threshold of BUCK
and LDO output monitors to update with the correct timing, the following operating procedures must be followed
when updating the _VSET values of the regulators to avoid detection of OV/UV fault:
• BUCK and LDO regulators must be enabled at the same time as or earlier than as their VMON
• New voltage level must not be set before the start-up has finished
• New voltage level must not be set before the previous voltage change (ramp plus settling time) has
completed
The voltage monitors of unused BUCK or LDO regulators can be used for external supply rails monitoring. In
three-phase configuration, the Voltage Monitor of BUCK3 (on FB_B3 pin) becomes a free available resource
for monitoring an external supply voltage. In four-phase configuration, the Voltage Monitor of both BUCK3
(on FB_B3 pin) and BUCK4 (on FB_B4 pin) become free available resources for monitoring two external
supply voltages.. The target output voltage is set by the corresponding BUCKn_VSET1, BUCKn_VSET2,
or LDOn_VSET registers, and the deviation from the target output voltage set (the voltage window) by
the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers.
Following aspects need to be taken into account if Voltage Monitors of unused BUCK or LDO regulators are
used for monitoring external supply rails:
• For voltage monitors of unused LDO regulators: the voltage level applied at the VOUT_LDOx pin, inclusive
expected tolerances, must be below the supply voltage applied at the PVIN_LDOx pin

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• For voltage monitors of unused BUCK and LDO regulators: the maximum nominal supply voltage of the
monitored supply rail is 3.3V
• For voltage monitors of unused BUCK regulators and for voltage monitors of BUCK3 and/or BUCK4
regulators if used in a three-phase or four-phase configuration: the configured values for the BUCKn_VSET
and the BUCKn_SLEW_RATE determine the delay-time for the voltage monitoring to become active after
the corresponding BUCKn_VMON_EN bit is set. See equation (2) in Section 8.3.2.1.6. If BUCK3 and/or
BUCK4 regulators are used in a three-phase or four-phase configuration: even though the values for the
BUCK1_VSET and BUCK1_SLEW_RATE bits determine the output voltage and slew-rate of the three-phase
or four-phase output rail, the values for BUCK3_VSET respectively BUCK4_VSET and BUCK3_SLEW_RATE
respectively BUCK4_SLEW_RATE bits determine the power-good level and the voltage monitoring delay
time for the BUCK3 respectively BUCK4 Voltage Monitors.
• For voltage monitors of unused LDO regulators: the delay-time for the voltage monitoring to become active
after the corresponding LDOn_VMON_EN bit is set it 601..606μs.

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8.3.4 Thermal Monitoring

The TPS6593-Q1 device includes several thermal monitoring functions for internal thermal protection of the
PMIC.
The TPS6593-Q1 device integrates thermal detection modules to monitor the temperature of the die. These
modules are placed on opposite sides of the device and close to the LDO and BUCK modules. An over-
temperature condition at either module first generates a warning to the system, and if the temperature continues
to rise, then a switch-off of the PMIC device can occur before damage to the die.
Three thermal protection levels are available. One of these protections is a thermal warning function described in
Section 8.3.4.1, that sends an interrupt to software. Software is expected to close any noncritical running tasks
to reduce power. The second and third protections are the thermal shutdown (TS) function described in Section
8.3.4.2, that begins device shutdown orderly or immediately.
Thermal monitoring is automatically enabled when one of the BUCK or LDO outputs is enabled within the
mission states. The thermal monitoring is deactivated in the LP_STANDBY state, when only the internal
regulators are enabled, to minimize the device power consumption. Indication of a thermal warning event is
written to the TWARN_INT register.
The current consumption of the thermal monitoring can be decreased in the mission states when the low power
dissipation is important. If LPM_EN bit is set and the temperature is below thermal warning level in all thermal
detection modules, only one thermal detection module is monitored. If the temperature rises in this module,
monitoring in all thermal detection modules is started.
If the die temperature of the TPS6593-Q1 device continues to rise while the device is in mission state, an
TSD_ORD_INT or TSD_IMM_INT interrupt is generated, causing a SEVERE or MODERATE error trigger
(respectively) in the state machine. While the sequencing and error handling is NVM memory dependent,
TI recommends a sequenced shutdown for MODERATE errors, and an immediate shutdown, using resistive
discharging, for SEVERE errors to prevent damage to the device. The system cannot restart until the
temperature falls below the thermal warning threshold.
8.3.4.1 Thermal Warning Function
The thermal monitor provides a warning to the host processor through the interrupt system when the
temperature reaches within a cautionary range. The threshold value must be set to less than the thermal
shutdown threshold.
The integrated thermal warning function provides the MCU an early warning of over-temperature condition. This
monitoring system is connected to the interrupt controller and can send an TWARN_INT interrupt when the
temperature is higher than the preset threshold. The TPS6593-Q1 device uses the TWARN_LEVEL register bit
to set the thermal warning threshold temperature at 130°C or 140°C. There is no hysteresis for the thermal
warning level.
When the power-management software triggers an interrupt, immediate action must be taken to reduce the
amount of power drawn from the PMIC device (for example, noncritical applications must be closed).
8.3.4.2 Thermal Shutdown
The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at
which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status
register. There are two levels of thermal shutdown threshold. When the die temperature reaches the TSD_orderly
level, the TPS6593-Q1 device performs an orderly shutdown of all output power rails. If the die temperature
raises rapidly and reaches the TSD_imm level before the orderly shutdown process completes, the TPS6593-Q1
device performs an immediate shutdown with activated pull-down on all output power rails, in order to turn off
all of the output power rails as rapidly as possible. After the thermal shutdown takes place, the system cannot
restart until the die temperature is below the thermal warning threshold.

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8.3.5 Backup Supply Power-Path

The LDOVRTC is supplied from either the VBACKUP (backup supply from either coin-cell or super-cap) input or
VCCA. The power-path is designed to prioritize VCCA to maximize the life of the backup supply.
When VCCA drops below the VCCA_UVLO threshold, the device shuts down all rails except the LDOVRTC,
and enters the BACKUP mode. At this point, the Backup Supply Power-Path switches to the VBACKUP as the
input of LDOVRTC. When the voltage of VCCA returns to level above the VCCA_UVLO threshold level, the
power-path switches the input of LDOVRTC back to VCCA.
When both the VCCA voltage drop below the VCCA_UVLO threshold, and the VBACKUP voltage drops below
1.7V (RTC_LDO_UVLO threshold), the LDOVRTC is turned OFF and the digital core is reset, which forces the
device into the NO SUPPLY state.
Note: a backup supply is not required for the device to operate. The device skips the BACKUP state if the
VBACKUP pin is grounded.
8.3.6 General-Purpose I/Os (GPIO Pins)
The TPS6593-Q1 device integrates eleven configurable general-purpose I/Os that are multiplexed with
alternative features as listed in Section 6
For GPIOs characteristics, refer to Electrical Characteristics tables for Digital Input Signal Parameters and Digital
Output Signal Parameters.
When configured as primary functions, all GPIOs are controlled through the following set of registers bits under
the individual GPIOn_CONF register.
• GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input)
• GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin
• GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN =
'1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected
• GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull
• GPIOn_DIR: Configures the input or output direction of each GPIO pin
Each GPIO event can generate an interrupt on a rising edge, falling edge, or both, configured through the
GPIOn_FALL_MASK and the GPIOn_RISE_MASK register bits. A GPIO-interrupt applies when the primary
function (general-purpose I/O) has been selected and also for the following alternative functions:
• nRSTOUT_SOC
• PGOOD
• nERR_MCU
• nERR_SoC
• TRIG_WDOG
• DISABLE_WDOG
• NSLEEP1, NSLEEP2
• WKUP1, WKUP2
• LP_WKUP1, LP_WKUP2
The GPIOn_SEL[2:0] register bits under the GPIOn_CONF registers control the selection between a primary and
an alternative function. When a pre-defined function is selected, some predetermined IO characteristics (such as
pullup, pulldown, push-pull or open drain) for the pin are enforced regardless of the settings of the associated
GPIO configuration register. Please note that if the GPIOn_SEL[2:0] is changed during device operation, a signal
glitch may occur which may cause digital malfunction, especially if it involves a clock signal such as SCL_I2C2,
CLK32KOUT, SCL_SPMI, SYNCCLKIN, or SYNCCLKOUT. Please refer to Section 6.1 for more detail on the
predetermined IO characteristics for each pre-defined digital interface function.
All GPIOs can be configured as a wake-up input when it is configured as a WKUP1 or a WKUP2 signal. Only
GPIO3 and GPIO4 can be configured as LP_WKUP1 or LP_WKUP2 signal so that they can be used to wake-up
the device from LP_STANDBY state. All GPIOs can also be configured as a NSLEEP1 or a NSLEEP2 input.
For more information regarding the usage of the NSLEEPx pins and the WKUPx pins, please refer to Section
8.4.1.2.4.3 and Section 8.4.1.2.4.4.

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Any of the GPIO pin can also be configured as part of the power-up sequence to enable external devices such
as external BUCKs when it is configured as a general-purpose output port.
The nINT pin, the EN_DRV pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC have
readback monitoring to detect errors on the signals. The monitoring of the EN_DRV pin checks for mismatch in
both low and high levels. For the nINT pin, the nRSTOUT pin and the GPIO pin assigned as nRSTOUT_SOC,
the readback monitoring only checks for mismatches in the low level, therefore it is allowed to combine these
signals with other external pull-down sources. The readback mismatch is continuously monitored without deglitch
circuitry during operation, and the monitoring is gated for tgate_readback period when the signal state is changed
or when a new function is selected for the GPIO pin with the GPIOn_SEL bits. NINT_READBACK_INT,
EN_DRV_READBACK_INT, NRSTOUT_READBACK_INT, and NRSTOUT_SOC_READBACK_INT are the
interrupt bits that are set in an event of a readback mismatch for these pins, respectively.

Note
All GPIO pin are set to generic input pins with resistive pull-down before NVM memory is loaded
during device power up. Therefore, if any GPIOs has external pull-up resistors connecting to a voltage
domain that is energized before the NVM memory is loaded, the GPIO pin is pulled high before the
configuration for the pin is loaded from the NVM.

Note
For GPIO pins with internal pull down enabled, additional leakage current flows into the GPIO pin if
this pin is pulled-up to a voltage higher than the voltage level of its output power domain. If the internal
pull down must be enabled, please use a resistor divider to divide down the input voltage, or use a
series resistor to connect to the input source and ensure the voltage level at the GPIO pin is below the
voltage level of its output power domain.

8.3.7 nINT, EN_DRV, and nRSTOUT Pins

The nINT, EN_DRV and nRSTOUT pin, and the GPIO pin assigned as nRSTOUT_SoC are IO pins with
dedicated functions.
The nINT pin is the open drain interrupt output pin. More description regarding the function of this pin can be
found under Section 8.3.8.
The nRSTOUT pin, together with the GPIO pin assigned as nRSTOUT_SoC, are the system reset pins which
can be configured as open-drain or push-pull outputs. These pins stay in the default low state until the PFSM
of the TPS6593-Q1 sets the associated control bits NRSTOUT and NRSTOUT_SOC in the register map.
These control bits NRSTOUT and NRSTOUT_SOC are set by the PFSM typically after the end of a power-up
sequence. At the beginning of a power-down sequence, the PFSM clears these control bits NRSTOUT and
NRSTOUT_SOC in order to pull-down the nRSTOUT and nRSTOUT_SoC pins before the ramp-down of the
voltage rails.
The purpose of the EN_DRV pin is to indicate that the TPS6593-Q1 has entered a safe state. The EN_DRV
pin has an internal 10kΩ high-side pull-up to the VCCA supply. The TPS6593-Q1 pulls this EN_DRV pin to the
default low state, and releases the pull-down when the MCU sets the ENABLE_DRV bit to '1'.

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8.3.8 Interrupts
The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the
following categories:

BUCK ERROR These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC)
and over-current (ILIM) error conditions found on the BUCK regulators .
LDO ERROR These interrupts indicate OV, UV, and SC error conditions found on the LDO
regulators, as well as OV and UV error conditions found on the VCCA supply.
VMON ERROR These interrupts indicate OV and UV error conditions found on the VCCA supply.
SEVERE ERROR These errors indicate severe device error conditions, such as thermal shutdown,
PFSM sequencing and execution error and VCCA over-voltage, that causes the
device to trigger the PFSM to execute immediate shutdown of all digital outputs,
external voltage rails and monitors, and proceed to the Safe Recovery State.
MODERATE ERROR These interrupts provide warnings to the system to indicate multiple restart attempts
from SAFE RECOVERY state exceeding the allowed recovery count, multiple warm-
reset executions exceeding the allowed recovery count, detection of long press
nPWRON button, SPMI communication error, register CRC error, BIST failure, read-
back error on nRSTOUT or nINT pins, or junction temperature reaching orderly
shutdown level. These warning causes the device to trigger the PFSM to execute
orderly shutdown of all digital outputs, external voltage rails and monitors, and
proceed to the SAFE RECOVERY state.3
MISCELLANEOUS These interrupts provide information to the system to indicate detection of WDOG or
WARNING ESM errors, die temperature crossing thermal warning threshold, device passing BIST
test, or external sync clock availability.
START-UP SOURCE These interrupts provide information to the system on the mechanism that caused the
device to start up, which includes FSD, RTC alarm or timer interrupts, the activation of
the ENABLE pin or the nPRWON pin button detection.
GPIO DETECTION These interrupts indicate a High-Level or Rising-Edge detection, or indicate a Low-
Level or Falling-Edge detection at the GPIO1 through GPIO11 pins.
FSM ERROR These interrupts indicate the detection of an error that causes the device mission
INTERRUPT state changes.

All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read
the INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to
the corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt
occurs while the nINT pin is still active, all of the corresponding interrupt register bits retain the interrupt source
information until it is cleared by the host.
Hierarchical Structure of Interrupt Registers shows the hierarchical structure of the interrupt registers according
to the categories described above. The purpose of this register structure is to reduce the number of interrupt
register read cycles the host has to perform in order to identify the source of the interrupt. Summary of Interrupt
Signals summarizes the trigger and the clearing mechanism for all of the interrupt signals. This table also shows
which interrupt sources can be masked by setting the corresponding mask register to '1'. When an interrupt is
masked, the interrupt bit is not updated when the associated event occurs, the nINT line is not affected, and
the event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit reflects the
event until the bit is cleared. While the event is masked, the interrupt register bit is not over-written when a new
event occurs.

3 The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite
state machine (PFSM) settings always follow this described error handling to meet device specifications.

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INT_TOP[7:0]

INT_FSM_ERR[7:0]
READBACK SOC_PWR MCU_PWR ORD_ IMM_
WD_INT ESM_INT COMM_ERR_INT
_ERR_INT _ERR_INT _ERR_INT SHUTDOWN_INT SHUTDOWN_INT

INT_COMM_ERR[7:0]
I2C2_ADR I2C2_CRC COMM_ADR COMM_CRC COMM_FRM
FSM_ERR_INT

_ERR_INT _ERR_INT _ERR_INT _ERR_INT _ERR_INT

INT_READBACK_ERR[7:0]
NRSTOUT_SOC EN_DRV
_READBACK_INT _READBACK_INT
INT_ESM[7:0]
ESM_MCU ESM_MCU ESM_MCU ESM_SOC ESM_SOC ESM_SOC
_RST_INT _FAIL_INT _PIN_INT _RST_INT _FAIL_INT _PIN_INT

INT_SEVERE_ERR[7:0]
_ERR_INT
SEVERE

PFSM_ERR_INT VCCA_OVP_INT TSD_IMM_INT

MODERATE

INT_MODERATE_ERR[7:0]
_ERR_INT

NRSTOUT NINT_READBACK NPWRON_LONG

SPMI_ERR_INT RECOV_CNT_INT REG_CRC_ERR_INT BIST_FAIL TSD_ORD_INT
_READBACK_INT _INT _INT

INT_MISC[7:0]
MISC_INT

TWARN_INT EXT_CLK_INT BIST_PASS_INT

STARTUP_INT

INT_STARTUP[7:0]
NPWRON
SOFT_REBOOT_INT FSD_INT RTC_INT ENABLE_INT
_START_INT

INT_GPIO[7:0]
GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT
GPIO_INT

INT_GPIO1_8[7:0]
GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT

INT_LDO_VMON[7:0]
VCCA_INT LDO3_4_INT LDO1_2_INT
LDO_VMON_INT

INT_VMON[7:0]
VCCA_UV_INT VCCA_OV_INT

INT_LDO3_4[7:0]
LDO4_ILIM_INT LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_INT LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT

INT_LDO1_2[7:0]
LDO2_ILIM_INT LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_INT LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT

INT_BUCK[7:0]
BUCK5_INT BUCK3_4_INT BUCK1_2_INT

INT_BUCK5[7:0]
BUCK_INT

BUCK5_ILIM_INT BUCK5_SC_INT BUCK5_UV_INT BUCK5_OV_INT

INT_BUCK3_4[7:0]
BUCK4_ILIM_INT BUCK4_SC_INT BUCK4_UV_INT BUCK4_OV_INT BUCK3_ILIM_INT BUCK3_SC_INT BUCK3_UV_INT BUCK3_OV_INT

INT_BUCK1_2[7:0]
BUCK2_ILIM_INT BUCK2_SC_INT BUCK2_UV_INT BUCK2_OV_INT BUCK1_ILIM_INT BUCK1_SC_INT BUCK1_UV_INT BUCK1_OV_INT

Figure 8-12. Hierarchical Structure of Interrupt Registers

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Table 8-6. Summary of Interrupt Signals

MASK FOR INTERRUPT
EVENT TRIGGER FOR FSM RESULT (1) RECOVERY INTERRUPT BIT LIVE STATUS BIT
INTERRUPT CLEAR
EN_ILIM_FSM_CTR
EN_ILIM_FSM_CT
L=1: Write 1 to
RL=1:
According to BUCKn_ILIM_INT
Transition according Depends on PFSM
BUCK regulator BUCKn_GRP_SEL bit
to FSM trigger and configuration, see BUCKn_ILIM_INT =
forward current limit and x_RAIL_TRIG BUCKn_ILIM_MASK BUCKn_ILIM_STAT Interrupt is not
interrupt PFSM transition 1
triggered bits cleared if current
EN_ILIM_FSM_CT diagram
EN_ILIM_FSM_CTR limit violation is
RL=0:
L=0: active
Interrupt only
N/A
EN_ILIM_FSM_CTR
EN_ILIM_FSM_CT
L=1:
RL=1: Write 1 to
According to
Transition according Depends on PFSM LDOn_ILIM_INT bit
LDOn_GRP_SEL
LDO regulator current to FSM trigger and configuration, see Interrupt is not
and x_RAIL_TRIG LDOn_ILIM_INT = 1 LDOn_ILIM_MASK LDOn_ILIM_STAT
limit triggered interrupt PFSM transition cleared if current
bits
EN_ILIM_FSM_CT diagram limit violation is
EN_ILIM_FSM_CTR
RL=0: active
L=0:
Interrupt only
N/A
Write 1 to
BUCKn_SC_INT bit
Interrupt is not
cleared if the
According to Regulator disable Depends on PFSM BUCKn is enabled
BUCK output or switch BUCKn_GRP_SEL and transition configuration, see and the BUCKn
BUCKn_SC_INT = 1 N/A N/A
short circuit detected and x_RAIL_TRIG according to FSM PFSM transition output voltage is
bits trigger and interrupt diagram below the short-
circuit threshold
after elapse of
expected ramp-up
time interval
Write 1 to
LDOn_SC_INT bit
Interrupt is not
cleared if the LDOn
According to Regulator disable Depends on PFSM
is enabled and the
LDO output short LDOn_GRP_SEL and transition configuration, see
LDOn_SC_INT = 1 N/A N/A LDOn output voltage
circuit detected and x_RAIL_TRIG according to FSM PFSM transition
is below the short-
bits trigger and interrupt diagram
circuit threshold
after elapse of
expected ramp-up
time interval
Write 1 to
BUCKn_OV_INT bit
According to Depends on PFSM
Transition according Interrupt is not
BUCK regulator BUCKn_GRP_SEL configuration, see
to FSM trigger and BUCKn_OV_INT = 1 BUCKn_OV_MASK BUCKn_OV_STAT cleared if the
overvoltage and x_RAIL_TRIG PFSM transition
interrupt associated fault
bits diagram
condition is still
present
Write 1 to
BUCKn_UV_INT bit
According to Depends on PFSM
Transition according Interrupt is not
BUCK regulator BUCKn_GRP_SEL configuration, see
to FSM trigger and BUCKn_UV_INT = 1 BUCKn_UV_MASK BUCKn_UV_STAT cleared if the
undervoltage and x_RAIL_TRIG PFSM transition
interrupt associated fault
bits diagram
condition is still
present
Write 1 to
LDOn_OV_INT bit
According to Depends on PFSM
Transition according Interrupt is not
LDO regulator LDOn_GRP_SEL configuration, see
to FSM trigger and LDOn_OV_INT = 1 LDOn_OV_MASK LDOn_OV_STAT cleared if the
overvoltage and x_RAIL_TRIG PFSM transition
interrupt associated fault
bits diagram
condition is still
present
Write 1 to
LDOn_UV_INT bit
According to Depends on PFSM
Transition according Interrupt is not
LDO regulator LDOn_GRP_SEL configuration, see
to FSM trigger and LDOn_UV_INT = 1 LDOn_UV_MASK LDOn_UV_STAT cleared if the
undervoltage and x_RAIL_TRIG PFSM transition
interrupt associated fault
bits diagram
condition is still
present
Write 1 to
VCCA_OV_INT bit
According to Depends on PFSM
VCCA input Transition according Interrupt is not
VCCA_GRP_SEL configuration, see
overvoltage to FSM trigger and VCCA_OV_INT = 1 VCCA_OV_MASK VCCA_OV_STAT cleared if the
and x_RAIL_TRIG PFSM transition
monitoring interrupt associated fault
bits diagram
condition is still
present

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Table 8-6. Summary of Interrupt Signals (continued)

MASK FOR INTERRUPT
EVENT TRIGGER FOR FSM RESULT (1) RECOVERY INTERRUPT BIT LIVE STATUS BIT
INTERRUPT CLEAR
Write 1 to
VCCA_UV_INT bit
According to Depends on PFSM
VCCA input Transition according Interrupt is not
VCCA_GRP_SEL configuration, see
undervoltage to FSM trigger and VCCA_UV_INT = 1 VCCA_UV_MASK VCCA_UV_STAT cleared if the
and x_RAIL_TRIG PFSM transition
monitoring interrupt associated fault
bits diagram
condition is still
present
Write 1 to
TWARN_INT bit
Interrupt is
Thermal warning N/A Interrupt only Not valid TWARN_INT = 1 TWARN_MASK TWARN_STAT not cleared if
temperature is
above thermal
warning level
Write 1 to
TSD_ORD_INT bit
This interrupt bit
All regulators Automatic start-up to
ORDERLY_SHUTDO can only be read
deactivated and STARTUP_DEST[1:0]
Thermal shutdown, WN by the MCU after
Output GPIOx set to state after TSD_ORD_INT = 1 N/A TSD_ORD_STAT
orderly sequenced (MODERATE_ERR_I the device has
low in a sequence temperature is below
NT) recovered from a
and interrupt(1) TWARN level
previously occurred
over-temperature
event.
Write 1 to
TSD_IMM_INT bit
All regulators
This interrupt bit
deavtivated with Automatic start-up to
can only be read
IMMEDIATE_SHUTD pull-down resistors STARTUP_DEST[1:0]
Thermal shutdown, by the MCU after
OWN and Output GPIOx state after TSD_IMM_INT = 1 N/A TSD_IMM_STAT
immediate the device has
(SEVERE_ERR_INT) set to low temperature is below
recovered from a
immediately and TWARN level
previously occurred
interrupt(1)
over-temperature
event.
All regulators
ORDERLY_SHUTDO
deactivated and Automatic start-up to
WN Write 1 to
BIST error Output GPIOx set STARTUP_DEST[1:0] BIST_FAIL_INT = 1 BIST_FAIL_MASK N/A
(MODERATE_ERR_I BIST_FAIL_INT bit
to low immediately state
NT)
and interrupt(1)
All regulators
ORDERLY_SHUTDO
deactivated and Automatic start-up to Write 1 to
WN REG_CRC_ERR_IN
Register CRC error Output GPIOx set STARTUP_DEST[1:0] REG_CRC_ERR_MASK N/A REG_CRC_ERR_IN
(MODERATE_ERR_I T=1
to low immediately state T bit
NT)
and interrupt(1)
All regulators
ORDERLY_SHUTDO
deactivated and Automatic start-up to
SPMI communication WN Write 1 to
Output GPIOx set STARTUP_DEST[1:0] SPMI_ERR_INT = 1 SPMI_ERR_MASK N/A
error (MODERATE_ERR_I SPMI_ERR_INT bit
to low immediately state
NT)
and interrupt(1)
Write 1 to
COMM_FRM_ERR_ COMM_FRM_ERR_MA
SPI frame error N/A Interrupt only Not valid N/A COMM_FRM_ERR_
INT = 1(4) SK
INT bit
Write 1 to
COMM_CRC_ERR_ COMM_CRC_ERR_MA
I2C1 or SPI CRC error N/A Interrupt only Not valid N/A COMM_CRC_ERR_
INT = 1 SK
INT bit
Write 1 to
I2C1 or SPI address COMM_ADR_ERR_ COMM_ADR_ERR_MA
N/A Interrupt only Not valid N/A COMM_ADR_ERR_
error(5) INT = 1 SK
INT bit
Write 1 to
I2C2_CRC_ERR_IN
I2C2 CRC error N/A Interrupt only Not valid I2C2_CRC_ERR_MASK N/A I2C2_CRC_ERR_IN
T=1
T bit
Write 1 to
I2C2_ADR_ERR_IN
I2C2 address error(5) N/A Interrupt only Not valid I2C2_ADR_ERR_MASK N/A I2C2_ADR_ERR_IN
T=1
T bit
All regulators Automatic start-up to
deactivated with STARTUP_DEST[1:0]
IMMEDIATE_SHUTD pull-down resistors state. If previous
PFSM_ERR_INT = Write 1 to
PFSM error OWN and Output GPIOx PFSM_ERR_INT is N/A
1 PFSM_ERR_INT bit
(SEVERE_ERR_INT) set to low pending, VCCA power
immediately and cycle needed for
interrupt(1) recovery.
Write 1 to
EN_DRV_READBA
CK_INT bit
EN_DRV pin read-
EN_DRV_READBA EN_DRV_READBACK_ EN_DRV_READBA Interrupt is not
back error (monitoring N/A Interrupt only Not valid
CK_INT = 1 MASK CK_STAT cleared if the
high and low states)
associated fault
condition is still
present

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Table 8-6. Summary of Interrupt Signals (continued)

MASK FOR INTERRUPT
EVENT TRIGGER FOR FSM RESULT (1) RECOVERY INTERRUPT BIT LIVE STATUS BIT
INTERRUPT CLEAR
Write 1 to
NINT_READBACK_I
All regulators
ORDERLY_SHUTDO NT bit
NINT pin read-back deactivated and Automatic start-up to
WN NINT_READBACK_I NINT_READBACK_MA NINT_READBACK Interrupt is not
error (monitoring low Output GPIOx set STARTUP_DEST[1:0]
(MODERATE_ERR_I NT = 1 SK _STAT cleared if the
state) to low immediately state
NT) associated fault
and interrupt(1)
condition is still
present
Write 1 to
NRSTOUT_READB
All regulators
ORDERLY_SHUTDO ACK_INT bit
NRSTOUT pin read- deactivated and Automatic start-up to
WN NRSTOUT_READB NRSTOUT_READBACK NRSTOUT_READB Interrupt is not
back error (monitoring Output GPIOx set STARTUP_DEST[1:0]
(MODERATE_ERR_I ACK_INT = 1 _MASK ACK_STAT cleared if the
low state) to low immediately state
NT) associated fault
and interrupt(1)
condition is still
present
Write 1 to
NRSTOUT_SOC_R
EADBACK_INT bit
NRSTOUT_SOC pin
NRSTOUT_SOC_R NRSTOUT_SOC_READ NRSTOUT_SOC_R Interrupt is not
read-back error N/A Interrupt only Not valid
EADBACK_INT = 1 BACK_MASK EADBACK_STAT cleared if the
(monitoring low state)
associated fault
condition is still
present
Write 1 to
Fault detected by ESM_SOC_PIN_IN
SOC ESM (level T bit
mode: low level ESM_SOC_PIN_IN Interrupt is not
N/A Interrupt only Not valid ESM_SOC_PIN_MASK N/A
detected, PWM mode: T=1 cleared if the
PWM signal timing associated fault
violation) condition is still
present
Fault detected by Write 1 to
SOC ESM (level ESM_SOC_FAIL_IN
mode: low level T bit
Interrupt and
longer than DELAY1 ESM_SOC_FAIL_IN Interrupt is not
N/A EN_DRV = 0 Not valid ESM_SOC_FAIL_MASK N/A
time, PWM mode: T=1 cleared if the
(configurable)
ESM error counter > associated fault
FAIL_THR longer than condition is still
DELAY1time) present
Write 1 to
Fault detected
ESM_SOC_RST_IN
by SOC ESM
T bit
(level mode: low
Automatically returns This bit can only be
level longer than
Interrupt, and to the current read by the MCU
DELAY1+DELAY2 ESM_SOC_RST_IN
ESM_SOC_RST NRSTOUT_SOC operating state after ESM_SOC_RST_MASK N/A after the TPS6593-
time, PWM mode: T=1
toggle(1) the completion of SoC Q1 has executed
ESM error counter >
warm reset a warm-reset and
FAIL_THR longer than
the recovery counter
DELAY1+DELAY2
does not exceed the
time)
recovery threshold
Write 1 to
Fault detected by ESM_MCU_PIN_IN
MCU ESM (level T bit
mode: low level ESM_MCU_PIN_IN Interrupt is not
N/A Interrupt only Not valid ESM_MCU_PIN_MASK N/A
detected, PWM mode: T=1 cleared if the
PWM signal timing associated fault
violation condition is still
present
Fault detected by Write 1 to
MCU ESM (level ESM_MCU_FAIL_IN
mode: low level T bit
Interrupt and
longer than DELAY1 ESM_MCU_FAIL_IN Interrupt is not
N/A EN_DRV = 0 Not valid ESM_MCU_FAIL_MASK N/A
time, PWM mode: T=1 cleared if the
(configurable)
ESM error counter > associated fault
FAIL_THR longer than condition is still
DELAY1 time) present
Write 1 to
Fault detected
ESM_MCU_RST_IN
by MCU ESM
T bit
(level mode: low
Interrupt and Warm Automatically returns This bit can only be
level longer than
Reset (EN_DRV = 0 to the current read by the MCU
DELAY1+DELAY2 ESM_MCU_RST_IN
ESM_MCU_RST and NRSTOUT and operating state after ESM_MCU_RST_MASK N/A after the TPS6593-
time, PWM mode: T=1
NRSTOUT_SOC the completion of Q1 has executed
ESM error counter >
toggle)(1) warm reset a warm-reset and
FAIL_THR longer than
the recovery counter
DELAY1+DELAY2
does not exceed the
time)
recovery threshold

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Table 8-6. Summary of Interrupt Signals (continued)

MASK FOR INTERRUPT
EVENT TRIGGER FOR FSM RESULT (1) RECOVERY INTERRUPT BIT LIVE STATUS BIT
INTERRUPT CLEAR
Write 1 to
External clock is EXT_CLK_INT bit
expected, but it is Interrupt is not
not available or the N/A Interrupt only Not valid EXT_CLK_INT = 1(2) EXT_CLK_MASK EXT_CLK_STAT cleared if the
frequency is not in the associated fault
valid range condition is still
present
BIST completed BIST_PASS_INT = Write 1 to
N/A Interrupt only Not valid BIST_PASS_MASK N/A
successfully 1 BIST_PASS_INT bit
Clear interrupt and
Watchdog fail counter Interrupt and Write 1 to
N/A WD_FAIL_CNT < WD_FAIL_INT = 1 N/A N/A
above fail threshold EN_DRV = 0 WD_FAIL_INT bit
WD_FAIL_TH
Write 1 to
WD_RST_INT bit
Interrupt and
This bit can only be
Warm Reset if Automatically returns
read by the MCU
WD_RST_EN = 1 to the current
Watchdog fail counter WD_RST (if after the TPS6593-
(EN_DRV = 0 operating state after WD_RST_INT = 1 N/A N/A
above reset threshold WD_RST_EN = 1) Q1 has executed
and NRSTOUT and the completion of
a warm-reset and
NRSTOUT_SOC warm reset
the recovery counter
toggle)(1)
does not exceed the
recovery threshold
Write 1 to
WD_LONGWIN_TI
MEOUT_INT bit
Interrupt and Warm Automatically returns This bit can only be
Reset (EN_DRV = 0 to the current read by the MCU
Watchdog long WD_LONGWIN_TI
WD_RST and NRSTOUT and operating state after N/A N/A after the TPS6593-
window timeout MEOUT_INT = 1
NRSTOUT_SOC the completion of Q1 has executed
toggle)(1) warm reset a warm-reset and
the recovery counter
does not exceed the
recovery threshold
Start-up to
STARTUP_DEST[1: Write 1 to ALARM
RTC alarm wake-up TRIGGER_SU_x Not valid ALARM = 1 IT_ALARM = 0 N/A
0] state and bit
interrupt(1)
Start-up to
STARTUP_DEST[1:
RTC timer wake-up TRIGGER_SU_x Not valid TIMER = 1 IT_TIMER = 0 N/A Write 1 to TIMER bit
0] state and
interrupt(1)
Start-up to
Write 1 to
Low state in STARTUP_DEST[1: NPWRON_START_I NPWRON_START_MAS
TRIGGER_SU_x Not valid NPWRON_IN NPWRON_START_I
NPWRON pin 0] state and NT = 1 K
NT bit
interrupt(1)
All regulators
deactivated and Write 1 to
Long low state in ORDERLY_SHUTDO Valid power-on NPWRON_LONG_I NPWRON_LONG_MAS
Output GPIOx set to NPWRON_IN NPWRON_LONG_I
NPWRON pin WN request NT = 1 K
low in a sequence NT bit
and interrupt(1)
Transition to
TRIGGER_FORCE_ STANDBY or
Low state in ENABLE STANDBY/ LP_STANDBY
ENABLE pin rise N/A N/A N/A N/A
pin TRIGGER_FORCE_ depending on the
LP_STANDBY LP_STANDBY_SEL
bit setting(1)
(1) Write 1 to
ENABLE pin rise TRIGGER_SU_x Not valid ENABLE_INT = 1 ENABLE_MASK ENABLE_STAT
ENABLE_INT bit
All regulators
deactivated and Automatic start-up to Write 1 to
Fault causing orderly ORDERLY_SHUTDO ORD_SHUTDOWN_ ORD_SHUTDOWN_MA
Output GPIOx set to STARTUP_DEST[1:0] N/A ORD_SHUTDOWN_
shutdown WN INT SK
low in a sequence state INT
and interrupt(1)
All regulators
deactivated
(depending on NVM
configuration with Automatic start-up to Write 1 to
Fault causing IMMEDIATE_SHUTD IMM_SHUTDOWN_I IMM_SHUTDOWN_MA
or without pull- STARTUP_DEST[1:0] N/A IMM_SHUTDOWN_I
immediate shutdown OWN NT SK
down resistors) and state NT
Output GPIOx set
to low immediately
and interrupt(1)
Depends on PFSM
Transition according Write 1 to
Power supply error for MCU_POWER_ERR configuration, see MCU_PWR_ERR_I MCU_PWR_ERR_MAS
to FSM trigger and N/A MCU_PWR_ERR_I
MCU OR PFSM transition NT K
interrupt NT
diagram

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Table 8-6. Summary of Interrupt Signals (continued)

MASK FOR INTERRUPT
EVENT TRIGGER FOR FSM RESULT (1) RECOVERY INTERRUPT BIT LIVE STATUS BIT
INTERRUPT CLEAR
Depends on PFSM
Transition according Write 1 to
Power supply error for SOC_POWER_ERR configuration, see SOC_PWR_ERR_I SOC_PWR_ERR_MAS
to FSM trigger and N/A SOC_PWR_ERR_I
SOC OR PFSM transition NT K
interrupt NT
diagram
Write 1 to
VCCA_OVP _INT bit
This bit can only be
All regulators
read by the MCU if
deactivated with Automatic start-up to
VCCA < VCCAOVP
IMMEDIATE_SHUTD pull-down resistors STARTUP_DEST[1:0]
VCCA over-voltage VCCA_OVP_INT = level. As long as
OWN and Output GPIOx state after VCCA N/A VCCA_OVP_STAT
(VCCAOVP) 1 VCCA ⩾ VCCAOVP
(SEVERE_ERR_INT) set to low voltage is below
level, device stays
immediately and VCCAOVP
in SAFE RECOVEY
interrupt(1)
state, and hence this
interrupt cannot be
not cleared.
According to
GPIOx_FSM_MASK Transition according
GPIOx_RISE_MASK Write 1 to
GPIO interrupt and to FSM trigger and Not valid GPIOx_INT = 1 GPIOx_IN
GPIOx_FALL_MASK GPIOx_INT bit
GPIOx_FSM_MASK_ interrupt
POL bits
Transition to
WKUP1 and GPIOx_RISE_MASK Write 1 to
WKUP1 ACTIVE state and Not valid N/A GPIOx_IN
LP_WKUP1 signals GPIOx_FALL_MASK GPIOx_INT bit
interrupt(1)
Transition to MCU
WKUP2 and GPIOx_RISE_MASK Write 1 to
WKUP2 ONLY state and Not valid N/A GPIOx_IN
LP_WKUP2 signals GPIOx_FALL_MASK GPIOx_INT bit
interrupt(1)
According to State transition
NSLEEP1 signal,
NSLEEP1 and based on NSLEEP1 Not valid N/A NSLEEP1_MASK GPIOx_IN N/A
NSLEEP1B bit
NSLEEP2 and NSLEEP2
According to State transition
NSLEEP2 signal,
NSLEEP1 and based on NSLEEP1 Not valid N/A NSLEEP2_MASK GPIOx_IN N/A
NSLEEP2B bit
NSLEEP2 and NSLEEP2
All regulators
deactivated with
LDOVINT over- or Reset condition for pull-down resistors Valid LDOVINT
N/A N/A N/A N/A
undervoltage all logic circuits and Output GPIOx voltage
set to low
immediately(1)
All regulators
deactivated with
Main clock outside Reset condition for pull-down resistors
VCCA power cycle N/A N/A N/A N/A
valid frequency all logic circuits and Output GPIOx
set to low
immediately(1)
All regulators
Recovery counter limit ORDERLY_SHUTDO deactivated and
VCCA power cycle N/A N/A N/A N/A
exceeded(3) WN Output GPIOx set to
low in a sequence(1)
All regulators
deactivated with
VCCA supply falling Reset condition for pull-down resistors
VCCA voltage rising N/A N/A N/A N/A
below VCCAUVLO all logic circuits and Output GPIOx
set to low
immediately(1)
Start-up to
First supply detection,
STARTUP_DEST[1: Write 1 to FSD_INT
VCCA supply rising TRIGGER_SU_x Not valid FSD_INT = 1 FSD_MASK N/A
0] state and bit
above VCCAUVLO
interrupt(1)

(1) The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results
can be configured differently in NVM memory. TI recommends reviewing of the system and device functional safety goal and
documentation before deviating from these recommendations.
(2) Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled.
(3) This event does not occur if RECOV_CNT_THR = 0, even though RECOV_CNT continues to accumulate and increase, and eventually
saturates when it reaches the maximum count of 15.
(4) Due to a digital logic errata in the device, a write or read SPI command which coincide with the rising edge of the CS signal may not
cause the COMM_FRM_ERR_INT interrupt.
(5) I2C1, I2C2, or SPI address error only occur in safety applications if the interface CRC feature is enabled, when both
I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'.

8.3.9 RTC
8.3.9.1 General Description
The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions.

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The main functions of the RTC block are:

• Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) code
• Calendar information (day, month, year, and day of the week) in BCD code up to year 2099
• Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and
masked individually:
– Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods)
– Alarm interrupt at a precise time of the day (alarm function)
• Oscillator frequency calibration and time correction with 1/32768 resolution
Figure 8-13 shows the RTC block diagram.
32-kHz
clock input

32-kHz Frequency
Week days Control
counter compensation

Seconds Minutes Hours Days Months Years

Interrupt Alarm INT_ALARM

INT_TIMER

Figure 8-13. RTC Block Diagram

8.3.9.2 Time Calendar Registers

All the time and calendar information is available in the time calendar (TC) dedicated registers:
SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and
YEARS_REG. The TC register values are written in BCD code.
• Year data ranges from 00 to 99.
– Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on)
– Common Year = Other years
• Month data ranges from 01 to 12.
• Day value ranges:
– 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12
– 1 to 30 when months are 4, 6, 9, 11
– 1 to 29 when month is 2 and year is a leap year
– 1 to 28 when month is 2 and year is a common year
• Weekday value ranges from 0 to 6.
• Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode.
• Minutes value ranges from 0 to 59.
• Seconds value ranges from 0 to 59.
Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are listed
in Table 8-7:
Table 8-7. RTC Time Calendar Registers Example
REGISTER CONTENT
RTC_SECONDS 0x36
RTC_MINTURES 0x54

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Table 8-7. RTC Time Calendar Registers Example (continued)

The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG
register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically
cleared when the rounding time is performed.
Example:
• If current time is 10H59M45S, round operation changes time to 11H00M00S
• If current time is 10H59M29S, round operation changes time to 10H59M00S
8.3.9.2.1 TC Registers Read Access
TC register read access can be done in two ways:
• A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and
the real time because the RTC keeps running because some of the registers can toggle in between register
accesses. Software must manage the register change during the reading.
• Read access to shadowed TC registers. These registers are at the same addresses as the normal TC
registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit
is set, the content of all TC registers is transferred into shadow registers so they represent a coherent
timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the
TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of
register access.
8.3.9.2.2 TC Registers Write Access
TC registers write accesses can be done while RTC is stopped. MCU can stop the RTC by the clearing the
STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. MCU
then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final
written values are aligned with the targeted values.

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8.3.9.3 RTC Alarm

RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG,
ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm time or
date to the corresponding generated ALARM interrupts. See Section 8.3.9.2 for how these register values are
written in BCD code, with the same data range as described for the TC registers.
8.3.9.4 RTC Interrupts
The RTC supports two types of interrupts:
• ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM
registers is reached. This interrupt is activated and deactivated by setting the IT_ALARM bit. It is important to
set the IT_ALARM = 0 to deactivate the alarm interrupt prior to configuring the ALARM registers to prevent
the interrupt from mis-firing.
• TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the
EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt occurs when the
RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer interrupt
is set for every hour at 2:59 AM, the first interrupt occurs at 3:00 AM instead of 3:59 AM. This interrupt is
activated and deactivated by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to disable the
timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing.
Both types of the RTC interrupts can be used to wake-up the device from the STANDBY state or the
LP_STANDBY state when they are not masked.
8.3.9.5 RTC 32-kHz Oscillator Drift Compensation
The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any inaccuracy
of the 32-kHz clock output from the 32-kHz crystal oscillator. To compensate for any inaccuracy, MCU
must perform an external calibration of the oscillator frequency by calculating the needed drift compensation
compared to one hour time-period, and load the compensation registers with the drift compensation value.
The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The
compensation process happens after the first second of each hour. The time between second 1 and second
2 (T_ADJ) is adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG
registers. These two registers form a 16-bit, 2 s complement value COMP_REG (from –32767 to 32767) that
is subtracted from the 32-kHz counter as per the following formula to adjust the length of T_ADJ: (32768 -
COMP_REG) / 32768. Therefore, this compensation mechanism can adjust the compensation with a 1/32768-
second time-unit accuracy per hour and up to 1 second per hour.
Software must ensure that these registers are updated before each compensation process (there is no hardware
protection). For example, software can load the compensation value into these registers after each hour event,
during second 0 to second 1, just before the compensation period, happening from second 1 to second 2.
If the SET_32_COUNTER bit in the RTC_CTRL_REG register is set to '1', the internal 32-kHz counter is pre-
loaded with the content of the RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers. This preloading
of the internal 32-kHz counter can only be done when the RTC is stopped.
Figure 8-14 shows the RTC compensation scheduling.

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HOURS_REG 3 4 5 6

SECONDS_REG 0 1 ... 58 59 0 1 ... 58 59 0 1 ... 58 59 0 1 ... 58 59

HOURS_REG 3 4

SECONDS_REG 58 59 0 2 3

RTC_COMP_xxx_REG New Compensation Value Compensation Value Frozen

Figure 8-14. RTC Compensation Scheduling

8.3.10 Watchdog (WDOG)

The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the
MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic-level of the
EN_DRV pin when the watchdog detects correct operation of the MCU. When the watchdog detects an incorrect
operation of the MCU, the TPS6593-Q1 device pulls the EN_DRV pin low . This EN_DRV pin can be used in
the application as a control-signal to deactivate the power output stages, for example a motor driver, in case of
incorrect operation of the MCU.
The watchdog has two different modes that are defined as follows:

Trigger mode In trigger mode, the MCU applies a pulse signal with a minimum pulse width of tWD_pulse on the
pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode, the
MCU must clear bit WD_MODE_SELECT. Watchdog Trigger Mode provides more details.
Q&A In Q&A mode, the MCU sends watchdog answers through the I2C1 bus , I2C2 bus or SPI
(question and bus. (Which of these communication busses is to be used depends on the NVM configuration.
answer) mode Please refer to the user's guide of the orderable part number for further details). To select this
mode, the MCU must set bit WD_MODE_SELECT. Watchdog Question-Answer Mode provides
more details.

8.3.10.1 Watchdog Fail Counter and Status

The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or
decrements because of good events. Furthermore, the watchdog includes two configurable thresholds:
1. Fail-threshold (configurable through bits WD_FAIL_TH[2:0])
2. Reset-threshold (configurable through bits WD_RST_TH[2:0])
When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold
(WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-
flags are set.
When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold
(WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag
WD_FAIL_INT, and pulls the nINT pin low.
When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset
threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is
enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine
(see PFSM Trigger Selections) and sets the error-flag WD_RST_INT, and pulls the nINT pin low. Unless
described otherwise in the user's guide of the orderable part number, this WD_ERROR trigger in the state
machine causes the TPS6593-Q1 to execute a warm-reset, during which the nRSTOUT pin pulled low, and
released after a pre-configured delay time.

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The device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits
WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’ to these bits.
Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status gives an overview of the
Watchdog Fail Counter value ranges and the corresponding device status.
Table 8-8. Overview of Watchdog Fail Counter Value Ranges and Corresponding Device Status
Watchdog Fail Counter value
Device Status
WD_FAIL_CNT[3:0]
MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no
WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0]
other error-flags are set.
WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] + The device sets error-flag WD_FAIL_INT and pulls the nINT pin low.
WD_RST_TH[2:0]) Furthermore, , the device clears the ENABLE_DRV bit.
If configuration bit WD_RST_EN=1, device generates WD_ERROR
trigger in the state machine and reacts as defined in the PFSM,
WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])
sets the error-flag WD_RST_INT, and pulls the nINT pin low. See
Summary of Interrupt Signals for the interrupt handling of WD_RST.

The WD_FAIL_CNT[3:0] counter responds as follows:

• When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000
• A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1
• A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1
Refer to Watchdog Trigger Mode and Watchdog Q&A Related Definitions respectively for definitions of good
events and bad events.
8.3.10.2 Watchdog Start-Up and Configuration
When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has
a time interval (tLONG_WINDOW) with a default value set in bits WD_LONGWIN[7:0].
As long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following
register bits:
• WD_EN to enable or disable the watchdog
• WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval
• WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode)
• WD_PWRHOLD to activate the Watchdog Disable function (more detail in Section 8.3.10.4)
• WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence
after the completion of the current watchdog sequence (more detail in Section 8.3.10.4)
• WD_WIN1[6:0] to configure the duration of the Window-1 time-interval
• WD_WIN2[6:0] to configure the duration of the Window-2 time-interval
• WD_RST_EN to enable or disable the watchdog-reset function
• WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold
• WD_RST_TH[2:0] to configure the Watchdog-Reset threshold
• WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation
• WD_QA_LFSR[1:0] to configure the settings for the question-generation
• WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation
The device keeps the above register bit values configured by the MCU as long as the device is powered.
The MCU can configure the time interval of the Long Window (tLONG_WINDOW) with the WD_LONGWIN[7:0] bits.
The WD_LONGWIN[7:0] bits are defined as:
• 0x00: 80 ms
• 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps
• 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps
Use Equation 3 and Equation 4 to calculate the minimum and maximum values for the Long Window
(tLONG_WINDOW) time interval when WD_LONGWIN[7:0] > 0x00:

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tLONG_WINDOW_MIN = WD_LONGWIN[7:0] × 0.95 (3)

tLONG_WINDOW_MAX = WD_LONGWIN[7:0] × 1.05 (4)

Note
If the MCU software changes the duration of the Long-Window to an interval shorter than the time in
which the watchdog has been in the Long-Window, the time-out function of the Long-Window does no
longer operate.

When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog.
When the watchdog is deactivated in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog
again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit
WD_PWRHOLD before setting bit WD_EN back to ‘1’ to start the watchdog in Long Window.
The watchdog locks the following configuration register bits when it goes out of the Long Window and starts the
first watchdog sequence:
• WD_WIN1[6:0]
• WD_WIN2[6:0]
• WD_LONGWIN[7:0]
• WD_MODE_SELECT
• WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0]
• WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0]
8.3.10.3 MCU to Watchdog Synchronization
In order to go out of the Long Window and start the first watchdog sequence, the MCU must do the following
before elapse of the Long Window time interval:
• Clear bits WD_PWRHOLD (more detail in Section 8.3.10.4)
• Apply a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin in the case the
watchdog is configured for Trigger mode, or
• Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode
When the MCU fails to get the watchdog out of the Long Window before the configured Long
Window time interval (tLONG_WINDOW) elapses, the device goes through a warm reset, and sets the
WD_LONGWIN_TIMEOUT_INT. This bit latched until the MCU writes a ‘1’ to clear it.
8.3.10.4 Watchdog Disable Function
The watchdog in the TPS6593-Q1 device has a Watchdog Disable function to prevent an unwanted MCU
reset in case the MCU is un-programmed or needs to be reprogrammed. In order to activate this Watchdog
Disable function for an un-programmed MCU, DISABLE_WDOG pin must be asserted to a logic-high level for
a time-interval longer than tWD_DIS prior to the moment the device releases the nRSTOUT pin. If the Watchdog
Disable function is activated in this way, the device sets bit WD_PWRHOLD to keep the watchdog in the Long
Window. The watchdog stays in the Long Window until the MCU clears the WD_PWRHOLD bit.
In case the MCU needs to be reprogrammed while the watchdog monitors the correct operation of the MCU,
the MCU can set bit WD_RETURN_LONGWIN to put the watchdog back in the Long Window. When the MCU
set this bit, the watchdog returns to the Long Window after the current Watchdog Sequence completes. In order
to make the watchdog stay in the Long Window as long as needed the MCU can either re-configure the Long
Window (tLONG_WINDOW) time interval, or set the WD_PWRHOLD bit. Once the MCU starts the first watchdog
sequence (as described in Section 8.3.10.3), the MCU must clear bit WD_RETURN_LONGWIN before the end
of the first watchdog sequence in order to continue the watchdog sequence operation.
8.3.10.5 Watchdog Sequence
Once the watchdog is out of the Long Window, each watchdog sequence starts with a Window-1 followed by
a Window-2. The watchdog ends the current sequence and after one 20-MHz system clock cycle starts a next
sequence when one of the events below occurs:
• The configured Window-2 time period elapses

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• The watchdog detects a pulse signal with a minimum pulse-width tWD_pulse on the pre-assigned GPIO pin if
the watchdog is used in Trigger mode
• The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A
mode
The MCU can configure the time periods of the Window-1 (tWINDOW1) and Window-2 (tWINDOW2) with the bits
WD_WIN1[6:0] and WD_WIN2[6:0] respectively, before starting the sequence.
Use Equation 5 and Equation 6 to calculate the minimum and maximum values for the tWINDOW1 time interval.

tWINDOW1_MIN = (WD_WIN1[6:0] + 1) × 0.55 × 0.95 ms (5)

tWINDOW1_MAX = (WD_WIN1[6:0] + 1) × 0.55 × 1.05 ms (6)

Use Equation 7 and Equation 8 to calculate the minimum and maximum values for the tWINDOW-2 time interval.

tWINDOW2_MIN = (WD_WIN2[6:0] + 1) × 0.55 × 0.95 ms (7)

tWINDOW2_MAX = (WD_WIN2[6:0] + 1) × 0.55 × 1.05 ms (8)

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8.3.10.6 Watchdog Trigger Mode

When the TPS6593-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the
watchdog-triggers from the MCU on the pre-assigned GPIO pin . A rising edge on this , followed by a stable
logic-high level on that pin for more than the maximum pulse time, tWD_pulse(max), is a watchdog-trigger. The
watchdog uses a deglitch filter with a tWD_pulse filter time and the internal 20-MHz system clock to create the
internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin .
The watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the
watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of
Window-2 to generate such a good event.
The watchdog detects a bad event when one of the following events occurs:
• The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO
pin must occur for at least the tWD_pulse time before the end of Window-1 to generate such a bad event. In
case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT.
• No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the
device sets bits WD_TIMEOUT and WD_BAD_EVENT.
Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time tWD_pulse (max).
The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of
the watchdog-sequence.
WatchDog Flow Chart and Timing Diagrams in Trigger Mode shows the flow-chart of the watchdog in Trigger
mode.

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8.3.10.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode

NO SUPPLY
Device sets WD_RST_EN=1 per default
Device sets WD_EN=1 per default.
Wake-up
NO
request?

YES

RESTART
from all Reset-Extension
NO
states except me-interval
elapsed?
NO SUPPLY
YES

WATCHDOG LONG WINDOW

- MCU reset inac ve WD_RETURN_
- Device forces ENABLE_DRV= 0 YES
LONGWIN=1?
- MCU clears error-ags
- Device releases nINT pin if no other error-ags are set
- Device unlocks Watchdog-Conguraon registers NO
- Device sets WD_FAIL_CNT[3:0]=4'b0000 and sets WD_FIRST_OK=0
MCU either clears WD_EN, or:
1) MCU congures watchdog in Trigger mode WINDOW-1
2) MCU congures Window-1 and Window-2 me-intervals - If FIRST_WD_OK=0, device forces
3) MCU congures WD_FAIL_TH, WD_RST_TH and WD_RST_EN ENABLE_DRV=0, else device does not change
4) MCU sends trigger pulse ENABLE_DRV bit
- Device waits unl WINDOW-1 me elapses
NO

- Device sets
WD_TRG_EARLY
NO WD_PWRHOLD=0? error-ag Device has
YES NO WINDOW-1
- Device sets Received trigger-
me-interval
WD_BAD_EVENT pulse ?
elapsed?
YES error-ag

YES

NO WD_EN=0?
WINDOW-2
- If FIRST_WD_OK=0, device forces
YES ENABLE_DRV=0, else device does not
YES change ENABLE_DRV bit
- MCU sends trigger-pulse
NO
NORMAL – NO Watchdog
- MCU reset inacve WD_EN=0? NO
- MCU can set Device sets
ENABLE_DRV=1 if no other WD_TIMEOUT error- Device has
WINDOW-2
error-ags are set ag YES
me-interval
NO Received trigger- Device clears
- Interrupt inac ve if no - Device sets pulse ? WD_BAD_EVENT
elapsed?
other error- ag set WD_BAD_EVENT error-ag
error-ag
YES

- Device decrements WD_FAIL_CNT

Device has - Device sets WD_FIRST_OK=1
Device locks all Watchdog
received trigger YES
conguraon register bits, except - MCU can set ENABLE_DRV=1 if no other error-ags are set
pulse?
WD_RETURN_LONGWIN bit

Device Increments
WD_FAIL_CNT[3:0]
LONG-WINDOW
NO
me-interval
elapsed?

YES WD_FAIL_CNT[3:0] > NO

WD_FAIL_TH
Device sets [2:0]
WD_LONGWIN_TIMEOUT
error-ag
YES

WATCHDOG-RESET
- Device forces ENABLE_DRV=0
- Device pulls MCU & SoC reset
- Device sets WD_FAIL_INT
pins low (trigger to FSM)
error-ag
- Device forces ENABLE_DRV=0
- Interrupt acve
- Device clears WD_FIRST_OK bit

Reset-Extension
YES NO
me-interval
elapsed?
WD_FAIL_CNT[3:0] >
- Device sets WD_RST_INT (WD_FAIL_TH[2:0] +
error-ag YES
WD_RST_TH[2:0])
NO
- Interrupt ac ve &
- Device clears WD_RST_EN=1
WD_BAD_EVENT error-!ag

Figure 8-15. Flow Chart for WatchDog Monitor in Trigger Mode

Figure 8-16, Figure 8-17, Figure 8-18, Figure 8-19, and Figure 8-20 give examples of watchdog is trigger mode
with good and bad events after device start-up. In these figures, the red bended arrows indicate a delay of one
20-MHz system clock cycle.

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nRSTOUT RESET Extension Time

(Reset to MCU, controlled by
internal RSTOUT-control signal

t > tWD_pulse t > tWD_pulse t > tWD_pulse

Watchdog-Trigger
on GPIO pin

tWD_pulse tWD_pulse tWD_pulse

Internally Generated
Trigger Pulse

tt <
tt < tLONG_WINDOWt tt = tWINDOW-1t tt < tWINDOW-2t tt = tWINDOW-1t
tWINDOW-2t

Watchdog Windows Long Window Window-1 Window-2 Window-1 Window-2 Window-1

WD_FAIL_CNT[3:0] xxxx 0000 0000 0000

WD_FIRST_OK x 0 1

MCU clears watchdog error-flags

WD_FAIL_INT x 0

WD_RST_INT x 0

WD_LONGWIN_TIMEOUT
x 0
_INT

WD_TRIG_EARLY x 0

WD_TIMEOUT x 0

MCU sets ENABLE_DRV (only possible when

FIRST_WD_OK=1)

ENABLE_DRV x 0 1

Device State x ACTIVE or MCU_ONLY

RECOV_CNT[2:0] 000

Figure 8-16. Watchdog in Trigger Mode – Normal MCU Start-up with Correct Watchdog-Triggers

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RESET Extension Time RESET Extension Time RESET Extension Time

nRSTOUT
(Reset to MCU)

Watchdog-Trigger on
GPIO pin

Internally Generated
Trigger Pulse

tt = tLONG_WINDOWt tt = tLONG_WINDOWt

Watchdog Windows Long Window Long Window Long Window

WD_FAIL_CNT[3:0] xxxx 0000 0000 0000

WD_FIRST_OK x 0 0 0

MCU clears watchdog error-flags

WD_FAIL_INT x 0

WD_RST_INT x 0

WD_LONGWIN_
x 0 1 1 1
TIMEOUT_INT

WD_TRG_EARLY x 0

WD_TIMEOUT x 0

ENABLE_DRV x 0 0 0 0

ACTIVE or MCU_ONLY ACTIVE or MCU_ONLY

Device State x ACTIVE or MCU_ONLY Warm Reset
(same state as previously)
Warm Reset
(same state as previously)
Warm Reset SHUTDOWN

RECOV_CNT[2:0] 000 001 010 « 110 111 000

Figure 8-17. Watchdog in Trigger Mode – MCU Does Not Send Watchdog-Triggers After Start-up

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RESET Extension
RESET Extension Time
Time
nRSTOUT
(Reset to MCU)
t > tWD_pulse t > tWD_pulse t > tWD_pulse t > tWD_pulse
Watchdog-Trigger
on GPIO pin

tWD_pulse tWD_pulse tWD_pulse tWD_pulse

Internally Generated
Trigger Pulse

tt < tLONG_WINDOWt tt = tWINDOW-1t tt < tWINDOW-2t tt < tWINDOW-1t tt < tWINDOW-1t

Watchdog Long Window Long

Window-1 Window-2 Window-1 Window-1
Windows Window

WD_FAIL_CNT[3:0]
WD_FAIL_TH[2:0]=000 xxxx 0000 0000 0001 0010 0000
WD_RST_TH[2:0]=001
WD_FAIL_CNT WD_FAIL_CNT >
> WD_FAIL_TH WD_FAIL_TH + WD_RST_TH

WD_FIRST_OK x 0 1 0
MCU clears watchdog error-flags

WD_FAIL_INT x 0 1

WD_RST_INT x 0 1

WD_LONGWIN x 0
_TIMEOUT_INT

WD_TRG_EARLY x 0 1 1

WD_TIMEOUT x 0

MCU sets ENABLE_DRV (only possible when

FIRST_WD_OK=1)

ENABLE_DRV x 0 1 0

ACTIVE or MCU_ONLY (same

Device State x ACTIVE or MCU_ONLY Warm Reset
state as previously)

RECOV_CNT[2:0] 000 001

Figure 8-18. Watchdog in Trigger Mode – Bad Event (Watchdog-Triggers in Window-1) After Start-up

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RESET
RESET Extension Time Extension Time
nRSTOUT
(Reset to MCU)
t > tWD_pulse t > tWD_pulse t < tWD_pulse

Watchdog-Trigger
on GPIO pin

tWD_pulse tWD_pulse tWD_pulse

Internally Generated
Trigger Pulse

tt < tLONG_WINDOWt tt = tWINDOW-1t tt < tWINDOW-2t tt = tWINDOW-1t tt = tWINDOW-2t tt = tWINDOW-1t tt = tWINDOW-2t

Watchdog Windows Long Window Window-1 Window-2 Window-1 Window-2 Window-1 Window-2 Long Window

WD_FAIL_CNT[3:0]
xxxx 0000 0000 0001 0010 0000
WD_FAIL_TH[2:0]=000
WD_RST_TH[2:0]=001 WD_FAIL_CNT >
WD_FAIL_CNT > WD_FAIL_TH WD_FAIL_TH + WD_RST_TH

FIRST_WD_OK x 0 1 0

MCU clears watchdog error-flags

WD_FAIL_INT x 0 1

WD_RST_INT x 0 1

WD_LONGWIN_ x 0
TIMEOUT_INT

WD_TRIG_EARLY x 0

x 0 1
WD_TIMEOUT
MCU sets ENABLE_DRV (only possible when FIRST_WD_OK=1)

ENABLE_DRV x 0 1 0

x Warm ACTIVE or MCU_ONLY

Device State ACTIVE or MCU_ONLY Reset (same state as previously)

RECOV_CNT[2:0] 000 001

Figure 8-19. Watchdog in Trigger Mode – Bad Events (Too Short or no Trigger in Window-2) After Start-up

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RESET Extension Time

nRSTOUT
(Reset to MCU)
t > tWD_pulse t > tWD_pulse t < tWD_pulse t > tWD_pulse

Watchdog-Trigger
on GPIO pin
tWD_pulse tWD_pulse tWD_pulse tWD_pulse tWD_pulse
Internally Generated
Trigger Pulse tt <
tt < tt < tt <
tLONG_WINDOW tt = tWINDOW-1t tt = tWINDOW-1t tt = tWINDOW-2t tt = tWINDOW-1t tt = tWINDOW-1t
tWINDOW-2t tWINDOW-2t tWINDOW-2t
t
Watchdog Windows Long Window Window-1 Window-2 Window-1 Window-2 Window-1 Window-2 Window-1 Window-2 Window-1

WD_FAIL_CNT[3:0] 00
WD_FAIL_TH[2:0]=000 xxxx 0000 0000 0001 0000
00
WD_RST_TH[2:0]=001
WD_FAIL_CNT > WD_FAIL_TH

FIRST_WD_OK x 0 1
MCU clears WD_FAIL_TH error-flag (only
possible when WD_FAIL_CNT =< WD_FAIL_TH)
MCU clears watchdog error-flags

WD_FAIL_INT x 0 1 0

WD_RST_INT x 0

WD_LONGWIN_ x 0
TIMEOUT_INT

WD_TRIG_EARLY x 0

WD_TIMEOUT x 0 1
MCU sets ENABLE_DRV (only possible when MCU sets ENABLE_DRV (only
FIRST_WD_OK=1) possible when FIRST_WD_OK=1)

ENABLE_DRV x 0 1 0 1

Device State x ACTIVE or MCU_ONLY

RECOV_CNT[2:0] 000

Figure 8-20. Watchdog in Trigger Mode – Good Events (Correct Watchdog-Triggers) After Start-up, Followed by a Bad-Event (No Watchdog-
Trigger in Window-2) and After That Followed by a Good Event.

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8.3.10.8 Watchdog Question-Answer Mode

When the TPS6593-Q1 device is configured to use the Watchdog Question Answer mode, the watchdog
requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU.
The device provides a question for the MCU in WD_QUESTION[3:0] during operation. The MCU performs a
fixed series of arithmetic operations on this question to calculate the required 32-bit answer. This answer is split
into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The MCU writes these answer bytes
one byte at a time into WD_ANSWER[7:0] from the SPI or the dedicated I2C2 interface, mapped to GPIO1 and
GPIO2 pins.
A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the
correct watchdog window and in the correct sequence.
A bad event occurs when one of the events that follows occur:
• The MCU sends the correct answer-bytes, but not in the correct watchdog window.
• The MCU sends incorrect answer-bytes.
• The MCU returns correct answer-bytes, but in the incorrect sequence.
If the MCU stops providing answer-bytes for the duration of the watchdog time-period, the watchdog detects
a time-out event. This time-out event sets the WD_TIMEOUT status bit, increments the WD_FAIL_CNT[3:0]
counter, and starts a new watchdog sequence.
8.3.10.8.1 Watchdog Q&A Related Definitions
A question and answer are defined as follows:

Question A question is a 4-bit word (see Section 8.3.10.8.2).

The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits.
The MCU can request each new question at the start of the watchdog sequence, but this is not
required to calculate the answer. The MCU can also have a software implementation that generates
the question according the circuit shown in Figure 8-23. Nevertheless, the answer and therefore the
answer-bytes are always based on the question generated inside the watchdog of the device. So,
if the MCU generates an incorrect question and gives answer-bytes calculated from this incorrect
question, the watchdog detects a bad event

Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and
Answer-0.
The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For
each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing
and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0
in Window 2) to detect a good event.

The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a
time-out event when the Window-2 time-interval elapses.

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Window-1 Window-2
t = tWINDOW-1 t = tWINDOW-2
Three correct answer-bytes must be provided in Window-1 and
The fourth answer-byte, Answer-0, must be provided
in the correct order:
in Window-2.
x Answer-3
x Answer-2
After the MCU writes the fourth Answer-0 to
x Answer-1
WD_ANSWER[7:0], the Watchdog generates the
next question within 1 Internal System Clock Cycle,
After the Window-1 time elapses, Window 2 begins.
after which the next Watchdog Sequence
(Q&A [n + 1]) begins
The MCU needs to write the answer-bytes to the WD_ANSWER[7:0] bits.

Question Answer
(1) (2)
MCU reads question MCU provides answer

Read bits WD_ Write to Write to Write to Write to

QUESTION[3:0] WD_ANSWER[7:0] WD_ANSWER[7:0] WD_ANSWER[7:0] WD_ANSWER[7:0]
I2C2 / SPI -> Answer-3 -> Answer-2 -> Answer-1 -> Answer-0
Commands

NCS Pin (for

SPI only)

1 Internal System Clock Cycle

to Generate a new question for the next watchdog
sequence Q&A [n + 1]
Q&A [n] Q&A [n + 1]

Watchdog Sequence

The register WD_QUESTION_ANSW_CNT has following bits:

• Bit 6: Reserved
• Bit 5-4: WD_ANSW_CNT. These bits give the number for the next expected answer-byte
• Bit 3-0: WD_QUESTION. These bits give the value of the current generated question
(1) For the question generation, the MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3,
Answer-2, Answer-1 as soon as Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the
watchdog receives the final Answer-0.
(2) The MCU can put other I2C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the
question). The insertion of other commands in-between the write-commands to WD_ANSWER[7:0] has no influence on the detection of
a good event, as long as the three correct answer-bytes in Window-1 are in the correct sequence, and the fourth correct answer-byte is
provided before the configured Window-2 time-interval elapses.

Figure 8-21. Watchdog Sequence in Q&A Mode

8.3.10.8.2 Question Generation

The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in Figure 8-22), and a 4-bit Markov chain to
generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog
generates a new question when the question counter increments, which only occurs when the watchdog detects
a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event.
The question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000.
The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes out
of the Long Window.

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Note
The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In
following situations, the MCU software needs to read the current question in order to synchronize with
the Question-Generator:
• After MCU re-boot from a warm-reset
• After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long
Window
• After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1

Figure 8-22 shows the logic combination for the WD_QUESTION[3:0] generation.
Figure 8-23 shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits
generates the reference answer-bytes.

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4-Bit LFSR Polynomial Equation(1)

WD_QA_LFSR[1:0] = 0x00: y = x4 + x3 + 1 (Default Value)
WD_QA_LFSR[1:0] = 0x01: y = x4 + x2 + 1
WD_QA_LFSR[1:0] = 0x10: y = x3 + x2 + 1
WD_QA_LFSR[1:0] = 0x11: y = x4 + x3 + x2 +1

x1 x2 x3 x4
Bit 0 Bit 1 Bit 2 Bit 3

4-bit SEED Value Loaded when the device goes to the RESET state
(Configurable Through WD_QUESTION_SEED[3:0])
(Default Value 4'b1010)

x1 x2 x3 x4 x2 00
x1 01 WD_QUESTION[0]
SEED 1 0 1 0 x4 10
x3 11
1 1 1 0 1
2 1 1 1 0 QST_CNT[1] 00
QST_CNT[0] 01
3 1 1 1 1 QST_CNT[3] 10
QST_CNT[2] 11
4 0 1 1 1
Question Sequence Order 1 to 15

5 0 0 1 1 x4 00
x3 01 WD_QUESTION[1]
6 0 0 0 1 x2 10
x1 11
7 1 0 0 0
8 0 1 0 0 QST_CNT[3] 00
QST_CNT[2] 01
QST_CNT[1] 10
9 0 0 1 0 QST_CNT[0] 11
10 1 0 0 1
x1 00
11 1 1 0 0 x4 01 WD_QUESTION[2]
x3 10
12 0 1 1 0 x2 11
13 1 0 1 1
QST_CNT[0] 00
14 0 1 0 1 QST_CNT[3] 01
QST_CNT[2] 10
15 1 0 1 0 QST_CNT[1] 11

The default question-sequence order with the default

x3 00
WD_QUESTION_SEED[3:0] and WD_QA_LFSR[1:0] values x2 WD_QUESTION[3]
01
x1 10
x4 11
µ4XHVWLRQ¶ &RXQWHU
CNT [0] QST_CNT[0] QST_CNT[2] 00
QST_CNT[1] 01
³JRRG HYHQW´ CNT [1] QST_CNT[1] QST_CNT[0] 10
INCR + 1
QST_CNT[3] 11
trigger CNT [2] QST_CNT[2]

CNT [3] QST_CNT[3]

Feedback settings are controllable through the bits

WD_QA_FDBK[1:0]
(Default value is 2'b00; the selected signals are in red)

(1) If the current value for bits (x1, x2, x3, x4) is 4'b0000, the next value for these bits (x1, x2, x3, x4) is 4'b0001, and all further question
generation begins from this value.

Figure 8-22. Watchdog Question Generation

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WD_QUESTION[0] 00
WD_QUESTION[1] 01 Reference-Answer-X[0]
WD_QUESTION[2] 10
WD_QUESTION[3] 11 X = 3, 2,1, 0
WD_ANSW_CNT[1]

WD_QUESTION[3] 00
WD_QUESTION[2] 01
WD_QUESTION[1] 10
WD_QUESTION[0] 11

WD_QUESTION[0] 00
WD_QUESTION[1] 01 Reference-Answer-X[1]
WD_QUESTION[2] 10
WD_QUESTION[3] 11 X = 3, 2,1, 0

WD_QUESTION[2] 00
WD_QUESTION[1] 01
WD_QUESTION[0] 10
WD_QUESTION[3] 11
WD_QUESTION[1]

WD_ANSW_CNT[1]
WD_QUESTION[0] 00
WD_QUESTION[3] 01 Reference-Answer-X[2]
WD_QUESTION[1] 10
WD_QUESTION[1] 11 X = 3, 2,1, 0

WD_QUESTION[3] 00
WD_QUESTION[2] 01
WD_QUESTION[1] 10
WD_QUESTION[0] 11

WD_QUESTION[1]
WD_ANSW_CNT[1]
WD_QUESTION[2] 00
WD_QUESTION[1] 01
WD_QUESTION[0] Reference-Answer-X[3]
10
WD_QUESTION[3] 11 X = 3, 2,1, 0

WD_QUESTION[0] 00
WD_QUESTION[3] 01
WD_QUESTION[2] 10
WD_QUESTION[1] 11
WD_QUESTION[3]
WD_ANSW_CNT[1]

WD_QUESTION[1] 00
WD_QUESTION[0] 01 Reference-Answer-X[4]
WD_QUESTION[2] 10
WD_QUESTION[3] 11 X = 3, 2,1, 0
WD_ANSW_CNT[0]
WD_QUESTION[3] 00
WD_QUESTION[2] 01
WD_QUESTION[1] Reference-Answer-X[5]
10
WD_QUESTION[0] 11 X = 3, 2,1, 0
WD_ANSW_CNT[0]
WD_QUESTION[0] 00
WD_QUESTION[3] 01
WD_QUESTION[2] 10 Reference-Answer-X[6]
WD_QUESTION[1] 11 X = 3, 2,1, 0
WD_ANSW_CNT[0]
WD_QUESTION[2] 00
WD_QUESTION[1] 01
WD_QUESTION[0] Reference-Answer-X[7]
10 X = 3, 2,1, 0
WD_QUESTION[3] 11
WD_ANSW_CNT[0]

Feedback settings are controllable through the bits WD_QA_FDBK[1:0] Calculated Reference-Answer-X byte
(Default value is 2'b00; the selected signals are in red)

Figure 8-23. Watchdog Reference Answer Calculation

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8.3.10.8.3 Answer Comparison

The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and
controls the generation of the reference answer-byte as shown in Figure 8-23. At the start of each watchdog
sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects
the MCU to write the correct Answer-3 in WD_ANSWER[7:0].
The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears
this status bit only if the MCU writes a ‘1’ to this bit.
8.3.10.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value:
• WD_ANSW_CNT[1:0] = 2‘b11:
1. The watchdog calculates the reference Answer-3.
2. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0].
3. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0].
4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status
bit to 1 if the Answer-3 byte was incorrect.

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• WD_ANSW_CNT[1:0] = 2b‘10:
1. The watchdog calculates the reference Answer-2.
2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0].
3. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0]..
4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status
bit to 1 if the Answer-2 byte was incorrect.
• WD_ANSW_CNT[1:0] = 2b‘01:
1. The watchdog calculates the reference Answer-1.
2. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0].
3. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0]..
4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status
bit to 1 if the Answer-1 byte was incorrect.
• WD_ANSW_CNT[1:0] = 2b‘00:
1. The watchdog calculates the reference Answer-0.
2. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0].
3. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0].
4. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect.
5. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’.
The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit.
Table 8-9. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG
Register
ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0])
WD QUESTION
ANSWER-3 ANSWER-2 ANSWER-1 ANSWER-0
WD_ANSW_CNT [1:0] = WD_ANSW_CNT [1:0] = WD_ANSW_CNT [1:0] = WD_ANSW_CNT [1:0] =
WD_QUESTION[3:0]
2’b11 2’b10 2’b01 2’b00
0x0 FF 0F F0 00
0x1 B0 40 BF 4F
0x2 E9 19 E6 16
0x3 A6 56 A9 59
0x4 75 85 7A 8A
0x5 3A CA 35 C5
0x6 63 93 6C 9C
0x7 2C DC 23 D3
0x8 D2 22 DD 2D
0x9 9D 6D 92 62
0xA C4 34 CB 3B
0xB 8B 7B 84 74
0xC 58 A8 57 A7
0xD 17 E7 18 E8
0xE 4E BE 41 B1
0xF 01 F1 0E FE

8.3.10.8.3.2 Watchdog Sequence Events and Status Updates

The watchdog sequence events are as follows for the different scenarios listed:
• A good event occurs when all answer bytes are correct in value and timing. After such a good event,
following events occur:
1. The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence.
2. The question-counter increments by one and the watchdog generates a new question.
• A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad
event, following events occur:

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1. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before
watchdog has received Answer-3, Answer-2 and Answer-1.
2. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers
in Window-1.
3. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.
4. The question-counter does not change, and hence the watchdog does not generate a new question.
• A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After
such a bad event, following events occur:
1. The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an
incorrect answer-byte.
2. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.
3. The question-counter does not change, and hence the watchdog does not generate a new question.
• A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing.
After such a bad event, following events occur:
1. The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an
incorrect answer-byte.
2. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before
watchdog has received Answer-3, Answer-2 and Answer-1.
3. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-
bytes in Window-1.
4. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.
5. The question-counter does not change, and hence the watchdog does not generate a new question.
• A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval
elapses. After a time-out event occurs, following events occur:
1. WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before
watchdog has received Answer-3, Answer-2 and Answer-1.
2. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence.
3. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.
4. The question-counter does not change, and hence the watchdog does not generate a new question.
The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of
the watchdog-sequence.
The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’
to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next
watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at
the end of the watchdog-sequence.
Figure 8-24 shows the flow-chart of the watchdog in Q&A mode.

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WD_RETURN_
YES
LONGWIN=1?

NO
NO SUPPLY
ANSWER-3
Device sets WD_RST_EN=1 per default - Device sets WD_ANSW_CNT[2:0]=2'b11
Device sets WD_EN=1 per default. - If FIRST_WD_OK=0, device forces
Wake-up ENABLE_DRV=0, else device does not
NO
request? change ENABLE_DRV bit
NO NO - MCU sends ANSWER-3
- Device sets
YES WD_SEQ_ERR
error-ag
- Device sets Device has
WINDOW-2 YES WINDOW-1 NO received
WD_BAD
,me-interval me-interval ANSWER-3 ?
_EVENT
elapsed? elapsed?
error-ag
RESTART YES
from all Reset-Extension
NO
states except )me-interval YES - Device sets
NO SUPPLY
elapsed? WD_ANSW_ERR error-ag NO
ANSWER-3
- Device sets correct?
YES WD_BAD_EVENT error-ag
YES

WATCHDOG LONG WINDOW ANSWER-2

- Device releases MCU reset pin - Device sets WD_ANSW_CNT[2:0]=2'b10
- Device forces ENABLE_DRV= 0 - If FIRST_WD_OK=0, device forces
- MCU clears error-ags ENABLE_DRV=0, else device does not
- Device releases nINT pin if no other error-ags are set change ENABLE_DRV bit
NO
- Device unlocks Watchdog-Conguraon registers NO - MCU sends ANSWER-2
- Device sets WD_ANSW_CNT[2:0]=2'b11
- Device sets WD_FAIL_CNT[3:0]=4'b0000 and sets WD_FIRST_OK=0 - Device sets
MCU either clears WD_EN, or: WD_SEQ_ERR
1) MCU congures watchdog in Q&A mode WINDOW-2 error- ag WINDOW-1
Device has
YES NO
2) MCU congures Window-1 and Window-2 me-intervals +me-interval - Device sets me-interval
received
3) MCU congures WD_FAIL_TH, WD_RST_TH and WD_RST_EN elapsed? WD_BAD elapsed?
ANSWER-2?
4) MCU sends 4 answers _EVENT
error-!ag YES

YES
- Device sets
WD_ANSW_ERR error-ag NO
ANSWER-2
- Device sets correct?
NO WD_PWRHOLD=0?
WD_BAD_EVENT error-ag
YES
YES
ANSWER-1
- Device sets WD_ANSW_CNT[2:0]=2'b01
- If FIRST_WD_OK=0, device forces
NO WD_EN=0? ENABLE_DRV=0, else device does not
NO change ENABLE_DRV bit
NO - MCU sends ANSWER-1
YES
YES - Device sets
WD_SEQ_ERR
error-"ag
- Device sets Device has
NORMAL – NO Watchdog WINDOW-2 YES WINDOW-1 NO received
- MCU reset inac ve WD_EN=0? NO *me-interval WD_BAD me-interval
_EVENT ANSWER-1?
- MCU can set elapsed? elapsed?
error-#ag
ENABLE_DRV=1 if no other YES
error- ags are set
- Device released nINT pin if YES - Device sets
no other error- ag set WD_ANSW_ERR error-$ag
- -Device sets NO ANSWER-1
WD_BAD_EVENT error-%ag correct?

YES
Device generates 1st
Device has
QUESTION
received 4 YES ANSWER-0
- Device locks all Watchdog
answers ?
con0gura1on register bits, - Device sets WD_ANSW_CNT[2:0]=2'b00
except - If FIRST_WD_OK=0, device forces
WD_RETURN_LONGWIN bit ENABLE_DRV=0, else device does not
NO NO change ENABLE_DRV bit
- MCU sends ANSWER-0
Device sets
WD_TIMEOUT
LONG-WINDOW error-ag Device has
NO WINDOW-2
me-interval - Device sets YES NO received
elapsed?
Device me-interval
WD_BAD_EVENT ANSWER-0?
Increments elapsed?
error-ag
WD_FAIL_CNT YES
YES [3:0]

Device sets Device sets

WINDOW-1
WD_LONGWIN_TIMEOUT WD_ANSW_EARLY error-ag
error--ag YES me-interval
- Device sets
not elapsed?
WD_FAIL_CNT[3:0] > NO WD_BAD_EVENT error-ag
WD_FAIL_TH
WATCHDOG-RESET [2:0]
- Device pulls MCU & SoC reset NO
pins low (trigger to FSM)
- Device forces ENABLE_DRV=0 YES - Device sets
Device clears
- Device clears WD_FIRST_OK bit WD_ANSW_ERR error-&ag
NO ANSWER-0 WD_BAD_EVENT
- Device forces ENABLE_DRV=0 - Device sets
error-(ag
- Device sets WD_FAIL_INT WD_BAD_EVENT error-'ag correct?
error-.ag
YES
- Interrupt ac/ve
Reset-Extension
YES NO
me-interval
elapsed? - Device sets WD_RST_INT YES WD_BAD_EVENT
error- ag =1?
- Interrupt acve
- Device clears
WD_BAD_EVENT error-ag NO
WD_FAIL_CNT[3:0] >
(WD_FAIL_TH[2:0] + - Device decrements WD_FAIL_CNT
YES NO - Device generates next QUESTION
WD_RST_TH[2:0])
& - Device sets WD_FIRST_OK=1
WD_RST_EN=1 - MCU can set ENABLE_DRV=1 if no other error- ags are set

Figure 8-24. Flow Chart for WatchDog in Q&A Mode

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8.3.10.8.3.3 Watchdog Q&A Sequence Scenarios

Table 8-10. Correct and Incorrect WD Q&A Sequence Run Scenarios
NUMBER OF WD ANSWERS WD STATUS BITS IN WDT_STATUS REGISTER
RESPONSE RESPONSE ACTION COMMENTS
ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT
WINDOW 1 WINDOW 2
-New WD cycle starts after the
end of RESPONSE WINDOW 2
0 answers 0 answers -Increment WD failure counter 0b 0b 1b 1b No answers
-New WD cycle starts with the
same WD question
-New WD cycle starts after the
4th WD answer
4 INCORRECT
0 answers -Increment WD failure counter 1b 0b 1b 0b WD_ANSW_CNT[1:0] = 3
answers
-New WD cycle starts with the
same WD question
-New WD cycle starts after the
4th WD answer
4 CORRECT
0 answers -Increment WD failure counter 0b 0b 1b 0b WD_ANSW_CNT[1:0] = 3
answers
-New WD cycle starts with the
same WD question
0 answers 1 CORRECT answer Less than 3 CORRECT
-New WD cycle starts after the
ANSWER in RESPONSE
1 CORRECT answer 1 CORRECT answer end of RESPONSE WINDOW 2 WINDOW 1 and 1
-Increment WD failure counter 0b 0b 1b 1b
CORRECT ANSWER in
-New WD cycle starts with the
2 CORRECT answer 1 CORRECT answer same WD question RESPONSE WINDOW 2
(WD_ANSW_CNT[1:0] < 3)
1 INCORRECT
0 answers Less than 3 CORRECT
answer -New WD cycle starts after the
ANSWER in RESPONSE
end of RESPONSE WINDOW 2
1 INCORRECT WINDOW 1 and 1
1 CORRECT answer -Increment WD failure counter 1b 0b 1b 1b
answer INCORRECT ANSWER in
-New WD cycle starts with the
RESPONSE WINDOW 2
2 CORRECT 1 INCORRECT same WD question
(WD_ANSW_CNT[1:0] < 3)
answers answer
4 CORRECT
0 answers
answers -New WD cycle starts after the Less than 3 CORRECT
4th WD answer ANSWER in WIN1 and more
3 CORRECT
1 CORRECT answer -Increment WD failure counter 0b 0b 1b 0b than 1 CORRECT ANSWER
answers
-New WD cycle starts with the in RESPONSE WINDOW 2
2 CORRECT 2 CORRECT same WD question (WD_ANSW_CNT[1:0] = 3)
answers answers
4 INCORRECT
0 answers Less than 3 CORRECT
answers -New WD cycle starts after the
ANSWER in RESPONSE
4th WD answer
3 INCORRECT WINDOW 1 and more than
1 CORRECT answer -Increment WD failure counter 1b 0b 1b 0b
answers 1 INCORRECT ANSWER
-New WD cycle starts with the
in RESPONSE WINDOW 2
2 CORRECT 2 INCORRECT same WD question
(WD_ANSW_CNT[1:0] = 3)
answers answers
-New WD cycle starts after the
end of RESPONSE WINDOW 2
3 CORRECT
0 answers -Increment WD failure counter 0b 0b 1b 1b Less than 3 INCORRECT
answers
-New WD cycle starts with the ANSWER in RESPONSE
same WD question WINDOW 1 and more than
1 INCORRECT 2 CORRECT -New WD cycle starts after the 1 CORRECT ANSWER in
answer answers end of RESPONSE WINDOW 2 RESPONSE WINDOW 2
-Increment WD failure counter 1b 0b 1b 1b (WD_ANSW_CNT[1:0] < 3)
2 INCORRECT
1 CORRECT answer -New WD cycle starts with the
answers same WD question
3 INCORRECT
0 answers Less than 3 INCORRECT
answers -New WD cycle starts after the
ANSWER in RESPONSE
end of RESPONSE WINDOW 2
1 INCORRECT 2 INCORRECT WINDOW 1 and more than
-Increment WD failure counter 1b 0b 1b 1b
answer answer 1 INCORRECT ANSWER
-New WD cycle starts with the
in RESPONSE WINDOW 2
2 INCORRECT 1 INCORRECT same WD question
(WD_ANSW_CNT[1:0] < 3)
answer answer
4 CORRECT
0 answers 0b 0b 1b 0b Less than 3 INCORRECT
answers -New WD cycle starts after the
ANSWER in RESPONSE
4th WD answer
1 INCORRECT 3 CORRECT WINDOW 1 and more than
-Increment WD failure counter
answer answers 1 CORRECT ANSWER in
-New WD cycle starts with the 1b 0b 1b 0b RESPONSE WINDOW 2
2 INCORRECT 2 CORRECT same WD question
(WD_ANSW_CNT[1:0] = 3)
answers answers
4 INCORRECT
0 answers Less than 3 INCORRECT
answers -New WD cycle starts after the
ANSWER in RESPONSE
4th WD answer
1 INCORRECT 3 INCORRECT WINDOW 1 and more than
-Increment WD failure counter 1b 0b 1b 0b
answer answers 1 INCORRECT ANSWER
-New WD cycle starts with the
in RESPONSE WINDOW 2
2 INCORRECT 2 INCORRECT same WD question
(WD_ANSW_CNT[1:0] = 3)
answers answers

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Table 8-10. Correct and Incorrect WD Q&A Sequence Run Scenarios (continued)
NUMBER OF WD ANSWERS WD STATUS BITS IN WDT_STATUS REGISTER
RESPONSE RESPONSE ACTION COMMENTS
ANSW_ERR ANSW_EARLY SEQ_ERR TIME_OUT
WINDOW 1 WINDOW 2
3 CORRECT
0 answers 0b 0b 0b 1b
answers -New WD cycle starts after the Less than 4 CORRECT ANSW
end of RESPONSE WINDOW 2 in RESPONSE WINDOW 1
2 CORRECT
0 answers -Increment WD failure counter and more than 0 ANSWER
answers
-New WD cycle starts with the 0b 0b 1b 1b in RESPONSE WINDOW 2
1 CORRECT same WD Question (WD_ANSW_CNT[1:0] < 3)
0 answers
answers
-New WD cycle starts after the
4th WD answer
3 CORRECT
1 CORRECT answer -Decrement WD failure counter 0b 0b 0b 0b CORRECT SEQUENCE
answers
-New WD cycle starts with a new
WD question
-New WD cycle starts after the
4th WD answer
3 CORRECT 1 INCORRECT
-Increment WD failure counter 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3
answers answers
-New WD cycle starts with the
same WD question
-New WD cycle starts after the
end of RESPONSE WINDOW 2
3 INCORRECT
0 answers -Increment WD failure counter 1b 0b 0b 1b WD_ANSW_CNT[1:0] < 3
answers
-New WD cycle starts with the
same WD question
-New WD cycle starts after the
4th WD answer
3 INCORRECT
1 CORRECT answer -Increment WD failure counter 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3
answers
-New WD cycle starts with the
same WD question
-New WD cycle starts after the
4th WD answer
3 INCORRECT 1 INCORRECT
-Increment WD failure counter 1b 0b 0b 0b WD_ANSW_CNT[1:0] = 3
answers answer
-New WD cycle starts with the
same WD question
-New WD cycle starts after the
4th WD answer
4 CORRECT
Not applicable -Increment WD failure counter 0b 1b 0b 0b
answers
-New WD cycle starts with the
same WD question
3 CORRECT
answers + 1 Not applicable 4 CORRECT or INCORRECT
INCORRECT answer ANSWER in RESPONSE
-New WD cycle starts after the WINDOW 1
2 CORRECT
4th WD answer
answers +
Not applicable -Increment WD failure counter 1b 1b 0b 0b
2 INCORRECT
-New WD cycle starts with the
answers
same WD question
1 CORRECT answer
+ 3 INCORRECT Not applicable
answers

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8.3.11 Error Signal Monitor (ESM)

The TPS6593-Q1 device has two error signal monitor (ESMs): one ESM_MCU to monitor the MCU error output
signal at the nERR_MCU input pin, and one ESM_SoC to monitor the SoC error output signal at the nERR_SoC
input pin.
At device start-up, the ESM_MCU and ESM_SoC can be enabled or deactivated through configuration bits
ESM_MCU_EN and ESM_SOC_EN. The values for these configuration bits are stored in the NVM memory of
the device. To start the enabled ESM, the MCU sets the start bits ESM_MCU_START or ESM_SOC_START for
the corresponding ESM through software after the system is powered up and the initial software configuration
is completed. If the MCU clears a start bit, the ESM stops monitoring its input pin. The MCU can set the
ENABLE_DRV bit only when the MCU has either started or deactivated the ESM. When the corresponding ESM
is started, the following configuration registers are write protected and can only be read:
Configuration registers write-protected by the ESM_MCU_START register bit:
• ESM_MCU_DELAY1_REG
• ESM_MCU_DELAY2_REG
• ESM_MCU_MODE_CFG
• ESM_MCU_HMAX_REG
• ESM_MCU_HMIN_REG
• ESM_MCU_LMAX_REG
• ESM_MCU_LMIN_REG
Configuration registers write-protected by the ESM_SOC_START register bit:
• ESM_SOC_DELAY1_REG
• ESM_SOC_DELAY2_REG
• ESM_SOC_MODE_CFG
• ESM_SOC_HMAX_REG
• ESM_SOC_HMIN_REG
• ESM_SOC_LMAX_REG
• ESM_SOC_LMIN_REG
The ESM uses a deglitch-filter with deglitch-time tdegl_ESMx to monitor its related input pin.
The MCU can configure the ESM in two different modes that are defined as follows:
Level the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the
Mode deglitch-time tdegl_ESMx.
To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this
mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See Section 8.3.11.1.1 for further
detail
.
PWM the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or
Mode duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event
when the frequency and duty cycle of the PWM signal match with the expected signal for one signal
period.
The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which
increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM
detects an ESM-error when the error-counter value is more than its related threshold value.
To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this mode
for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See Section 8.3.11.1.2 for further details.

The MCU can configure each ESM as long as its related start bit is cleared to 0 (bit ESM_MCU_START or
ESM_SOC_START). As soon as the MCU sets a start bit, the device sets a write-protection on the configuration
registers of the related ESM except the related start bits ESM_MCU_START and ESM_SOC_START.

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8.3.11.1 ESM Error-Handling Procedure

Each ESM has two of its own configurable delay-timers that are reset when the device clears the respective
ESM_x_START bit. Below steps describe the procedure through which the ESM goes in case it detects an
ESM-error:
1. If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or
ESM_SOC_PIN_INT, and pulls the nINT pin low.
2. The ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or
ESM_SOC_DELAY1[7:0] bits).
3. If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT or
ESM_SOC_PIN_INT before the delay-1 timer elapses, the device releases the nINTpin, the ESM resets the
delay-1 and delay-2 timers and continues to monitor its input pin.
4. If the ESM-error is still present, or if MCU has not cleared the related interrupt bit ESM_MCU_PIN_INT
or ESM_SOC_PIN_INT, and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if bit
ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1.
5. If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits)
is set to 0, then the ESM skips steps 6 of this list, and performs step 7.
6. If the delay-2 timer is not set to 0, then:
a. ESM starts the delay-2 timer,
b. If ESM_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin
low and starts the delay-2 timer.
c. If ESM_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low
and starts the delay-2 timer.
7. If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before
the delay-2 timer elapses, the device releases the nINTpin, the ESM resets the delay-1 and delay-2 timers
and continues to monitor its input pin:
• ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or
• ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6)
8. If the ESM-error is still present, or if MCU has not cleared the related interrupt bits ESM_MCU_PIN_INT and
ESM_MCU_FAIL_INT , or ESM_SOC_PIN_INT and ESM_SOC_FAIL_INT, and the delay-2 timer elapses,
then :
a. For ESM_MCU, the device:
i. clears the ESM_MCU_START BIT
ii. sets interrupt bits ESM_MCU_FAIL_INT and ESM_MCU_RST_INT, which the device handles as an
ESM_MCU_RST trigger for FSM, described in Summary of Interrupt Signals
iii. After this trigger handling completes, the device re-initializes the ESM_MCU
b. For ESM_SoC, the device:
i. clears the ESM_SOC_START bit
ii. sets interrupt bits ESM_SOC_FAIL_INT and ESM_SOC_RST_INT, which the device handles as an
ESM_SOC_RST trigger for FSM, described in Summary of Interrupt Signals
iii. After this trigger handling completes, the device re-initializes the ESM_SoC
ESM_MCU_DELAY1[7:0] and ESM_SOC_DELAY1[7:0] set the delay-1 time-interval (tDELAY-1) for the related
ESM_MCU or ESM_SoC. Use Equation 9 and Equation 10 to calculate the worst-case values for the tDELAY-1:

Min. tDELAY-1 = (ESM_x_DELAY1[7:0] × 2.048 ms) × 0.95 (9)

Max. tDELAY-1 = (ESM _x_DELAY1[7:0] × 2.048 ms) × 1.05 (10)

, in which x stands for either MCU or SoC.

ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits set the delay-2 time-interval (tDELAY-2) for the related
ESM_MCU or ESM_SoC. Use Equation 11 and Equation 12 to calculate the worst-case values for the tDELAY-2:

Min. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 0.95 (11)

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Max. tDELAY-2 = (ESM_x_DELAY2[7:0] × 2.048 ms) × 1.05 (12)

, in which x stands for either MCU or SoC.

8.3.11.1.1 Level Mode
In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM
monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on
its input pin remains low for a time equal or longer than the deglitch-time tdegl_ESMx. When an ESM_x detects
an ESM-error, it starts the ESM Error-Handling procedure as described in Section 8.3.11.1. The Error-Handling
Procedure is stopped if, before elapse of the delay-1 or delay-2 interval, the voltage level on the input pin
remains high for a time equal or longer than the deglitch-time tdegl_ESMx and the MCU clears all corresponding
interrupt bits. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM
sends a ESM_x_RST trigger to the PFSM and the device clear the ESM_x_START bit. After the PFSM
completes the handling of the ESM_x_RST trigger, the device re-initializes the ESM.
For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in Figure 8-25.
In this flow-chart, the _x stands for either _MCU or _SoC. Figure 8-26, Figure 8-27, Figure 8-28, and Figure
8-29 show example wave forms for several error-cases for the ESM in Level Mode. In these examples, only the
ESM_MCU is shown.

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START Global Reset Conditions:

- Warm-Reset from Watchdog or ESM_x ESM_x Level Mode
ESM_x in Level-Mode
- Immediate or Orderly Shutdown Procedure - Device releases MCU/SoC reset pin
- Device Power-On-Reset - MCU can set ENABLE_DRV bit
NO - Device releases nINT pin
ESM_x_EN=1
- no ESM_x interrupt bit set
?

YES

ESM_x pin
NO
level
- Device clears ESM_x_START=0 = 0?
- Device resets the ESM_x_DELAY1 YES
and ESM_x_DELAY2 timers

ESM_x-INTERRUPT
Note: the procedures ^Check - If ESM_x_PIN_MASK=0, device sets
ESM_x_START=1" and ^ESM_x Level ESM_x_PIN_INT interrupt bit And pulls nINT
- Device releases
D} WŒ} µŒ ^ Œµv ]v ‰ Œ oo o. pin low
nINT pin if all
Reset-Extension - Device starts ESM_x_DELAY1 timer, or
NO time-interval
If ESM_x_START=0, the device stops interrupt bits are
continues to run this timer if already started
cleared
elapsed? the ^ESM_x Level Mode - Device does not change ENABLE_DRV bit
- ESM resets
WŒ} µŒ ^ - Device does not change the level of the
ESM_x_DELAY1 and
MCU/SoC reset pins
ESM_x_DELAY2
Check ESM_x_START=1 timers
YES
- Device stops ESM_x
Level Mode Procedure
NO ESM_x_START YES ESM_x pin
- Device resets the
=1? level =1 &
ESM_x_DELAY1 and YES
ESM_x_PIN_INT=0
ESM_x_DELAY2 timers
?

ESM_x-CONFIGURE
- Device releases MCU/SoC reset pin ESM_x_DELAY1
NO
- For ESM_MCU: Device forces ENABLE_DRV = 0 time-interval
- For ESM_SoC: Device forces ENABLE_DRV = 0 if ESM_SoC_ENDRV = 1 elapsed?
- MCU clears all interrupt bits
- Device releases nINT pin if no other interrupt bits are set
- ESM_x configuration registers unlocked YES
- MCU either clears ESM_x_EN, or
1) MCU configures ESM_x in Level-Mode (bit ESM_x_MODE)
2) MCU configures ESM_x_DELAY1, ESM_x_DELAY2 and ESM_x_ENDRV Configuration bit
3) MCU sets ESM_x_START YES Device forces
ESM_x_ENDRV =1? ENABLE_DRV= 0

Device locks all NO

ESM_x
ESM_x_START YES
configuration
=1?
registers

NO
ESM_x_DELAY2 YES
set to 0?
NO ESM_x_EN
=0? NO

- If ESM_x_FAIL_MASK=0, device sets

YES
ESM_x_FAIL_INT interrupt bit And pulls
nINT pin low
- Device starts ESM_x_DELAY2 timer, or
NO ESM_x continues to run this timer if already started
- MCU/SoC reset inactive
- MCU can set ENABLE_DRV bit (if
no other interrupt bits are set)
- nINT pin released
(if no other interrupt bits are set) YES
- no ESM_x interrupt bit set ESM_x pin level =1
& ESM_x_PIN_INT=0 &
ESM_x_FAIL_INT=0
?

ESM_x Level-Mode NO
NO ESM_x_EN YES
=0? Error-Handling
Procedure ESM_x_DELAY2
NO
time-interval
elapsed?

YES

- If ESM_x_FAIL_MASK=0, device sets

ESM_x_FAIL_INT interrupt bIt and pulls nINT
pin low

ESM_x-RESET
- ESM_x_RST trigger send to to FSM
- If ESM_x_RST_MASK=0, device sets
ESM_x_RST_INT interrupt bit and
pulls nINT pin low

Figure 8-25. Flow Chart for Error Detection in Level Mode

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MCU Reset-Extension Time

nRSTOUT Pin
MCU sets
ESM_MCU_START

ESM_MCU_START x 0 1

tdegl_ESMx 15 s tLOW_ERROR <

ESM_MCU_DELAY1

ESM_MCU Input
Pin
tdegl_ESMx 15 s

tdegl_ESMx 15 s

Deglitched ESM_MCU
Input Signal

tdegl_ESMx 15 s
ESM_MCU_DELAY1 timer reset after
MCU clears ESM_MCU_PIN_INT
ESM_MCU_DELAY1

MCU clears
ESM_MCU_PIN_INT &
Deglitched ESM_MCU Input Signal = high

ESM_MCU_PIN_INT
0 1 0
(ESM_MCU_PIN_MASK=0)

nINT goes immediately low,

MCU needs to check
whether it initiated the nINT goes high after MCU clears
nINT Pin ESM_MCU_PIN_INT
fault-injection or not

ESM_MCU_FAIL_INT 0
(ESM_MCU_FAIL_MASK=0)

ESM_MCU_RST_INT 0
(ESM_MCU_RST_MASK=0)

ENABLE_DRV x 0 1

MCU sets ENABLE_DRV (only

possible when
ESM_MCU_START=1)

Device State x ACTIVE or MCU_ONLY

0 t

Case Number 1:
MCU initiated a fault-injection, and MCU clears the ESM_MCU_PIN_INT interrupt bit before elapse of ESM_MCU_DELAY1 time-interval

Figure 8-26. Example Waveform for ESM in Level Mode - Case Number 1: ESM_MCU Signal Recovers Before Elapse of Delay-1 time-interval

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MCU Reset-Extension Time

nRSTOUT Pin
MCU sets
ESM_MCU_START

ESM_MCU_START x 0 1

tESM_DEGLITCH 15 s
tLOW_ERROR < (ESM_MCU_DELAY1 +
ESM_MCU_DELAY2)

ESM_MCU Input Pin

tdegl_ESMx 15 s

Deglitched ESM_MCU
Input Signal

tdegl_ESMx 15 s
ESM_MCU_DELAY1 and
ESM_MCU_DELAY2 timers reset after
MCU clears ESM_MCU_PIN_INT and
ESM_MCU_FAIL_INT
ESM_MCU_DELAY1 ESM_MCU_DELAY2

MCU clears
ESM_MCU_PIN_INT &
Deglitched ESM_MCU Input Signal = high

ESM_MCU_PIN_INT
0 1 0
(ESM_MCU_PIN_MASK=0)

nINT goes immediately low,

MCU needs to check
whether it initiated the nINT goes high after MCU clears
nINT Pin & ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT
fault-injection or not

MCU clears
ESM_MCU_FAIL_INT
ESM_MCU_FAIL_INT
(ESM_MCU_FAIL_MASK=0) 0 1 0

ESM_MCU_RST_INT 0
(ESM_MCU_RST_MASK=0)

ENABLE_DRV x 0 1 0 1

MCU sets ENABLE_DRV (only

possible when MCU sets ENABLE_DRV
ESM_MCU_START=1)

Device State x ACTIVE or MCU_ONLY

0 t

Case Number 2: ESM_MCU_DELAY2 > 0

An error event occurred in the MCU, but the MCU recovers and clears the interrupt bits before elapse of the ESM_MCU_DELAY2 time-interval

Figure 8-27. Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Signal
Recovers Before Elapse of Delay-2 Time-Interval

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MCU Reset-Extension Time MCU Reset-Extension Time

nRSTOUT Pin MCU sets

MCU sets ESM_MCU_START after all
ESM_MCU_START interrupt bits are cleared

ESM_MCU_START x 0 1 0 1

tdegl_ESMx 15 s
tLOW_ERROR

ESM_MCU Input
Pin
tdegl_ESMx 15 s tdegl_ESMx 15 s

Deglitched ESM_MCU
Input Signal
tdegl_ESMx 15 s

ESM_MCU_DELAY1 timer
ESM_MCU_DELAY1 reset when ESM resets the
MCU MCU clears
ESM_MCU_PIN_INT &
Deglitched ESM_MCU Input Signal = high

ESM_MCU_PIN_INT
(ESM_MCU_PIN_MASK=0) 0 1 0

nINT goes immediately low,

MCU needs to check
whether it initiated the nINT goes high after MCU clears
nINT Pin & ESM_MCU_PIN_INT and ESM_MCU_RST_INT
fault-injection or not

ESM_MCU_FAIL_INT
(ESM_MCU_FAIL_MASK=0) 0
MCU clears
ESM_MCU_RST_INT
ESM_MCU_RST_INT
0 1
(ESM_MCU_RST_MASK=0)

ENABLE_DRV x 0 1 0 1

MCU sets ENABLE_DRV (only MCU sets ENABLE_DRV (only

possible when possible when
ESM_MCU_START=1) ESM_MCU_START=1)

Device State Warm

x ACTIVE or MCU_ONLY Reset ACTIVE or MCU_ONLY (same as previous)

0 t

Case Number 3a: ESM_MCU_DELAY2 = 0

An error event occurred in the MCU, and the MCU is unable to correct the error before elapse of the ESM_MCU_DELAY1 time-interval. Hence the PMIC resets the MCU

Figure 8-28. Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and ESM_MCU_ENDRV=1, ESM_MCU Input Signal
Recovers Too Late and MCU-Reset Occurs

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MCU Reset-Extension Time MCU Reset-Extension Time

nRSTOUT Pin
MCU sets MCU sets ESM_MCU_START
ESM_MCU_START after all interrupt bits are cleared

ESM_MCU_START x 0 1 0 1

tdegl_ESMx 15 s
tLOW_ERROR

ESM_MCU Input Pin

tdegl_ESMx 15 s tdegl_ESMx 15 s

Internally Deglitched
ESM_MCU Input Signal

tdegl_ESMx 15 s ESM_MCU_DELAY1 and

ESM_MCU_DELAY2
timers reset when ESM MCU clears
ESM_MCU_DELAY1 ESM_MCU_DELAY2 resets the MCU ESM_MCU_PIN_INT &
Deglitched ESM_MCU Input Signal = high

ESM_MCU_PIN_INT
0 1 0
(ESM_MCU_PIN__MASK=0)

nINT goes immediately low,

MCU needs to check nINT goes high after MCU clears
whether it initiated the &
nINT Pin ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT
fault-injection or not and ESM_MCU_RST_INT

MCU clears
ESM_MCU_FAIL_INT
ESM_MCU_FAIL_INT
0 1 0
(ESM_MCU_FAIL_MASK=0)
MCU clears
ESM_MCU_RST_INT
ESM_MCU_RST_INT
0 1 0
(ESM_MCU_RST_MASK=0)

ENABLE_DRV x 0 1 0 1
MCU sets ENABLE_DRV (only MCU sets ENABLE_DRV (only
possible when possible when
ESM_MCU_START=1) ESM_MCU_START=1)

Device State Warm

x ACTIVE or MCU_ONLY Reset ACTIVE or MCU_ONLY (same as previous)

0 t

Case Number 3b: ESM_MCU_DELAY2 > 0

An error event occurred in the MCU, and the MCU is unable to correct the error before elapse of the ESM_MCU_DELAY1 and ESM_MCU_DELAY2 time-intervals. Hence the PMIC resets the MCU

Figure 8-29. Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, ESM_MCU Input
Signal Recovers Too Late and MCU-Reset Occurs

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MCU Reset-Extension Time MCU Reset-Extension Time

nRSTOUT Pin
MCU sets MCU sets ESM_MCU_START
ESM_MCU_START after all interrupt bits are cleared

ESM_MCU_START x 0 1 0 1

tdegl_ESMx 15 s
tLOW_ERROR

ESM_MCU Input Pin

tdegl_ESMx 15 s tdegl_ESMx 15 s

Internally Deglitched
ESM_MCU Input Signal

tdegl_ESMx 15 s ESM_MCU_DELAY1 and

ESM_MCU_DELAY2
timers reset when ESM MCU clears
ESM_MCU_DELAY1 ESM_MCU_DELAY2 resets the MCU ESM_MCU_PIN_INT &
Deglitched ESM_MCU Input Signal = high

ESM_MCU_PIN_INT
0 1 0
(ESM_MCU_PIN__MASK=0)

nINT goes immediately low,

MCU needs to check nINT goes high after MCU clears
whether it initiated the &
nINT Pin ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT
fault-injection or not and ESM_MCU_RST_INT
MCU clears
ESM_MCU_FAIL_INT MCU clears
ESM_MCU_FAIL_INT
ESM_MCU_FAIL_INT
0 1 0 1 0
(ESM_MCU_FAIL_MASK=0)
MCU clears
ESM_MCU_RST_INT
ESM_MCU_RST_INT
0 1 0
(ESM_MCU_RST_MASK=0)

ENABLE_DRV x 0 1 0 1
MCU sets ENABLE_DRV (only MCU sets ENABLE_DRV (only
possible when possible when
ESM_MCU_START=1) ESM_MCU_START=1)

Device State Warm

x ACTIVE or MCU_ONLY Reset ACTIVE or MCU_ONLY (same as previous)

0 t

Case Number 3c: ESM_MCU_DELAY2 > 0

An error event occurred in the MCU, the MCU recovers and clears ESM_MCU_FAIL_INT, but fails to clear ESM_MCU_PIN_INT before elapse of the ESM_MCU_DELAY2 time-interval.
Hence the PMIC resets the MCU and sets ESM_FAIL_INT (if ESM_MCU_FAIL_MASK=0).

Figure 8-30. Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and ESM_MCU_ENDRV=1, MCU Fails to Clear
ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2

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8.3.11.1.2 PWM Mode

8.3.11.1.2.1 Good-Events and Bad-Events
In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as
follows:
• After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low
after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM detects a bad event and
the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold,
the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse
time-duration monitoring
• After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high
after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM detects a bad event and
the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold,
the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse
time-duration monitoring.
In addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the
deglitched signal of the related input pin nERR_MCU or nERR_SoC:
• A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is
configured in corresponding register bits ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0].
• A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is
configured in corresponding register bits ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0].
• A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is
configured in corresponding register bits ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0].
• A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is
configured in corresponding register bits ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0].
Each ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of
the related input pin nERR_MCU or nERR_SoC:
• A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a
high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or
• A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-
pulse duration within the minimum and maximum low-pulse time-thresholds
Register bits ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold
(tHIGH_MAX_TH) for the related ESM. Use Equation 13 and Equation 14 to calculate the worst-case values for the
tHIGH_MAX_TH:

Min. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95 (13)

Max. tHIGH_MAX_TH = (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05 (14)

, in which x stands for either MCU or SoC.

ESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for
the related ESM. Use Equation 15 and Equation 16 to calculate the worst-case values for the tHIGH_MIN_TH:

Min. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95 (15)

Max. tHIGH_MIN_TH = (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05 (16)

, in which x stands for either MCU or SoC.

ESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for
the related ESM. Use Equation 17 and Equation 18 to calculate the worst-case values for the tLOW_MAX_TH:

Min. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95 (17)

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Max. tLOW_MAX_TH = (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05 (18)

, in which x stands for either MCUor SoC.

ESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for
the related ESM. Use Equation 19 and Equation 20 to calculate the worst-case values for the tLOW_MIN_TH:

Min. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95 (19)

Max. tLOW_MIN_TH = (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05 (20)

, in which x stands for either MCU or SoC.

Please note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need
to be configured such that clock tolerances from the TPS6593-Q1 and from the processor are incorporated.
Equation 21, Equation 22, Equation 23, and Equation 24 are a guideline on how to incorporate these clock-
tolerances:

ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) (21)

ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) (22)

ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance) (23)

ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance) (24)

, in which x stands for either MCU or SoC.

8.3.11.1.2.2 ESM Error-Counter
If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits
ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits
ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1.
The device clears each ESM error counter when ESM_x_START=0. Furthermore, the device clears the error-
counter ESM_SOC_ERR[4:0] when it resets the SoC.
Each ESM error-counter has a related threshold (bits ESM_MCU_ERR_CNT_TH[3:0] or bits
ESM_SOC_ERR_CNT_TH[3:0]) that the MCU can configure if the related ESM_x_START bit is 0. If the ESM
error-counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and
starts the Error-Handling Procedure as described in Section 8.3.11.1. If the ESM error-counter reached a value
equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the
MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the
Error-Handling Procedure as described in Section 8.3.11.1. If the ESM-error persists such that the configured
delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the PFSM and the device clears the
ESM_x_START bit. After the PFSM completes the handling of the ESM_x_RST trigger, the device re-initializes
the related ESM.
8.3.11.1.2.3 ESM Start-Up in PWM Mode
After the MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two
possible scenarios:
1. The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In
this scenario, the related ESM starts the following procedure:
a. Start a timer with a time-length according the value configured in corresponding ESM_MCU_LMAX[7:0]
or ESM_SOC_LMAX[7:0].
b. Wait for a first rising edge on its deglitched input signal.
c. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and
starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as
described in Section 8.3.11.1.2.1. Figure 8-32 shows an example this scenario as Case Number 1.

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d. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or

ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter
with +2. Hereafter, the ESM detects good-events or bad-events as described in Section 8.3.11.1.2.1.
Figure 8-34 shows an example this scenario as Case Number 3.
e. If the ESM error-counter value is above its configured threshold, the related ESM has detected a
so-called ESM-error and starts the Error-Handling Procedure as described in Section 8.3.11.1.2.1.
f. During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates
the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling
Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which,
depending on the PFSM configuration, resets the MCU or SoC. Figure 8-35 shows a scenario in which
the device resets the MCU or SoC as Case Number 4.
g. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the
configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits,
the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in
Section 8.3.11.1.2.1.
2. The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this
scenario, the related ESM starts the following procedure:
a. Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0]
or ESM_SOC_HMAX[7:0].
b. Wait for a first falling edge on its deglitched input signal.
c. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and
starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as
described in Section 8.3.11.1.2.1. Figure 8-33 shows an example this scenario as Case Number 2.
d. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or
ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter
with +2. Hereafter, the ESM detects good-events or bad-events as described in Section 8.3.11.1.2.1.
e. If the ESM error-counter value is above its configured threshold, the related ESM has detected a
so-called ESM-error and starts the Error-Handling Procedure as described in Section 8.3.11.1.2.1.
f. During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates
the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling
Procedure reaches the step in which the ESM sends an ESM_x_RST trigger to the PFSM, which,
depending on the PFSM configuration, resets the MCU or SoC, as Case Number 4.
g. If the ESM error-counter reaches a value equal or less its configured threshold before the elapse of the
configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits,
the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in
Section 8.3.11.1.2.1.
8.3.11.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode
For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in Figure 8-31. In
this flow-chart, the _x stands for either _MCU or _SoC Figure 8-32, Figure 8-33, Figure 8-34, and Figure 8-35
show example waveforms for several error-cases for the ESM in PWM Mode. In this flow-chart, the _x stands for
either _MCU or _SoC

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Global Reset Conditions:

- Warm-Reset from Watchdog or ESM_x ESM_x-CONFIGURE NO
NO ESM_x NO
- Immediate or Orderly Shutdown - Device releases MCU/SoC reset pins - MCU/SoC reset inacve
- Device forces ENABLE_DRV= 0 ESM_x_EN YES - MCU can set ENABLE_DRV bit -
- Device Power-On-Reset ESM_x_START NO
- MCU clears all interrupt bits =0? nINT pin released ESM_x_EN
=1?
- Device releases nINT pin if no other interrupt bits are set (if no other interrupt bits are set) =0?
- ESM_x conguraon registers unlocked YES
START - MCU either clears ESM_x_EN, or
- no ESM_x interrupt bit set
1) MCU congures ESM in PWM-Mode + YES
Device locks all
ESM_x_H/L_MAX/MIN mes
ESM_x - Device stops
2) MCU con gures ESM_x_DELAY1, ESM_x_DELAY2 and YES
con gura on ESM_x_PWM Mode
ESM_x_EN=1 NO ESM_x_ENDRV
registers Procedure and ESM_x
? 3) MCU sets ESM_x_START
ESM_x_ PWM Error-Handling
YES START=1? NO Procedure
Note: the procedures „Check ESM_x_START=1", „ESM_x PWM Mode Procedure“ and „ESM_x Check - Device resets the
PWM Error-Handling Procedure“ run in parallel. If ESM_x_START=0, the device stops the ESM_x_START=1 ESM_x_DELAY1 and
„ESM_x PWM Mode Procedure“ and the „ESM_x PWM Error-Handling Procedure“ ESM_x_DELAY2 mers
- Device clears
ESM_x_START=0
- Device resets the ESM_x_ PWM Mode Procedure
ESM_x_DELAY1 YES
and ESM_x_DELAY2 NO NO
mers
ESM_x_ ESM_x ESM_x ESM_x_
LMAX time NO detects YES ESM_x pin detects
NO NO HMAX time
elapsed? Rising Edge level Falling Edge elapsed?
? = 0? ?
NO
YES - MCU/SoC reset inac ve YES
Reset-Extension ESM_x YES - MCU can set ENABLE_DRV bit YES ESM_x
me-interval PWM Error- - nINT pin released PWM Error-
elapsed? Device increase (if no other interrupt bits are set) Device increase
ESM_x Handling Handling ESM_x
- no ESM_x interrupt bit set
Error-Counter Procedure Procedure Error-Counter
with +2 with +2

NO NO

ESM_x_ ESM_x ESM_x ESM_x_

YES detects detects YES
HMAX time NO NO LMAX time
elapsed? Falling Edge Rising Edge elapsed?
? ?
Device increase Device increase
ESM_x
YES YES ESM_x
Error-Counter Error-Counter
with +2 with +2
ESM_x_ ESM_x_
Device increase NO HMIN time LMIN time Device increase
NO
ESM_x ESM_x
Error-Counter
elapsed? elapsed? Error-Counter
with +2 with +2
YES YES

ESM_x PWM Error- ESM_x PWM Error-

Handling Procedure Handling Procedure
Device decrease
ESM_x
NO Error-Counter NO
with -1

ESM_x_ ESM_x ESM_x ESM_x_

LMAX time NO detects detects NO HMAX time
elapsed? Rising Edge Falling Edge elapsed?
? ?
Device decrease
YES ESM_x YES
Error-Counter
Device increase ESM_x with -1
Device increase ESM_x
Error-Counter with +2
YES YES Error-Counter with +2

ESM_x PWM Error- ESM_x PWM Error-

Handling Procedure Handling Procedure
ESM_x_ ESM_x_
Device increase ESM_x NO LMIN time HMIN time NO Device increase ESM_x
Error-Counter with +2 Error-Counter with +2
elapsed? elapsed?

YES YES
ESM_x PWM Error- ESM_x PWM Error-
Handling Procedure Handling Procedure

ESM_x PWM Error-Handling Procedure

NO
Note: until step ESM_x-RESET, the
ESM_x_PWM Mode Procedure runs
ESM_x-INTERRUPT ESM_x
in parallel - If ESM_x_PIN_MASK=0, device sets Error-Counter Conguraon
ESM_x_DELAY1
ESM_x_PIN_INT interrupt bit and pulls nINT Threshold & NO YES bit YES
me-interval
ESM_x pin low ESM_x_PIN_INT= ESM_x_ENDRV
elapsed?
START Error-Counter YES - Device starts ESM_x_DELAY1 mer, or 0? =1?
>Threshold connues to run this mer if already started
- Device does not change ENABLE_DRV bit NO Device forces
- Device does not change the level of the YES ENABLE_DRV= 0
NO MCU/SoC reset pins

- Device releases nINT pin if

END all interrupt bits are cleared ESM_x_DELAY2 YES
- ESM resets ESM_x_DELAY1 YES set to 0?
and ESM_x_DELAY2 mers
NO
ESM_x-RESET ESM_x
If ESM_x_RST_MASK=0: - If ESM_x_FAIL_MASK=0, Error-Counter
- ESM_x_RST trigger send device sets ESM_x_FAIL_INT ESM_x_DELAY2 < Threshold & - If ESM_x_FAIL_MASK=0, device sets
YES NO ESM_x_FAIL_INT interrupt bit and pulls nINT pin
to to FSM interrupt bit and pulls nINT me-interval ESM_x_PIN_INT=0 &
- device sets pin low elapsed? ESM_x_FAIL_INT low
ESM_x_RST_INT interrupt =0? - Device starts ESM_x_DELAY2 mer, or connues
bit and pulls nINT pin low to run this mer if already started
NO

Figure 8-31. Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode

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Reset-Extension Time

nRSTOUT /
nRSTOUT_SoC Pin

MCU sets ESM_x_START

x 0 1
ESM_x_START

tdegl_ESMx 15 s

tHIGH_MAX_TH = tHIGH_MAX_TH =
(ESM_x_HMAX [7:0] + 1) × 15 s (ESM_x_HMAX [7:0] + 1) × 15 s

tHIGH_MIN_TH = tHIGH_MIN_TH =
(ESM_x_HMIN [7:0] + 1) (ESM_x_HMIN [7:0] + 1)
× 15 s × 15 s

tLOW_MAX_TH = tLOW_MAX_TH = tLOW_MAX_TH =

(ESM_x_LMAX[7:0] + 1) × 15 s (ESM_x_LMAX[7:0] + 1) × 15 s (ESM_x_LMAX[7:0] + 1) × 15 s

tLOW_MIN_TH = tLOW_MIN_TH =
(ESM_x_LMIN[7:0] + 1) × 15 s (ESM_x_LMIN[7:0] + 1) × 15 s

High-Pulse Timer High-Pulse Timer

Low-Pulse Timer Stopped, Stopped,
Reset and Low-Pulse Timer Low-Pulse Timer
Deglitched ESM_x Started Reset and Started Reset and Started
Low-Pulse Timer Low-Pulse Timer Low-Pulse Timer
Input Signal Stopped, Stopped, Stopped,
High-Pulse Timer High-Pulse Timer High-Pulse Timer
no bad event trigger as Reset and Started Reset and Started Reset and Started
long as rising edge on tPWM_HIGH tPWM_LOW tPWM_HIGH tPWM_LOW
ESM_x signal comes
before elapse of
tLOW_MAX_TH 1 ESM_x good-event 1 ESM_x good-event

Internal ESM_x
bad event Trigger

Internal ESM_x
good event Trigger

ESM_x_ERR_CNT[4:0] x 00000

ESM_x_PIN_INT
(ESM_x_PIN_MASK=0) 0

nINT Pin

ESM_x_FAIL_INT
0
(ESM_x_FAIL_MASK=0)

ESM_x_RST_INT
0
(ESM_x_RST_MASK=0)

ENABLE_DRV
x 0 1

MCU sets ENABLE_DRV (ESM_MCU, only possible if

ESM_MCU_START=1. ESM_SOC possible if ESM_SOC_ENDRV=0
or if ESM_SOC_ENDRV=1 and ESM_SOC_START=1)

Case Number 1:
PWM signal has a low level at the moment the MCU sets bit ESM_x_start, and the PMIC receives a PWM Error Signal with Correct Timing afterwards

Figure 8-32. Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at Deglitched Input signal, and Receives
Correct PWM Signal Afterwards. (The _x stand for _MCU or _SoC)

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Reset-Extension Time

nRSTOUT /
nRSTOUT_SoC Pin

MCU sets ESM_x_START

x 0 1
ESM_x_START

tdegl_ESMx 15 s

tHIGH_MAX_TH = tHIGH_MAX_TH = tHIGH_MAX_TH =

(ESM_x_HMAX [7:0] + 1) × 15 s (ESM_x_HMAX [7:0] + 1) × 15 s (ESM_x_HMAX [7:0] + 1) × 15 s

tHIGH_MIN_TH = tHIGH_MIN_TH =
(ESM_x_HMIN [7:0] + 1) (ESM_x_HMIN [7:0] + 1)
× 15 s × 15 s

tLOW_MAX_TH = tLOW_MAX_TH =
(ESM_x_LMAX[7:0] + 1) × 15 s (ESM_x_LMAX[7:0] + 1) × 15 s

tLOW_MIN_TH = tLOW_MIN_TH =
(ESM_x_LMIN[7:0] + 1) × 15 s (ESM_x_LMIN[7:0] + 1) × 15 s
High-Pulse Timer
Reset and Started High-Pulse Timer High-Pulse Timer High-Pulse Timer
Stopped, Stopped, Stopped,
Deglitched ESM_x Low-Pulse Timer Low-Pulse Timer Low-Pulse Timer
Input Signal Reset and Started Low-Pulse Timer Reset and Started Low-Pulse Timer Reset and Started
Stopped, Stopped,
High-Pulse Timer High-Pulse Timer
no bad event trigger as Reset and Started Reset and Started
long as falling edge on tPWM_LOW tPWM_HIGH tPWM_LOW tPWM_HIGH
ESM_x signal comes
before elapse of
tHIGH_MAX_TH 1 ESM_x good-event 1 ESM_x good-event

Internal ESM_x
bad event Trigger

Internal ESM_x
good event Trigger

ESM_x_ERR_CNT[4:0] x 00000

ESM_x_PIN_INT
0
(ESM_x_PIN_MASK=0)

nINT Pin

ESM_x_FAIL_INT
(ESM_x_FAIL_MASK=0) 0

ESM_x_RST_INT
0
(ESM_x_RST_MASK=0)

ENABLE_DRV x 0 1

MCU sets ENABLE_DRV (ESM_MCU, only possible if

ESM_MCU_START=1. ESM_SOC possible if ESM_SOC_ENDRV=0
or if ESM_SOC_ENDRV=1 and ESM_SOC_START=1)

Case Number 2:
PWM signal has a high level at the moment the MCU sets bit ESM_x_start, and the PMIC receives a PWM Error Signal with Correct Timing afterwards

Figure 8-33. Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at Deglitched Input Signal, and Receives
Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC)

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Reset-Extension Time
nRSTOUT /
nRSTOUT_SoC Pin
MCU sets ESM_x_START

ESM_x_START x 0 1

tdegl_ESMx 15 s
tHIGH_MAX_TH = tHIGH_MAX_TH = tHIGH_MAX_TH =
(ESM_x_HMAX [7:0] + 1) × (ESM_x_HMAX [7:0] + 1) × (ESM_x_HMAX [7:0] + 1) ×
15 s 15 s 15 s

tHIGH_MIN_TH = tHIGH_MIN_TH = tHIGH_MIN_TH =

(ESM_x_HMIN (ESM_x_HMIN (ESM_x_HMIN
[7:0] + 1) × 15 s [7:0] + 1) × 15 s [7:0] + 1) × 15 s

tLOW_MAX_TH = tLOW_MAX_TH = tLOW_MAX_TH = tLOW_MAX_TH = tLOW_MAX_TH =

(ESM_x_LMAX[7:0] + 1) (ESM_x_LMAX[7:0] + 1) (ESM_x_LMAX[7:0] + 1) (ESM_x_LMAX[7:0] + 1) (ESM_x_LMAX[7:0] + 1)
× 15 s × 15 s × 15 s × 15 s × 15 s

tLOW_MIN_TH = tLOW_MIN_TH = tLOW_MIN_TH =

(ESM_x_LMIN[7:0] (ESM_x_LMIN[7:0] (ESM_x_LMIN[7:0]
+ 1) × 15 s + 1) × 15 s + 1) × 15 s

Deglitched ESM_x
Input Signal

tPWM_HIGH tPWM_LOW tPWM_HIGH tPWM_LOW tPWM_HIGH tPWM_LOW

1 ESM_x good event 1 ESM_x good event 1 ESM_x good event

Internal ESM_x bad

event Trigger
Internal ESM_x good
event Trigger

ESM_x_ERR_CNT[4:0] x 00000 00010 00001 00000 00000

ESM_x_ERR_CNT_
TH[3:0] = 0001 ESM_x_DELAY1 ESM_x_DELAY2 ESM_x_DELAY1 and
ESM_x_DELAY2 timers reset after
MCU clears ESM_x_PIN_INT & MCU clears ESM_x_PIN_INT and
ESM_x_ERR_CNT[4:0] ” ESM_x_FAIL_INT
ESM_x_ERR_CNT_TH[3:0]
ESM_x_PIN_INT 0 1 0

nINT Pin &

MCU clears
ESM_x_FAIL_INT
ESM_x_FAIL_INT 0 1 0

ESM_x_RST_INT 0

ENABLE_DRV x 0 1 0 1
MCU sets ENABLE_DRV (ESM_MCU, only possible if Note: PMIC clears ENABLE_DRV MCU sets ENABLE_DRV (ESM_MCU,
ESM_MCU_START=1. ESM_SOC possible if ESM_SOC_ENDRV=0 only possible if ESM_MCU_START=1.
only when configuration bit ESM_SOC possible if
or if ESM_SOC_ENDRV=1 and ESM_SOC_START=1)
ESM_x_ENDRV=1 ESM_SOC_ENDRV=0 or if
ESM_SOC_ENDRV=1 and
ESM_SOC_START=1)

Case Number 3: ESM_DELAY2 > 0

PWM signal has a low level at the moment the MCU sets bit ESM_x_start, but the PMIC receives the PWM Error Signal too late. Afterwards PWM Error Signal recovers with Correct Timing and
ESM_x_ERR_CNT[4:0] reaches a value less than the configured ESM_x_ERR_CNT_TH[3:0] before elapse of the ESM_x_DELAY2 time-interval

Figure 8-34. Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at Deglitched Input Signal, but Receives
Too Late a Correct PWM Signal Afterwards (The _x stand for _MCU or _SoC)

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Reset-Extension
Reset-Extension Time
Time
nRSTOUT /
nRSTOUT_SoC Pin MCU sets
ESM_x_START after all
MCU sets ESM_x_START interrupt bits are cleared

ESM_x_START x 0 1 0 1

tdegl_ESMx 15 s tdegl_ESMx 15 s

tHIGH_MAX_TH = tHIGH_MAX_TH = tHIGH_MAX_TH = tHIGH_MAX_TH =

(ESM_x_HMAX (ESM_x_HMAX (ESM_x_HMAX (ESM_x_HMAX
[7:0] + 1) × 15 s [7:0] + 1) × 15 s[7:0] + 1) × 15 s [7:0] + 1) × 15 s
tHIGH_MIN_TH = tHIGH_MIN_TH = tHIGH_MIN_TH = tHIGH_MIN_TH =
(ESM_x_ (ESM_x_ (ESM_x_ (ESM_x_
HMIN [7:0] + HMIN [7:0] + HMIN [7:0] + HMIN [7:0] +
1) x 15 s 1) x 15 s 1) x 15 s 1) × 15 s
tLOW_MAX_TH = tLOW_MAX_TH = tLOW_MAX_TH = tLOW_MAX_TH = tLOW_MAX_TH = tLOW_MAX_TH =
(ESM_x_LMAX[7:0] + 1) (ESM_x_LMAX[7:0] + 1) (ESM_x_LMAX[7:0] + 1) (ESM_x_LMAX[7:0] + 1) (ESM_x_LMAX[7:0] + 1) (ESM_x_LMAX[7:0]
× 15 s × 15 s × 15 s × 15 s × 15 s + 1) × 15 s

tLOW_MIN_TH = tLOW_MIN_TH = tLOW_MIN_TH = tLOW_MIN_TH =

Deglitched ESM_x (ESM_x_LMIN[7: (ESM_x_LMIN[7: (ESM_x_LMIN[7: (ESM_x_LMIN[7:
Input Signal 0] + 1) × 15 s 0] + 1) × 15 s 0] + 1) × 15 s 0] + 1) × 15 s

tPWM_HIGH tPWM_LOW tPWM_HIGH tPWM_LOW tPWM_HIGH tPWM_LOW tPWM_HIGH tPWM_LOW

1 ESM_x good event 1 ESM_x good event

Internal ESM_x bad

event Trigger

Internal ESM_x good

event Trigger

ESM_x_ERR_
CNT[4:0] x 00000 00010 00100 00110 00101 00000
ESM_x_ERR_CNT_ ESM_x_DELAY1 and ESM_x_DELAY2 timers
TH[3:0] = 0011 ESM_x_DELAY1 ESM_x_DELAY2 reset when ESM_x resets the MCU or SoC
MCU clears ESM_x_PIN_INT &
ESM_x_ERR_CNT[4:0] ”
ESM_x_ERR_CNT_TH[3:0]
ESM_x_PIN_INT
0 1 0
(ESM_x_PIN_MASK
=0)
&
nINT Pin
MCU clears
ESM_x_FAIL_INT ESM_x_FAIL_INT
(ESM_x_FAIL_MASK 0 1 0
=0) MCU clears
ESM_x_RST_INT
ESM_x_RST_INT
(ESM_x_RST_MASK 0 1 0
=0)
ENABLE_DRV x 0 1 0 1

MCU sets ENABLE_DRV (ESM_MCU, only possible if

ESM_MCU_START=1. ESM_SOC possible if
Note: PMIC clears ENABLE_DRV MCU sets ENABLE_DRV (ESM_MCU, only
ESM_SOC_ENDRV=0 or if ESM_SOC_ENDRV=1 and only when configuration bit possible if ESM_MCU_START=1. ESM_SOC
ESM_SOC_START=1) ESM_x_ENDRV=1 possible if ESM_SOC_ENDRV=0 or if
ESM_SOC_ENDRV=1 and ESM_SOC_START=1)

Case Number 4: _DELAY2 > 0

PWM signal has an error after start-up, and the ESM_x_ERR_CNT[4:0] > ESM_x_ERR_CNT_TH[3:0] during the elapse of ESM_x_DELAY1 and ESM_x_DELAY2. Hence the PMIC
pulls the nRSTOUT / nRSOUT_SoC pin low, and releases this pin after the reset-extension time. After this, MCU clears all errors and restarts the ESM_x

Figure 8-35. Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level at Deglitched Input Signal and Receives a
Correct PWM Signal. Afterwards the ESM Detects Bad Events, and the PWM Signal Recovers Too Late which Leads to an ESM_x Reset Trigger
to the PFSM (The _x stand for _MCU or _SoC)

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8.4 Device Functional Modes

8.4.1 Device State Machine
The TPS6593-Q1 device integrates a finite state machine (FSM) engine that manages the state of the device
during operating state transitions. The device supports NVM-configurable mission states with configurable input
triggers for transitions between states. Any resources, including the 5 BUCK regulators, 4 LDO regulators, and
all of the digital IO pins including the 11 GPIO pins on the device can be controlled during power sequencing.
When a resource is not controlled or configured through a power sequence, the resource is left in the default
state as pre-configured by the NVM.
Each resource can be pre-configured through the NVM configuration, or re-configured through register bits.
Therefore, the user can statically control the resource through the control interfaces (I2C or SPI), or the FSM can
automatically control the resource during state sequences.
The FSM is powered by an internal LDO that is automatically enabled when VCCA supply is available to the
device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper
operation of all the power resources as well as the control interface and device IOs.
There are three parts of the FSM that control the operational modes of the TPS6593-Q1 device:
• Fixed Device Power Finite State Machine (FFSM)
• Pre-configurable Finite State Machine (PFSM) for Mission States (ACTIVE, MCU_ONLY, S2R,
DEEP_SLEEP)
• Error Handling Operations
The PFSM provides configurable rail and voltage monitoring sequencing utilizing instructions in configuration
memory. This flexibility enables customers to alter power-up sequences on a platform basis. The FFSM handles
the majority of fixed functionality that is internally mandated and common to all platforms.
8.4.1.1 Fixed Device Power FSM
The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails
are fully enabled and ready to power external loadings, and the power down of the device when in the event of
insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device
Powers states, the ENABLE_DRV bit remains low.
The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured.
Following are the definitions of the Device Power states:
NO SUPPLY The device is not powered by a valid energy source on the system power rail. The device is
completely powered off.
BACKUP (RTC The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO);
backup a backup power source, however, is present and is within the operating range of the
battery) LDOVRTC. The RTC clock counter remains active in this state if it has been previously
activated by appropriate register enable bit. The calendar function of the RTC block is
activated, but not accessible in this state. Customer has the option to enable the shelf mode
by disconnecting the VCCA supply completely, even while the backup battery is connected to
the VBACKUP pin. The shelf mode forces the device to skip the BACKUP state and enters the
NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup
battery.
LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or
an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC
clock counter and the RTC Alarm or Timer Wake-up functions are active if they have been
previously activated by appropriate register enable bit. Low Power Wake-up input monitor in
the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on
request monitors are also enabled in this state. When a logic level transition from high-to-low
or low-to-high with a minimum pulse length of tLP_WKUP is detected on the assigned LP_WKUP
pin, or if the device detects a valid on-request or a wake-up signal from the RTC block, the

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device proceeds to power up the device and reach the default mission state. More details
regarding the LP_WAKE function can be found in Section 8.4.1.2.4.5.
INIT The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If
the device was previously in LP_STANDBY state, it has received an external wake-up signal
at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from
the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC
reads its internal NVM memory in this state and configures default values to registers, IO
configuration and FSM accordingly.
BOOT BIST The device is running the built-in self-test routine that includes

Note
The ABIST on the voltage monitor circuits for the BUCK regulators, the LDO
regulators is performed after the start-up of these regulators. The ABIST on the
VMON1 and VMON2 is performed after these voltage monitors are enabled. See
Voltage Monitors.

An option is available to shorten the device power up time from the NO_SUPPLY state by
setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also set the
FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY state. When
the device arrives at this state from the SAFE_RECOVERY state, LBIST is automatically
skipped if it has not previously failed. If LBIST failed, but passed after multiple re-tries before
exceeding the recovery counter limit, the device powers up normally. The following NVM bits
are pre-configured options to enable or disable parts of the CRC tests if further sequence time
reduction is required (please refer to the user's guide of the orderable part number):
• REG_CRC_EN = '0': disables the register map and SRAM CRC check

Note
Note: the BIST tests are executed as parallel processes, and the longest process
determines the total BIST duration

Note
the ABIST on the voltage monitor circuits of the BUCKx regulator, LDOn regulators,
VMON1 and VMON2 is performed individually after these voltage monitors are
enabled. See Voltage Monitors)

RUNTIME BIST A request was received from the MCU to exercise a run-time built-in self-test
(RUNTIME_BIST) on the device. No rails are modified and all external signals, including
all I2C or SPI interface communications, are ignored during the RUNTIME_ BIST. During the
RUNTIME_BIST, the device performs the same self-test routines as listed for the BOOT_BIST
state. Furthermore, during RUNTIME_BIST the device performs the ABIST routine on all
enabled voltage monitor circuits.
If the device passed BIST, it resumes the previous operation. If the device failed BIST, it shuts
down all of the regulator outputs and proceed to the SAFE RECOVERY state. In order to
avoid a register CRC error, all register writes must be avoided after the request for the BIST
operation until the device pulls the nINT pin low to indicate the completion of BIST. The results
of the RUNTIME_BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT interrupt
bits.

Note
After completion of the RUNTIME_BIST, the LDOx_UV detections are masked for
a time-interval equal to the configured LDOx ramp-up time (25 mV/μs or 3 mV/μs
according configuration bit LDOx_SLOW_RAMP). The actual LDOx output voltages
are not affected by this masking of the LDOx_UV detections.

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SAFE The device meets the qualified error condition for immediate or ordered shutdown request.
RECOVERY If the error is recovered within the recovery time interval or meets the restart condition, the
device increments the recovery counter, and returns to INIT state if the recovery counter value
does not exceed the threshold value. Until a supply power cycle occurs, the device stays in
the SAFE RECOVERY state if one of the following conditions occur:
• the recovery counter exceeds the threshold value
• the die temperature cannot be reduced to less than TWARN level
• VCCA stays above OVP threshold

When multiple system conditions occur simultaneously that demand power state arbitration, the device goes to
the higher priority state according to the following priority order:
1. NO SUPPLY
2. BACKUP
3. SAFE_RECOVERY
4. LP_STANDBY
5. MISSION STATES
Figure 8-36 shows the power transition states of the FSM engine.

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NO
SUPPLY
LDOVRTC UVLO Condion or
Shelf Mode enabled

VCCA < VCCA_UVLO

BACKUP or LDOVINT UVLO Condion All States
Except NO SUPPLY

VCCA > VCCA_UV

LP STANDBY
VCCA > VCCA_UV

LP_STANDBY_SEL = 1 and
Valid WAKE Request1
no valid WAKE request1

INIT

All States Error recovered or INIT done and O request and

Recovery meets restart condi on no error detected LP_STANDBY_SEL = 1
counter exceeded

Thermal Shutdown or
VCCA OVP
Error Condions
SAFE BOOT
(recovery cnt +1)
RECOVERY BIST

BOOT BIST error

(recovery cnt +1)

Orderly shutdown
Condion
(recovery cnt +1) BOOT BIST success

Severe or Moderate
PFSM Errors
(recovery cnt +1)

Mission States

RUNTIME BIST complete RUNTIME BIST request

RUNTIME
BIST

1
A valid WAKE request consist of:
nPWRON/ENABLE on request detecon if the device arrived the LP_STANDBY state through
the long key-press of the nPWRON pin or by disabling the ENABLE pin, or
RTC Alarm, RTC Timer, LP_WKUP1 or LP_WKUP2 detecon if the device arrived the
LP_STANDBY state through wring to a TRIGGER_I2C_0 bit.
Figure 8-36. State Diagram for Device Power States

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8.4.1.1.1 Register Resets and NVM Read at INIT State

Several registers inside the TPS6593-Q1 have pre-configured default values that are stored in the NVM of the
TPS6593-Q1. These registers are referred to as NVM pre-configured registers.
When the device transitions from the LP_STANDBY or the SAFE_RECOVERY to the INIT state, based on
FIRST_STARTUP_DONE bit, the registers are reset and the NVM is read. When the FIRST_STARTUP_DONE
is '0', registers which are not in the RTC domain are reset, and all of the NVM pre-configured registers including
the ones in the RTC domain, are loaded from the NVM. When the FIRST_STARTUP_DONE bit is set to
'1', typically after the initial power up from a supply power cycle, the registers in the RTC domain are not
reset, and the NVM pre-configured registers in the RTC domain are not re-loaded from the NVM. Setting the
FIRST_STARTUP_DONE bit prevents the control and status bits stored in the RTC domain registers from being
over written.
Table 8-11. Register resets and NVM read at INIT state
Registers without NVM
FIRST NVM pre-configured Other NVM pre-configured Registers without
pre-configuration in RTC
_STARTUP_DONE registers in RTC Domain registers NVM pre-configuration
Domain
Reset and defaults read
0 Defaults read from NVM No changes Reset
from NVM
Reset and defaults read
1 No changes No changes Reset
from NVM

Below are the NVM pre-configured register bits in the RTC domain:
• GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits
• GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits
• NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits
• FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits
• STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits
• PFSM_DELAYn, and RTC_SPARE_n bits
Below are the register bits without NVM pre-configuration in the RTC domain:
• FIRST_STARTUP_DONE bit
• SCRATCH_PAD_n bits
• All of RTC control and configuration registers
8.4.1.2 Pre-Configurable Mission States
When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine
(PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and
the operation states that together form the configurable sub state machine within the scope of mission states.
This sub state machine can be used to control and sequence the different voltage outputs as well as any
GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the
capacity to supply the processor and other platform modules depending on the power rail configuration. The
definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike
the user registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the
PMIC determines that a transition to another operation state is necessary, it reads the configuration memory to
determine what sequencing is needed for the state transition. Furthermore, the PFSM has four storage registers,
further referred to as PFSM storage registers (R0-3).
Table 8-15 shows how the trigger signals for each state transition can come from a variety of interface or GPIO
inputs, or potential error sources. Figure 8-37 shows how the device processes all of the possible error sources
inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be
handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error,
and so forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry
and exit condition for each configured mission state.

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All Potential Error (Interrupt) Sources

INTERRUPT
First level mask to filter out non-error interrupts vs. interrupts which require error handling
is given

VCCA BUCK1 BUCK2 BUCK3 BUCK4 BUCK5 LDO1 LDO2 LDO3 LDO4
Recovery Counter Limit to FSM
OR WD error to FSM
function Severe Global
Error
MCU Rail Group SoC Error Monitor to FSM
Mask Moderate Global
SoC Rail Group Error MCU Error Monitor to FSM

Other Rail Group

IMMEDIATE
SHUTDOWN trigger
Immediate Shutdown Trigger Mask
input to FSM
ORDERLY
SHUTDOWN trigger Orderly Shutdown Trigger Mask
input to FSM
MCU Power
MCU Power Error Trigger Mask
Error Signal

SoC Power
SoC Power Error Trigger Mask
Error Signal

Figure 8-37. Error Source Hierarchical Mask System

Figure 8-39 shows an example of how the PFSM engine utilizes instructions to execute the configured device
state and sequence transitions of the mission state-machine. Table 8-12 provides the instruction set and usage
description of each instruction in the following sections. Section 8.4.1.2.2 describes how the instructions are
stored in the NVM memory.
Table 8-12. PFSM Instruction set
Command Opcode Command Command Description
Write the specified data, except the masked bits, to the specified
"0000" REG_WRITE_MASK_PAGE0_IMM
page 0 register address.
"0001" REG_WRITE_IMM Write the specified data to the specified register address.
Write the specified data, except the masked bits, to the specified
"0010" REG_WRITE_MASK_IMM
register address.
Write the target voltage of a specified regulator after a specified
"0011" REG_WRITE_VOUT_IMM
delay.
Write the operation mode of a specified regulator after a specified
"0100" REG_WRITE_VCTRL_IMM
delay.
Write the data from PFSM storage register (R0-3), except the
"0101" REG_WRITE_MASK_SREG
masked bits, to the specified register address.
Write PFSM storage register (R0-3) with data from a specified
"0110" SREG_READ_REG
address.
Execution is paused until the specified type of the condition is met
"0111" WAIT
or timed out.
"1000" DELAY_IMM Delay the execution by a specified time.
Delay the execution by a time value stored in the specified PFSM
"1001" DELAY_SREG
storage register (R0-3).
Set a trigger destination address for a given input signal or
"1010" TRIG_SET
condition.
"1011" TRIG_MASK Sets a trigger mask that determines which triggers are active.
"1100" END Mark the final instruction in a sequential task.
Write the specified data to the BIT_SEL location of the specified
"1101" REG_WRITE_BIT_PAGE0_IMM
page 0 register address.
Write the specified data to the SHIFT location of the specified
"1110" REG_WRITE_WIN_PAGE0_IMM
page 0 register address.

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Table 8-12. PFSM Instruction set (continued)

Command Opcode Command Command Description
"1111" SREG_WRITE_IMM Write the specified data to the PFSM storage register (R0-3).

8.4.1.2.1 PFSM Commands

Following section describes each PFSM command in detail and provides example usage codes. More
information on example NVM configuration, available device options and documentations can be found at Fully
Customizable Integrated Power.
8.4.1.2.1.1 REG_WRITE_IMM Command
Description: Write the specified data to the specified register address
Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data>
Address and Data can be in any literal integer format (decimal, hex, and so forth).
'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order.
Examples:
• REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D
• REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10
• REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10
8.4.1.2.1.2 REG_WRITE_MASK_IMM Command
Description: Write the specified data, except the masked bits, to the specified register address
Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask>
Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth).
'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order.
Examples:
• REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address
0x1D
• REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the
register at address 0x10
• REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the
register at address 0x10
8.4.1.2.1.3 REG_WRITE_MASK_PAGE0_IMM Command
Description: Write the specified data, except the masked bits, to the specified page 0 register address
Assembly command: REG_WRITE_MASK_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data>
[MASK=]<Mask>
Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth).
'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order.
Examples:
• REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at
address 0x1D
• REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4
bits of the register at address 0x10
• REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4
bits of the register at address 0x10
8.4.1.2.1.4 REG_WRITE_BIT_PAGE0_IMM Command
Description: Write the specified data to the BIT_SEL location of the specified page 0 register address

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Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data>

Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth).
'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order.
Examples:
• REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D
• REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address
0x10
8.4.1.2.1.5 REG_WRITE_WIN_PAGE0_IMM Command
Description: Write the specified data to the SHIFT location of the specified page 0 register address
Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask>
[SHIFT=]<Shift>
Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth).
'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order.
Examples:
• REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10
to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. These two bits are then left shifted
2 bit-positions to give full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10.
8.4.1.2.1.6 REG_WRITE_VOUT_IMM Command
Description: Write the target voltage of a specified regulator after a specified delay. This command is a spin-off of
the REG_WRITE_IMM command with the intention to save instruction bits.
Assembly command: REG_WRITE_VOUT_IMM [REGULATOR=]<Regulator ID> [SEL=]<VSEL>
[VOUT=]<Vout> [DELAY=]<Delay>[BYPASS=]<BYPASS>
'REGULATOR=', ''SEL=', 'VOUT=', 'DELAY=' and 'BYPASS=' are syntax options. When included, the parameters
can be in any order.
Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4.
VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command writes to if Regulator ID is
BUCK1-5. VSEL is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3':
Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored.
VOUT = output voltage in mV or V. Unit must be listed.
DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between
0-63, which becomes the threshold count for the counter running a step size specified in the register
PFSM_DELAY_STEP. The delay value is rounded to the nearest achievable delay time based on the current
step size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous
command in the same sequence. Assembler reports an error if the step size is too large or too small to meet the
delay.
BYPASS selects whether the selected LDO needs to operate in linear mode (BYPASS=0) or bypass mode
(BYPASS=1)
Examples:
• REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active
BUCK3_VSET register after 100 µs
• REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms BYPASS=0 — Sets
LDO1 to 700 mV in linear mode after 6 ms.
• REG_WRITE_VOUT_IMM REGULATOR=LDO2 SEL=0 VOUT=3.3V DELAY=0 ms BYPASS=1 — Sets
LDO2 to 3.3VV in bypass mode after 0 ms

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8.4.1.2.1.7 REG_WRITE_VCTRL_IMM Command

Description: Write the operation mode of a specified regulator after a specified delay. This command is a spin-off
of the REG_WRITE_IMM command with the intention to save instruction bits.
Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL>
[MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode>
'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any
order.
Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4.
VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields:
• BUCKs: BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn _FPWM_MP, BUCKn_FPWM, and
BUCKn_EN
• LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN
DELAY = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between
0-63, which becomes the threshold count for the counter running a step size specified in the register
PFSM_DELAY_STEP. Delay value is be rounded to the nearest achievable delay time based on the current step
size. Current step size is based on the default NVM setting or a SET_DELAY value from a previous command in
the same sequence. Assembler reports an error if the step size is too large or too small to meet the delay.
Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches)
MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always)
Examples:
• REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000)
after 100 µs
• REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set
LDO1_VMON and LDO1_EN to '1' after 10 ms
8.4.1.2.1.8 REG_WRITE_MASK_SREG Command
Description: Write the data from a PFSM storage register, except the masked bits, to the specified register
address
Assembly command: REG_WRITE_MASK_SREG [REG=]<PFSM Storage Register> [ADDR=]<Address>
[MASK=]<Mask>
'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order.
PFSM Storage Register can be R0, R1, R2, or R3.
Address and Mask can be in any literal integer format (decimal, hex, and so forth).
Examples:
• REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of PFSM storage register R2 to address
0x22
• REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of PFSM storage
register R0 to address 0x54
8.4.1.2.1.9 SREG_READ_REG Command
Description: Write PFSM storage register (R0-3) with data from a specified address
Assembly command: SREG_READ_REG [REG=]<PFSM Storage Register> [ADDR=]<Address>
'REG=' and 'ADDR=' are options. When included, the parameters can be in any order.
PFSM Storage Register can be R0, R1, R2, or R3.
Address can be in any literal integer format (decimal, hex, and so forth).
Examples:

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• SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to PFSM storage
register R2
• SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to
PFSM storage register R3
8.4.1.2.1.10 SREG_WRITE_IMM Command
Description: Write the specified data to the scratch register (R0-3)
Assembly command: SREG_WRITE_IMM [REG=]<PFSM Storage Register> [DATA=]<Data>
Data can be in any literal integer format (decimal, hex, and so forth).
PFSM Storage Register can be R0, R1, R2, or R3.
'REG=' and 'DATA=' are options. When included, the parameters can be in any order.
Examples:
• SREG_WRITE_IMM R2 0x15 — Write 0x15 to PFSM storage register R2
• SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to PFSM storage register R3
8.4.1.2.1.11 WAIT Command
Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is
met or timed out
Assembly command: WAIT [COND=]<Condition> [TYPE=]<Type> [TIMEOUT=]<Timeout>
[DEST=]<Destination>
Alternative assembly command: JUMP [DEST=]<Destination>
'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order.
Condition are listed in Table 8-13. Examples: GPIO1, BUCK1_PG, I2C_1
Type = LOW, HIGH, RISE, or FALL
Timeout = timeout value in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between
0-63. Timeout value is be rounded to the nearest achievable time based on the current step size. Current
step size is based on the default NVM setting or a SET_DELAY value from a previous command in the same
sequence. Assembler reports an error if the step size is too large or too small to meet the delay.
Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory.
Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1'
indicates the destination address is external and represents a FSM state ID.
When using the jump command, the PFSM performs an unconditional jump. The command is be compiled
as "WAIT COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so
the condition is never satisfied and hence always times out. Therefore this command always jumps to the
destination.
Examples:
• WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address
when a rise edge is detected at GPIO4, or after 1 second
• WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the
commands at <mcu2act_seq> address as soon as BUCK1 output is within power-good range, or after 500 µs
Table 8-13. WAIT Command Conditions
COND_ Condition Name COND_ Condition Name COND_ Condition Name COND_ Condition Name
SEL SEL SEL SEL
0 GPIO1(1) 16 LDO1_PG 32 I2C_0(2) 48 LP_STANDBY_SEL
1 GPIO2(1) 17 LDO2_PG 33 I2C_1(2) 49 N/A
2 GPIO3(1) 18 LDO3_PG 34 I2C_2(2) 50 N/A

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Table 8-13. WAIT Command Conditions (continued)

COND_ Condition Name COND_ Condition Name COND_ Condition Name COND_ Condition Name
SEL SEL SEL SEL
3 GPIO4(1) 19 LDO4_PG 35 I2C_3(2) 51 N/A
4 GPIO5(1) 20 PGOOD 36 I2C_4(2) 52 N/A
5 GPIO6(1) 21 TWARN_EVENT 37 I2C_5(2) 53 N/A
6 GPIO7 22 INTERRUPT_PIN 38 I2C_6(2) 54 N/A
7 GPIO8 23 N/A 39 I2C_7(2) 55 N/A
8 GPIO9 24 N/A 40 SREG0_0(3) 56 N/A
9 GPIO10 25 N/A 41 SREG0_1(3) 57 N/A
10 GPIO11 26 N/A 42 SREG0_2(3) 58 N/A
11 BUCK1_PG 27 N/A 43 SREG0_3(3) 59 N/A
12 BUCK2_PG 28 N/A 44 SREG0_4(3) 60 N/A
13 BUCK3_PG 29 N/A 45 SREG0_5(3) 61 N/A
14 BUCK4_PG 30 N/A 46 SREG0_6(3) 62 0
15 BUCK5_PG(use 31 N/A 47 SREG0_7(3) 63 1
for EXT_VMON
PowerGood)

(1) Conditions GPIO1..GPIO6 are only processed if the associated GPIOx pins are configured as GPIO
(2) Conditions I2C0..7 refer to register bits TRIGGER_I2C_0..7, and are located in register FSM_I2C_TRIGGER
(3) Conditions SREG0_0...7 refer to bits 9...7 in PFSM storage register R0

8.4.1.2.1.12 DELAY_IMM Command

Description: Delay the execution by a specified time
Assembly command: DELAY_IMM <Delay>
Delay = delay time in ns, µs, ms, or s. If no unit is entered, this field must be an integer value between 0-63.
Delay value is be rounded to the nearest achievable time based on the current step size. Current step size is
based on the default NVM setting or a SET_DELAY value from a previous command. Assembler reports an error
if the step size is too large or too small to meet the delay.
Examples:
• DELAY_IMM 100 µs — Delay execution by 100 µs
• DELAY_IMM 10 ms — Delay execution by 10 ms
• DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step
8.4.1.2.1.13 DELAY_SREG Command
Description: Delay the execution by a time value stored in the specified scratch register. The delay is calculated
based on the curernt step size based on the value stored in PFSM_DELAY_STEP, or a SET_DELAY value from
a previous command.
Assembly command: DELAY_SREG <PFSM Storage Register>
PFSM Storage Register can be R0, R1, R2, or R3.
Examples:
• DELAY_SREG R0 — Delay execution by the time value stored in PFSM storage register R0
8.4.1.2.1.14 TRIG_SET Command
Description: Set a trigger destination address for a given input signal or condition. These commands must be
defined at the beginning of PFSM configuration memory.
Assembly command: TRIG_SET [DEST=]<Destination> [ID=]<Trig_ID> [SEL=]<Trig_sel>
[TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space>

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'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any
order.
Destination is the label where this trigger starts executing.
Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in
numeric order based on the priority of the trigger.
Trig_Sel is the 'Trigger Name' from the Table 8-15. This 'Trigger Name' is the trigger signal to be associated with
the specified TRIG_ID.
Trig_type = LOW, HIGH, RISE, or FALL.
IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the
trigger is activated immediately and can abort a sequence.
REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, that allows a self-
branching trigger to execute the current sequence again.
Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1'
indicates the destination address is external and represents a FSM state ID.
Examples:
• TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered,
start executing at ‘seq1’ label.
• TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising
WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label.
8.4.1.2.1.15 TRIG_MASK Command
Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger,
setting a ‘1’ disables (masks) the trigger.
Assembly command: TRIG_MASK <Mask value>
Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth).
Examples:
• TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0
8.4.1.2.1.16 END Command
Table 8-14 shows the format of the END commands.
Table 8-14. END Command Format
Bit[3:0]
CMD
4 bits

Description: Marks the final instruction in a sequential task

Fields:
• CMD: Command opcode (0xC)
Assembly command: END
8.4.1.2.2 Configuration Memory Organization and Sequence Execution
The configuration memory is loaded from NVM into an SRAM. Figure 8-38 shows an example configuration
memory with only two configured sequences.

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pfsm_start:
TRIG_SET DEST=sequence_name1 ID=0 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1
TRIG_SET DEST=sequence_name2 ID=1 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1
TRIG_SET DEST=sequence_name3 ID=2 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1
TRIG_SET DEST=sequence_name4 ID=4 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1
TRIG_SET DEST=sequence_name5 ID=4 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1
««
TRIG_MASK 0xFFFFFF0
END
sequence_name1
REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting These TRIG_SET instructions are used to
REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting define the trigger types which initiates each
REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting power state sequence. There are a total of
REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time 28 TRIG_SET available for each PMIC. TYPE
REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time parameter defines the type of trigger as:
DELAY_IMM delay_time
REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting
REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time
High: active high (level sensitive)
REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting Low: active low (level sensitive)
TRIG_MASK 0xFC00EDF Rise: active high (edge sensitive)
END Fall: active low (edge sensitive)
««
sequence_name4
REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting
DELAY_IMM delay_time
REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting
REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time
REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time
DELAY_IMM delay_time
REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time
REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting
REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time
REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting
TRIG_MASK 0xFEF6EDC
END

Figure 8-38. Configuration Memory Script Example

As soon as the PMIC state reaches the mission states, it starts reading from the configuration memory until
it hits the first END command. Setting up the triggers (1-28) must be the first section of the configuration
memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to
an internal lookup table that contains the starting address associated with each trigger in the configuration
memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the
trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state
transitions. The signal source of each trigger is listed under Table 8-15.
When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address
associated with the highest priority unmasked trigger, and starts executing commands until it hits an END
command. The last commands before END statement is generally the TRIG_MASK command, which directs the
PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the new set
is serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The priority of the
trigger decreases as the associated trigger ID increases. As a result, the critical error triggers are usually located
at the lowest trigger IDs.
The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced
immediately, which involves branching from the current sequence of commands to reach a new target
destination. The non-immediate triggers are accumulated and serviced in the order of priority through the
execution of each given sequence until the END command in reached. Therefore, the trigger ID assignment for
each trigger can be arranged to produce the desired PFSM behavior.
The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually
placed just before the END instruction. The TRIG_MASK takes a 28-bit input to allow any combination of
triggers to be enabled with a single command. Through the definition of the active triggers after each sequence
execution the TRIG_MASK command can be conceptualized as establishing a power state.
The above sequence of waiting for triggers and executing the sequence associated with an activated trigger
is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The

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fixed device power FSM takes over control from the execution engine each time an event occurs that requires a
transition from the MISSION state of the PMIC to a fixed device state.
Table 8-15. PFSM Trigger Selections
Trigger Name Trigger Source
An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and
IMMEDIATE_SHUTDOWN
the intended action for the activated trigger is to immediate shutdown the device.
MCU_POWER_ERROR Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01').
ORDERLY_SHUTDOWN An event which causes MODERATE_ERR_INT = '1'.
nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL =
FORCE_STANDBY
'00'.
SPMI_WD_BIST_DONE Completion of SPMI WatchDog BIST.
ESM_MCU_ERROR An event that causes ESM_MCU_RST_INT.
WD_ERROR An event that causes WD_RST_INT.
SOC_POWER_ERROR Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10').
ESM_SOC_ERROR An event that causes ESM_SOC_RST_INT
NSLEEP2 and NSLEEP1 = '11'. . More information regarding the NSLEEP1 and NSLEEP2 functions
A
can be found under Section 8.4.1.2.4.3.
WKUP1 A rising or falling edge detection on a GPIO pin that is configured as WKUP1 or LP_WKUP1.
SU_ACTIVE A valid On-Request detection when STARTUP_DEST = '11'.
NSLEEP2 and NSLEEP1 = '10'. . More information regarding the NSLEEP1 and NSLEEP2 functions
B
can be found under Section 8.4.1.2.4.3.
WKUP2 A rising or falling edge detection on a GPIO pin that is configured as WKUP2 or LP_WKUP2.
SU_MCU_ONLY A valid On-Request detection when STARTUP_DEST = '10'.
NSLEEP2 and NSLEEP1 = '01'. More information regarding the NSLEEP1 and NSLEEP2 functions
C
can be found under Section 8.4.1.2.4.3.
NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions
D
can be found under Section 8.4.1.2.4.3.
SU_STANDBY A valid On-Request detection when STARTUP_DEST = '00'.
SU_X A valid On-Request detection when STARTUP_DEST = '01'.
PFSM WAIT command condition timed out. More information regarding the WAIT command can be
WAIT_TIMEOUT
found under Section 8.4.1.2.1.11.
GPIO1 Input detection at GPIO1 pin. Only processed as trigger if GPIO1 is configured as GPIO.
GPIO2 Input detection at GPIO2 pin. Only processed as trigger if GPIO2 is configured as GPIO.
GPIO3 Input detection at GPIO3 pin. Only processed as trigger if GPIO3 is configured as GPIO.
GPIO4 Input detection at GPIO4 pin. Only processed as trigger if GPIO4 is configured as GPIO.
GPIO5 Input detection at GPIO5 pin. Only processed as trigger if GPIO5 is configured as GPIO.
GPIO6 Input detection at GPIO6 pin. Only processed as trigger if GPIO6 is configured as GPIO.
GPIO7 Input detection at GPIO7 pin. Only processed as trigger if GPIO7 is configured as GPIO.
GPIO8 Input detection at GPIO8 pin. Only processed as trigger if GPIO8 is configured as GPIO.
GPIO9 Input detection at GPIO9 pin. Only processed as trigger if GPIO9 is configured as GPIO.
GPIO10 Input detection at GPIO10 pin. Only processed as trigger if GPIO10 is configured as GPIO.
GPIO11 Input detection at GPIO11 pin. Only processed as trigger if GPIO11 is configured as GPIO.
I2C_0 Input detection of TRIGGER_I2C_0 bit (in register FSM_I2C_TRIGGERS)
I2C_1 Input detection of TRIGGER_I2C_1 bit (in register FSM_I2C_TRIGGERS)
I2C_2 Input detection of TRIGGER_I2C_2 bit (in register FSM_I2C_TRIGGERS)
I2C_3 Input detection of TRIGGER_I2C_3 bit (in register FSM_I2C_TRIGGERS)
I2C_4 Input detection of TRIGGER_I2C_4 bit (in register FSM_I2C_TRIGGERS)
I2C_5 Input detection of TRIGGER_I2C_5 bit (in register FSM_I2C_TRIGGERS)
I2C_6 Input detection of TRIGGER_I2C_6 bit (in register FSM_I2C_TRIGGERS)

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Table 8-15. PFSM Trigger Selections (continued)

Trigger Name Trigger Source
I2C_7 Input detection of TRIGGER_I2C_7 bit (in register FSM_I2C_TRIGGERS)
SREG0_0 Input detection of bit 0 in PFSM storage register R0
SREG0_1 Input detection of bit 1 in PFSM storage register R0
SREG0_2 Input detection of bit 2 in PFSM storage register R0
SREG0_3 Input detection of bit 3 in PFSM storage register R0
SREG0_4 Input detection of bit 4 in PFSM storage register R0
SREG0_5 Input detection of bit 5 in PFSM storage register R0
SREG0_6 Input detection of bit 6 in PFSM storage register R0
SREG0_7 Input detection of bit 7 in PFSM storage register R0
0 Always '0'
1 Always '1'

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8.4.1.2.3 Mission State Configuration

The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs
in the user defined states. The Figure 8-39 is used as an example state machine that is defined through the
configuration memory using the configuration FSM instructions.
To Safe Recovery To LP_STANDBY
State State

From any Severe or LP_STANDBY_SEL

Operation States Immediate or Orderly Moderate PFSM =1
Shutdown Condition Errors
Detected

Valid On Request and

STARTUP_DEST[1:0] = 0x00 STANDBY

Valid On Request and

STARTUP_DEST[1:0] = 0x03 OFF request
Warm Reset triggered by
ESM or WDOG error

Valid On Request and ACTIVE OFF request

STARTUP_DEST[1:0] = 0x02

OFF request
WKUP1 0W1 or
NSLEEP2&NSLEEP1
NSLEEP1
11W10
0W1

NSLEEP2 WKUP1 0W 1 or
1:0 MCU ONLY NSLEEP2&NSLEEP1
00W11

WKUP2 0W 1 or
Warm Reset triggered by NSLEEP2 NSLEEP2&NSLEEP1
ESM or WDOG error 1:0 00W10

DEEP SLEEP
/S2R

Figure 8-39. Example of a Mission State-Machine

Each power state (light blue bubbles in Figure 8-39) defines the ON or OFF state and the sequencing timing of
the external regulators and GPIO outputs. This example defines four power states: STANDBY, ACTIVE, MCU
ONLY, and DEEP_SLEEP/S2R three power states: STANDBY, ACTIVE and RETENTION states. The priority
order of these states is as follows:
1. ACTIVE
2. MCU ONLY
3. DEEP SLEEP/S2R
4. STANDBY
The transitions between each power state is determined by the trigger signals source pre-selected from Table
8-15. These triggers are then placed in the order of priority through the trigger ID assignment of each trigger
source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an
on-going sequence. The non-error triggers, which are used to enable state transitions during normal device
operation, are then placed according to the priority order of the state the device is transitioning to. Table 8-16 list
the trigger signal sources, in the order of priority, used to define the power states and transitions of the example

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mission state machine shown in Figure 8-39. This table also helps to determine which triggers must be masked
by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM behavior.
Table 8-16. List of Trigger Used in Example Mission State Machine
Trigger ID Trigger Masked In Each User Defined Power State
Trigger Signal State Transitions DEEP
STANDBY ACTIVE MCU ONLY
SLEEP / S2R
0 IMMEDIATE_SHUTDOWN (1) From any state to SAFE
RECOVERY
1 MCU_POWER_ERROR (1) From any state to SAFE
RECOVERY
2 ORDERLY_SHUTDOWN (1) From any state to SAFE
RECOVERY
3 TRIGGER_FORCE_STANDBY From any state
to STANDBY or Masked
LP_STANDBY
4 WD_ERROR Perform warm reset of all
power rails and return to Masked Masked Masked
ACTIVE
5 ESM_MCU_ERROR Perform warm reset of all
power rails and return to Masked Masked Masked
ACTIVE
6 ESM_SOC_ERROR Perform warm reset of
power rails in SOC
Masked Masked Masked
domain and return to
ACTIVE
7 WD_ERROR Perform warm reset of all
power rails and return to Masked Masked Masked
MCU ONLY
8 ESM_MCU_ERROR Perform warm reset of all
power rails and return to Masked Masked Masked
MCU ONLY
9 SOC_POWER_ERROR ACTIVE to MCU ONLY Masked Masked Masked
10 TRIGGER _I2C_1 (self-cleared) Start RUNTIME_BIST Masked Masked
11 TRIGGER_I2C_2 (self-cleared) Enable I2C CRC
Masked Masked
Function
12 TRIGGER_SU_ACTIVE STANDBY to ACTIVE Masked Masked
13 TRIGGER_WKUP1 Any State to ACTIVE
14 TRIGGER_A (NSLEEP2&NSLEEP1 MCU ONLY or DEEP
Masked
= '11') SLEEP/S2R to ACTIVE
15 TRIGGER_SU_MCU_ONLY STANDBY to MCU ONLY Masked Masked
16 TRIGGER_WKUP2 STANDBY or DEEP
SLEEP/S2R to MCU Masked
ONLY
17 TRIGGER_B (NSLEEP2&NSLEEP1 ACTIVE or DEEP
= '10') SLEEP/S2R to MCU Masked
ONLY
18 TRIGGER_D or TRIGGER_C ACTIVE or MCU ONLY
Masked Masked
(NSLEEP2 = '0' ) to DEEP SLEEP/S2R
19 TRIGGER_I2C_0 (self-cleared) Any state to STANDBY Masked Masked
20 Always '1' (2) STANDBY to SAFE
Mask Masked Masked Masked
RECOVERY
21 Not Used Mask Masked Masked Masked
22 Not Used Mask Masked Masked Masked
23 Not Used Mask Masked Masked Masked
24 Not Used Mask Masked Masked Masked

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Table 8-16. List of Trigger Used in Example Mission State Machine (continued)
Trigger ID Trigger Masked In Each User Defined Power State
Trigger Signal State Transitions DEEP
STANDBY ACTIVE MCU ONLY
SLEEP / S2R
25 Not Used Mask Masked Masked Masked
26 Not Used Mask Masked Masked Masked
27 Not Used Mask Masked Masked Masked
28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180 0xFF01270 0xFFC9FF0

(1) This is an immediate trigger.

(2) When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be
removed while all other non-immediate triggers are masked. The device exits the mission states and the FFSM state machine takes
over control of the device power states once this trigger is executed.

8.4.1.2.4 Pre-Configured Hardware Transitions

There are some pre-defined trigger sources, such as on-requests and off-requests, that are constructed with
the combination of hardware input signals and register bits settings. This section provides more detail to these
pre-defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to
state transitions.
8.4.1.2.4.1 ON Requests
ON requests are used to switch on the device, which then transitions the device from the STANDBY or the
LP_STANDBY to the state specified by STARTUP_DEST[1:0].
After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the
SLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is
cleared, the device stays or moves to the next state corresponding to the NSLEEP signals state assignment as
specified in Table 8-20.
Table 8-17 lists the available ON requests.
Table 8-17. ON Requests
EVENT MASKABLE COMMENT DEBOUNCE
nPWRON (pin) Yes Edge sensitive 50 ms
ENABLE (pin) Yes Level sensitive 8 µs
VCCA > VCCA_UV and FSD
First Supply Detection (FSD) Yes N/A
unmasked
RTC ALARM Interrupt Yes N/A
RTC TIMER Interrupt Yes N/A
WKUP1 or WKUP2 Detection Yes Edge sensitive 8 µs
LP_WKUP1 or LP_WKUP2
Yes Edge sensitive N/A
Detection
Recover from system errors
Recovery from Immediate and which caused immediate or
No N/A
Orderly Shutdown orderly shutdown of the
device

If one of the events listed in Table 8-17 occurs, then the event powers on the device unless one of the gating
conditions listed in Table 8-18 is present.
Table 8-18. ON Requests Gating Conditions
EVENT MASKABLE COMMENT
VCCA > VCCA_OVP Device stays in SAFE RECOVERY until VCCA
VCCA_OVP (event) No
< VCCA_OVP
VCCA_UVLO (event) No VCCA < VCCA_UVLO
VINT_OVP (event) No LDOVINT > 1.98 V

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Table 8-18. ON Requests Gating Conditions (continued)

EVENT MASKABLE COMMENT
VINT_UVLO (event) No LDOVINT < 1.62 V
Device stays in SAFE RECOVERY until temperature decreases
TSD (event) No
below TWARN level

The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin is treated as a power on
press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a short
button press detection is latched internally as a device enable signal until the NPWRON_START_INT is cleared,
or a long press key event is detected. The short button press detection occurs when an falling edge is detected
at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device does no longer react to the
changing state of the pin as the nPWRON press button.
The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion
enables the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device does no longer
react to the changing state of the pin as the ENABLE switch.
8.4.1.2.4.2 OFF Requests
An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission
state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit.
Table 8-19 lists the conditions to generate the OFF requests and the corresponding destination state.
Table 8-19. OFF Requests
LP_STANDBY_SEL BIT
EVENT DEBOUNCE DESTINATION STATE
SETTING

nPWRON (pin) LP_STANDBY_SEL = 0 STANDBY

8s
(long press key event) LP_STANDBY_SEL = 1 LP_STANDBY
LP_STANDBY_SEL = 0 STANDBY
ENABLE (pin) 8 µs
LP_STANDBY_SEL = 1 LP_STANDBY
LP_STANDBY_SEL = 0 STANDBY
I2C_TRIGGER_0 NA
LP_STANDBY_SEL = 1 LP_STANDBY

The long press key event occurs when the nPWRON pin stays low for longer than tLPK_TIME while the device is in
a mission state.
When the nPWRON or ENABLE pin is used as the OFF request, the device wakes up from the STANDBY or
the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or the
ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin. If
the device needs to enter the LP_STANDBY state through the OFF request, it is important that the state of the
nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may
result in unsuccessful wake-up from the LP_STANDBY state when the pin re-initiates On request.
Using the I2C_TRIGGER_0 bit as the OFF request enables the device to wake up from the STANDBY or
the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer
interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals
are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active. Also the
interrupt bits ENABLE_INT, FSD_INT and the GPIOx_INT bits (for the GPIOx pins assigned as WKUP1 or
WKUP2) must be cleared before setting the I2C_TRIGGER_0 bit to '1'.
8.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins that are the secondary
functions of the 11 GPIO pins. These pins can be selected through GPIO configuration using the GPIOx_SEL
register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits
can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register
bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2
pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal.

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A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level
transition reverses the sleep request in the example PFSM from Figure 8-39. When a NSLEEPn signal
transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state.
When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power
state.
The NSLEEP1 signal is designed to control the SoC supply rails. The NSLEEP2 signal is designed to control
the MCU supply rails. When NSLEEP1 signal changes from 1 → 0, depending on the state of NSLEEP2, the
TPS6593-Q1 device exits ACTIVE state and enters either the MCU ONLY or the S2R states. When NSLEEP2
signal changes from 1 → 0, the device enters the S2R state regardless the state of NSLEEP1.
When the NSLEEP2 input signal changes from 0 →1, the MCU supply rails are enabled and the device
exits S2R state. Depending on the state of NSLEEP1 signal, the device enters either the MCU ONLY or the
ACTIVE state. In order for the system to function correctly, the MCU rails must be enabled when the NSLEEP1
input signal changes from 0 →1, which enables the SOC supply rails. NSLEEP1 0 →1 transition is ignored if
NSLEEP2 is 0.
The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn
signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal is ignored. Table 8-20 shows how
the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to
control the power state of the device.
The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the
LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP
SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP
SLEEP/S2R states.
Table 8-20 shows the corresponding state assignment based on the state of the NSLEEPn and their
corresponding mask signals using the example PFSM from Figure 8-39.
Table 8-20. NSLEEPn Transitions and Mission State Assignments
Current State NSLEEP1 NSLEEP2 NSLEEP1 MASK NSLEEP2 MASK Trigger to FSM Next State
DEEP SLEEP/S2R 0 0→1 0 0 TRIGGER B MCU ONLY
DEEP SLEEP/S2R 0→1 0→1 0 0 TRIGGER A ACTIVE
DEEP SLEEP/S2R Don't care 0→1 1 0 TRIGGER A ACTIVE
DEEP SLEEP/S2R 0→1 Don't care 0 1
TRIGGER A ACTIVE
or MCU ONLY
MCU ONLY 0→1 1 0 0 TRIGGER A ACTIVE
MCU ONLY 0 1→0 0 0 DEEP SLEEP
TRIGGER D
or S2R
MCU ONLY Don't care 1→0 1 0 DEEP SLEEP
TRIGGER D
or S2R
ACTIVE 1→0 1 0 0 TRIGGER B MCU ONLY
ACTIVE 1→0 1→0 0 0 DEEP SLEEP
TRIGGER D
or S2R
ACTIVE Don't care 1→0 1 0 DEEP SLEEP
TRIGGER D
or S2R
ACTIVE 1→0 Don't care 0 1 TRIGGER B MCU ONLY

8.4.1.2.4.4 WKUP1 and WKUP2 Functions

The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these
GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL
bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in Figure 8-39, when a GPIO
pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the
GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise if
a GPIO pin is configured as a WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state.

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If multiple edge detections of WKUP signals occur simultaneous, the device goes to the state in the following
priority order:
1. ACTIVE
2. MCU ONLY
When a valid edge is detected at a WKUP pin, the nINT pin generates an interrupt to signal the MCU of the
wake-up event, and the GPIOx_INT interrupt bit is set. The wake request remains active until the GPIOx_INT bit
is cleared by the MCU. While the wake request is executing, the device does not react to sleep requests to enter
a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to cancel the wake request. After
the wake request is canceled, the device returns to the state indicated by the NSLEEP1 and NSLEEP2 signals
as shown in Table 8-20.
8.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY
The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary
functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state
when a high speed wake-up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4
pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by
the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) wakes up the device to the ACTIVE state. Likewise,
if the pin is configured as an LP_WKUP2 pin, a detected edge wakes up the device to the MCU ONLY state. If
multiple edge detections of LP_WKUP signals occur simultaneously, the device goes to the state in the following
priority order:
1. ACTIVE
2. MCU ONLY

Note
Due to a digital control erratum in the device, the ENABLE_MASK/NPWRON_START_MASK bit must
be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly
wake up the device to the MCU_ONLY state.

The TPS6593-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an
input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse
width of tWK_PW_MIN is detected on the assigned LP_WKUP1/2 pins, the device wakes up asynchronously and
executes the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP
pin. If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from
an external supply when TPS6593-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled
down to the recommenced GPIO input voltage level specified in the electrical characteristics table.
In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP
pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn
signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid
wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. The nINT pin generates an
interrupt to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit is set. The
wake request remains active until the interrupt bit is cleared by the MCU. Table 8-20 shows how the device
returns to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is canceled.
Figure 8-40 illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the
internal wake-up signal.

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> tWK_PW_MIN

High Pulse Input at LP_WKUP pin

(GPIO3 or GPIO4)
(e.g. INH-signal)

Wake Signal Latched

on rising edge

MCU clears the

> tWK_PW_MIN
Wake interrupt
Low Pulse Input at LP_WKUP pin
(GPIO3 or GPIO4)
(e.g. RXD-signal)

Wake Signal Latched

on falling edge

MCU clears the

Wake interrupt

Figure 8-40. CAN Wake-Up Timing Diagram

8.4.1.3 Error Handling Operations

The FSM engine of the TPS6593-Q1 device is designed to handle the following types of errors throughout the
operation:
• Power Rail Output Error
• Boot BIST Error
• Runtime BIST Error
• Catastrophic Error
• Watchdog Error
• Error Signal Monitor (ESM) Error
• Warnings
8.4.1.3.1 Power Rail Output Error
A power rail output error occurs when an error condition is detected on the output rails of the device that are
used to power the attached MCU or SoC. These errors include the following:
• Rails not reaching or maintaining within the power good voltage level threshold.
• A short condition that is detected at a regulator output.
• The load current that exceeds the forward current limit.
The BUCKx_GRP_SEL, LDOn_GRP_SEL and VCCA_GRP_SEL registers are used to configure the rail group
for all of the Bucks, LDOs, and the voltage monitors that are available for external rails. The selectable rail
groups are MCU rail group, SoC rail group, or OTHER rail group. The TPS6593-Q1 device is designed to react
differently when an error is detected from a power resource assigned to the different rail groups.
Figure 8-37 shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0]
register bits are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power
Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error
handling sequence that the assigned groups of rails perform in case of an output error. The PFSM engine can be
configured to execute the appropriate error handling sequence for the following error handling sequence options:
immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example, if an immediate
shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0] register bits, any
failure detected in this group of rails causes the IMMEDIATE_SHUTDOWN trigger to be executed. This trigger
is expected to start the immediate shutdown sequence and cause the device to enter the SAFE RECOVERY
state. The device immediately resets the attached MCU and SoC by driving the nRSTOUT and nRSTOUT_SoC
(GPO1 or GPIO11) pins low. All of the power resources assigned to the MCU and SOC shut down immediately
without a sequencing order. The nINT pin signals that an MCU_PWR_ERR_INT interrupt event has occurred
and the EN_DRV pin is forced low. If the error is recoverable within the recovery time interval, the device
increments the recovery count, returns to INIT state, and reattempts the power up sequence (if the recovery
count has not exceeded the counter threshold). If the recovery count has already exceeded the threshold, the

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device stays in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO threshold and the
device is power-cycled.
The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling
sequence. In this PFSM example depicted in Figure 8-39, when a power resource in this group is detected,
the PFSM typically causes the device to execute the shutdown of all the resources assigned to the SoC rail
group, and the device enters the MCU ONLY state. The device immediately resets the attached SoC by toggling
the nRSTOUT_SoC (GPO1 or GPIO11) pin. The reset output to the MCU and the resources assigned to the
MCU rail group remain unchanged. The EN_DRV pin also remains unchanged, and the nINT pin signals that an
SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after a SOC power
error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This action signals
TPS6593-Q1 that MCU has acknowledged the SOC power error, and is ready to return to normal operation.
MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and reattempt the
SoC power up. Refer to Section 8.4.1.2.4.3 for information regarding the setting of the NSLEEP1 and NSLEEP2
signals.
The power resources used for peripheral devices in the system, for which no error-handling action is required,
the rail mapping needs to be selected as "no group assigned".
8.4.1.3.2 Catastrophic Error
Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage,
LDOVINT supply for control logic, errors on internal clock signals, device temperature passing the thermal
shutdown threshold, error detected on the SPMI bus, or an error detected in the PFSM sequence.
Following errors are grouped as severe errors:
• VCCA > OVP threshold
• Junction temperature > immediate shutdown level
• Error in PFSM Sequence
For these above listed errors, depending on the setting of bits SEVERE_ERR_TRIG[1:0], an immediate
or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the
IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY
state.
Following errors are grouped as moderate errors:
• Junction temperature > orderly shutdown level
• BIST failure
• CRC error in register map
• Recovery counter exceeding the threshold value
• Error on SPMI bus
• Readback error on nRSTOUT pin or nINT pin
For these above listed errors, depending on the setting of bits MODERATE_ERR_TRIG[1:0], an immediate
or orderly shutdown condition is created. The PFSM executes the corresponding sequence for the
IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN trigger and enters the SAFE RECOVERY
state.
For following errors, the device performs an immediate shutdown and resets all internal logic circuits:
• VCCA < UVLO threshold
• Error on LDOVINT supply
• Errors on internal clock signals
• Unrecoverable CRC error in the SRAM memory of the PFSM
For all of the above listed errors, the device resets the attached MCU and SoC by driving the nRSTOUT and
the GPIO pin used as nRSTOUT_SoC (GPO1 or GPIO11) pins low. All of the power resources assigned to the
attached MCUand SOC are shut down. The nINT pin is driven low to signal an interrupt event has occurred, and
the EN_DRV pin is forced low.

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8.4.1.3.3 Watchdog (WDOG) Error

Watchdog (WDOG) describes details about the Watchdog (WDOG) errors detection mechanisms.
8.4.1.3.4 Warnings
Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the
device detects the error and handles the error through the interrupt handler. These are errors such as thermal
warnings, I2C, or SPI communication errors, or power resource current limit detection while the output voltage
still maintains within the power good threshold. When these errors occur, the nINT pin is driven low to signal an
interrupt event has occurred. The device remains in the operation state and the state of the EN_DRV pin, the
power resources, and the reset outputs remain unchanged.
The power resource current limit detection can, by setting bit EN_ILIM_FSM_CTRL=1, be configured such that it
is handled as a Power Rail Output Error as described in Section 8.4.1.3.1.
8.4.1.4 Device Start-up Timing
Figure 8-41 shows the timing diagram of the TPS6593-Q1 after the first supply detection.

VCCA

VCCA_UVLO
tINIT_REF_CLK_LDO

Reference Block &

System Clock Ready

VINT & VRTC tINIT_NVM_ANALOG

NVM
Inializa on
tBOOT_BIST

Boot BIST
Compleon

Valid On Request Power Sequence Time

Power Up Rail
Sequencing Reset delay

nRSTOUT

NO SUPPLY INIT BOOT BIST STANDBY ACTIVE

Figure 8-41. Device Start-up Timing Diagram

tINIT_REFCLK_LDO is the start-up time for the reference block. tINIT_NVM_ANALOG is the time for the device to load
the default values of the NVM configurable registers from the NVM memory, and the start-up time for the analog
circuits in the device. tINIT_REFCLK_LDO and tINIT_NVM_ANALOG are defined in the electrical characteristics table.

BOOT_BIST is the sum of tLBISTrun (which is defined in the electrical characterization tables) and a less than 60us
time-interval needed for the cyclic redundancy check on the register map and the SRAM.
The Power Sequence time is the total time for the device to complete the power up sequence. Please refer to
Section 8.4.1.5 for more details.
The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the
power up sequence is completed.

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8.4.1.5 Power Sequences

A power sequence is an automatic preconfigured sequence the TPS6593-Q1 device applies to its resources,
which include the states of the BUCKs, LDOs, 32-kHz clock and the GPIO output signals. For a detailed
description of the GPIOs signals, please refer to General-Purpose I/Os (GPIO Pins).
Figure 8-42 shows an example of a power up transition followed by a power down transition. The power up
sequence is triggered through a valid on request, and the power down sequence is trigger by a valid off request.
The resources controlled (for this example) are: BUCK3, LDO1, BUCK2, LDO2, GPIO1 , LDO4, and LDO3. The
time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition.
A resource not assigned to any power sequence remains in off mode during the power-up sequence. The
attached MCU or SoC can enable and configure this resource independently when the power-up sequence
completes. Also the EN_DRV remains low during the power-up sequence. The attached MCU or SoC can
release the EN_DRV pin by setting the ENABLE_DRV bit (requires running watchdog, ESM started and no
pending interrupt bits).
Power Up Sequence Power Down Sequence

Valid On X X
Request

Valid Off X X
Request
BUCK3 t(inst16)
t(inst1)
LDO1 t(inst15)
t(inst2)
BUCK2 t(inst14)
t(inst3)
LDO2 t(inst13)
t(inst4)
REGEN1 t(inst12)
t(inst5)
LDO4 t(inst11)
t(inst6)
LDO3

GPIO7 t(inst7) t(inst10)

t(inst8) t(inst9)
nRSTOUT/
nRSTOUT_SoC

Figure 8-42. Power Sequence Example

As the power sequences of the TPS6593-Q1 device are defined according to the processor requirements, the
total time for the completion of the power sequence varies across various system definitions.
8.4.1.6 First Supply Detection
The TPS6593-Q1 device can be configured to automatically start up from a first supply-detection (FSD)
event detection. This feature is enabled by setting the FSD_MASK register bit to '0', and setting the
NPWRON_SEL[1:0] registers bits to '10' or '11' to mask the functionality of the nPWRON/ENABLE pin. When the
device is powered up from the NO SUPPLY state, the FSD detection is validated after the NVM default for this
feature is loaded into the device memory.
When the FSD feature is enabled, the PMIC immediately powers up from the NO SUPPLY state to an operation
state, configured by the STARTUP_DEST[1:0] bits when VCCA > VCCA_UV, while VCCA_UV gating is
performed, and only when VCCA voltage monitoring is enabled (VCCA_VMON_EN = 1). After the device arrives
the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2
signals accordingly before clearing the FSD_INT interrupt. Once the interrupt is cleared, the device either stays
in the current state or moves to the destination state according to the state of the NSLEEP1 and NSLEEP2
signals as specified in Table 8-20.

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8.4.1.7 Register Power Domains and Reset Levels

The TPS6593-Q1 registers are defined by the following categories:
• LDOVINT registers
• LDOVRTC registers (registers in RTC domain)

LDOVINT The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the
registers device enters the LP_STANDBY state or the BACKUP state after the device was fully powered
up and in operation. When this occurs, LDOVINT is powered off, all LDOVINT registers (including
the VSET registers which store the output voltage levels for all of the external power rails)
are reset. As the device re-enters the INIT state from a wake up signal or an On-request, the
registers powered by the LDOVINT are re-written with the default values from NVM (Non-Volatile
Memory). All registers in the device, except the LDOVRTC registers (registers in RTC domain),
are powered by LDOVINT.
LDOVRTC The LDOVRTC registers (registers in RTC domain) retain their values until a Power-On-Reset
registers (POR) occurs. POR occurs when the device loses supply power and enters the NO SUPPLY
(registers in state. When this occurs, LDOVRTC is powered off, and all LDOVRTC registers are reset.
RTC
Following are the LDOVRTC registers:
domain)
• All RTC registers
• RTC and Crystal Oscillator bits
• Status registers for the following events: TSD and RTC reset
• Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor
during LP_STANDBY state)
• Following interrupt registers:
– FSD_INT
– RECOV_CNT_INT
– TSD_ORD_INT
– TSD_IMM_INT
– PFSM_ERR_INT
– VCCA_OVP_INT
– ESM_MCU_RST_INT
– ESM_SOC_RST_INT
– WD_RST_INT
– WD_LONGWIN_TIMEOUT_INT
– NPWRON_LONG_INT

8.4.2 Multi-PMIC Synchronization

A multi-PMIC synchronization scheme is implemented in the TPS6593-Q1 device to synchronize the power
state changes with other PMIC devices. This feature consolidates and simplifies the IO control signals required
between the application processor or the microcontroller and multiple PMICs in the system. The control interface
consists of an SPMI protocol that communicates the next power state information from the primary PMIC to up
to 5 secondary PMICs, and receives feedback signal from the secondary PMICs to indicate any error condition
or power state information. Figure 8-43 is the block diagram of the power state synchronization scheme. The
primary PMIC in this block diagram is responsible for broadcasting the synchronous system power state data,
and processing the error feedback signals from the secondary PMICs. The primary PMIC is the controller device
on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus.

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Synchronous-System Power-State Data

Error Feedback

Primary PMIC Secondary PMIC Secondary PMIC

Sequencing and Power

State Configurations in Sequencing and Power Sequencing and Power
Power-State Power-State
Nonvolatile Memory State Configurations in State Configurations in
Sequencer Sequencer
Power-State Controller Nonvolatile Memory Controller Nonvolatile Memory
Power supply
Sequencer Controller
configuration
STATE 1 Exit Condition 1
Signal list
Internal condition list
Error Conditions
Timeout on PGOOD
Thermal
Power supply Power supply
configuration configuration
Current STATE 1 Exit Condition 1 STATE 1 Exit Condition 1
STATE_1 Voltage Signal list Signal list
Error Conditions Error Conditions
... Internal condition list Timeout on PGOOD Internal condition list Timeout on PGOOD
STATE 2 Exit Condition 1

Effective Effective
Thermal

Effective
Thermal
Signal list Current Current
Internal condition list STATE_1 Voltage Voltage
STATE_1
... ...
OFF STATE 2 Exit Condition 1 STATE 2 Exit Condition 1
STATE 2 Exit Condition 2
Signal list Signal list
STATE_2 Signal list
Internal condition list Internal condition list

power
Internal condition list

ERROR
OFF
STATE_2
STATE 2 Exit Condition 2
Signal list
Internal condition list power OFF
STATE_2
STATE 2 Exit Condition 2
Signal list
Internal condition list
power
state
(SAFE STATE)

STATE_3
Controller for
ERROR
(SAFE STATE)
state ERROR
(SAFE STATE)
state
STATE_3

Controller for STATE_3

Controller for
Output Power
STATE_N
Output Power Output Power
Supply Rails STATE_N STATE_N

Power Power Supply Rails Power Supply Rails

Signal Arbitration
Logic supply supply supply
error error error

ENABLE or WAKE
signals from
external hardware

Power-State Control
Signals such as:
ACTIVE, SLEEP, RESET, Scalable Microprocessor and System on Chip
ERROR, TRACKING

Figure 8-43. Multi-PMIC Power State Synchronization Block Diagram

In this scheme, each primary and secondary PMIC runs on its own system clock, and maintains its own register
map. Each PMIC monitors its own activities and pulls down the open-drain output of nINT or PGOOD pin when
errors are detected. The microprocessor must read the status bits from each PMIC device through the I2C or
SPI interface to find out the source of the error that is reported.
To synchronize the timing when entering and exiting from the LP_STANDBY state, the VOUT_LDOVINT of
the TPS6593-Q1 device must be connected to the ENABLE input of the secondary PMICs, which are the
target devices in the SPMI interface bus. Figure 8-44 illustrates the pin connections between the primary, the
secondary, and the application processor or the System-on-Chip.

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x VIO

Secondary PMIC
I2C_SCL
I2C_SDA
SDATA
SCLK
Power Interrupt
Sequencer nINT Handler

Power Good
ENABLE PGOOD Monitor
x

Secondary PMIC
I2C_SCL
I2C_SDA
SDATA
SCLK
Power
Sequencer nINT
x

ENABLE PGOOD µProcessor

&
System
Primary PMIC on
I2C1_SCL
Chip
I2C1_SDA
VOUT_LDOVINT
nPWRON/ENABLE nINT

nERRORx

Power nSLEEPx
Sequencer
GPIO
nRSTOUTx
WAKEn

SCLK PG
SDATA

I2C2_SCL
Q&A
I2C2_SDA
WDOG

Figure 8-44. Multi-PMIC Pin Connections

The power sequencer of the multiple PMICs are synchronized at the beginning of each power up and power
down sequence; a variation in the sequence timing, however, is still possible due to the ±5% clock accuracy of
the independent system clocks on the primary and secondary PMICs. The worst-case sequence timing variation
from different PMIC rails is up to ±10% of the target delay time. Figure 8-45 illustrates the creation of this timing
variation between PMICs.

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Primary PMIC
System clock
(+/-5% accuracy)
... ...
Primary PMIC
Rail X

Sequence delay between rails in Primary PMIC

Primary PMIC
Rail Y

Secondary PMIC
...
System clock
...
(+/-5% accuracy)

Sequence delay between rails in secondary PMIC

Secondary PMIC
Rail Z

Sequencing timing variation between PMIC rails

Figure 8-45. Multi-PMIC Rail Sequencing Timing Variation

8.4.2.1 SPMI Interface System Setup

An SPMI interface in the TPS6593-Q1 device is utilized to communicate the power state transition across
multiple PMICs in the system. The SPMI interface contains a controller block and a target block. There is only
one PMIC, which is the primary PMIC, that acts as SPMI controller in any given system. As the SPMI controller it
initiates SPMI interface BIST and executes periodic checking of the SPMI bus health.
The primary PMIC has a controller-ID (CID)= 1. The target block of SPMI interface in the primary PMIC device
is activated as well, in order to receive SPMI communication messages from the secondary PMICs. The primary
PMIC has a target-ID (TID) = 0101.
Each secondary PMIC on the SPMI network only has the target block of its SPMI interface enabled. There
cannot be more than five secondary PMICs in the system. The target-IDs (TIDs) for the five secondary PMICs
are:
• 1st target device: 0011
• 2nd target device: 1100
• 3rd target device: 1001
• 4th target device: 0110
• 5th target device: 1010
All devices in the SPMI network listen to the group target-ID (GTID): 1111. This address is used to communicate
all power state transition information in broadcast mode to all connected devices on the SPMI bus.
8.4.2.2 Transmission Protocol and CRC
The communication between the devices on the network utilizes Extended Register Write command to GTID
address 1111 with byte length of 2. Sequence format complies with MIPI SPMI 2.0 specification. First data frame
carries the data payload of 5 bits and 3 filler bits.
Communication over the SPMI interface may contain information regarding the power state transition or the
unique TID of one or more target devices. In the case of power state information, the data payload contains 5
bits of Trigger ID information and 3 trigger state bits. In the case of TID information, all 8 bits contain the TID of
the target device.
Second data frame carries 8 bits of CRC information. CRC polynomial used is X8 + X2 + X + 1. CRC is
calculated over the SPMI command frame, the address frame, and the first data frame (which contains the
payload and excludes the parity bits in these three frames).
Figure 8-46 shows the data format of the SPMI Extended Register Write Command.

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SCLK

SDATA SA3 SA2 SA1 SA0 0 0 0 0 BC3 BC2 BC1 BC0 P

SSC Extended register-write command frame

SCLK

SDATA P A7 A6 A5 A4 A3 A2 A1 A0 P

Register address (data frame) for first register

SCLK

SDATA P D7 D6 D5 D4 D3 D2 D1 D0 P

First data frame

... Intermediate Data Frames ...

SCLK

SDATA P D7 D6 D5 D4 D3 D2 D1 D0 P 0

Last data frame Bus park ACK or Bus park

NAK

Signal driven by BOM or request-capable peripheral device

(SCLK always driven by BOM only)
Signal not driven; pulldown only.
Response by peripheral devices

For reference only

Figure 8-46. SPMI Extended Register Write Command

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8.4.2.2.1 Operation with Transmission Errors

If the receiving device detects a parity or CRC error in the incoming sequence it responds with negative ACK/
NACK per SPMI standard.
If the transmitting device sees NACK response, it tries to resend the message as many times as indicated
by SPMI_RETRY_LIMIT register bits. After that it considers the SPMI bus inoperable, sets SPMI_ERR_INT
interrupt and goes to the safe recovery state and executes an orderly shutdown. Bus arbitration requests do not
count as failed attempts if a target device loses bus arbitration. SPMI_RETRY_LIMIT counter is reset after each
successful transmission by the device.
If a target device has determined that SPMI does not work reliably it does not respond to any SPMI commands
anymore until power-on-reset event has occurred. This "no-response" behavior is to prevent continued operation
in a situation where SPMI is unreliable. If a target device does no longer respond to any SPMI command, the
controller device on the SPMI bus detects a missing target device on the network during the periodic testing of
SPMI bus. The target device then internally handles the SPMI error condition per error handling rules set for the
device (in general executing an orderly shutdown). SPMI block signals to the device that SPMI bus error has
occurred after the retry limit has been exceeded.
8.4.2.2.2 Transmitted Information
The SPMI bus is used to carry two types of information:
• PFSM Trigger ID between the SPMI controller and target devices
• TID from SPMI target devices to SPMI controller device
The SPMI controller device reads the TID of the target devices periodically to check the health of the interface.
Exchanging Trigger IDs for the power state transition is sufficient to keep the PFSMs of all the devices on the
SPMI network in synchronization. Device interrupts explain reason for the power state transitions.
8.4.2.3 SPMI Target Device Communication to SPMI Controller Device
An SPMI target device communicates to the SPMI controller device and any other SPMI target devices, only
if there is an internal error that is not SPMI related. The target device initiates the error communication using
Arbitration Request with A-bit as defined in the SPMI 2.0 specification. SPMI 2.0 protocol manages the situation
with multiple target devices requesting error communication at the same time, by using the target arbitration
process as described in SPMI 2.0 specification. Once the SPMI target device wins the arbitration using the A-bit
protocol, it performs an Extended Register Write command to Group Target ID (GTID) address 1111 by using the
protocol described in Section 8.4.2.2 for communicating PFSM trigger ID.
8.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
In case the SPMI controller device detects an arbitration request on the SPMI interface, but the received
sequence has an error or is incomplete, the SPMI controller device immediately performs the SPMI Built-In
Self-Test (SPMI-BIST). If this SPMI-BIST fails, the SPMI controller device executes the error handling for the
SPMI error. If the SPMI-BIST passes successfully, the SPMI controller device resumes normal operation.
8.4.2.4 SPMI-BIST Overview
The SPMI-BIST is performed during BIST state and regularly during runtime operation. Figure 8-47 below
illustrates how the SPMI-BIST operates during device power-up.

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PMIC internal sequencing

PWRON/ENABLE causes transition
x read NVM to active mode
x initialization Power sequence
x Etc. FTTI >> SPMI BIST interval

VIN

PWRON/ENABLE

PMIC State BOOT BIST STANDBY ACTIVE/MISSION

SPMI

SPMI BIST pattern as part of BOOT SPMI BIST patterns

BIST sequence
SPMI messaging to secondary PMIC
to go to ACTIVE state

Figure 8-47. SPMI-BIST Operation

After the input power is detected and verified to be at the correct level, the TPS6593-Q1 initializes itself by
reading the NVM and performs all actions that are needed to prepare for operation. After this initialization, the
TPS6593-Q1 enters the BOOT BIST state, in which the internal logic performs a series of tests to verify that the
TPS6593-Q1 device is OK. As part of this test, the SPMI- BIST is performed. After it is completed successfully,
the TPS6593-Q1 device goes to the standby state and waits for further signals from the system to initiate the
power-up sequence of the processor.
A valid on request initiates the processor power-up sequence. The controller device communicates this event
through the SPMI bus to all of the target devices. After that, the power-up sequence is executed and TPS6593-
Q1 enters the configured mission state.
8.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
During Boot BIST and RUNTIME BIST, both the Logic BIST (LBIST) on the SPMI logic and the SPMI-BIST
are performed to check correct operation of the SPMI bus. The LBIST is performed first before the SPMI-BIST
during BOOT BIST and RUNTIME BIST. The SPMI-BIST is implemented by reading TID from each target device
on the SPMI bus into the controller device, and ensuring they are unique and match the expected amount of
target devices. This process of checking the TID of each target device ensures that:
• All SPMI target devices are present in the system as expected
• The SPMI logic blocks are working on the SPMI controller device and all of the SPMI target devices
• The pins and wires on the ICs and PCB are in working order
The SPMI-BIST is initiated by the SPMI controller block in the primary PMIC by writing a request to all SPMI
target device(s) (using GTID) to send their TIDs to the SPMI controller block of the primary PMIC. Upon
receiving this command from the SPMI controller device, the SPMI target devices request SPMI bus arbitration
using the SR-bit protocol. Upon winning the bus arbitration the SPMI target devices transmit their TID into the
SPMI target block of the primary PMIC.
The SPMI controller block of the primary PMIC contains a list of all SPMI target device(s) on the SPMI bus and
their TIDs in the register set. The SPMI controller block of the primary PMIC reads the TID from each SPMI
target device and compares the result with the stored TID for the corresponding SPMI target device. The SPMI
controller device has to ensure that every non-zero TID on its list is returned, in order to support use cases in
which there are two or more identical SPMI target devices, with same TID, in the system. In these cases, it is
mandatory that the expected number of the same TIDs is returned. If no identical PMICs are to be used, then a
return of the same TID multiple times is an error due to incorrect assembly of identical PMICs onto the PCB. An

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all-zero TID stored in the list of the primary PMIC indicates that there are no SPMI target device(s) present on
the SPMI Bus.
8.4.2.4.2 Periodic Checking of the SPMI
The SPMI controller block in the primary PMIC executes the SPMI-BIST periodically while device is operating.
The time-period after the SPMI-BIST is repeated according factory-configured settings during the device boot
time, and after the device reaches mission states. The factory-configured settings of this SPMI-BIST time period
must be the same for all PMICs on the same SPMI network. The SPMI target devices on the SPMI bus expect a
request for sending its TID from the SPMI controller device within 1.5x the factory-configured period . This factor
1.5x provides enough margin for clock uncertainty between the SPMI controller device and the SPMI target
device.
During mission state operation, the SPMI controller device expects the SPMI target devices to respond to the
TID request within the factory-configured polling time-out period . In other words, from the polling start command
each SPMI target device must respond within this factory-configured time interval.
During boot time or when the device enters Safe Recovery state, to prevent the SPMI controller device from
polling the SPMI target devices too often while one or more of these recovering from a system error such as a
thermal shutdown event, the device sets a longer timeout period that allows the SPMI target devices to respond
to the SPMI controller device before he SPMI controller device reports an error.
If one or more devices on the SPMI bus cause a violating of the polling time-out period either during start-up
or during normal operation, the SPMI controller block in the affected PMIC(s) sets a SPMI error trigger signal
to the PFSM of the affected PMIC(s), causing a complete shutdown of the affected PMIC(s). As a result, the
affected PMIC(s) no longer respond on the SPMI bus, which in turn is detected by the SPMI controller block off
the non-affected PMICs on the SPMI bus. The SPMI controller block in these PMICs sets an SPMI error to the
PFSM in these PMICs, causing a complete shutdown of these PMICs. Therefore, all PMICs are finally shutdown
if one or more devices on the SPMI bus cause a violating of the polling time-out period .
8.4.2.4.3 SPMI Message Priorities
The SPMI Bus uses the protocol priority levels listed in Table 8-21 for each type of communication message.
Table 8-21. SPMI Message Types and Priorities
SPMI protocol priority level Name of priority level in SPMI standard Message types
State transition messages from
Highest A-bit arbitration target device(s) to controller
device
State transition messages from
priority arbitration controller device to target
device(s)
target device TID to controller
SR-bit arbitration
device
Controller device request of TIDs
Lowest secondary arbitration
from target device(s)

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8.5 Control Interfaces

The device has two, exclusive selectable (from factory settings) interfaces. Please refer to the user's guide
of the orderable part number which option has been selected. The first selection is up to two high-speed
I2C interfaces. The second selection is one SPI interface. The SPI and I2C1 interfaces are used to fully
control and configure the device, and have access to all of the configuration registers and Watchdog registers.
During normal operating mode, when the I2C configuration is selected, and the GPIO1 and GPIO2 pins are
configured as the SCL_I2C2 and SDA_I2C2 pins, the I2C2 interface becomes the dedicated interface for the
Q&A Watchdog communication channel, while I2C1 interface no longer has access to the Watchdog registers. .
8.5.1 CRC Calculation for I2C and SPI Interface Protocols
For safety applications, the TPS6593-Q1 supports read and write protocols with embedded CRC data fields. The
TPS6593-Q1 uses a standard CRC-8 polynomial to calculate the checksum value: X8 + X2 + X + 1. The CRC
algorithm details are as follows:
• Initial value for the remainder is all 1s
• Big-endian bit stream order
• Result inversion is not applied
For I2C Interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum
value on every bit except the ACK and NACK bits it receives from the MCU during a write protocol. The
TPS6593-Q1 compares this calculated checksum with the R_CRC checksum value that it receives from the
MCU. The TPS6593-Q1 also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum
value during a read protocol. This T_CRC checksum value is based on every bit that the TPS6593-Q1 receives,
except the ACK and NACK bits, and the data that the TPS6593-Q1 transmits to the MCU during a read protocol.
The MCU must use this same CRC-8 polynomial to calculate the checksum value based on the bits that
the MCU receives from the TPS6593-Q1. The MCU must compare this calculated checksum with the T_CRC
checksum value that it receives from the TPS6593-Q1.
For the SPI interface, the TPS6593-Q1 uses the above mentioned CRC-8 polynomial to calculate the checksum
value on every bit it receives from the MCU during a write protocol. The TPS6593-Q1 compares this calculated
checksum with the R_CRC checksum value, that it receives from the MCU. During a read protocol, the device
also uses the above mentioned CRC-8 polynomial to calculate the T_CRC checksum value based on the first 16
bits sent by the MCU, and the next 8 bits the TPS6593-Q1 transmits to the MCU. The MCU must use this same
CRC-8 polynomial to calculate the checksum value based on the bits which the MCU sends to and receives from
the TPS6593-Q1, and compare it with the T_CRC checksum value that it receives from the TPS6593-Q1.
Figure 8-48 and Figure 8-49 are examples for the 8-bit R_CRC and the T_CRC calculation from 16-bit databus.

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24 24-bit bus ordering value for I2C: 0

I2C_ID[7:1] RW ADDR[7:0] WDATA[7..0]

t
rs
24 24-bit bus ordering value for SPI: 0
it
b
nt

ADDR[7:0] PAGE[2:0] 0 RESERVED[3:0] WDATA[7..0]

i
ign
ts
os
M

Flip-Flop the Preload Value

(Seed Value)

1 Q D 1 Q D 1Q D 1Q D 1 Q D 1 Q D 1 Q D 1Q D

Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop

R_CRC[7] R_CRC[6] R_CRC[5] R_CRC[4] R_CRC[3] R_CRC[2] R_CRC[1] R_CRC[0]

Figure 8-48. Calculation of 8-Bit CRC on Received Data (R_CRC)

32 32-bit bus ordering value for I2C: 0

I2C_ID[7:1] RW ADDR[7:0] I2C_ID[7:1] RW WDATA[7..0]

t
rs

24 24-bit bus ordering value for SPI: 0

it
b
nt

ADDR[7:0] PAGE[2:0] 0 RESERVED[3:0] WDATA[7..0]

i
ign
ts
os
M

Flip-Flop the Preload Value

(Seed Value)

1 1 1 1 1 1 1 1
Q D Q D Q D Q D Q D Q D Q D Q D

Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop Flip Flop

T_CRC[7] T_CRC[6] T_CRC[5] T_CRC[4] T_CRC[3] T_CRC[2] T_CRC[1] T_CRC[0]

Figure 8-49. Calculation of 8-Bit CRC on Transmitted Data (T_CRC)

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8.5.2 I2C-Compatible Interface

The default I2C1 7-bit device address of the TPS6593-Q1 device is set to a binary value that is described in the
user's guide of the orderable part number of the TPS6593-Q1 PMIC, while the two least-significant bits can be
changed for alternative page selection listed under Section 8.6.1. The default 7-bit device address for the I2C2
interface, for accessing the watchdog configuration registers and for operating the watchdog in Q&A mode, is
described in the user's guide of the orderable part number of the TPS6593-Q1 PMIC.
The I2C-compatible synchronous serial interface provides access to the configurable functions and registers
on the device. This protocol uses a two-wire interface for bidirectional communications between the devices
connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL).
Every device on the bus is assigned a unique address and acts as either a controller or a target depending on
whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor
placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode
(100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode
(3.4 MHz) only when VIO is 1.8 V.
8.5.2.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.

SCL

SDA

data data data data data

change valid change valid change
allowed allowed allowed

Figure 8-50. Data Validity Diagram

8.5.2.2 Start and Stop Conditions

The device is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning
and end of the I2C session. A START condition is defined as the SDA signal going from HIGH to LOW while the
SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL
signal is HIGH. The I2C controller device always generates the START and STOP conditions.

SDA

SCL

S P
START STOP
Condition Condition

Figure 8-51. Start and Stop Sequences

The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C controller
device can generate repeated START conditions during data transmission. A START and a repeated START
condition are equivalent function-wise. Figure 8-52 shows the SDA and SCL signal timing for the I2C-compatible
bus. For timing values, see the Specification section.

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tBUF
SDA

tfDA trCL tHD;STA trDA

tLOW tfCL
tSP

SCL
tHD;STA tSU;STA tSU;STO
tHIGH
tHD;DAT
S
tSU;DAT RS P S
START REPEATED STOP START
START

Figure 8-52. I2C-Compatible Timing

8.5.2.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the controller device. The controller device releases the SDA line (HIGH) during the acknowledge clock pulse.
The device pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates
an acknowledge after each byte has been received.
There is one exception to the acknowledge after every byte rule. When the controller device is the receiver,
it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last
byte clocked out of the target device. This negative acknowledge still includes the acknowledge clock pulse
(generated by the controller device), but the SDA line is not pulled down.
After the START condition, the bus controller device sends a chip address. This address is seven bits long
followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a
WRITE and a 1 indicates a READ. The second byte selects the register to which the data is written. The third
byte contains data to write to the selected register. Figure 8-53 shows an example bit format of device address
110000-Bin = 60Hex.
MSB LSB

1 1 0 0 0 0 0 R/W
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

I2C Address (chip address)

Figure 8-53. Example Device Address

For safety applications, the device supports read and write protocols with embedded CRC data fields. In a write
cycle, the I2C controller device (the MCU) must provide the 8-bit CRC value after sending the write data bits and
receiving the ACK from the target (the TPS6593-Q1 PMIC). The CRC value must be calculated from every bit
included in the write protocol except the ACK bits from the target. See CRC Calculation for I2C and SPI Interface
Protocols. In a read cycle, the I2C target must provide the 8-bit CRC value after sending the read data bits and
the ACK bit, and expect to receive the NACK from the controller at the end of the protocol. The CRC value must
be calculated from every bit included in the read protocol except the ACK and NACK bits. See CRC Calculation
for I2C and SPI Interface Protocols.

Note
If I2C CRC is enabled in the device and an I2C write without R_CRC bits is done, the device does not
process the write request. The device does not set any interrupt bit and does not pull the nINT pin low.

The embedded CRC field can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN
register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM.

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In case the calculated CRC-value does not match the received CRC-check-sum, an I2C-CRC-error is detected,
the COMM_CRC_ERR_INT bit is set, unless it is masked by the COMM_CRC_ERR_MASK bit. The MCU must
clear this bit by writing a ‘1’ to the COMM_CRC_ERR_INT bit.
When the CRC field is enabled, in the case when MCU attempts to write to a read-only register
or a register-address that does not exist, the device sets the COMM_ADR_ERR_INT bit, unless the
COMM_ADR_ERR_MASK bit is set. The MCU must clear this bit by writing a ‘1’ to the COMM_ADR_ERR_INT
bit.
START ACK ACK ACK STOP

I2C_ID[7:1] 0 ADDR[7:0] WDATA[7:0] STOP

SCL

0x60 0x36 0x16

SDA

Figure 8-54. I2C Write Cycle without CRC

START ACK ACK ACK STOP

I2C_ID[7:1] 0 ADDR[7:0] WDATA[7:0] R_CRC[7:0] STOP

SCL

0x60 0x36 0x16 0x43

SDA

The I2C controller device (the MCU) provides R_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24
bits). See CRC Calculation for I2C and SPI Interface Protocols.

Figure 8-55. I2C Write Cycle with CRC

REPEATED STOP
START ACK ACK START ACK NCK

I2C_ID[7:1] 0 ADDR[7:0] I2C_ID[7:1] 1 RDATA[7:0] STOP

SCL

0x60 0x36 0x60 0x16

SDA

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

Figure 8-56. I2C Read Cycle without CRC

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REPEATED STOP
START
START ACK ACK ACK ACK NCK

I2C_ID[7:1] 0 ADDR[7:0] I2C_ID[7:1] 1 RDATA[7:0] T_CRC[7:0] STOP

SCL

0x60 0x36 0x60 0x16 0x7D

SDA

The I2C target device (the TPS6593-Q1) provides T_CRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the
RDATA bits (32 bits). See CRC Calculation for I2C and SPI Interface Protocols.

Figure 8-57. I2C READ Cycle with CRC

8.5.2.4 Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an
8-bit word is sent to the device, the internal address index counter is incremented by one and the next register is
written. Table 8-22 lists the writing sequence to two consecutive registers. Note that auto increment feature does
not support CRC protocol.
Table 8-22. Auto-Increment Example
DEVICE
REGISTER
ACTION START ADDRESS = WRITE DATA DATA STOP
ADDRESS
0x60
PMIC device ACK ACK ACK ACK

8.5.3 Serial Peripheral Interface (SPI)

The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts
as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if
CRC is enabled) in the following order:
• Bits 1-8: ADDR[7:0], Register address
• Bits 9-11: PAGE[2:0], Page address for register
• Bit 12: Read/Write definition, 0 = WRITE, 1 = READ.
• Bits 13-16: RESERVED[4:0], Reserved, use all zeros.
• For Write: Bits 17-24: WDATA[7:0], write data
• For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the
controller device (the MCU). See Section 8.5.1.
• For Read: Bits 17-24: RDATA[7:0], read data
• For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the
controller device (the MCU), and bits 17-24, sent by the peripheral device (the TPS6593-Q1). See Section
8.5.1.
The embedded CRC filed can be enabled or deactivated from the protocol by setting the I2C1_SPI_CRC_EN
register bit to '1' - enabled, '0' - deactivated. The default of this bit is configurable through the NVM.
The SDO output is in a high-impedance state when the CS pin is high. When the CS pin is low, the SDO output
is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent,
the SDO output is driven accordingly.
The address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS) must be low during
the cycle transmission. The CS signal resets the interface when it is high, and must be taken high between
successive cycles. Data is clocked in on the rising edge of the SCLK clock signal and it is clocked out on the
falling edge of SCLK clock signal.
The SPI Timing diagram shows the timing information for these signals.

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CS_SPI

SCLK_SPI

PAGE
SDI_SPI ADDR[7:0] [2:0]
0 Reserved[3:0] WDATA[7:0]

SDO_SPI Hi-Z Hi-Z

Figure 8-58. SPI Write Cycle

CS_SPI

SCLK_SPI

PAGE
SDI_SPI ADDR[7:0] [2:0]
0 Reserved[3:0] WDATA[7:0] R_CRC[7:0]

SDO_SPI Hi-Z Hi-Z

Figure 8-59. SPI Write Cycle with CRC

CS_SPI

SCLK_SPI

PAGE
SDI_SPI ADDR[7:0] [2:0]
1 Reserved[3:0]

SDO_SPI Hi-Z RDATA[7:0] Hi-Z

Figure 8-60. SPI Read Cycle

CS_SPI

SCLK_SPI

PAGE
SDI_SPI ADDR[7:0] [2:0] 1 Reserved[3:0]

SDO_SPI Hi-Z RDATA[7:0] T_CRC[7:0] Hi-Z

Figure 8-61. SPI Read Cycle with CRC

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Note
Due to a digital control erratum in the device, the TPS6593-Q1 pulls the nINT pin low and sets
interrupt bit COMM_FRM_ERR_INT if the pin CS_SPI is low during device power-up and goes high
after completion of the device power-up sequence. After system start-up, the MCU must clear this
COMM_FRM_ERR_INT bit such that the TPS6593-Q1 can release the nINT pin.

8.6 Configurable Registers

8.6.1 Register Page Partitioning
The registers in the TPS6593-Q1 device are organized into five internal pages. Each page represents a different
type of register. The below list shows the pages with their register types:
• Page 0: User Registers
• Page 1: NVM Control, Configuration, and Test Registers
• Page 2: Trim Registers
• Page 3: SRAM for PFSM Registers
• Page 4: Watchdog Registers

Note
When I2C Interfaces are used, each of the above listed register pages has its own 6-bit I2C device
address. In order to address Page 0 to 3, the two LSBs if the pre-configured I2C1_ID are replaced
with 00 for Page 0, 01 for Page 1, 10 for Page 2 and 11 for Page 3. As an example, if I2C1_ID=0x26
(0100110b) , Page 0 to 3 have following addresses:
• Page 0: 0100100
• Page 1: 0100101
• Page 2: 0100110
• Page 3: 0100111
For Page 4 the I2C device address is according register bits I2C2_ID. Therefore, in case both I2C1
and I2C2 Interfaces are used, each TPS6593-Q1 device occupies four I2C device addresses (for Page
0, Page 1, Page 2 and Page 3) on the I2C1 bus and one I2C device address (for Page 4) on the
I2C2 bus. And in case only I2C1 Interfaces is used, each TPS6593-Q1 device occupies five I2C device
addresses (for Page 0, Page 1, Page 2, Page 3 and Page 4) on the I2C1 bus. In case multiple devices
are used on a common I2C bus, care must be taken to avoid overlapping I2C device addresses.

Note
When SPI Interface is used, the above listed register pages are addresses with the PAGE[2:0] bits:
0x0 addresses Page 0, 0x1 addresses Page 1, 0x2 addresses Page 2, 0x3 addresses Page 3

8.6.2 CRC Protection for Configuration, Control, and Test Registers

The TPS6593-Q1 device includes a CRC-16 engine to protect all the static registers of the device. Static
registers are registers in Page 1, 2, and 3, with values that do not change once loaded from NVM. The
CRC-16 engine continuously checks the control registers and the SRAM in the TPS6593-Q1. The expected
CRC-16 value is stored in the NVM. When the CRC-16 engine detects a mismatch between the calculated
and expected CRC-16 values, the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly
shutdown sequence to return to the SAFE RECOVERY state. The device NVM control, configuration, and test
registers in page 1 are protected against read or write access when the device is in normal functional mode. .
The CRC-16 engine uses a standard CRC-16 polynomial to calculate the internal known-good checksum-value,
which is X16 + X14 + X13 + X12 + X10 + X8 + X6 + X4 + X3 + X + 1.
The initial value for the remainder of the polynomial is all 1s and is in big-endian bit-stream order. The inversion
of the calculated result is enabled.

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Note
The CRC-16 engine assumes a default value of '0' for all undefined or reserved bits in all control
registers. Therefore, the software MUST NOT write the value of '1' to any of these undefined or
reserved bits. If the value of '1 is written to any undefined or reserved bit of a writable register, the
CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, and hence
the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to
return to the SAFE RECOVERY state.

8.6.3 CRC Protection for User Registers

At device power-up, after the NVM data is loaded into the register map, the TPS6593-Q1 performs an initial CRC
check on the User Registers. These User Registers are located in page 0 and page 4 of the register map. For
this initial CRC check on the User Registers, the TPS6593-Q1 uses the same CRC-16 engine and polynomial as
described in Section 8.6.2, and compares the calculated CRC-16 values against the reference CRC-16 values
read from the NVM.
After power-up, the content of these User Registers can change due to a write-access through an I2C or
SPI interface, or by the PFSM during a state transition. To protect the content of these User Registers during
operation, the TPS6593-Q1 uses a dynamic CRC-8 engine for each 128-bit segment. When a write-access
occurs to the User Registers, the dynamic CRC-8 engine calculates the checksum value of the current data in
the accessed segment before the update to confirm that the data in the access segment before the update is still
correct. In parallel, the CRC-8 engine calculates a new checksum value of the data from the same segment, with
the new data inserted at the intended register address. If the checksum on the current data before the update
is correct, the new calculated checksum value is used for the next CRC cycles. During operation, the checksum
value are continuously computed and verified in a round-robin fashion.
The CRC-8 engine utilizes the Polynomial(0xA6) = X8 + X6 + X3 + X2 + 1, which provides a H4 hamming
distance.

Note
If a RESERVED bit in a R/W configuration register gets set to 1h through a I2C/SPI write, the
TPS6593-Q1 detects a CRC error in the register map. Therefore, it is important that system software
involved in the I2C/SPI write-access to the TPS6593-Q1 keeps all RESERVED bits (all bits with the
word RESERVED in the Register Field Description tables in the Register Map section at 0h.

8.6.4 Register Write Protection

For safety application, in order to prevent unintentional writes to the control registers, the TPS6593-Q1 device
implements locking and unlocking mechanisms to many of its configuration/control registers described in the
following subsections.
8.6.4.1 Watchdog and ESM Configuration Registers
The configuration registers for the watchdog and the ESM are locked when their monitoring functions are in
operation. The locking mechanism and the list of the locked watchdog register is described under Section
8.3.10.2. The locking mechanism and the list of the locked ESM registers is described under
Error Signal Monitor (ESM)
8.6.4.2 User Registers
User registers in page 0, except the ESM and the WDOG configuration registers described in Section 8.6.4.1,
and the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a
dedicated lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any
value other than '0x9B' activates the lock again. To check the register lock status, user must read the
REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this
bit is '1', the user registers are locked. During start-up sequence such as powering up for the first time, waking
up from LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers are unlocked automatically.

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8.7 Register Maps

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8.7.1 TPS6593-Q1 Registers

Table 8-23 lists the memory-mapped registers for the TPS6593-Q1 registers. All register offset addresses not
listed in Table 8-23 should be considered as reserved locations and the register contents should not be modified.
Table 8-23. TPS6593-Q1 Registers
Offset Acronym Register Name Section
1h DEV_REV Section 8.7.1.1
2h NVM_CODE_1 Section 8.7.1.2
3h NVM_CODE_2 Section 8.7.1.3
4h BUCK1_CTRL Section 8.7.1.4
5h BUCK1_CONF Section 8.7.1.5
6h BUCK2_CTRL Section 8.7.1.6
7h BUCK2_CONF Section 8.7.1.7
8h BUCK3_CTRL Section 8.7.1.8
9h BUCK3_CONF Section 8.7.1.9
Ah BUCK4_CTRL Section 8.7.1.10
Bh BUCK4_CONF Section 8.7.1.11
Ch BUCK5_CTRL Section 8.7.1.12
Dh BUCK5_CONF Section 8.7.1.13
Eh BUCK1_VOUT_1 Section 8.7.1.14
Fh BUCK1_VOUT_2 Section 8.7.1.15
10h BUCK2_VOUT_1 Section 8.7.1.16
11h BUCK2_VOUT_2 Section 8.7.1.17
12h BUCK3_VOUT_1 Section 8.7.1.18
13h BUCK3_VOUT_2 Section 8.7.1.19
14h BUCK4_VOUT_1 Section 8.7.1.20
15h BUCK4_VOUT_2 Section 8.7.1.21
16h BUCK5_VOUT_1 Section 8.7.1.22
17h BUCK5_VOUT_2 Section 8.7.1.23
18h BUCK1_PG_WINDOW Section 8.7.1.24
19h BUCK2_PG_WINDOW Section 8.7.1.25
1Ah BUCK3_PG_WINDOW Section 8.7.1.26
1Bh BUCK4_PG_WINDOW Section 8.7.1.27
1Ch BUCK5_PG_WINDOW Section 8.7.1.28
1Dh LDO1_CTRL Section 8.7.1.29
1Eh LDO2_CTRL Section 8.7.1.30
1Fh LDO3_CTRL Section 8.7.1.31
20h LDO4_CTRL Section 8.7.1.32
22h LDORTC_CTRL Section 8.7.1.33
23h LDO1_VOUT Section 8.7.1.34
24h LDO2_VOUT Section 8.7.1.35
25h LDO3_VOUT Section 8.7.1.36
26h LDO4_VOUT Section 8.7.1.37
27h LDO1_PG_WINDOW Section 8.7.1.38
28h LDO2_PG_WINDOW Section 8.7.1.39
29h LDO3_PG_WINDOW Section 8.7.1.40
2Ah LDO4_PG_WINDOW Section 8.7.1.41
2Bh VCCA_VMON_CTRL Section 8.7.1.42

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Table 8-23. TPS6593-Q1 Registers (continued)

Offset Acronym Register Name Section
2Ch VCCA_PG_WINDOW Section 8.7.1.43
31h GPIO1_CONF Section 8.7.1.44
32h GPIO2_CONF Section 8.7.1.45
33h GPIO3_CONF Section 8.7.1.46
34h GPIO4_CONF Section 8.7.1.47
35h GPIO5_CONF Section 8.7.1.48
36h GPIO6_CONF Section 8.7.1.49
37h GPIO7_CONF Section 8.7.1.50
38h GPIO8_CONF Section 8.7.1.51
39h GPIO9_CONF Section 8.7.1.52
3Ah GPIO10_CONF Section 8.7.1.53
3Bh GPIO11_CONF Section 8.7.1.54
3Ch NPWRON_CONF Section 8.7.1.55
3Dh GPIO_OUT_1 Section 8.7.1.56
3Eh GPIO_OUT_2 Section 8.7.1.57
3Fh GPIO_IN_1 Section 8.7.1.58
40h GPIO_IN_2 Section 8.7.1.59
41h RAIL_SEL_1 Section 8.7.1.60
42h RAIL_SEL_2 Section 8.7.1.61
43h RAIL_SEL_3 Section 8.7.1.62
44h FSM_TRIG_SEL_1 Section 8.7.1.63
45h FSM_TRIG_SEL_2 Section 8.7.1.64
46h FSM_TRIG_MASK_1 Section 8.7.1.65
47h FSM_TRIG_MASK_2 Section 8.7.1.66
48h FSM_TRIG_MASK_3 Section 8.7.1.67
49h MASK_BUCK1_2 Section 8.7.1.68
4Ah MASK_BUCK3_4 Section 8.7.1.69
4Bh MASK_BUCK5 Section 8.7.1.70
4Ch MASK_LDO1_2 Section 8.7.1.71
4Dh MASK_LDO3_4 Section 8.7.1.72
4Eh MASK_VMON Section 8.7.1.73
4Fh MASK_GPIO1_8_FALL Section 8.7.1.74
50h MASK_GPIO1_8_RISE Section 8.7.1.75
51h MASK_GPIO9_11 Section 8.7.1.76
52h MASK_STARTUP Section 8.7.1.77
53h MASK_MISC Section 8.7.1.78
54h MASK_MODERATE_ERR Section 8.7.1.79
56h MASK_FSM_ERR Section 8.7.1.80
57h MASK_COMM_ERR Section 8.7.1.81
58h MASK_READBACK_ERR Section 8.7.1.82
59h MASK_ESM Section 8.7.1.83
5Ah INT_TOP Section 8.7.1.84
5Bh INT_BUCK Section 8.7.1.85
5Ch INT_BUCK1_2 Section 8.7.1.86
5Dh INT_BUCK3_4 Section 8.7.1.87

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Table 8-23. TPS6593-Q1 Registers (continued)

Offset Acronym Register Name Section
5Eh INT_BUCK5 Section 8.7.1.88
5Fh INT_LDO_VMON Section 8.7.1.89
60h INT_LDO1_2 Section 8.7.1.90
61h INT_LDO3_4 Section 8.7.1.91
62h INT_VMON Section 8.7.1.92
63h INT_GPIO Section 8.7.1.93
64h INT_GPIO1_8 Section 8.7.1.94
65h INT_STARTUP Section 8.7.1.95
66h INT_MISC Section 8.7.1.96
67h INT_MODERATE_ERR Section 8.7.1.97
68h INT_SEVERE_ERR Section 8.7.1.98
69h INT_FSM_ERR Section 8.7.1.99
6Ah INT_COMM_ERR Section 8.7.1.100
6Bh INT_READBACK_ERR Section 8.7.1.101
6Ch INT_ESM Section 8.7.1.102
6Dh STAT_BUCK1_2 Section 8.7.1.103
6Eh STAT_BUCK3_4 Section 8.7.1.104
6Fh STAT_BUCK5 Section 8.7.1.105
70h STAT_LDO1_2 Section 8.7.1.106
71h STAT_LDO3_4 Section 8.7.1.107
72h STAT_VMON Section 8.7.1.108
73h STAT_STARTUP Section 8.7.1.109
74h STAT_MISC Section 8.7.1.110
75h STAT_MODERATE_ERR Section 8.7.1.111
76h STAT_SEVERE_ERR Section 8.7.1.112
77h STAT_READBACK_ERR Section 8.7.1.113
78h PGOOD_SEL_1 Section 8.7.1.114
79h PGOOD_SEL_2 Section 8.7.1.115
7Ah PGOOD_SEL_3 Section 8.7.1.116
7Bh PGOOD_SEL_4 Section 8.7.1.117
7Ch PLL_CTRL Section 8.7.1.118
7Dh CONFIG_1 Section 8.7.1.119
7Eh CONFIG_2 Section 8.7.1.120
80h ENABLE_DRV_REG Section 8.7.1.121
81h MISC_CTRL Section 8.7.1.122
82h ENABLE_DRV_STAT Section 8.7.1.123
83h RECOV_CNT_REG_1 Section 8.7.1.124
84h RECOV_CNT_REG_2 Section 8.7.1.125
85h FSM_I2C_TRIGGERS Section 8.7.1.126
86h FSM_NSLEEP_TRIGGERS Section 8.7.1.127
87h BUCK_RESET_REG Section 8.7.1.128
88h SPREAD_SPECTRUM_1 Section 8.7.1.129
8Ah FREQ_SEL Section 8.7.1.130
8Bh FSM_STEP_SIZE Section 8.7.1.131
8Eh USER_SPARE_REGS Section 8.7.1.132

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Table 8-23. TPS6593-Q1 Registers (continued)

Offset Acronym Register Name Section
8Fh ESM_MCU_START_REG Section 8.7.1.133
90h ESM_MCU_DELAY1_REG Section 8.7.1.134
91h ESM_MCU_DELAY2_REG Section 8.7.1.135
92h ESM_MCU_MODE_CFG Section 8.7.1.136
93h ESM_MCU_HMAX_REG Section 8.7.1.137
94h ESM_MCU_HMIN_REG Section 8.7.1.138
95h ESM_MCU_LMAX_REG Section 8.7.1.139
96h ESM_MCU_LMIN_REG Section 8.7.1.140
97h ESM_MCU_ERR_CNT_REG Section 8.7.1.141
98h ESM_SOC_START_REG Section 8.7.1.142
99h ESM_SOC_DELAY1_REG Section 8.7.1.143
9Ah ESM_SOC_DELAY2_REG Section 8.7.1.144
9Bh ESM_SOC_MODE_CFG Section 8.7.1.145
9Ch ESM_SOC_HMAX_REG Section 8.7.1.146
9Dh ESM_SOC_HMIN_REG Section 8.7.1.147
9Eh ESM_SOC_LMAX_REG Section 8.7.1.148
9Fh ESM_SOC_LMIN_REG Section 8.7.1.149
A0h ESM_SOC_ERR_CNT_REG Section 8.7.1.150
A1h REGISTER_LOCK Section 8.7.1.151
A6h MANUFACTURING_VER Section 8.7.1.152
A7h CUSTOMER_NVM_ID_REG Section 8.7.1.153
ABh SOFT_REBOOT_REG Section 8.7.1.154
B5h RTC_SECONDS Section 8.7.1.155
B6h RTC_MINUTES Section 8.7.1.156
B7h RTC_HOURS Section 8.7.1.157
B8h RTC_DAYS Section 8.7.1.158
B9h RTC_MONTHS Section 8.7.1.159
BAh RTC_YEARS Section 8.7.1.160
BBh RTC_WEEKS Section 8.7.1.161
BCh ALARM_SECONDS Section 8.7.1.162
BDh ALARM_MINUTES Section 8.7.1.163
BEh ALARM_HOURS Section 8.7.1.164
BFh ALARM_DAYS Section 8.7.1.165
C0h ALARM_MONTHS Section 8.7.1.166
C1h ALARM_YEARS Section 8.7.1.167
C2h RTC_CTRL_1 Section 8.7.1.168
C3h RTC_CTRL_2 Section 8.7.1.169
C4h RTC_STATUS Section 8.7.1.170
C5h RTC_INTERRUPTS Section 8.7.1.171
C6h RTC_COMP_LSB Section 8.7.1.172
C7h RTC_COMP_MSB Section 8.7.1.173
C8h RTC_RESET_STATUS Section 8.7.1.174
C9h SCRATCH_PAD_REG_1 Section 8.7.1.175
CAh SCRATCH_PAD_REG_2 Section 8.7.1.176
CBh SCRATCH_PAD_REG_3 Section 8.7.1.177

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Table 8-23. TPS6593-Q1 Registers (continued)

Offset Acronym Register Name Section
CCh SCRATCH_PAD_REG_4 Section 8.7.1.178
CDh PFSM_DELAY_REG_1 Section 8.7.1.179
CEh PFSM_DELAY_REG_2 Section 8.7.1.180
CFh PFSM_DELAY_REG_3 Section 8.7.1.181
D0h PFSM_DELAY_REG_4 Section 8.7.1.182
401h WD_ANSWER_REG Section 8.7.1.183
402h WD_QUESTION_ANSW_CNT Section 8.7.1.184
403h WD_WIN1_CFG Section 8.7.1.185
404h WD_WIN2_CFG Section 8.7.1.186
405h WD_LONGWIN_CFG Section 8.7.1.187
406h WD_MODE_REG Section 8.7.1.188
407h WD_QA_CFG Section 8.7.1.189
408h WD_ERR_STATUS Section 8.7.1.190
409h WD_THR_CFG Section 8.7.1.191
40Ah WD_FAIL_CNT_REG Section 8.7.1.192

Complex bit access types are encoded to fit into small table cells. Table 8-24 shows the codes that are used for
access types in this section.
Table 8-24. TPS6593-Q1 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C W Write
1C 1 to clear
WSelfClrF W Write
Reset or Default Value
-n Value after reset or the default
value

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8.7.1.1 DEV_REV Register (Offset = 1h) [Reset = 00h]

DEV_REV is shown in Figure 8-62 and described in Table 8-25.
Return to the Summary Table.
Figure 8-62. DEV_REV Register
7 6 5 4 3 2 1 0
TI_DEVICE_ID
R/W-0h

Table 8-25. DEV_REV Register Field Descriptions

Bit Field Type Reset Description
7-0 TI_DEVICE_ID R/W 0h Refer to Technical Reference Manual / User's Guide for specific
numbering.
Note: This register can be programmed only by the manufacturer.
(Default from NVM memory)

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8.7.1.2 NVM_CODE_1 Register (Offset = 2h) [Reset = 00h]

NVM_CODE_1 is shown in Figure 8-63 and described in Table 8-26.
Return to the Summary Table.
Figure 8-63. NVM_CODE_1 Register
7 6 5 4 3 2 1 0
TI_NVM_ID
R/W-0h

Table 8-26. NVM_CODE_1 Register Field Descriptions

Bit Field Type Reset Description
7-0 TI_NVM_ID R/W 0h 0x00 - 0xF0 are reserved for TI manufactured NVM variants
0xF1 - 0xFF are reserved for special use
0xF1 = Engineering sample, blank NVM [trim and basic defaults
only], customer programmable for engineering use only
0xF2 = Production unit, blank NVM [trim and basic defaults only],
customer programmable in volume production
0xF3-FF = Reserved, do not use
Note: This register can be programmed only by the manufacturer.
(Default from NVM memory)

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8.7.1.3 NVM_CODE_2 Register (Offset = 3h) [Reset = 00h]

NVM_CODE_2 is shown in Figure 8-64 and described in Table 8-27.
Return to the Summary Table.
Figure 8-64. NVM_CODE_2 Register
7 6 5 4 3 2 1 0
TI_NVM_REV
R/W-0h

Table 8-27. NVM_CODE_2 Register Field Descriptions

Bit Field Type Reset Description
7-0 TI_NVM_REV R/W 0h NVM revision of the IC
Note: This register can be programmed only by the manufacturer.
(Default from NVM memory)

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8.7.1.4 BUCK1_CTRL Register (Offset = 4h) [Reset = 22h]

BUCK1_CTRL is shown in Figure 8-65 and described in Table 8-28.
Return to the Summary Table.
Figure 8-65. BUCK1_CTRL Register
7 6 5 4 3 2 1 0
RESERVED BUCK1_PLDN BUCK1_VMON BUCK1_VSEL BUCK1_FPWM BUCK1_FPWM BUCK1_EN
_EN _MP
R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h

Table 8-28. BUCK1_CTRL Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 BUCK1_PLDN R/W 1h Enable output pull-down resistor when BUCK1 is disabled:
(Default from NVM memory)
0h = Pull-down resistor disabled
1h = Pull-down resistor enabled
4 BUCK1_VMON_EN R/W 0h Enable BUCK1 OV, UV, SC and ILIM comparators:
(Default from NVM memory)
0h = OV, UV, SC and ILIM comparators are disabled
1h = OV, UV, SC and ILIM comparators are enabled
3 BUCK1_VSEL R/W 0h Select output voltage register for BUCK1:
(Default from NVM memory)
0h = BUCK1_VOUT_1
1h = BUCK1_VOUT_2
2 BUCK1_FPWM_MP R/W 0h Forces the BUCK1 regulator to operate always in multi-phase and
forced PWM operation mode:
(Default from NVM memory)
0h = Automatic phase adding and shedding.
1h = Forced to multi-phase operation, all phases in the multi-phase
configuration.
1 BUCK1_FPWM R/W 1h Forces the BUCK1 regulator to operate in PWM mode:
(Default from NVM memory)
0h = Automatic transitions between PFM and PWM modes (AUTO
mode).
1h = Forced to PWM operation.
0 BUCK1_EN R/W 0h Enable BUCK1 regulator:
(Default from NVM memory)
0h = BUCK regulator is disabled
1h = BUCK regulator is enabled

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8.7.1.5 BUCK1_CONF Register (Offset = 5h) [Reset = 22h]

BUCK1_CONF is shown in Figure 8-66 and described in Table 8-29.
Return to the Summary Table.
Figure 8-66. BUCK1_CONF Register
7 6 5 4 3 2 1 0
RESERVED BUCK1_ILIM BUCK1_SLEW_RATE
R/W-0h R/W-4h R/W-2h

Table 8-29. BUCK1_CONF Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 BUCK1_ILIM R/W 4h Sets the switch peak current limit of BUCK1. Can be programmed at
any time during operation:
(Default from NVM memory)
0h = Reserved
1h = Reserved
2h = 2.5 A
3h = 3.5 A
4h = 4.5 A
5h = 5.5 A
6h = Reserved
7h = Reserved
2-0 BUCK1_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK1 regulator (rising and
falling edges):
(Default from NVM memory)
0h = 33 mV/μs
1h = 20 mV/μs
2h = 10 mV/μs
3h = 5.0 mV/μs
4h = 2.5 mV/μs
5h = 1.3 mV/μs
6h = 0.63 mV/μs
7h = 0.31 mV/μs

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8.7.1.6 BUCK2_CTRL Register (Offset = 6h) [Reset = 22h]

BUCK2_CTRL is shown in Figure 8-67 and described in Table 8-30.
Return to the Summary Table.
Figure 8-67. BUCK2_CTRL Register
7 6 5 4 3 2 1 0
RESERVED BUCK2_PLDN BUCK2_VMON BUCK2_VSEL RESERVED BUCK2_FPWM BUCK2_EN
_EN
R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h

Table 8-30. BUCK2_CTRL Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 BUCK2_PLDN R/W 1h Enable output pull-down resistor when BUCK2 is disabled:
(Default from NVM memory)
0h = Pull-down resistor disabled
1h = Pull-down resistor enabled
4 BUCK2_VMON_EN R/W 0h Enable BUCK2 OV, UV, SC and ILIM comparators:
(Default from NVM memory)
0h = OV, UV, SC and ILIM comparators are disabled
1h = OV, UV, SC and ILIM comparators are enabled
3 BUCK2_VSEL R/W 0h Select output voltage register for BUCK2:
(Default from NVM memory)
0h = BUCK2_VOUT_1
1h = BUCK2_VOUT_2
2 RESERVED R/W 0h
1 BUCK2_FPWM R/W 1h Forces the BUCK2 regulator to operate in PWM mode:
(Default from NVM memory)
0h = Automatic transitions between PFM and PWM modes (AUTO
mode).
1h = Forced to PWM operation.
0 BUCK2_EN R/W 0h Enable BUCK2 regulator:
(Default from NVM memory)
0h = BUCK regulator is disabled
1h = BUCK regulator is enabled

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8.7.1.7 BUCK2_CONF Register (Offset = 7h) [Reset = 22h]

BUCK2_CONF is shown in Figure 8-68 and described in Table 8-31.
Return to the Summary Table.
Figure 8-68. BUCK2_CONF Register
7 6 5 4 3 2 1 0
RESERVED BUCK2_ILIM BUCK2_SLEW_RATE
R/W-0h R/W-4h R/W-2h

Table 8-31. BUCK2_CONF Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 BUCK2_ILIM R/W 4h Sets the switch peak current limit of BUCK2. Can be programmed at
any time during operation:
(Default from NVM memory)
0h = Reserved
1h = Reserved
2h = 2.5 A
3h = 3.5 A
4h = 4.5 A
5h = 5.5 A
6h = Reserved
7h = Reserved
2-0 BUCK2_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK2 regulator (rising and
falling edges):
(Default from NVM memory)
0h = 33 mV/μs
1h = 20 mV/μs
2h = 10 mV/μs
3h = 5.0 mV/μs
4h = 2.5 mV/μs
5h = 1.3 mV/μs
6h = 0.63 mV/μs
7h = 0.31 mV/μs

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8.7.1.8 BUCK3_CTRL Register (Offset = 8h) [Reset = 22h]

BUCK3_CTRL is shown in Figure 8-69 and described in Table 8-32.
Return to the Summary Table.
Figure 8-69. BUCK3_CTRL Register
7 6 5 4 3 2 1 0
RESERVED BUCK3_PLDN BUCK3_VMON BUCK3_VSEL BUCK3_FPWM BUCK3_FPWM BUCK3_EN
_EN _MP
R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h

Table 8-32. BUCK3_CTRL Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 BUCK3_PLDN R/W 1h Enable output pull-down resistor when BUCK3 is disabled:
(Default from NVM memory)
0h = Pull-down resistor disabled
1h = Pull-down resistor enabled
4 BUCK3_VMON_EN R/W 0h Enable BUCK3 OV, UV, SC and ILIM comparators:
(Default from NVM memory)
0h = OV, UV, SC and ILIM comparators are disabled
1h = OV, UV, SC and ILIM comparators are enabled
3 BUCK3_VSEL R/W 0h Select output voltage register for BUCK3:
(Default from NVM memory)
0h = BUCK3_VOUT_1
1h = BUCK3_VOUT_2
2 BUCK3_FPWM_MP R/W 0h Forces the BUCK3 regulator to operate always in multi-phase and
forced PWM operation mode:
(Default from NVM memory)
0h = Automatic phase adding and shedding.
1h = Forced to multi-phase operation, all phases in the multi-phase
configuration.
1 BUCK3_FPWM R/W 1h Forces the BUCK3 regulator to operate in PWM mode:
(Default from NVM memory)
0h = Automatic transitions between PFM and PWM modes (AUTO
mode).
1h = Forced to PWM operation.
0 BUCK3_EN R/W 0h Enable BUCK3 regulator:
(Default from NVM memory)
0h = BUCK regulator is disabled
1h = BUCK regulator is enabled

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8.7.1.9 BUCK3_CONF Register (Offset = 9h) [Reset = 22h]

BUCK3_CONF is shown in Figure 8-70 and described in Table 8-33.
Return to the Summary Table.
Figure 8-70. BUCK3_CONF Register
7 6 5 4 3 2 1 0
RESERVED BUCK3_ILIM BUCK3_SLEW_RATE
R/W-0h R/W-4h R/W-2h

Table 8-33. BUCK3_CONF Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 BUCK3_ILIM R/W 4h Sets the switch peak current limit of BUCK3. Can be programmed at
any time during operation:
(Default from NVM memory)
0h = Reserved
1h = Reserved
2h = 2.5 A
3h = 3.5 A
4h = 4.5 A
5h = 5.5 A
6h = Reserved
7h = Reserved
2-0 BUCK3_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK3 regulator (rising and
falling edges):
(Default from NVM memory)
0h = 33 mV/μs
1h = 20 mV/μs
2h = 10 mV/μs
3h = 5.0 mV/μs
4h = 2.5 mV/μs
5h = 1.3 mV/μs
6h = 0.63 mV/μs
7h = 0.31 mV/μs

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8.7.1.10 BUCK4_CTRL Register (Offset = Ah) [Reset = 22h]

BUCK4_CTRL is shown in Figure 8-71 and described in Table 8-34.
Return to the Summary Table.
Figure 8-71. BUCK4_CTRL Register
7 6 5 4 3 2 1 0
RESERVED BUCK4_PLDN BUCK4_VMON BUCK4_VSEL RESERVED BUCK4_FPWM BUCK4_EN
_EN
R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h

Table 8-34. BUCK4_CTRL Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 BUCK4_PLDN R/W 1h Enable output pull-down resistor when BUCK4 is disabled:
(Default from NVM memory)
0h = Pull-down resistor disabled
1h = Pull-down resistor enabled
4 BUCK4_VMON_EN R/W 0h Enable BUCK4 OV, UV, SC and ILIM comparators:
(Default from NVM memory)
0h = OV, UV, SC and ILIM comparators are disabled
1h = OV, UV, SC and ILIM comparators are enabled
3 BUCK4_VSEL R/W 0h Select output voltage register for BUCK4:
(Default from NVM memory)
0h = BUCK4_VOUT_1
1h = BUCK4_VOUT_2
2 RESERVED R/W 0h
1 BUCK4_FPWM R/W 1h Forces the BUCK4 regulator to operate in PWM mode:
(Default from NVM memory)
0h = Automatic transitions between PFM and PWM modes (AUTO
mode).
1h = Forced to PWM operation.
0 BUCK4_EN R/W 0h Enable BUCK4 regulator:
(Default from NVM memory)
0h = BUCK regulator is disabled
1h = BUCK regulator is enabled

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8.7.1.11 BUCK4_CONF Register (Offset = Bh) [Reset = 22h]

BUCK4_CONF is shown in Figure 8-72 and described in Table 8-35.
Return to the Summary Table.
Figure 8-72. BUCK4_CONF Register
7 6 5 4 3 2 1 0
RESERVED BUCK4_ILIM BUCK4_SLEW_RATE
R/W-0h R/W-4h R/W-2h

Table 8-35. BUCK4_CONF Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 BUCK4_ILIM R/W 4h Sets the switch peak current limit of BUCK4. Can be programmed at
any time during operation:
(Default from NVM memory)
0h = Reserved
1h = Reserved
2h = 2.5 A
3h = 3.5 A
4h = 4.5 A
5h = 5.5 A
6h = Reserved
7h = Reserved
2-0 BUCK4_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK4 regulator (rising and
falling edges):
(Default from NVM memory)
0h = 33 mV/μs
1h = 20 mV/μs
2h = 10 mV/μs
3h = 5.0 mV/μs
4h = 2.5 mV/μs
5h = 1.3 mV/μs
6h = 0.63 mV/μs
7h = 0.31 mV/μs

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8.7.1.12 BUCK5_CTRL Register (Offset = Ch) [Reset = 22h]

BUCK5_CTRL is shown in Figure 8-73 and described in Table 8-36.
Return to the Summary Table.
Figure 8-73. BUCK5_CTRL Register
7 6 5 4 3 2 1 0
RESERVED BUCK5_PLDN BUCK5_VMON BUCK5_VSEL RESERVED BUCK5_FPWM BUCK5_EN
_EN
R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h

Table 8-36. BUCK5_CTRL Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 BUCK5_PLDN R/W 1h Enable output pull-down resistor when BUCK5 is disabled:
(Default from NVM memory)
0h = Pull-down resistor disabled
1h = Pull-down resistor enabled
4 BUCK5_VMON_EN R/W 0h Enable BUCK5 OV, UV, SC and ILIM comparators:
(Default from NVM memory)
0h = OV, UV, SC and ILIM comparators are disabled
1h = OV, UV, SC and ILIM comparators are enabled
3 BUCK5_VSEL R/W 0h Select output voltage register for BUCK5:
(Default from NVM memory)
0h = BUCK5_VOUT_1
1h = BUCK5_VOUT_2
2 RESERVED R/W 0h
1 BUCK5_FPWM R/W 1h Forces the BUCK5 regulator to operate in PWM mode:
(Default from NVM memory)
0h = Automatic transitions between PFM and PWM modes (AUTO
mode).
1h = Forced to PWM operation.
0 BUCK5_EN R/W 0h Enable BUCK5 regulator:
(Default from NVM memory)
0h = BUCK regulator is disabled
1h = BUCK regulator is enabled

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8.7.1.13 BUCK5_CONF Register (Offset = Dh) [Reset = 22h]

BUCK5_CONF is shown in Figure 8-74 and described in Table 8-37.
Return to the Summary Table.
Figure 8-74. BUCK5_CONF Register
7 6 5 4 3 2 1 0
RESERVED BUCK5_ILIM BUCK5_SLEW_RATE
R/W-0h R/W-4h R/W-2h

Table 8-37. BUCK5_CONF Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 BUCK5_ILIM R/W 4h Sets the switch peak current limit of BUCK5. Can be programmed at
any time during operation:
(Default from NVM memory)
0h = Reserved
1h = Reserved
2h = 2.5 A
3h = 3.5 A
4h = Reserved
5h = Reserved
6h = Reserved
7h = Reserved
2-0 BUCK5_SLEW_RATE R/W 2h Sets the output voltage slew rate for BUCK5 regulator (rising and
falling edges):
(Default from NVM memory)
0h = 33 mV/μs
1h = 20 mV/μs
2h = 10 mV/μs
3h = 5.0 mV/μs
4h = 2.5 mV/μs
5h = 1.3 mV/μs
6h = 0.63 mV/μs
7h = 0.31 mV/μs

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8.7.1.14 BUCK1_VOUT_1 Register (Offset = Eh) [Reset = 00h]

BUCK1_VOUT_1 is shown in Figure 8-75 and described in Table 8-38.
Return to the Summary Table.
Figure 8-75. BUCK1_VOUT_1 Register
7 6 5 4 3 2 1 0
BUCK1_VSET1
R/W-0h

Table 8-38. BUCK1_VOUT_1 Register Field Descriptions

Bit Field Type Reset Description
7-0 BUCK1_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.15 BUCK1_VOUT_2 Register (Offset = Fh) [Reset = 00h]

BUCK1_VOUT_2 is shown in Figure 8-76 and described in Table 8-39.
Return to the Summary Table.
Figure 8-76. BUCK1_VOUT_2 Register
7 6 5 4 3 2 1 0
BUCK1_VSET2
R/W-0h

Table 8-39. BUCK1_VOUT_2 Register Field Descriptions

Bit Field Type Reset Description
7-0 BUCK1_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.16 BUCK2_VOUT_1 Register (Offset = 10h) [Reset = 00h]

BUCK2_VOUT_1 is shown in Figure 8-77 and described in Table 8-40.
Return to the Summary Table.
Figure 8-77. BUCK2_VOUT_1 Register
7 6 5 4 3 2 1 0
BUCK2_VSET1
R/W-0h

Table 8-40. BUCK2_VOUT_1 Register Field Descriptions

Bit Field Type Reset Description
7-0 BUCK2_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.17 BUCK2_VOUT_2 Register (Offset = 11h) [Reset = 00h]

BUCK2_VOUT_2 is shown in Figure 8-78 and described in Table 8-41.
Return to the Summary Table.
Figure 8-78. BUCK2_VOUT_2 Register
7 6 5 4 3 2 1 0
BUCK2_VSET2
R/W-0h

Table 8-41. BUCK2_VOUT_2 Register Field Descriptions

Bit Field Type Reset Description
7-0 BUCK2_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.18 BUCK3_VOUT_1 Register (Offset = 12h) [Reset = 00h]

BUCK3_VOUT_1 is shown in Figure 8-79 and described in Table 8-42.
Return to the Summary Table.
Figure 8-79. BUCK3_VOUT_1 Register
7 6 5 4 3 2 1 0
BUCK3_VSET1
R/W-0h

Table 8-42. BUCK3_VOUT_1 Register Field Descriptions

Bit Field Type Reset Description
7-0 BUCK3_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.19 BUCK3_VOUT_2 Register (Offset = 13h) [Reset = 00h]

BUCK3_VOUT_2 is shown in Figure 8-80 and described in Table 8-43.
Return to the Summary Table.
Figure 8-80. BUCK3_VOUT_2 Register
7 6 5 4 3 2 1 0
BUCK3_VSET2
R/W-0h

Table 8-43. BUCK3_VOUT_2 Register Field Descriptions

Bit Field Type Reset Description
7-0 BUCK3_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.20 BUCK4_VOUT_1 Register (Offset = 14h) [Reset = 00h]

BUCK4_VOUT_1 is shown in Figure 8-81 and described in Table 8-44.
Return to the Summary Table.
Figure 8-81. BUCK4_VOUT_1 Register
7 6 5 4 3 2 1 0
BUCK4_VSET1
R/W-0h

Table 8-44. BUCK4_VOUT_1 Register Field Descriptions

Bit Field Type Reset Description
7-0 BUCK4_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.21 BUCK4_VOUT_2 Register (Offset = 15h) [Reset = 00h]

BUCK4_VOUT_2 is shown in Figure 8-82 and described in Table 8-45.
Return to the Summary Table.
Figure 8-82. BUCK4_VOUT_2 Register
7 6 5 4 3 2 1 0
BUCK4_VSET2
R/W-0h

Table 8-45. BUCK4_VOUT_2 Register Field Descriptions

Bit Field Type Reset Description
7-0 BUCK4_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.22 BUCK5_VOUT_1 Register (Offset = 16h) [Reset = 00h]

BUCK5_VOUT_1 is shown in Figure 8-83 and described in Table 8-46.
Return to the Summary Table.
Figure 8-83. BUCK5_VOUT_1 Register
7 6 5 4 3 2 1 0
BUCK5_VSET1
R/W-0h

Table 8-46. BUCK5_VOUT_1 Register Field Descriptions

Bit Field Type Reset Description
7-0 BUCK5_VSET1 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.23 BUCK5_VOUT_2 Register (Offset = 17h) [Reset = 00h]

BUCK5_VOUT_2 is shown in Figure 8-84 and described in Table 8-47.
Return to the Summary Table.
Figure 8-84. BUCK5_VOUT_2 Register
7 6 5 4 3 2 1 0
BUCK5_VSET2
R/W-0h

Table 8-47. BUCK5_VOUT_2 Register Field Descriptions

Bit Field Type Reset Description
7-0 BUCK5_VSET2 R/W 0h Voltage selection for buck regulator. See Buck regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.24 BUCK1_PG_WINDOW Register (Offset = 18h) [Reset = 00h]

BUCK1_PG_WINDOW is shown in Figure 8-85 and described in Table 8-48.
Return to the Summary Table.
Figure 8-85. BUCK1_PG_WINDOW Register
7 6 5 4 3 2 1 0
RESERVED BUCK1_UV_THR BUCK1_OV_THR
R/W-0h R/W-0h R/W-0h

Table 8-48. BUCK1_PG_WINDOW Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 BUCK1_UV_THR R/W 0h Powergood low threshold level for BUCK1:
(Default from NVM memory)
0h = -3% / -30mV
1h = -3.5% / -35 mV
2h = -4% / -40 mV
3h = -5% / -50 mV
4h = -6% / -60 mV
5h = -7% / -70 mV
6h = -8% / -80 mV
7h = -10% / -100mV
2-0 BUCK1_OV_THR R/W 0h Powergood high threshold level for BUCK1:
(Default from NVM memory)
0h = +3% / +30mV
1h = +3.5% / +35 mV
2h = +4% / +40 mV
3h = +5% / +50 mV
4h = +6% / +60 mV
5h = +7% / +70 mV
6h = +8% / +80 mV
7h = +10% / +100mV

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8.7.1.25 BUCK2_PG_WINDOW Register (Offset = 19h) [Reset = 00h]

BUCK2_PG_WINDOW is shown in Figure 8-86 and described in Table 8-49.
Return to the Summary Table.
Figure 8-86. BUCK2_PG_WINDOW Register
7 6 5 4 3 2 1 0
RESERVED BUCK2_UV_THR BUCK2_OV_THR
R/W-0h R/W-0h R/W-0h

Table 8-49. BUCK2_PG_WINDOW Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 BUCK2_UV_THR R/W 0h Powergood low threshold level for BUCK2:
(Default from NVM memory)
0h = -3% / -30mV
1h = -3.5% / -35 mV
2h = -4% / -40 mV
3h = -5% / -50 mV
4h = -6% / -60 mV
5h = -7% / -70 mV
6h = -8% / -80 mV
7h = -10% / -100mV
2-0 BUCK2_OV_THR R/W 0h Powergood high threshold level for BUCK2:
(Default from NVM memory)
0h = +3% / +30mV
1h = +3.5% / +35 mV
2h = +4% / +40 mV
3h = +5% / +50 mV
4h = +6% / +60 mV
5h = +7% / +70 mV
6h = +8% / +80 mV
7h = +10% / +100mV

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8.7.1.26 BUCK3_PG_WINDOW Register (Offset = 1Ah) [Reset = 00h]

BUCK3_PG_WINDOW is shown in Figure 8-87 and described in Table 8-50.
Return to the Summary Table.
Figure 8-87. BUCK3_PG_WINDOW Register
7 6 5 4 3 2 1 0
RESERVED BUCK3_UV_THR BUCK3_OV_THR
R/W-0h R/W-0h R/W-0h

Table 8-50. BUCK3_PG_WINDOW Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 BUCK3_UV_THR R/W 0h Powergood low threshold level for BUCK3:
(Default from NVM memory)
0h = -3% / -30mV
1h = -3.5% / -35 mV
2h = -4% / -40 mV
3h = -5% / -50 mV
4h = -6% / -60 mV
5h = -7% / -70 mV
6h = -8% / -80 mV
7h = -10% / -100mV
2-0 BUCK3_OV_THR R/W 0h Powergood high threshold level for BUCK3:
(Default from NVM memory)
0h = +3% / +30mV
1h = +3.5% / +35 mV
2h = +4% / +40 mV
3h = +5% / +50 mV
4h = +6% / +60 mV
5h = +7% / +70 mV
6h = +8% / +80 mV
7h = +10% / +100mV

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8.7.1.27 BUCK4_PG_WINDOW Register (Offset = 1Bh) [Reset = 00h]

BUCK4_PG_WINDOW is shown in Figure 8-88 and described in Table 8-51.
Return to the Summary Table.
Figure 8-88. BUCK4_PG_WINDOW Register
7 6 5 4 3 2 1 0
RESERVED BUCK4_UV_THR BUCK4_OV_THR
R/W-0h R/W-0h R/W-0h

Table 8-51. BUCK4_PG_WINDOW Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 BUCK4_UV_THR R/W 0h Powergood low threshold level for BUCK4:
(Default from NVM memory)
0h = -3% / -30mV
1h = -3.5% / -35 mV
2h = -4% / -40 mV
3h = -5% / -50 mV
4h = -6% / -60 mV
5h = -7% / -70 mV
6h = -8% / -80 mV
7h = -10% / -100mV
2-0 BUCK4_OV_THR R/W 0h Powergood high threshold level for BUCK4:
(Default from NVM memory)
0h = +3% / +30mV
1h = +3.5% / +35 mV
2h = +4% / +40 mV
3h = +5% / +50 mV
4h = +6% / +60 mV
5h = +7% / +70 mV
6h = +8% / +80 mV
7h = +10% / +100mV

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8.7.1.28 BUCK5_PG_WINDOW Register (Offset = 1Ch) [Reset = 00h]

BUCK5_PG_WINDOW is shown in Figure 8-89 and described in Table 8-52.
Return to the Summary Table.
Figure 8-89. BUCK5_PG_WINDOW Register
7 6 5 4 3 2 1 0
RESERVED BUCK5_UV_THR BUCK5_OV_THR
R/W-0h R/W-0h R/W-0h

Table 8-52. BUCK5_PG_WINDOW Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 BUCK5_UV_THR R/W 0h Powergood low threshold level for BUCK5:
(Default from NVM memory)
0h = -3% / -30mV
1h = -3.5% / -35 mV
2h = -4% / -40 mV
3h = -5% / -50 mV
4h = -6% / -60 mV
5h = -7% / -70 mV
6h = -8% / -80 mV
7h = -10% / -100mV
2-0 BUCK5_OV_THR R/W 0h Powergood high threshold level for BUCK5:
(Default from NVM memory)
0h = +3% / +30mV
1h = +3.5% / +35 mV
2h = +4% / +40 mV
3h = +5% / +50 mV
4h = +6% / +60 mV
5h = +7% / +70 mV
6h = +8% / +80 mV
7h = +10% / +100mV

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8.7.1.29 LDO1_CTRL Register (Offset = 1Dh) [Reset = 60h]

LDO1_CTRL is shown in Figure 8-90 and described in Table 8-53.
Return to the Summary Table.
Figure 8-90. LDO1_CTRL Register
7 6 5 4 3 2 1 0
RESERVED LDO1_PLDN LDO1_VMON_ RESERVED LDO1_SLOW_ LDO1_EN
EN RAMP
R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-53. LDO1_CTRL Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-5 LDO1_PLDN R/W 3h Enable output pull-down resistor when LDO1 is disabled:
(Default from NVM memory)
0h = 50 kOhm
1h = 125 Ohm
2h = 250 Ohm
3h = 500 Ohm
4 LDO1_VMON_EN R/W 0h Enable LDO1 OV and UV comparators:
(Default from NVM memory)
0h = OV and UV comparators are disabled
1h = OV and UV comparators are enabled.
3-2 RESERVED R/W 0h
1 LDO1_SLOW_RAMP R/W 0h LDO1 start-up slew rate selection
0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to
90% of LDOn_VSET
1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to
90% of LDOn_VSET
0 LDO1_EN R/W 0h Enable LDO1 regulator:
(Default from NVM memory)
0h = LDO1 regulator is disabled
1h = LDO1 regulator is enabled.

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8.7.1.30 LDO2_CTRL Register (Offset = 1Eh) [Reset = 60h]

LDO2_CTRL is shown in Figure 8-91 and described in Table 8-54.
Return to the Summary Table.
Figure 8-91. LDO2_CTRL Register
7 6 5 4 3 2 1 0
RESERVED LDO2_PLDN LDO2_VMON_ RESERVED LDO2_SLOW_ LDO2_EN
EN RAMP
R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-54. LDO2_CTRL Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-5 LDO2_PLDN R/W 3h Enable output pull-down resistor when LDO2 is disabled:
(Default from NVM memory)
0h = 50 kOhm
1h = 125 Ohm
2h = 250 Ohm
3h = 500 Ohm
4 LDO2_VMON_EN R/W 0h Enable LDO2 OV and UV comparators:
(Default from NVM memory)
0h = OV and UV comparators are disabled
1h = OV and UV comparators are enabled.
3-2 RESERVED R/W 0h
1 LDO2_SLOW_RAMP R/W 0h LDO2 start-up slew rate selection
0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to
90% of LDOn_VSET
1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to
90% of LDOn_VSET
0 LDO2_EN R/W 0h Enable LDO2 regulator:
(Default from NVM memory)
0h = LDO1 regulator is disabled
1h = LDO1 regulator is enabled.

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8.7.1.31 LDO3_CTRL Register (Offset = 1Fh) [Reset = 60h]

LDO3_CTRL is shown in Figure 8-92 and described in Table 8-55.
Return to the Summary Table.
Figure 8-92. LDO3_CTRL Register
7 6 5 4 3 2 1 0
RESERVED LDO3_PLDN LDO3_VMON_ RESERVED LDO3_SLOW_ LDO3_EN
EN RAMP
R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-55. LDO3_CTRL Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-5 LDO3_PLDN R/W 3h Enable output pull-down resistor when LDO3 is disabled:
(Default from NVM memory)
0h = 50 kOhm
1h = 125 Ohm
2h = 250 Ohm
3h = 500 Ohm
4 LDO3_VMON_EN R/W 0h Enable LDO3 OV and UV comparators:
(Default from NVM memory)
0h = OV and UV comparators are disabled
1h = OV and UV comparators are enabled.
3-2 RESERVED R/W 0h
1 LDO3_SLOW_RAMP R/W 0h LDO3 start-up slew rate selection
0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to
90% of LDOn_VSET
1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to
90% of LDOn_VSET
0 LDO3_EN R/W 0h Enable LDO3 regulator:
(Default from NVM memory)
0h = LDO1 regulator is disabled
1h = LDO1 regulator is enabled.

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8.7.1.32 LDO4_CTRL Register (Offset = 20h) [Reset = 60h]

LDO4_CTRL is shown in Figure 8-93 and described in Table 8-56.
Return to the Summary Table.
Figure 8-93. LDO4_CTRL Register
7 6 5 4 3 2 1 0
RESERVED LDO4_PLDN LDO4_VMON_ RESERVED LDO4_SLOW_ LDO4_EN
EN RAMP
R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-56. LDO4_CTRL Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-5 LDO4_PLDN R/W 3h Enable output pull-down resistor when LDO4 is disabled:
(Default from NVM memory)
0h = 50 kOhm
1h = 125 Ohm
2h = 250 Ohm
3h = 500 Ohm
4 LDO4_VMON_EN R/W 0h Enable LDO4 OV and UV comparators:
(Default from NVM memory)
0h = OV and UV comparators are disabled
1h = OV and UV comparators are enabled.
3-2 RESERVED R/W 0h
1 LDO4_SLOW_RAMP R/W 0h LDO4 start-up slew rate selection
0h = 25mV/us max ramp up slew rate for LDO output from 0.3V to
90% of LDOn_VSET
1h = 3mV/us max ramp up slew rate for LDO output from 0.3V to
90% of LDOn_VSET
0 LDO4_EN R/W 0h Enable LDO4 regulator:
(Default from NVM memory)
0h = LDO1 regulator is disabled
1h = LDO1 regulator is enabled.

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8.7.1.33 LDORTC_CTRL Register (Offset = 22h) [Reset = 00h]

LDORTC_CTRL is shown in Figure 8-94 and described in Table 8-57.
Return to the Summary Table.
Figure 8-94. LDORTC_CTRL Register
7 6 5 4 3 2 1 0
RESERVED LDORTC_DIS
R/W-0h R/W-0h

Table 8-57. LDORTC_CTRL Register Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R/W 0h
0 LDORTC_DIS R/W 0h Disable LDORTC regulator:
0h = LDORTC regulator is enabled
1h = LDORTC regulator is disabled

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8.7.1.34 LDO1_VOUT Register (Offset = 23h) [Reset = 00h]

LDO1_VOUT is shown in Figure 8-95 and described in Table 8-58.
Return to the Summary Table.
Figure 8-95. LDO1_VOUT Register
7 6 5 4 3 2 1 0
LDO1_BYPASS LDO1_VSET RESERVED
R/W-0h R/W-0h R/W-0h

Table 8-58. LDO1_VOUT Register Field Descriptions

Bit Field Type Reset Description
7 LDO1_BYPASS R/W 0h Set LDO1 to bypass mode:
(Default from NVM memory)
0h = LDO is set to linear regulator mode.
1h = LDO is set to bypass mode.
6-1 LDO1_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for
voltage levels.
(Default from NVM memory)
0 RESERVED R/W 0h

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8.7.1.35 LDO2_VOUT Register (Offset = 24h) [Reset = 00h]

LDO2_VOUT is shown in Figure 8-96 and described in Table 8-59.
Return to the Summary Table.
Figure 8-96. LDO2_VOUT Register
7 6 5 4 3 2 1 0
LDO2_BYPASS LDO2_VSET RESERVED
R/W-0h R/W-0h R/W-0h

Table 8-59. LDO2_VOUT Register Field Descriptions

Bit Field Type Reset Description
7 LDO2_BYPASS R/W 0h Set LDO2 to bypass mode:
(Default from NVM memory)
0h = LDO is set to linear regulator mode.
1h = LDO is set to bypass mode.
6-1 LDO2_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for
voltage levels.
(Default from NVM memory)
0 RESERVED R/W 0h

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8.7.1.36 LDO3_VOUT Register (Offset = 25h) [Reset = 00h]

LDO3_VOUT is shown in Figure 8-97 and described in Table 8-60.
Return to the Summary Table.
Figure 8-97. LDO3_VOUT Register
7 6 5 4 3 2 1 0
LDO3_BYPASS LDO3_VSET RESERVED
R/W-0h R/W-0h R/W-0h

Table 8-60. LDO3_VOUT Register Field Descriptions

Bit Field Type Reset Description
7 LDO3_BYPASS R/W 0h Set LDO3 to bypass mode:
(Default from NVM memory)
0h = LDO is set to linear regulator mode.
1h = LDO is set to bypass mode.
6-1 LDO3_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for
voltage levels.
(Default from NVM memory)
0 RESERVED R/W 0h

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8.7.1.37 LDO4_VOUT Register (Offset = 26h) [Reset = 00h]

LDO4_VOUT is shown in Figure 8-98 and described in Table 8-61.
Return to the Summary Table.
Figure 8-98. LDO4_VOUT Register
7 6 5 4 3 2 1 0
RESERVED LDO4_VSET
R/W-0h R/W-0h

Table 8-61. LDO4_VOUT Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-0 LDO4_VSET R/W 0h Voltage selection for LDO regulator. See LDO regulators chapter for
voltage levels.
(Default from NVM memory)

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8.7.1.38 LDO1_PG_WINDOW Register (Offset = 27h) [Reset = 00h]

LDO1_PG_WINDOW is shown in Figure 8-99 and described in Table 8-62.
Return to the Summary Table.
Figure 8-99. LDO1_PG_WINDOW Register
7 6 5 4 3 2 1 0
RESERVED LDO1_UV_THR LDO1_OV_THR
R/W-0h R/W-0h R/W-0h

Table 8-62. LDO1_PG_WINDOW Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 LDO1_UV_THR R/W 0h Powergood low threshold level for LDO1:
(Default from NVM memory)
0h = -3% / -30mV
1h = -3.5% / -35 mV
2h = -4% / -40 mV
3h = -5% / -50 mV
4h = -6% / -60 mV
5h = -7% / -70 mV
6h = -8% / -80 mV
7h = -10% / -100mV
2-0 LDO1_OV_THR R/W 0h Powergood high threshold level for LDO1:
(Default from NVM memory)
0h = +3% / +30mV
1h = +3.5% / +35 mV
2h = +4% / +40 mV
3h = +5% / +50 mV
4h = +6% / +60 mV
5h = +7% / +70 mV
6h = +8% / +80 mV
7h = +10% / +100mV

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8.7.1.39 LDO2_PG_WINDOW Register (Offset = 28h) [Reset = 00h]

LDO2_PG_WINDOW is shown in Figure 8-100 and described in Table 8-63.
Return to the Summary Table.
Figure 8-100. LDO2_PG_WINDOW Register
7 6 5 4 3 2 1 0
RESERVED LDO2_UV_THR LDO2_OV_THR
R/W-0h R/W-0h R/W-0h

Table 8-63. LDO2_PG_WINDOW Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 LDO2_UV_THR R/W 0h Powergood low threshold level for LDO2:
(Default from NVM memory)
0h = -3% / -30mV
1h = -3.5% / -35 mV
2h = -4% / -40 mV
3h = -5% / -50 mV
4h = -6% / -60 mV
5h = -7% / -70 mV
6h = -8% / -80 mV
7h = -10% / -100mV
2-0 LDO2_OV_THR R/W 0h Powergood high threshold level for LDO2:
(Default from NVM memory)
0h = +3% / +30mV
1h = +3.5% / +35 mV
2h = +4% / +40 mV
3h = +5% / +50 mV
4h = +6% / +60 mV
5h = +7% / +70 mV
6h = +8% / +80 mV
7h = +10% / +100mV

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8.7.1.40 LDO3_PG_WINDOW Register (Offset = 29h) [Reset = 00h]

LDO3_PG_WINDOW is shown in Figure 8-101 and described in Table 8-64.
Return to the Summary Table.
Figure 8-101. LDO3_PG_WINDOW Register
7 6 5 4 3 2 1 0
RESERVED LDO3_UV_THR LDO3_OV_THR
R/W-0h R/W-0h R/W-0h

Table 8-64. LDO3_PG_WINDOW Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 LDO3_UV_THR R/W 0h Powergood low threshold level for LDO3:
(Default from NVM memory)
0h = -3% / -30mV
1h = -3.5% / -35 mV
2h = -4% / -40 mV
3h = -5% / -50 mV
4h = -6% / -60 mV
5h = -7% / -70 mV
6h = -8% / -80 mV
7h = -10% / -100mV
2-0 LDO3_OV_THR R/W 0h Powergood high threshold level for LDO3:
Default from NVM memory)
0h = +3% / +30mV
1h = +3.5% / +35 mV
2h = +4% / +40 mV
3h = +5% / +50 mV
4h = +6% / +60 mV
5h = +7% / +70 mV
6h = +8% / +80 mV
7h = +10% / +100mV

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8.7.1.41 LDO4_PG_WINDOW Register (Offset = 2Ah) [Reset = 00h]

LDO4_PG_WINDOW is shown in Figure 8-102 and described in Table 8-65.
Return to the Summary Table.
Figure 8-102. LDO4_PG_WINDOW Register
7 6 5 4 3 2 1 0
RESERVED LDO4_UV_THR LDO4_OV_THR
R/W-0h R/W-0h R/W-0h

Table 8-65. LDO4_PG_WINDOW Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-3 LDO4_UV_THR R/W 0h Powergood low threshold level for LDO4:
(Default from NVM memory)
0h = -3% / -30mV
1h = -3.5% / -35 mV
2h = -4% / -40 mV
3h = -5% / -50 mV
4h = -6% / -60 mV
5h = -7% / -70 mV
6h = -8% / -80 mV
7h = -10% / -100mV
2-0 LDO4_OV_THR R/W 0h Powergood high threshold level for LDO4:
(Default from NVM memory)
0h = +3% / +30mV
1h = +3.5% / +35 mV
2h = +4% / +40 mV
3h = +5% / +50 mV
4h = +6% / +60 mV
5h = +7% / +70 mV
6h = +8% / +80 mV
7h = +10% / +100mV

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8.7.1.42 VCCA_VMON_CTRL Register (Offset = 2Bh) [Reset = 00h]

VCCA_VMON_CTRL is shown in Figure 8-103 and described in Table 8-66.
Return to the Summary Table.
Figure 8-103. VCCA_VMON_CTRL Register
7 6 5 4 3 2 1 0
RESERVED VMON_DEGLIT RESERVED VCCA_VMON_
CH_SEL EN
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-66. VCCA_VMON_CTRL Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 VMON_DEGLITCH_SEL R/W 0h Deglitch time select for BUCKx_VMON, LDOx_VMON and
VCCA_VMON
(Default from NVM memory)
0h = 4 us
1h = 20 us
4-1 RESERVED R/W 0h
0 VCCA_VMON_EN R/W 0h Enable VCCA OV and UV comparators:
(Default from NVM memory)
0h = OV and UV comparators are disabled
1h = OV and UV comparators are enabled.

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8.7.1.43 VCCA_PG_WINDOW Register (Offset = 2Ch) [Reset = 40h]

VCCA_PG_WINDOW is shown in Figure 8-104 and described in Table 8-67.
Return to the Summary Table.
Figure 8-104. VCCA_PG_WINDOW Register
7 6 5 4 3 2 1 0
RESERVED VCCA_PG_SE VCCA_UV_THR VCCA_OV_THR
T
R/W-0h R/W-1h R/W-0h R/W-0h

Table 8-67. VCCA_PG_WINDOW Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6 VCCA_PG_SET R/W 1h Powergood level for VCCA pin:
(Default from NVM memory)
0h = 3.3 V
1h = 5.0 V
5-3 VCCA_UV_THR R/W 0h Powergood low threshold level for VCCA pin:
(Default from NVM memory)
0h = -3%
1h = -3.5%
2h = -4%
3h = -5%
4h = -6%
5h = -7%
6h = -8%
7h = -10%
2-0 VCCA_OV_THR R/W 0h Powergood high threshold level for VCCA pin:
(Default from NVM memory)
0h = +3%
1h = +3.5%
2h = +4%
3h = +5%
4h = +6%
5h = +7%
6h = +8%
7h = +10%

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8.7.1.44 GPIO1_CONF Register (Offset = 31h) [Reset = 0Ah]

GPIO1_CONF is shown in Figure 8-105 and described in Table 8-68.
Return to the Summary Table.
Figure 8-105. GPIO1_CONF Register
7 6 5 4 3 2 1 0
GPIO1_SEL GPIO1_DEGLIT GPIO1_PU_PD GPIO1_PU_SE GPIO1_OD GPIO1_DIR
CH_EN _EN L
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-68. GPIO1_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO1_SEL R/W 0h GPIO1 signal function:
(Default from NVM memory)
0h = GPIO1
1h = SCL_I2C2/CS_SPI
2h = NRSTOUT_SOC
3h = NRSTOUT_SOC
4h = NSLEEP1
5h = NSLEEP2
6h = WKUP1
7h = WKUP2
4 GPIO1_DEGLITCH_EN R/W 0h GPIO1 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO1_PU_PD_EN R/W 1h Control for GPIO1 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO1_PU_SEL R/W 0h Control for GPIO1 pin pull-up/pull-down resistor:
GPIO1_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO1_OD R/W 1h GPIO1 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO1_DIR R/W 0h GPIO1 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.45 GPIO2_CONF Register (Offset = 32h) [Reset = 0Ah]

GPIO2_CONF is shown in Figure 8-106 and described in Table 8-69.
Return to the Summary Table.
Figure 8-106. GPIO2_CONF Register
7 6 5 4 3 2 1 0
GPIO2_SEL GPIO2_DEGLIT GPIO2_PU_PD GPIO2_PU_SE GPIO2_OD GPIO2_DIR
CH_EN _EN L
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-69. GPIO2_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO2_SEL R/W 0h GPIO2 signal function:
(Default from NVM memory)
0h = GPIO2
1h = TRIG_WDOG
2h = SDA_I2C2/SDO_SPI
3h = SDA_I2C2/SDO_SPI
4h = NSLEEP1
5h = NSLEEP2
6h = WKUP1
7h = WKUP2
4 GPIO2_DEGLITCH_EN R/W 0h GPIO2 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO2_PU_PD_EN R/W 1h Control for GPIO2 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO2_PU_SEL R/W 0h Control for GPIO2 pin pull-up/pull-down resistor:
GPIO2_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO2_OD R/W 1h GPIO2 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO2_DIR R/W 0h GPIO2 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.46 GPIO3_CONF Register (Offset = 33h) [Reset = 0Ah]

GPIO3_CONF is shown in Figure 8-107 and described in Table 8-70.
Return to the Summary Table.
Figure 8-107. GPIO3_CONF Register
7 6 5 4 3 2 1 0
GPIO3_SEL GPIO3_DEGLIT GPIO3_PU_PD GPIO3_PU_SE GPIO3_OD GPIO3_DIR
CH_EN _EN L
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-70. GPIO3_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO3_SEL R/W 0h GPIO3 signal function:
(Default from NVM memory)
0h = GPIO3
1h = CLK32KOUT
2h = NERR_SOC
3h = NERR_SOC
4h = NSLEEP1
5h = NSLEEP2
6h = LP_WKUP1
7h = LP_WKUP2
4 GPIO3_DEGLITCH_EN R/W 0h GPIO3 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO3_PU_PD_EN R/W 1h Control for GPIO3 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO3_PU_SEL R/W 0h Control for GPIO3 pin pull-up/pull-down resistor:
GPIO3_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO3_OD R/W 1h GPIO3 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO3_DIR R/W 0h GPIO3 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.47 GPIO4_CONF Register (Offset = 34h) [Reset = 0Ah]

GPIO4_CONF is shown in Figure 8-108 and described in Table 8-71.
Return to the Summary Table.
Figure 8-108. GPIO4_CONF Register
7 6 5 4 3 2 1 0
GPIO4_SEL GPIO4_DEGLIT GPIO4_PU_PD GPIO4_PU_SE GPIO4_OD GPIO4_DIR
CH_EN _EN L
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-71. GPIO4_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO4_SEL R/W 0h GPIO4 signal function:
(Default from NVM memory)
0h = GPIO4
1h = CLK32KOUT
2h = CLK32KOUT
3h = CLK32KOUT
4h = NSLEEP1
5h = NSLEEP2
6h = LP_WKUP1
7h = LP_WKUP2
4 GPIO4_DEGLITCH_EN R/W 0h GPIO4 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO4_PU_PD_EN R/W 1h Control for GPIO4 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO4_PU_SEL R/W 0h Control for GPIO4 pin pull-up/pull-down resistor:
GPIO4_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO4_OD R/W 1h GPIO4 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO4_DIR R/W 0h GPIO4 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.48 GPIO5_CONF Register (Offset = 35h) [Reset = 0Ah]

GPIO5_CONF is shown in Figure 8-109 and described in Table 8-72.
Return to the Summary Table.
Figure 8-109. GPIO5_CONF Register
7 6 5 4 3 2 1 0
GPIO5_SEL GPIO5_DEGLIT GPIO5_PU_PD GPIO5_PU_SE GPIO5_OD GPIO5_DIR
CH_EN _EN L
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-72. GPIO5_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO5_SEL R/W 0h GPIO5 signal function:
(Default from NVM memory)
0h = GPIO5
1h = SCLK_SPMI
2h = SCLK_SPMI
3h = SCLK_SPMI
4h = NSLEEP1
5h = NSLEEP2
6h = WKUP1
7h = WKUP2
4 GPIO5_DEGLITCH_EN R/W 0h GPIO5 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO5_PU_PD_EN R/W 1h Control for GPIO5 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO5_PU_SEL R/W 0h Control for GPIO5 pin pull-up/pull-down resistor:
GPIO5_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO5_OD R/W 1h GPIO5 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO5_DIR R/W 0h GPIO5 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.49 GPIO6_CONF Register (Offset = 36h) [Reset = 0Ah]

GPIO6_CONF is shown in Figure 8-110 and described in Table 8-73.
Return to the Summary Table.
Figure 8-110. GPIO6_CONF Register
7 6 5 4 3 2 1 0
GPIO6_SEL GPIO6_DEGLIT GPIO6_PU_PD GPIO6_PU_SE GPIO6_OD GPIO6_DIR
CH_EN _EN L
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-73. GPIO6_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO6_SEL R/W 0h GPIO6 signal function:
(Default from NVM memory)
0h = GPIO6
1h = SDATA_SPMI
2h = SDATA_SPMI
3h = SDATA_SPMI
4h = NSLEEP1
5h = NSLEEP2
6h = WKUP1
7h = WKUP2
4 GPIO6_DEGLITCH_EN R/W 0h GPIO6 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO6_PU_PD_EN R/W 1h Control for GPIO6 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO6_PU_SEL R/W 0h Control for GPIO6 pin pull-up/pull-down resistor:
GPIO6_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO6_OD R/W 1h GPIO6 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO6_DIR R/W 0h GPIO6 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.50 GPIO7_CONF Register (Offset = 37h) [Reset = 0Ah]

GPIO7_CONF is shown in Figure 8-111 and described in Table 8-74.
Return to the Summary Table.
Figure 8-111. GPIO7_CONF Register
7 6 5 4 3 2 1 0
GPIO7_SEL GPIO7_DEGLIT GPIO7_PU_PD GPIO7_PU_SE GPIO7_OD GPIO7_DIR
CH_EN _EN L
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-74. GPIO7_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO7_SEL R/W 0h GPIO7 signal function:
(Default from NVM memory)
0h = GPIO7
1h = NERR_MCU
2h = NERR_MCU
3h = NERR_MCU
4h = NSLEEP1
5h = NSLEEP2
6h = WKUP1
7h = WKUP2
4 GPIO7_DEGLITCH_EN R/W 0h GPIO7 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO7_PU_PD_EN R/W 1h Control for GPIO7 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO7_PU_SEL R/W 0h Control for GPIO7 pin pull-up/pull-down resistor:
GPIO7_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO7_OD R/W 1h GPIO7 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO7_DIR R/W 0h GPIO7 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.51 GPIO8_CONF Register (Offset = 38h) [Reset = 0Ah]

GPIO8_CONF is shown in Figure 8-112 and described in Table 8-75.
Return to the Summary Table.
Figure 8-112. GPIO8_CONF Register
7 6 5 4 3 2 1 0
GPIO8_SEL GPIO8_DEGLIT GPIO8_PU_PD GPIO8_PU_SE GPIO8_OD GPIO8_DIR
CH_EN _EN L
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-75. GPIO8_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO8_SEL R/W 0h GPIO8 signal function:
(Default from NVM memory)
0h = GPIO8
1h = CLK32KOUT
2h = SYNCCLKOUT
3h = DISABLE_WDOG
4h = NSLEEP1
5h = NSLEEP2
6h = WKUP1
7h = WKUP2
4 GPIO8_DEGLITCH_EN R/W 0h GPIO8 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO8_PU_PD_EN R/W 1h Control for GPIO8 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO8_PU_SEL R/W 0h Control for GPIO8 pin pull-up/pull-down resistor:
GPIO8_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO8_OD R/W 1h GPIO8 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO8_DIR R/W 0h GPIO8 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.52 GPIO9_CONF Register (Offset = 39h) [Reset = 0Ah]

GPIO9_CONF is shown in Figure 8-113 and described in Table 8-76.
Return to the Summary Table.
Figure 8-113. GPIO9_CONF Register
7 6 5 4 3 2 1 0
GPIO9_SEL GPIO9_DEGLIT GPIO9_PU_PD GPIO9_PU_SE GPIO9_OD GPIO9_DIR
CH_EN _EN L
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-76. GPIO9_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO9_SEL R/W 0h GPIO9 signal function:
(Default from NVM memory)
0h = GPIO9
1h = PGOOD
2h = DISABLE_WDOG
3h = SYNCCLKOUT
4h = NSLEEP1
5h = NSLEEP2
6h = WKUP1
7h = WKUP2
4 GPIO9_DEGLITCH_EN R/W 0h GPIO9 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO9_PU_PD_EN R/W 1h Control for GPIO9 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO9_PU_SEL R/W 0h Control for GPIO9 pin pull-up/pull-down resistor:
GPIO9_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO9_OD R/W 1h GPIO9 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO9_DIR R/W 0h GPIO9 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.53 GPIO10_CONF Register (Offset = 3Ah) [Reset = 0Ah]

GPIO10_CONF is shown in Figure 8-114 and described in Table 8-77.
Return to the Summary Table.
Figure 8-114. GPIO10_CONF Register
7 6 5 4 3 2 1 0
GPIO10_SEL GPIO10_DEGLI GPIO10_PU_P GPIO10_PU_S GPIO10_OD GPIO10_DIR
TCH_EN D_EN EL
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-77. GPIO10_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO10_SEL R/W 0h GPIO10 signal function:
(Default from NVM memory)
0h = GPIO10
1h = SYNCCLKIN
2h = SYNCCLKOUT
3h = CLK32KOUT
4h = NSLEEP1
5h = NSLEEP2
6h = WKUP1
7h = WKUP2
4 GPIO10_DEGLITCH_EN R/W 0h GPIO10 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO10_PU_PD_EN R/W 1h Control for GPIO10 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO10_PU_SEL R/W 0h Control for GPIO10 pin pull-up/pull-down resistor:
GPIO10_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO10_OD R/W 1h GPIO10 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO10_DIR R/W 0h GPIO10 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.54 GPIO11_CONF Register (Offset = 3Bh) [Reset = 0Ah]

GPIO11_CONF is shown in Figure 8-115 and described in Table 8-78.
Return to the Summary Table.
Figure 8-115. GPIO11_CONF Register
7 6 5 4 3 2 1 0
GPIO11_SEL GPIO11_DEGLI GPIO11_PU_P GPIO11_PU_S GPIO11_OD GPIO11_DIR
TCH_EN D_EN EL
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h

Table 8-78. GPIO11_CONF Register Field Descriptions

Bit Field Type Reset Description
7-5 GPIO11_SEL R/W 0h GPIO11 signal function:
(Default from NVM memory)
0h = GPIO11
1h = TRIG_WDOG
2h = NRSTOUT_SOC
3h = NRSTOUT_SOC
4h = NSLEEP1
5h = NSLEEP2
6h = WKUP1
7h = WKUP2
4 GPIO11_DEGLITCH_EN R/W 0h GPIO11 signal deglitch time when signal direction is input:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time.
3 GPIO11_PU_PD_EN R/W 1h Control for GPIO11 pin pull-up/pull-down resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 GPIO11_PU_SEL R/W 0h Control for GPIO11 pin pull-up/pull-down resistor:
GPIO11_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 GPIO11_OD R/W 1h GPIO11 signal type when configured to output:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output
0 GPIO11_DIR R/W 0h GPIO11 signal direction:
(Default from NVM memory)
0h = Input
1h = Output

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8.7.1.55 NPWRON_CONF Register (Offset = 3Ch) [Reset = 88h]

NPWRON_CONF is shown in Figure 8-116 and described in Table 8-79.
Return to the Summary Table.
Figure 8-116. NPWRON_CONF Register
7 6 5 4 3 2 1 0
NPWRON_SEL ENABLE_POL ENABLE_DEGL ENABLE_PU_P ENABLE_PU_S RESERVED NRSTOUT_OD
ITCH_EN D_EN EL
R/W-2h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h

Table 8-79. NPWRON_CONF Register Field Descriptions

Bit Field Type Reset Description
7-6 NPWRON_SEL R/W 2h NPWRON/ENABLE signal function:
(Default from NVM memory)
0h = ENABLE
1h = NPWRON
2h = None
3h = None
5 ENABLE_POL R/W 0h Control for ENABLE pin polarity:
(Default from NVM memory)
0h = Active high
1h = Active low
4 ENABLE_DEGLITCH_EN R/W 0h NPWRON/ENABLE signal deglitch time:
(Default from NVM memory)
0h = No deglitch, only synchronization.
1h = 8 us deglitch time when ENABLE, 50 ms deglitch time when
NPWRON.
3 ENABLE_PU_PD_EN R/W 1h Control for NPWRON/ENABLE pin pull-up resistor:
(Default from NVM memory)
0h = Pull-up/pull-down resistor disabled
1h = Pull-up/pull-down resistor enabled
2 ENABLE_PU_SEL R/W 0h Control for NPWRON/ENABLE pin pull-down resistor:
ENABLE_PU_PD_EN must be 1 to select the resistor.
(Default from NVM memory)
0h = Pull-down resistor selected
1h = Pull-up resistor selected
1 RESERVED R/W 0h
0 NRSTOUT_OD R/W 0h NRSTOUT signal type:
(Default from NVM memory)
0h = Push-pull output
1h = Open-drain output

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8.7.1.56 GPIO_OUT_1 Register (Offset = 3Dh) [Reset = 00h]

GPIO_OUT_1 is shown in Figure 8-117 and described in Table 8-80.
Return to the Summary Table.
Figure 8-117. GPIO_OUT_1 Register
7 6 5 4 3 2 1 0
GPIO8_OUT GPIO7_OUT GPIO6_OUT GPIO5_OUT GPIO4_OUT GPIO3_OUT GPIO2_OUT GPIO1_OUT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-80. GPIO_OUT_1 Register Field Descriptions

Bit Field Type Reset Description
7 GPIO8_OUT R/W 0h Control for GPIO8 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High
6 GPIO7_OUT R/W 0h Control for GPIO7 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High
5 GPIO6_OUT R/W 0h Control for GPIO6 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High
4 GPIO5_OUT R/W 0h Control for GPIO5 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High
3 GPIO4_OUT R/W 0h Control for GPIO4 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High
2 GPIO3_OUT R/W 0h Control for GPIO3 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High
1 GPIO2_OUT R/W 0h Control for GPIO2 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High
0 GPIO1_OUT R/W 0h Control for GPIO1 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High

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8.7.1.57 GPIO_OUT_2 Register (Offset = 3Eh) [Reset = 00h]

GPIO_OUT_2 is shown in Figure 8-118 and described in Table 8-81.
Return to the Summary Table.
Figure 8-118. GPIO_OUT_2 Register
7 6 5 4 3 2 1 0
RESERVED GPIO11_OUT GPIO10_OUT GPIO9_OUT
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-81. GPIO_OUT_2 Register Field Descriptions

Bit Field Type Reset Description
7-3 RESERVED R/W 0h
2 GPIO11_OUT R/W 0h Control for GPIO11 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High
1 GPIO10_OUT R/W 0h Control for GPIO10 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High
0 GPIO9_OUT R/W 0h Control for GPIO9 signal when configured to GPIO Output:
(Default from NVM memory)
0h = Low
1h = High

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8.7.1.58 GPIO_IN_1 Register (Offset = 3Fh) [Reset = 00h]

GPIO_IN_1 is shown in Figure 8-119 and described in Table 8-82.
Return to the Summary Table.
Figure 8-119. GPIO_IN_1 Register
7 6 5 4 3 2 1 0
GPIO8_IN GPIO7_IN GPIO6_IN GPIO5_IN GPIO4_IN GPIO3_IN GPIO2_IN GPIO1_IN
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-82. GPIO_IN_1 Register Field Descriptions

Bit Field Type Reset Description
7 GPIO8_IN R 0h Level of GPIO8 signal:
0h = Low
1h = High
6 GPIO7_IN R 0h Level of GPIO7 signal:
0h = Low
1h = High
5 GPIO6_IN R 0h Level of GPIO6 signal:
0h = Low
1h = High
4 GPIO5_IN R 0h Level of GPIO5 signal:
0h = Low
1h = High
3 GPIO4_IN R 0h Level of GPIO4 signal:
0h = Low
1h = High
2 GPIO3_IN R 0h Level of GPIO3 signal:
0h = Low
1h = High
1 GPIO2_IN R 0h Level of GPIO2 signal:
0h = Low
1h = High
0 GPIO1_IN R 0h Level of GPIO1 signal:
0h = Low
1h = High

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8.7.1.59 GPIO_IN_2 Register (Offset = 40h) [Reset = 00h]

GPIO_IN_2 is shown in Figure 8-120 and described in Table 8-83.
Return to the Summary Table.
Figure 8-120. GPIO_IN_2 Register
7 6 5 4 3 2 1 0
RESERVED NPWRON_IN GPIO11_IN GPIO10_IN GPIO9_IN
R-0h R-0h R-0h R-0h R-0h

Table 8-83. GPIO_IN_2 Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R 0h
3 NPWRON_IN R 0h Level of NPWRON/ENABLE signal:
0h = Low
1h = High
2 GPIO11_IN R 0h Level of GPIO11 signal:
0h = Low
1h = High
1 GPIO10_IN R 0h Level of GPIO10 signal:
0h = Low
1h = High
0 GPIO9_IN R 0h Level of GPIO9 signal:
0h = Low
1h = High

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8.7.1.60 RAIL_SEL_1 Register (Offset = 41h) [Reset = 00h]

RAIL_SEL_1 is shown in Figure 8-121 and described in Table 8-84.
Return to the Summary Table.
Figure 8-121. RAIL_SEL_1 Register
7 6 5 4 3 2 1 0
BUCK4_GRP_SEL BUCK3_GRP_SEL BUCK2_GRP_SEL BUCK1_GRP_SEL
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-84. RAIL_SEL_1 Register Field Descriptions

Bit Field Type Reset Description
7-6 BUCK4_GRP_SEL R/W 0h Rail group selection for BUCK4:
(Default from NVM memory)
0h = No group assigned
1h = MCU rail group
2h = SOC rail group
3h = OTHER rail group
5-4 BUCK3_GRP_SEL R/W 0h Rail group selection for BUCK3:
(Default from NVM memory)
0h = No group assigned
1h = MCU rail group
2h = SOC rail group
3h = OTHER rail group
3-2 BUCK2_GRP_SEL R/W 0h Rail group selection for BUCK2:
(Default from NVM memory)
0h = No group assigned
1h = MCU rail group
2h = SOC rail group
3h = OTHER rail group
1-0 BUCK1_GRP_SEL R/W 0h Rail group selection for BUCK1:
(Default from NVM memory)
0h = No group assigned
1h = MCU rail group
2h = SOC rail group
3h = OTHER rail group

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8.7.1.61 RAIL_SEL_2 Register (Offset = 42h) [Reset = 00h]

RAIL_SEL_2 is shown in Figure 8-122 and described in Table 8-85.
Return to the Summary Table.
Figure 8-122. RAIL_SEL_2 Register
7 6 5 4 3 2 1 0
LDO3_GRP_SEL LDO2_GRP_SEL LDO1_GRP_SEL BUCK5_GRP_SEL
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-85. RAIL_SEL_2 Register Field Descriptions

Bit Field Type Reset Description
7-6 LDO3_GRP_SEL R/W 0h Rail group selection for LDO3:
(Default from NVM memory)
0h = No group assigned
1h = MCU rail group
2h = SOC rail group
3h = OTHER rail group
5-4 LDO2_GRP_SEL R/W 0h Rail group selection for LDO2:
(Default from NVM memory)
0h = No group assigned
1h = MCU rail group
2h = SOC rail group
3h = OTHER rail group
3-2 LDO1_GRP_SEL R/W 0h Rail group selection for LDO1:
(Default from NVM memory)
0h = No group assigned
1h = MCU rail group
2h = SOC rail group
3h = OTHER rail group
1-0 BUCK5_GRP_SEL R/W 0h Rail group selection for BUCK5:
(Default from NVM memory)
0h = No group assigned
1h = MCU rail group
2h = SOC rail group
3h = OTHER rail group

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8.7.1.62 RAIL_SEL_3 Register (Offset = 43h) [Reset = 00h]

RAIL_SEL_3 is shown in Figure 8-123 and described in Table 8-86.
Return to the Summary Table.
Figure 8-123. RAIL_SEL_3 Register
7 6 5 4 3 2 1 0
RESERVED VCCA_GRP_SEL LDO4_GRP_SEL
R/W-0h R/W-0h R/W-0h

Table 8-86. RAIL_SEL_3 Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3-2 VCCA_GRP_SEL R/W 0h Rail group selection for VCCA monitoring:
(Default from NVM memory)
0h = No group assigned
1h = MCU rail group
2h = SOC rail group
3h = OTHER rail group
1-0 LDO4_GRP_SEL R/W 0h Rail group selection for LDO4:
(Default from NVM memory)
0h = No group assigned
1h = MCU rail group
2h = SOC rail group
3h = OTHER rail group

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8.7.1.63 FSM_TRIG_SEL_1 Register (Offset = 44h) [Reset = 00h]

FSM_TRIG_SEL_1 is shown in Figure 8-124 and described in Table 8-87.
Return to the Summary Table.
Figure 8-124. FSM_TRIG_SEL_1 Register
7 6 5 4 3 2 1 0
SEVERE_ERR_TRIG OTHER_RAIL_TRIG SOC_RAIL_TRIG MCU_RAIL_TRIG
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-87. FSM_TRIG_SEL_1 Register Field Descriptions

Bit Field Type Reset Description
7-6 SEVERE_ERR_TRIG R/W 0h Trigger selection for Severe Error:
(Default from NVM memory)
0h = Immediate shutdown
1h = Orderly shutdown
2h = MCU power error
3h = SOC power error
5-4 OTHER_RAIL_TRIG R/W 0h Trigger selection for OTHER rail group:
(Default from NVM memory)
0h = Immediate shutdown
1h = Orderly shutdown
2h = MCU power error
3h = SOC power error
3-2 SOC_RAIL_TRIG R/W 0h Trigger selection for SOC rail group:
(Default from NVM memory)
0h = Immediate shutdown
1h = Orderly shutdown
2h = MCU power error
3h = SOC power error
1-0 MCU_RAIL_TRIG R/W 0h Trigger selection for MCU rail group:
(Default from NVM memory)
0h = Immediate shutdown
1h = Orderly shutdown
2h = MCU power error
3h = SOC power error

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8.7.1.64 FSM_TRIG_SEL_2 Register (Offset = 45h) [Reset = 00h]

FSM_TRIG_SEL_2 is shown in Figure 8-125 and described in Table 8-88.
Return to the Summary Table.
Figure 8-125. FSM_TRIG_SEL_2 Register
7 6 5 4 3 2 1 0
RESERVED MODERATE_ERR_TRIG
R/W-0h R/W-0h

Table 8-88. FSM_TRIG_SEL_2 Register Field Descriptions

Bit Field Type Reset Description
7-2 RESERVED R/W 0h
1-0 MODERATE_ERR_TRIG R/W 0h Trigger selection for Moderate Error:
(Default from NVM memory)
0h = Immediate shutdown
1h = Orderly shutdown
2h = MCU power error
3h = SOC power error

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8.7.1.65 FSM_TRIG_MASK_1 Register (Offset = 46h) [Reset = 00h]

FSM_TRIG_MASK_1 is shown in Figure 8-126 and described in Table 8-89.
Return to the Summary Table.
Figure 8-126. FSM_TRIG_MASK_1 Register
7 6 5 4 3 2 1 0
GPIO4_FSM_M GPIO4_FSM_M GPIO3_FSM_M GPIO3_FSM_M GPIO2_FSM_M GPIO2_FSM_M GPIO1_FSM_M GPIO1_FSM_M
ASK_POL ASK ASK_POL ASK ASK_POL ASK ASK_POL ASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-89. FSM_TRIG_MASK_1 Register Field Descriptions

Bit Field Type Reset Description
7 GPIO4_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx:
(Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
6 GPIO4_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked
5 GPIO3_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx:
(Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
4 GPIO3_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked
3 GPIO2_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx:
(Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
2 GPIO2_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked
1 GPIO1_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx:
(Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
0 GPIO1_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked

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8.7.1.66 FSM_TRIG_MASK_2 Register (Offset = 47h) [Reset = 00h]

FSM_TRIG_MASK_2 is shown in Figure 8-127 and described in Table 8-90.
Return to the Summary Table.
Figure 8-127. FSM_TRIG_MASK_2 Register
7 6 5 4 3 2 1 0
GPIO8_FSM_M GPIO8_FSM_M GPIO7_FSM_M GPIO7_FSM_M GPIO6_FSM_M GPIO6_FSM_M GPIO5_FSM_M GPIO5_FSM_M
ASK_POL ASK ASK_POL ASK ASK_POL ASK ASK_POL ASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-90. FSM_TRIG_MASK_2 Register Field Descriptions

Bit Field Type Reset Description
7 GPIO8_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx:
(Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
6 GPIO8_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked
5 GPIO7_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx:
(Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
4 GPIO7_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked
3 GPIO6_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx:
(Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
2 GPIO6_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked
1 GPIO5_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx:
(Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
0 GPIO5_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked

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8.7.1.67 FSM_TRIG_MASK_3 Register (Offset = 48h) [Reset = 00h]

FSM_TRIG_MASK_3 is shown in Figure 8-128 and described in Table 8-91.
Return to the Summary Table.
Figure 8-128. FSM_TRIG_MASK_3 Register
7 6 5 4 3 2 1 0
RESERVED GPIO11_FSM_ GPIO11_FSM_ GPIO10_FSM_ GPIO10_FSM_ GPIO9_FSM_M GPIO9_FSM_M
MASK_POL MASK MASK_POL MASK ASK_POL ASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-91. FSM_TRIG_MASK_3 Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 GPIO11_FSM_MASK_PO R/W 0h FSM trigger masking polarity select for GPIOx:
L (Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
4 GPIO11_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked
3 GPIO10_FSM_MASK_PO R/W 0h FSM trigger masking polarity select for GPIOx:
L (Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
2 GPIO10_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked
1 GPIO9_FSM_MASK_POL R/W 0h FSM trigger masking polarity select for GPIOx:
(Default from NVM memory)
0h = Masking sets signal value to '0'
1h = Masking sets signal value to '1'
0 GPIO9_FSM_MASK R/W 0h FSM trigger mask for GPIOx:
(Default from NVM memory)
0h = Not masked
1h = Masked

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8.7.1.68 MASK_BUCK1_2 Register (Offset = 49h) [Reset = 00h]

MASK_BUCK1_2 is shown in Figure 8-129 and described in Table 8-92.
Return to the Summary Table.
Figure 8-129. MASK_BUCK1_2 Register
7 6 5 4 3 2 1 0
BUCK2_ILIM_M RESERVED BUCK2_UV_M BUCK2_OV_M BUCK1_ILIM_M RESERVED BUCK1_UV_M BUCK1_OV_M
ASK ASK ASK ASK ASK ASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-92. MASK_BUCK1_2 Register Field Descriptions

Bit Field Type Reset Description
7 BUCK2_ILIM_MASK R/W 0h Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
6 RESERVED R/W 0h
5 BUCK2_UV_MASK R/W 0h Masking of BUCK2 under-voltage detection interrupt
BUCK2_UV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 BUCK2_OV_MASK R/W 0h Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
3 BUCK1_ILIM_MASK R/W 0h Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 RESERVED R/W 0h
1 BUCK1_UV_MASK R/W 0h Masking of BUCK1 under-voltage detection interrupt
BUCK1_UV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 BUCK1_OV_MASK R/W 0h Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.69 MASK_BUCK3_4 Register (Offset = 4Ah) [Reset = 00h]

MASK_BUCK3_4 is shown in Figure 8-130 and described in Table 8-93.
Return to the Summary Table.
Figure 8-130. MASK_BUCK3_4 Register
7 6 5 4 3 2 1 0
BUCK4_ILIM_M RESERVED BUCK4_UV_M BUCK4_OV_M BUCK3_ILIM_M RESERVED BUCK3_UV_M BUCK3_OV_M
ASK ASK ASK ASK ASK ASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-93. MASK_BUCK3_4 Register Field Descriptions

Bit Field Type Reset Description
7 BUCK4_ILIM_MASK R/W 0h Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
6 RESERVED R/W 0h
5 BUCK4_UV_MASK R/W 0h Masking of BUCK4 under-voltage detection interrupt
BUCK4_UV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 BUCK4_OV_MASK R/W 0h Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
3 BUCK3_ILIM_MASK R/W 0h Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 RESERVED R/W 0h
1 BUCK3_UV_MASK R/W 0h Masking of BUCK3 under-voltage detection interrupt
BUCK3_UV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 BUCK3_OV_MASK R/W 0h Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.70 MASK_BUCK5 Register (Offset = 4Bh) [Reset = 00h]

MASK_BUCK5 is shown in Figure 8-131 and described in Table 8-94.
Return to the Summary Table.
Figure 8-131. MASK_BUCK5 Register
7 6 5 4 3 2 1 0
RESERVED BUCK5_ILIM_M RESERVED BUCK5_UV_M BUCK5_OV_M
ASK ASK ASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-94. MASK_BUCK5 Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3 BUCK5_ILIM_MASK R/W 0h Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 RESERVED R/W 0h
1 BUCK5_UV_MASK R/W 0h Masking of BUCK5 under-voltage detection interrupt
BUCK5_UV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 BUCK5_OV_MASK R/W 0h Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.71 MASK_LDO1_2 Register (Offset = 4Ch) [Reset = 00h]

MASK_LDO1_2 is shown in Figure 8-132 and described in Table 8-95.
Return to the Summary Table.
Figure 8-132. MASK_LDO1_2 Register
7 6 5 4 3 2 1 0
LDO2_ILIM_MA RESERVED LDO2_UV_MA LDO2_OV_MA LDO1_ILIM_MA RESERVED LDO1_UV_MA LDO1_OV_MA
SK SK SK SK SK SK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-95. MASK_LDO1_2 Register Field Descriptions

Bit Field Type Reset Description
7 LDO2_ILIM_MASK R/W 0h Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
6 RESERVED R/W 0h
5 LDO2_UV_MASK R/W 0h Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 LDO2_OV_MASK R/W 0h Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
3 LDO1_ILIM_MASK R/W 0h Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 RESERVED R/W 0h
1 LDO1_UV_MASK R/W 0h Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 LDO1_OV_MASK R/W 0h Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.72 MASK_LDO3_4 Register (Offset = 4Dh) [Reset = 00h]

MASK_LDO3_4 is shown in Figure 8-133 and described in Table 8-96.
Return to the Summary Table.
Figure 8-133. MASK_LDO3_4 Register
7 6 5 4 3 2 1 0
LDO4_ILIM_MA RESERVED LDO4_UV_MA LDO4_OV_MA LDO3_ILIM_MA RESERVED LDO3_UV_MA LDO3_OV_MA
SK SK SK SK SK SK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-96. MASK_LDO3_4 Register Field Descriptions

Bit Field Type Reset Description
7 LDO4_ILIM_MASK R/W 0h Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
6 RESERVED R/W 0h
5 LDO4_UV_MASK R/W 0h Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 LDO4_OV_MASK R/W 0h Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
3 LDO3_ILIM_MASK R/W 0h Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 RESERVED R/W 0h
1 LDO3_UV_MASK R/W 0h Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 LDO3_OV_MASK R/W 0h Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.73 MASK_VMON Register (Offset = 4Eh) [Reset = 00h]

MASK_VMON is shown in Figure 8-134 and described in Table 8-97.
Return to the Summary Table.
Figure 8-134. MASK_VMON Register
7 6 5 4 3 2 1 0
RESERVED VCCA_UV_MA VCCA_OV_MA
SK SK
R/W-0h R/W-0h R/W-0h

Table 8-97. MASK_VMON Register Field Descriptions

Bit Field Type Reset Description
7-2 RESERVED R/W 0h
1 VCCA_UV_MASK R/W 0h Masking of VCCA under-voltage detection interrupt VCCA_UV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 VCCA_OV_MASK R/W 0h Masking of VCCA over-voltage detection interrupt VCCA_OV_INT:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.74 MASK_GPIO1_8_FALL Register (Offset = 4Fh) [Reset = 00h]

MASK_GPIO1_8_FALL is shown in Figure 8-135 and described in Table 8-98.
Return to the Summary Table.
Figure 8-135. MASK_GPIO1_8_FALL Register
7 6 5 4 3 2 1 0
GPIO8_FALL_ GPIO7_FALL_ GPIO6_FALL_ GPIO5_FALL_ GPIO4_FALL_ GPIO3_FALL_ GPIO2_FALL_ GPIO1_FALL_
MASK MASK MASK MASK MASK MASK MASK MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-98. MASK_GPIO1_8_FALL Register Field Descriptions

Bit Field Type Reset Description
7 GPIO8_FALL_MASK R/W 0h Masking of interrupt for GPIO8 low state transition:
This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
6 GPIO7_FALL_MASK R/W 0h Masking of interrupt for GPIO7 low state transition:
This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
5 GPIO6_FALL_MASK R/W 0h Masking of interrupt for GPIO6 low state transition:
This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 GPIO5_FALL_MASK R/W 0h Masking of interrupt for GPIO5 low state transition:
This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
3 GPIO4_FALL_MASK R/W 0h Masking of interrupt for GPIO4 low state transition:
This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 GPIO3_FALL_MASK R/W 0h Masking of interrupt for GPIO3 low state transition:
This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
1 GPIO2_FALL_MASK R/W 0h Masking of interrupt for GPIO2 low state transition:
This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 GPIO1_FALL_MASK R/W 0h Masking of interrupt for GPIO1 low state transition:
This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.75 MASK_GPIO1_8_RISE Register (Offset = 50h) [Reset = 00h]

MASK_GPIO1_8_RISE is shown in Figure 8-136 and described in Table 8-99.
Return to the Summary Table.
Figure 8-136. MASK_GPIO1_8_RISE Register
7 6 5 4 3 2 1 0
GPIO8_RISE_ GPIO7_RISE_ GPIO6_RISE_ GPIO5_RISE_ GPIO4_RISE_ GPIO3_RISE_ GPIO2_RISE_ GPIO1_RISE_
MASK MASK MASK MASK MASK MASK MASK MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-99. MASK_GPIO1_8_RISE Register Field Descriptions

Bit Field Type Reset Description
7 GPIO8_RISE_MASK R/W 0h Masking of interrupt for GPIO8 high state transition:
This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
6 GPIO7_RISE_MASK R/W 0h Masking of interrupt for GPIO7 high state transition:
This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
5 GPIO6_RISE_MASK R/W 0h Masking of interrupt for GPIO6 high state transition:
This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 GPIO5_RISE_MASK R/W 0h Masking of interrupt for GPIO5 high state transition:
This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
3 GPIO4_RISE_MASK R/W 0h Masking of interrupt for GPIO4 high state transition:
This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 GPIO3_RISE_MASK R/W 0h Masking of interrupt for GPIO3 high state transition:
This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
1 GPIO2_RISE_MASK R/W 0h Masking of interrupt for GPIO2 high state transition:
This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 GPIO1_RISE_MASK R/W 0h Masking of interrupt for GPIO1 high state transition:
This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.76 MASK_GPIO9_11 Register (Offset = 51h) [Reset = 00h]

MASK_GPIO9_11 is shown in Figure 8-137 and described in Table 8-100.
Return to the Summary Table.
Figure 8-137. MASK_GPIO9_11 Register
7 6 5 4 3 2 1 0
RESERVED GPIO11_RISE_ GPIO10_RISE_ GPIO9_RISE_ GPIO11_FALL_ GPIO10_FALL_ GPIO9_FALL_
MASK MASK MASK MASK MASK MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-100. MASK_GPIO9_11 Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 GPIO11_RISE_MASK R/W 0h Masking of interrupt for GPIO11 high state transition:
This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 GPIO10_RISE_MASK R/W 0h Masking of interrupt for GPIO10 high state transition:
This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
3 GPIO9_RISE_MASK R/W 0h Masking of interrupt for GPIO9 high state transition:
This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 GPIO11_FALL_MASK R/W 0h Masking of interrupt for GPIO11 low state transition:
This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
1 GPIO10_FALL_MASK R/W 0h Masking of interrupt for GPIO10 low state transition:
This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 GPIO9_FALL_MASK R/W 0h Masking of interrupt for GPIO9 low state transition:
This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register.
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.77 MASK_STARTUP Register (Offset = 52h) [Reset = 00h]

MASK_STARTUP is shown in Figure 8-138 and described in Table 8-101.
Return to the Summary Table.
Figure 8-138. MASK_STARTUP Register
7 6 5 4 3 2 1 0
RESERVED SOFT_REBOO FSD_MASK RESERVED ENABLE_MAS NPWRON_STA
T_MASK K RT_MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-101. MASK_STARTUP Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 SOFT_REBOOT_MASK R/W 0h Masking of SOFT_REBOOT_MASK interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 FSD_MASK R/W 0h Masking of FSD_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
3-2 RESERVED R/W 0h
1 ENABLE_MASK R/W 0h Masking of ENABLE_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 NPWRON_START_MASK R/W 0h Masking of NPWRON_START_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.78 MASK_MISC Register (Offset = 53h) [Reset = 00h]

MASK_MISC is shown in Figure 8-139 and described in Table 8-102.
Return to the Summary Table.
Figure 8-139. MASK_MISC Register
7 6 5 4 3 2 1 0
RESERVED TWARN_MASK RESERVED EXT_CLK_MAS BIST_PASS_M
K ASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-102. MASK_MISC Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3 TWARN_MASK R/W 0h Masking of TWARN_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 RESERVED R/W 0h
1 EXT_CLK_MASK R/W 0h Masking of EXT_CLK_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 BIST_PASS_MASK R/W 0h Masking of BIST_PASS_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.79 MASK_MODERATE_ERR Register (Offset = 54h) [Reset = 00h]

MASK_MODERATE_ERR is shown in Figure 8-140 and described in Table 8-103.
Return to the Summary Table.
Figure 8-140. MASK_MODERATE_ERR Register
7 6 5 4 3 2 1 0
NRSTOUT_RE NINT_READBA NPWRON_LON SPMI_ERR_MA RESERVED REG_CRC_ER BIST_FAIL_MA RESERVED
ADBACK_MAS CK_MASK G_MASK SK R_MASK SK
K
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-103. MASK_MODERATE_ERR Register Field Descriptions

Bit Field Type Reset Description
7 NRSTOUT_READBACK_ R/W 0h Masking of NRSTOUT_READBACK_INT interrupt:
MASK (Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
6 NINT_READBACK_MASK R/W 0h Masking of NINT_READBACK_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
5 NPWRON_LONG_MASK R/W 0h Masking of NPWRON_LONG_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 SPMI_ERR_MASK R/W 0h Masking of SPMI_ERR_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
3 RESERVED R/W 0h
2 REG_CRC_ERR_MASK R/W 0h Masking of REG_CRC_ERR_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
1 BIST_FAIL_MASK R/W 0h Masking of BIST_FAIL_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 RESERVED R/W 0h

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8.7.1.80 MASK_FSM_ERR Register (Offset = 56h) [Reset = 00h]

MASK_FSM_ERR is shown in Figure 8-141 and described in Table 8-104.
Return to the Summary Table.
Figure 8-141. MASK_FSM_ERR Register
7 6 5 4 3 2 1 0
RESERVED SOC_PWR_ER MCU_PWR_ER ORD_SHUTDO IMM_SHUTDO
R_MASK R_MASK WN_MASK WN_MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-104. MASK_FSM_ERR Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3 SOC_PWR_ERR_MASK R/W 0h Masking of SOC_PWR_ERR_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 MCU_PWR_ERR_MASK R/W 0h Masking of MCU_PWR_ERR_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
1 ORD_SHUTDOWN_MAS R/W 0h Masking of ORD_SHUTDOWN_INT interrupt:
K (Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 IMM_SHUTDOWN_MASK R/W 0h Masking of IMM_SHUTDOWN_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.81 MASK_COMM_ERR Register (Offset = 57h) [Reset = 00h]

MASK_COMM_ERR is shown in Figure 8-142 and described in Table 8-105.
Return to the Summary Table.
Figure 8-142. MASK_COMM_ERR Register
7 6 5 4 3 2 1 0
I2C2_ADR_ER RESERVED I2C2_CRC_ER RESERVED COMM_ADR_E RESERVED COMM_CRC_E COMM_FRM_E
R_MASK R_MASK RR_MASK RR_MASK RR_MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-105. MASK_COMM_ERR Register Field Descriptions

Bit Field Type Reset Description
7 I2C2_ADR_ERR_MASK R/W 0h Masking of I2C2_ADR_ERR_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
6 RESERVED R/W 0h
5 I2C2_CRC_ERR_MASK R/W 0h Masking of I2C2_CRC_ERR_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 RESERVED R/W 0h
3 COMM_ADR_ERR_MASK R/W 0h Masking of COMM_ADR_ERR_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 RESERVED R/W 0h
1 COMM_CRC_ERR_MAS R/W 0h Masking of COMM_CRC_ERR_INT interrupt:
K (Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 COMM_FRM_ERR_MAS R/W 0h Masking of COMM_FRM_ERR_INT interrupt:
K (Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.82 MASK_READBACK_ERR Register (Offset = 58h) [Reset = 00h]

MASK_READBACK_ERR is shown in Figure 8-143 and described in Table 8-106.
Return to the Summary Table.
Figure 8-143. MASK_READBACK_ERR Register
7 6 5 4 3 2 1 0
RESERVED NRSTOUT_SO RESERVED EN_DRV_REA
C_READBACK DBACK_MASK
_MASK
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-106. MASK_READBACK_ERR Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3 NRSTOUT_SOC_READB R/W 0h Masking of NRSTOUT_SOC_READBACK_INT interrupt:
ACK_MASK (Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2-1 RESERVED R/W 0h
0 EN_DRV_READBACK_M R/W 0h Masking of EN_DRV_READBACK_INT interrupt:
ASK (Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.83 MASK_ESM Register (Offset = 59h) [Reset = 00h]

MASK_ESM is shown in Figure 8-144 and described in Table 8-107.
Return to the Summary Table.
Figure 8-144. MASK_ESM Register
7 6 5 4 3 2 1 0
RESERVED ESM_MCU_RS ESM_MCU_FAI ESM_MCU_PIN ESM_SOC_RS ESM_SOC_FAI ESM_SOC_PIN
T_MASK L_MASK _MASK T_MASK L_MASK _MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-107. MASK_ESM Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 ESM_MCU_RST_MASK R/W 0h Masking of ESM_MCU_RST_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
4 ESM_MCU_FAIL_MASK R/W 0h Masking of ESM_MCU_FAIL_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
3 ESM_MCU_PIN_MASK R/W 0h Masking of ESM_MCU_PIN_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
2 ESM_SOC_RST_MASK R/W 0h Masking of ESM_SOC_RST_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
1 ESM_SOC_FAIL_MASK R/W 0h Masking of ESM_SOC_FAIL_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.
0 ESM_SOC_PIN_MASK R/W 0h Masking of ESM_SOC_PIN_INT interrupt:
(Default from NVM memory)
0h = Interrupt generated
1h = Interrupt not generated.

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8.7.1.84 INT_TOP Register (Offset = 5Ah) [Reset = 00h]

INT_TOP is shown in Figure 8-145 and described in Table 8-108.
Return to the Summary Table.
Figure 8-145. INT_TOP Register
7 6 5 4 3 2 1 0
FSM_ERR_INT SEVERE_ERR MODERATE_E MISC_INT STARTUP_INT GPIO_INT LDO_VMON_IN BUCK_INT
_INT RR_INT T
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-108. INT_TOP Register Field Descriptions

Bit Field Type Reset Description
7 FSM_ERR_INT R 0h Interrupt indicating that INT_FSM_ERR register has pending
interrupt. The reason for the interrupt is indicated in INT_FSM_ERR
register.
This bit is cleared automatically when INT_FSM_ERR register is
cleared to 0x00.
6 SEVERE_ERR_INT R 0h Interrupt indicating that INT_SEVERE_ERR register has pending
interrupt. The reason for the interrupt is indicated in
INT_SEVERE_ERR register.
This bit is cleared automatically when INT_SEVERE_ERR register is
cleared to 0x00.
5 MODERATE_ERR_INT R 0h Interrupt indicating that INT_MODERATE_ERR register has
pending interrupt. The reason for the interrupt is indicated in
INT_MODERATE_ERR register.
This bit is cleared automatically when INT_MODERATE_ERR
register is cleared to 0x00.
4 MISC_INT R 0h Interrupt indicating that INT_MISC register has pending interrupt.
The reason for the interrupt is indicated in INT_MISC register.
This bit is cleared automatically when INT_MISC register is cleared
to 0x00.
3 STARTUP_INT R 0h Interrupt indicating that INT_STARTUP register has pending
interrupt. The reason for the interrupt is indicated in INT_STARTUP
register.
This bit is cleared automatically when INT_STARTUP register is
cleared to 0x00.
2 GPIO_INT R 0h Interrupt indicating that INT_GPIO register has pending interrupt.
The reason for the interrupt is indicated in INT_GPIO register.
This bit is cleared automatically when INT_GPIO register is cleared
to 0x00.
1 LDO_VMON_INT R 0h Interrupt indicating that INT_LDO_VMON register has pending
interrupt. The reason for the interrupt is indicated in
INT_LDO_VMON register.
This bit is cleared automatically when INT_LDO_VMON register is
cleared to 0x00.
0 BUCK_INT R 0h Interrupt indicating that INT_BUCK register has pending interrupt.
The reason for the interrupt is indicated in INT_BUCK register.
This bit is cleared automatically when INT_BUCK register is cleared
to 0x00.

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8.7.1.85 INT_BUCK Register (Offset = 5Bh) [Reset = 00h]

INT_BUCK is shown in Figure 8-146 and described in Table 8-109.
Return to the Summary Table.
Figure 8-146. INT_BUCK Register
7 6 5 4 3 2 1 0
RESERVED BUCK5_INT BUCK3_4_INT BUCK1_2_INT
R-0h R-0h R-0h R-0h

Table 8-109. INT_BUCK Register Field Descriptions

Bit Field Type Reset Description
7-3 RESERVED R 0h
2 BUCK5_INT R 0h Interrupt indicating that INT_BUCK5 register has pending interrupt.
The reason for the interrupt is indicated in INT_BUCK5 register.
This bit is cleared automatically when INT_BUCK5 register is cleared
to 0x00.
1 BUCK3_4_INT R 0h Interrupt indicating that INT_BUCK3_4 register has pending
interrupt.
This bit is cleared automatically when INT_BUCK3_4 register is
cleared to 0x00.
0 BUCK1_2_INT R 0h Interrupt indicating that INT_BUCK1_2 register has pending
interrupt.
This bit is cleared automatically when INT_BUCK1_2 register is
cleared to 0x00.

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8.7.1.86 INT_BUCK1_2 Register (Offset = 5Ch) [Reset = 00h]

INT_BUCK1_2 is shown in Figure 8-147 and described in Table 8-110.
Return to the Summary Table.
Figure 8-147. INT_BUCK1_2 Register
7 6 5 4 3 2 1 0
BUCK2_ILIM_I BUCK2_SC_IN BUCK2_UV_IN BUCK2_OV_IN BUCK1_ILIM_I BUCK1_SC_IN BUCK1_UV_IN BUCK1_OV_IN
NT T T T NT T T T
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-110. INT_BUCK1_2 Register Field Descriptions

Bit Field Type Reset Description
7 BUCK2_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK2 output current limit has
been triggered.
Write 1 to clear.
6 BUCK2_SC_INT R/W1C 0h Latched status bit indicating that the BUCK2 output voltage has
fallen below 150 mV level during operation.
Write 1 to clear.
5 BUCK2_UV_INT R/W1C 0h Latched status bit indicating that BUCK2 output under-voltage has
been detected.
Write 1 to clear.
4 BUCK2_OV_INT R/W1C 0h Latched status bit indicating that BUCK2 output over-voltage has
been detected.
Write 1 to clear.
3 BUCK1_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK1 output current limit has
been triggered.
Write 1 to clear.
2 BUCK1_SC_INT R/W1C 0h Latched status bit indicating that the BUCK1 output voltage has
fallen below 150 mV level during operation.
Write 1 to clear.
1 BUCK1_UV_INT R/W1C 0h Latched status bit indicating that BUCK1 output under-voltage has
been detected.
Write 1 to clear.
0 BUCK1_OV_INT R/W1C 0h Latched status bit indicating that BUCK1 output over-voltage has
been detected.
Write 1 to clear.

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8.7.1.87 INT_BUCK3_4 Register (Offset = 5Dh) [Reset = 00h]

INT_BUCK3_4 is shown in Figure 8-148 and described in Table 8-111.
Return to the Summary Table.
Figure 8-148. INT_BUCK3_4 Register
7 6 5 4 3 2 1 0
BUCK4_ILIM_I BUCK4_SC_IN BUCK4_UV_IN BUCK4_OV_IN BUCK3_ILIM_I BUCK3_SC_IN BUCK3_UV_IN BUCK3_OV_IN
NT T T T NT T T T
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-111. INT_BUCK3_4 Register Field Descriptions

Bit Field Type Reset Description
7 BUCK4_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK4 output current limit has
been triggered.
Write 1 to clear.
6 BUCK4_SC_INT R/W1C 0h Latched status bit indicating that the BUCK4 output voltage has
fallen below 150 mV level during operation.
Write 1 to clear.
5 BUCK4_UV_INT R/W1C 0h Latched status bit indicating that BUCK4 output under-voltage has
been detected.
Write 1 to clear.
4 BUCK4_OV_INT R/W1C 0h Latched status bit indicating that BUCK4 output over-voltage has
been detected.
Write 1 to clear.
3 BUCK3_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK3 output current limit has
been triggered.
Write 1 to clear.
2 BUCK3_SC_INT R/W1C 0h Latched status bit indicating that the BUCK3 output voltage has
fallen below 150 mV level during operation.
Write 1 to clear.
1 BUCK3_UV_INT R/W1C 0h Latched status bit indicating that BUCK3 output under-voltage has
been detected.
Write 1 to clear.
0 BUCK3_OV_INT R/W1C 0h Latched status bit indicating that BUCK3 output over-voltage has
been detected.
Write 1 to clear.

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8.7.1.88 INT_BUCK5 Register (Offset = 5Eh) [Reset = 00h]

INT_BUCK5 is shown in Figure 8-149 and described in Table 8-112.
Return to the Summary Table.
Figure 8-149. INT_BUCK5 Register
7 6 5 4 3 2 1 0
RESERVED BUCK5_ILIM_I BUCK5_SC_IN BUCK5_UV_IN BUCK5_OV_IN
NT T T T
R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-112. INT_BUCK5 Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3 BUCK5_ILIM_INT R/W1C 0h Latched status bit indicating that BUCK5 output current limit has
been triggered.
Write 1 to clear.
2 BUCK5_SC_INT R/W1C 0h Latched status bit indicating that the BUCK5 output voltage has
fallen below 150 mV level during operation.
Write 1 to clear.
1 BUCK5_UV_INT R/W1C 0h Latched status bit indicating that BUCK5 output under-voltage has
been detected.
Write 1 to clear.
0 BUCK5_OV_INT R/W1C 0h Latched status bit indicating that BUCK5 output over-voltage has
been detected.
Write 1 to clear.

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8.7.1.89 INT_LDO_VMON Register (Offset = 5Fh) [Reset = 00h]

INT_LDO_VMON is shown in Figure 8-150 and described in Table 8-113.
Return to the Summary Table.
Figure 8-150. INT_LDO_VMON Register
7 6 5 4 3 2 1 0
RESERVED VCCA_INT RESERVED LDO3_4_INT LDO1_2_INT
R-0h R-0h R-0h R-0h R-0h

Table 8-113. INT_LDO_VMON Register Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R 0h
4 VCCA_INT R 0h Interrupt indicating that INT_VMON register has pending interrupt.
The reason for the interrupt is indicated in INT_VMON register.
This bit is cleared automatically when INT_VMON register is cleared
to 0x00.
3-2 RESERVED R 0h
1 LDO3_4_INT R 0h Interrupt indicating that INT_LDO3_4 register has pending interrupt.
This bit is cleared automatically when INT_LDO3_4 register is
cleared to 0x00.
0 LDO1_2_INT R 0h Interrupt indicating that INT_LDO1_2 register has pending interrupt.
This bit is cleared automatically when INT_LDO1_2 register is
cleared to 0x00.

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8.7.1.90 INT_LDO1_2 Register (Offset = 60h) [Reset = 00h]

INT_LDO1_2 is shown in Figure 8-151 and described in Table 8-114.
Return to the Summary Table.
Figure 8-151. INT_LDO1_2 Register
7 6 5 4 3 2 1 0
LDO2_ILIM_IN LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_IN LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT
T T
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-114. INT_LDO1_2 Register Field Descriptions

Bit Field Type Reset Description
7 LDO2_ILIM_INT R/W1C 0h Latched status bit indicating that LDO2 output current limit has been
triggered.
Write 1 to clear.
6 LDO2_SC_INT R/W1C 0h Latched status bit indicating that LDO2 output voltage has fallen
below 150 mV level during operation.
Write 1 to clear.
5 LDO2_UV_INT R/W1C 0h Latched status bit indicating that LDO2 output under-voltage has
been detected.
Write 1 to clear.
4 LDO2_OV_INT R/W1C 0h Latched status bit indicating that LDO2 output over-voltage has been
detected.
Write 1 to clear.
3 LDO1_ILIM_INT R/W1C 0h Latched status bit indicating that LDO1 output current limit has been
triggered.
Write 1 to clear.
2 LDO1_SC_INT R/W1C 0h Latched status bit indicating that LDO1 output voltage has fallen
below 150 mV level during operation.
Write 1 to clear.
1 LDO1_UV_INT R/W1C 0h Latched status bit indicating that LDO1 output under-voltage has
been detected.
Write 1 to clear.
0 LDO1_OV_INT R/W1C 0h Latched status bit indicating that LDO1 output over-voltage has been
detected.
Write 1 to clear.

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8.7.1.91 INT_LDO3_4 Register (Offset = 61h) [Reset = 00h]

INT_LDO3_4 is shown in Figure 8-152 and described in Table 8-115.
Return to the Summary Table.
Figure 8-152. INT_LDO3_4 Register
7 6 5 4 3 2 1 0
LDO4_ILIM_IN LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_IN LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT
T T
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-115. INT_LDO3_4 Register Field Descriptions

Bit Field Type Reset Description
7 LDO4_ILIM_INT R/W1C 0h Latched status bit indicating that LDO4 output current limit has been
triggered.
Write 1 to clear.
6 LDO4_SC_INT R/W1C 0h Latched status bit indicating that LDO4 output voltage has fallen
below 150 mV level during operation.
Write 1 to clear.
5 LDO4_UV_INT R/W1C 0h Latched status bit indicating that LDO4 output under-voltage has
been detected.
Write 1 to clear.
4 LDO4_OV_INT R/W1C 0h Latched status bit indicating that LDO4 output over-voltage has been
detected.
Write 1 to clear.
3 LDO3_ILIM_INT R/W1C 0h Latched status bit indicating that LDO3 output current limit has been
triggered.
Write 1 to clear.
2 LDO3_SC_INT R/W1C 0h Latched status bit indicating that LDO3 output voltage has fallen
below 150 mV level during operation.
Write 1 to clear.
1 LDO3_UV_INT R/W1C 0h Latched status bit indicating that LDO3 output under-voltage has
been detected.
Write 1 to clear.
0 LDO3_OV_INT R/W1C 0h Latched status bit indicating that LDO3 output over-voltage has been
detected.
Write 1 to clear.

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8.7.1.92 INT_VMON Register (Offset = 62h) [Reset = 00h]

INT_VMON is shown in Figure 8-153 and described in Table 8-116.
Return to the Summary Table.
Figure 8-153. INT_VMON Register
7 6 5 4 3 2 1 0
RESERVED VCCA_UV_INT VCCA_OV_INT
R/W-0h R/W1C-0h R/W1C-0h

Table 8-116. INT_VMON Register Field Descriptions

Bit Field Type Reset Description
7-2 RESERVED R/W 0h
1 VCCA_UV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has
decreased below the under-voltage monitoring level. The actual
status of the VCCA under-voltage monitoring is indicated by
VCCA_UV_STAT bit.
Write 1 to clear interrupt.
0 VCCA_OV_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has
exceeded the over-voltage detection level. The actual status of the
over-voltage is indicated by VCCA_OV_STAT bit.
Write 1 to clear interrupt.

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8.7.1.93 INT_GPIO Register (Offset = 63h) [Reset = 00h]

INT_GPIO is shown in Figure 8-154 and described in Table 8-117.
Return to the Summary Table.
Figure 8-154. INT_GPIO Register
7 6 5 4 3 2 1 0
RESERVED GPIO1_8_INT GPIO11_INT GPIO10_INT GPIO9_INT
R/W-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-117. INT_GPIO Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3 GPIO1_8_INT R 0h Interrupt indicating that INT_GPIO1_8 has pending interrupt. The
reason for the interrupt is indicated in INT_GPIO1_8 register.
This bit is cleared automatically when INT_GPIO1_8 register is
cleared to 0x00.
2 GPIO11_INT R/W1C 0h Latched status bit indicating that GPIO11 has pending interrupt.
GPIO11_IN bit in GPIO_IN_2 register shows the status of the
GPIO11 signal.
Write 1 to clear interrupt.
1 GPIO10_INT R/W1C 0h Latched status bit indicating that GPIO10 has pending interrupt.
GPIO10_IN bit in GPIO_IN_2 register shows the status of the
GPIO10 signal.
Write 1 to clear interrupt.
0 GPIO9_INT R/W1C 0h Latched status bit indicating that GPIO9 has pending interrupt.
GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9
signal.
Write 1 to clear interrupt.

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8.7.1.94 INT_GPIO1_8 Register (Offset = 64h) [Reset = 00h]

INT_GPIO1_8 is shown in Figure 8-155 and described in Table 8-118.
Return to the Summary Table.
Figure 8-155. INT_GPIO1_8 Register
7 6 5 4 3 2 1 0
GPIO8_INT GPIO7_INT GPIO6_INT GPIO5_INT GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-118. INT_GPIO1_8 Register Field Descriptions

Bit Field Type Reset Description
7 GPIO8_INT R/W1C 0h Latched status bit indicating that GPIO8 has has pending interrupt.
GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8
signal.
Write 1 to clear interrupt.
6 GPIO7_INT R/W1C 0h Latched status bit indicating that GPIO7 has has pending interrupt.
GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7
signal.
Write 1 to clear interrupt.
5 GPIO6_INT R/W1C 0h Latched status bit indicating that GPIO6 has has pending interrupt.
GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6
signal.
Write 1 to clear interrupt.
4 GPIO5_INT R/W1C 0h Latched status bit indicating that GPIO5 has has pending interrupt.
GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5
signal.
Write 1 to clear interrupt.
3 GPIO4_INT R/W1C 0h Latched status bit indicating that GPIO4 has has pending interrupt.
GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4
signal.
Write 1 to clear interrupt.
2 GPIO3_INT R/W1C 0h Latched status bit indicating that GPIO3 has has pending interrupt.
GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3
signal.
Write 1 to clear interrupt.
1 GPIO2_INT R/W1C 0h Latched status bit indicating that GPIO2 has pending interrupt.
GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2
signal.
Write 1 to clear interrupt.
0 GPIO1_INT R/W1C 0h Latched status bit indicating that GPIO1 has pending interrupt.
GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1
signal.
Write 1 to clear interrupt.

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8.7.1.95 INT_STARTUP Register (Offset = 65h) [Reset = 00h]

INT_STARTUP is shown in Figure 8-156 and described in Table 8-119.
Return to the Summary Table.
Figure 8-156. INT_STARTUP Register
7 6 5 4 3 2 1 0
RESERVED SOFT_REBOO FSD_INT RESERVED RTC_INT ENABLE_INT NPWRON_STA
T_INT RT_INT
R/W-0h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W1C-0h R/W1C-0h

Table 8-119. INT_STARTUP Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 SOFT_REBOOT_INT R/W1C 0h Latched status bit indicating that soft reboot event has been
detected.
Write 1 to clear.
4 FSD_INT R/W1C 0h Latched status bit indicating that PMIC has started from
NO_SUPPLY or BACKUP state (first supply dectection).
Write 1 to clear.
3 RESERVED R/W 0h
2 RTC_INT R 0h Latched status bit indicating that RTC_STATUS register has pending
interrupt.
This bit is cleared automatically when ALARM and TIMER interrupts
are cleared.
1 ENABLE_INT R/W1C 0h Latched status bit indicating that ENABLE pin active event has been
detected.
Write 1 to clear.
0 NPWRON_START_INT R/W1C 0h Latched status bit indicating that NPWRON start-up event has been
detected.
Write 1 to clear.

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8.7.1.96 INT_MISC Register (Offset = 66h) [Reset = 00h]

INT_MISC is shown in Figure 8-157 and described in Table 8-120.
Return to the Summary Table.
Figure 8-157. INT_MISC Register
7 6 5 4 3 2 1 0
RESERVED TWARN_INT RESERVED EXT_CLK_INT BIST_PASS_IN
T
R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h

Table 8-120. INT_MISC Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3 TWARN_INT R/W1C 0h Latched status bit indicating that the die junction temperature has
exceeded the thermal warning level. The actual status of the thermal
warning is indicated by TWARN_STAT bit in STAT_MISC register.
Write 1 to clear interrupt.
2 RESERVED R/W 0h
1 EXT_CLK_INT R/W1C 0h Latched status bit indicating that external clock is not valid.
Internal clock is automatically taken into use.
Write 1 to clear.
0 BIST_PASS_INT R/W1C 0h Latched status bit indicating that BOOT_BIST or RUNTIME_BSIT
has been completed.
Write 1 to clear interrupt.

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8.7.1.97 INT_MODERATE_ERR Register (Offset = 67h) [Reset = 00h]

INT_MODERATE_ERR is shown in Figure 8-158 and described in Table 8-121.
Return to the Summary Table.
Figure 8-158. INT_MODERATE_ERR Register
7 6 5 4 3 2 1 0
NRSTOUT_RE NINT_READBA NPWRON_LON SPMI_ERR_IN RECOV_CNT_I REG_CRC_ER BIST_FAIL_INT TSD_ORD_INT
ADBACK_INT CK_INT G_INT T NT R_INT
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-121. INT_MODERATE_ERR Register Field Descriptions

Bit Field Type Reset Description
7 NRSTOUT_READBACK_I R/W1C 0h Latched status bit indicating that NRSTOUT readback error has been
NT detected.
Write 1 to clear interrupt.
6 NINT_READBACK_INT R/W1C 0h Latched status bit indicating that NINT readback error has been
detected.
Write 1 to clear interrupt.
5 NPWRON_LONG_INT R/W1C 0h Latched status bit indicating that NPWRON long press has been
detected.
Write 1 to clear.
4 SPMI_ERR_INT R/W1C 0h Latched status bit indicating that the SPMI communication interface
has detected an error.
Write 1 to clear interrupt.
3 RECOV_CNT_INT R/W1C 0h Latched status bit indicating that RECOV_CNT has reached the limit
(RECOV_CNT_THR).
Write 1 to clear.
2 REG_CRC_ERR_INT R/W1C 0h Latched status bit indicating that the register CRC checking has
detected an error.
Write 1 to clear interrupt.
1 BIST_FAIL_INT R/W1C 0h Latched status bit indicating that the BOOT_BIST or
RUNTIME_BIST has detected an error.
Write 1 to clear interrupt.
0 TSD_ORD_INT R/W1C 0h Latched status bit indicating that the die junction temperature has
exceeded the thermal level causing a sequenced shutdown. The
regulators have been disabled. The regulators cannot be enabled if
this bit is active. The actual status of the temperature is indicated by
TSD_ORD_STAT bit in STAT_MODERATE_ERR register.
Write 1 to clear interrupt.

262 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

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8.7.1.98 INT_SEVERE_ERR Register (Offset = 68h) [Reset = 00h]

INT_SEVERE_ERR is shown in Figure 8-159 and described in Table 8-122.
Return to the Summary Table.
Figure 8-159. INT_SEVERE_ERR Register
7 6 5 4 3 2 1 0
RESERVED PFSM_ERR_IN VCCA_OVP_IN TSD_IMM_INT
T T
R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-122. INT_SEVERE_ERR Register Field Descriptions

Bit Field Type Reset Description
7-3 RESERVED R/W 0h
2 PFSM_ERR_INT R/W1C 0h Latched status bit indicating that the PFSM sequencer has detected
an error.
Write 1 to clear interrupt.
1 VCCA_OVP_INT R/W1C 0h Latched status bit indicating that the VCCA input voltage has
exceeded the over-voltage threshold level causing an immediate
shutdown. The regulators have been disabled.
Write 1 to clear interrupt.
0 TSD_IMM_INT R/W1C 0h Latched status bit indicating that the die junction temperature has
exceeded the thermal level causing an immediate shutdown. The
regulators have been disabled. The regulators cannot be enabled if
this bit is active. The actual status of the temperature is indicated by
TSD_IMM_STAT bit in THER_CLK_STATUS register.
Write 1 to clear interrupt.

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8.7.1.99 INT_FSM_ERR Register (Offset = 69h) [Reset = 00h]

INT_FSM_ERR is shown in Figure 8-160 and described in Table 8-123.
Return to the Summary Table.
Figure 8-160. INT_FSM_ERR Register
7 6 5 4 3 2 1 0
WD_INT ESM_INT READBACK_E COMM_ERR_I SOC_PWR_ER MCU_PWR_ER ORD_SHUTDO IMM_SHUTDO
RR_INT NT R_INT R_INT WN_INT WN_INT
R-0h R-0h R-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-123. INT_FSM_ERR Register Field Descriptions

Bit Field Type Reset Description
7 WD_INT R 0h Interrupt indicating that WD_ERR_STATUS register has pending
interrupt.
This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT
and WD_LONGWIN_TIMEOUT_INT are cleared.
6 ESM_INT R 0h Interrupt indicating that INT_ESM has pending interrupt.
This bit is cleared automatically when INT_ESM register is cleared to
0x00.
5 READBACK_ERR_INT R 0h Interrupt indicating that INT_READBACK_ERR has pending
interrupt.
This bit is cleared automatically when INT_READBACK_ERR
register is cleared to 0x00.
4 COMM_ERR_INT R 0h Interrupt indicating that INT_COMM_ERR has pending interrupt. The
reason for the interrupt is indicated in INT_COMM_ERR register.
This bit is cleared automatically when INT_COMM_ERR register is
cleared to 0x00.
3 SOC_PWR_ERR_INT R/W1C 0h Latched status bit indicating that SOC power error has been
detected.
Write 1 to clear.
2 MCU_PWR_ERR_INT R/W1C 0h Latched status bit indicating that MCU power error has been
detected.
Write 1 to clear.
1 ORD_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that orderly shutdown has been
detected.
Write 1 to clear.
0 IMM_SHUTDOWN_INT R/W1C 0h Latched status bit indicating that immediate shutdown has been
detected.
Write 1 to clear.

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8.7.1.100 INT_COMM_ERR Register (Offset = 6Ah) [Reset = 00h]

INT_COMM_ERR is shown in Figure 8-161 and described in Table 8-124.
Return to the Summary Table.
Figure 8-161. INT_COMM_ERR Register
7 6 5 4 3 2 1 0
I2C2_ADR_ER RESERVED I2C2_CRC_ER RESERVED COMM_ADR_E RESERVED COMM_CRC_E COMM_FRM_E
R_INT R_INT RR_INT RR_INT RR_INT
R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W-0h R/W1C-0h R/W1C-0h

Table 8-124. INT_COMM_ERR Register Field Descriptions

Bit Field Type Reset Description
7 I2C2_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 write to non-existing, protected
or read-only register address has been detected.
Write 1 to clear interrupt.
6 RESERVED R/W 0h
5 I2C2_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C2 CRC error has been detected.
Write 1 to clear interrupt.
4 RESERVED R/W 0h
3 COMM_ADR_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI write to non-existing,
protected or read-only register address has been detected.
Write 1 to clear interrupt.
2 RESERVED R/W 0h
1 COMM_CRC_ERR_INT R/W1C 0h Latched status bit indicating that I2C1/SPI CRC error has been
detected.
Write 1 to clear interrupt.
0 COMM_FRM_ERR_INT R/W1C 0h Latched status bit indicating that SPI frame error has been detected.
Write 1 to clear interrupt.

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8.7.1.101 INT_READBACK_ERR Register (Offset = 6Bh) [Reset = 00h]

INT_READBACK_ERR is shown in Figure 8-162 and described in Table 8-125.
Return to the Summary Table.
Figure 8-162. INT_READBACK_ERR Register
7 6 5 4 3 2 1 0
RESERVED NRSTOUT_SO RESERVED EN_DRV_REA
C_READBACK DBACK_INT
_INT
R/W-0h R/W1C-0h R/W-0h R/W1C-0h

Table 8-125. INT_READBACK_ERR Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3 NRSTOUT_SOC_READB R/W1C 0h Latched status bit indicating that NRSTOUT_SOC readback error
ACK_INT has been detected.
Write 1 to clear interrupt.
2-1 RESERVED R/W 0h
0 EN_DRV_READBACK_IN R/W1C 0h Latched status bit indicating that EN_DRV readback error has been
T detected.
Write 1 to clear interrupt.

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8.7.1.102 INT_ESM Register (Offset = 6Ch) [Reset = 00h]

INT_ESM is shown in Figure 8-163 and described in Table 8-126.
Return to the Summary Table.
Figure 8-163. INT_ESM Register
7 6 5 4 3 2 1 0
RESERVED ESM_MCU_RS ESM_MCU_FAI ESM_MCU_PIN ESM_SOC_RS ESM_SOC_FAI ESM_SOC_PIN
T_INT L_INT _INT T_INT L_INT _INT
R/W-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-126. INT_ESM Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5 ESM_MCU_RST_INT R/W1C 0h Latched status bit indicating that MCU ESM reset has been detected.
Write 1 to clear interrupt.
4 ESM_MCU_FAIL_INT R/W1C 0h Latched status bit indicating that MCU ESM fail has been detected.
Write 1 to clear interrupt.
3 ESM_MCU_PIN_INT R/W1C 0h Latched status bit indicating that MCU ESM fault has been detected.
Write 1 to clear interrupt.
2 ESM_SOC_RST_INT R/W1C 0h Latched status bit indicating that SOC ESM reset has been detected.
Write 1 to clear interrupt.
1 ESM_SOC_FAIL_INT R/W1C 0h Latched status bit indicating that SOC ESM fail has been detected.
Write 1 to clear interrupt.
0 ESM_SOC_PIN_INT R/W1C 0h Latched status bit indicating that SOC ESM fault has been detected.
Write 1 to clear interrupt.

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8.7.1.103 STAT_BUCK1_2 Register (Offset = 6Dh) [Reset = 00h]

STAT_BUCK1_2 is shown in Figure 8-164 and described in Table 8-127.
Return to the Summary Table.
Figure 8-164. STAT_BUCK1_2 Register
7 6 5 4 3 2 1 0
BUCK2_ILIM_S RESERVED BUCK2_UV_ST BUCK2_OV_ST BUCK1_ILIM_S RESERVED BUCK1_UV_ST BUCK1_OV_ST
TAT AT AT TAT AT AT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-127. STAT_BUCK1_2 Register Field Descriptions

Bit Field Type Reset Description
7 BUCK2_ILIM_STAT R 0h Status bit indicating that BUCK2 output current is above current limit
level.
6 RESERVED R 0h
5 BUCK2_UV_STAT R 0h Status bit indicating that BUCK2 output voltage is below under-
voltage threshold.
4 BUCK2_OV_STAT R 0h Status bit indicating that BUCK2 output voltage is above over-voltage
threshold.
3 BUCK1_ILIM_STAT R 0h Status bit indicating that BUCK1 output current is above current limit
level.
2 RESERVED R 0h
1 BUCK1_UV_STAT R 0h Status bit indicating that BUCK1 output voltage is below under-
voltage threshold.
0 BUCK1_OV_STAT R 0h Status bit indicating that BUCK1 output voltage is above over-voltage
threshold.

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8.7.1.104 STAT_BUCK3_4 Register (Offset = 6Eh) [Reset = 00h]

STAT_BUCK3_4 is shown in Figure 8-165 and described in Table 8-128.
Return to the Summary Table.
Figure 8-165. STAT_BUCK3_4 Register
7 6 5 4 3 2 1 0
BUCK4_ILIM_S RESERVED BUCK4_UV_ST BUCK4_OV_ST BUCK3_ILIM_S RESERVED BUCK3_UV_ST BUCK3_OV_ST
TAT AT AT TAT AT AT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-128. STAT_BUCK3_4 Register Field Descriptions

Bit Field Type Reset Description
7 BUCK4_ILIM_STAT R 0h Status bit indicating that BUCK4 output current is above current limit
level.
6 RESERVED R 0h
5 BUCK4_UV_STAT R 0h Status bit indicating that BUCK4 output voltage is below under-
voltage threshold.
4 BUCK4_OV_STAT R 0h Status bit indicating that BUCK4 output voltage is above over-voltage
threshold.
3 BUCK3_ILIM_STAT R 0h Status bit indicating that BUCK3 output current is above current limit
level.
2 RESERVED R 0h
1 BUCK3_UV_STAT R 0h Status bit indicating that BUCK3 output voltage is below under-
voltage threshold.
0 BUCK3_OV_STAT R 0h Status bit indicating that BUCK3 output voltage is above over-voltage
threshold.

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8.7.1.105 STAT_BUCK5 Register (Offset = 6Fh) [Reset = 00h]

STAT_BUCK5 is shown in Figure 8-166 and described in Table 8-129.
Return to the Summary Table.
Figure 8-166. STAT_BUCK5 Register
7 6 5 4 3 2 1 0
RESERVED BUCK5_ILIM_S RESERVED BUCK5_UV_ST BUCK5_OV_ST
TAT AT AT
R-0h R-0h R-0h R-0h R-0h

Table 8-129. STAT_BUCK5 Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R 0h
3 BUCK5_ILIM_STAT R 0h Status bit indicating that BUCK5 output current is above current limit
level.
2 RESERVED R 0h
1 BUCK5_UV_STAT R 0h Status bit indicating that BUCK5 output voltage is below under-
voltage threshold.
0 BUCK5_OV_STAT R 0h Status bit indicating that BUCK5 output voltage is above over-voltage
threshold.

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8.7.1.106 STAT_LDO1_2 Register (Offset = 70h) [Reset = 00h]

STAT_LDO1_2 is shown in Figure 8-167 and described in Table 8-130.
Return to the Summary Table.
Figure 8-167. STAT_LDO1_2 Register
7 6 5 4 3 2 1 0
LDO2_ILIM_ST RESERVED LDO2_UV_STA LDO2_OV_STA LDO1_ILIM_ST RESERVED LDO1_UV_STA LDO1_OV_STA
AT T T AT T T
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-130. STAT_LDO1_2 Register Field Descriptions

Bit Field Type Reset Description
7 LDO2_ILIM_STAT R 0h Status bit indicating that LDO2 output current is above current limit
level.
6 RESERVED R 0h
5 LDO2_UV_STAT R 0h Status bit indicating that LDO2 output voltage is below under-voltage
threshold.
4 LDO2_OV_STAT R 0h Status bit indicating that LDO2 output voltage is above over-voltage
threshold.
3 LDO1_ILIM_STAT R 0h Status bit indicating that LDO1 output current is above current limit
level.
2 RESERVED R 0h
1 LDO1_UV_STAT R 0h Status bit indicating that LDO1 output voltage is below under-voltage
threshold.
0 LDO1_OV_STAT R 0h Status bit indicating that LDO1 output voltage is above over-voltage
threshold.

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8.7.1.107 STAT_LDO3_4 Register (Offset = 71h) [Reset = 00h]

STAT_LDO3_4 is shown in Figure 8-168 and described in Table 8-131.
Return to the Summary Table.
Figure 8-168. STAT_LDO3_4 Register
7 6 5 4 3 2 1 0
LDO4_ILIM_ST RESERVED LDO4_UV_STA LDO4_OV_STA LDO3_ILIM_ST RESERVED LDO3_UV_STA LDO3_OV_STA
AT T T AT T T
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-131. STAT_LDO3_4 Register Field Descriptions

Bit Field Type Reset Description
7 LDO4_ILIM_STAT R 0h Status bit indicating that LDO4 output current is above current limit
level.
6 RESERVED R 0h
5 LDO4_UV_STAT R 0h Status bit indicating that LDO4 output voltage is below under-voltage
threshold.
4 LDO4_OV_STAT R 0h Status bit indicating that LDO4 output voltage is above over-voltage
threshold.
3 LDO3_ILIM_STAT R 0h Status bit indicating that LDO3 output current is above current limit
level.
2 RESERVED R 0h
1 LDO3_UV_STAT R 0h Status bit indicating that LDO3 output voltage is below under-voltage
threshold.
0 LDO3_OV_STAT R 0h Status bit indicating that LDO3 output voltage is above over-voltage
threshold.

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8.7.1.108 STAT_VMON Register (Offset = 72h) [Reset = 00h]

STAT_VMON is shown in Figure 8-169 and described in Table 8-132.
Return to the Summary Table.
Figure 8-169. STAT_VMON Register
7 6 5 4 3 2 1 0
RESERVED VCCA_UV_STA VCCA_OV_STA
T T
R-0h R-0h R-0h

Table 8-132. STAT_VMON Register Field Descriptions

Bit Field Type Reset Description
7-2 RESERVED R 0h
1 VCCA_UV_STAT R 0h Status bit indicating that VCCA input voltage is below under-voltage
level.
0 VCCA_OV_STAT R 0h Status bit indicating that VCCA input voltage is above over-voltage
level.

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8.7.1.109 STAT_STARTUP Register (Offset = 73h) [Reset = 00h]

STAT_STARTUP is shown in Figure 8-170 and described in Table 8-133.
Return to the Summary Table.
Figure 8-170. STAT_STARTUP Register
7 6 5 4 3 2 1 0
RESERVED ENABLE_STAT RESERVED
R-0h R-0h R-0h

Table 8-133. STAT_STARTUP Register Field Descriptions

Bit Field Type Reset Description
7-2 RESERVED R 0h
1 ENABLE_STAT R 0h Status bit indicating nPWRON / EN pin status
0 RESERVED R 0h

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8.7.1.110 STAT_MISC Register (Offset = 74h) [Reset = 00h]

STAT_MISC is shown in Figure 8-171 and described in Table 8-134.
Return to the Summary Table.
Figure 8-171. STAT_MISC Register
7 6 5 4 3 2 1 0
RESERVED TWARN_STAT RESERVED EXT_CLK_STA RESERVED
T
R-0h R-0h R-0h R-0h R-0h

Table 8-134. STAT_MISC Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R 0h
3 TWARN_STAT R 0h Status bit indicating that die junction temperature is above the
thermal warning level.
2 RESERVED R 0h
1 EXT_CLK_STAT R 0h Status bit indicating that external clock is not valid.
0 RESERVED R 0h

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8.7.1.111 STAT_MODERATE_ERR Register (Offset = 75h) [Reset = 00h]

STAT_MODERATE_ERR is shown in Figure 8-172 and described in Table 8-135.
Return to the Summary Table.
Figure 8-172. STAT_MODERATE_ERR Register
7 6 5 4 3 2 1 0
RESERVED TSD_ORD_STA
T
R-0h R-0h

Table 8-135. STAT_MODERATE_ERR Register Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R 0h
0 TSD_ORD_STAT R 0h Status bit indicating that the die junction temperature is above the
thermal level causing a sequenced shutdown.

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8.7.1.112 STAT_SEVERE_ERR Register (Offset = 76h) [Reset = 00h]

STAT_SEVERE_ERR is shown in Figure 8-173 and described in Table 8-136.
Return to the Summary Table.
Figure 8-173. STAT_SEVERE_ERR Register
7 6 5 4 3 2 1 0
RESERVED VCCA_OVP_S TSD_IMM_STA
TAT T
R-0h R-0h R-0h

Table 8-136. STAT_SEVERE_ERR Register Field Descriptions

Bit Field Type Reset Description
7-2 RESERVED R 0h
1 VCCA_OVP_STAT R 0h Status bit indicating that the VCCA voltage is above overvoltage
protection level.
0 TSD_IMM_STAT R 0h Status bit indicating that the die junction temperature is above the
thermal level causing an immediate shutdown.

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8.7.1.113 STAT_READBACK_ERR Register (Offset = 77h) [Reset = 00h]

STAT_READBACK_ERR is shown in Figure 8-174 and described in Table 8-137.
Return to the Summary Table.
Figure 8-174. STAT_READBACK_ERR Register
7 6 5 4 3 2 1 0
RESERVED NRSTOUT_SO NRSTOUT_RE NINT_READBA EN_DRV_REA
C_READBACK ADBACK_STAT CK_STAT DBACK_STAT
_STAT
R-0h R-0h R-0h R-0h R-0h

Table 8-137. STAT_READBACK_ERR Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R 0h
3 NRSTOUT_SOC_READB R 0h Status bit indicating that NRSTOUT_SOC pin output is high and
ACK_STAT device is driving it low.
2 NRSTOUT_READBACK_ R 0h Status bit indicating that NRSTOUT pin output is high and device is
STAT driving it low.
1 NINT_READBACK_STAT R 0h Status bit indicating that NINT pin output is high and device is driving
it low.
0 EN_DRV_READBACK_S R 0h Status bit indicating that EN_DRV pin output is different than driven.
TAT

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8.7.1.114 PGOOD_SEL_1 Register (Offset = 78h) [Reset = 00h]

PGOOD_SEL_1 is shown in Figure 8-175 and described in Table 8-138.
Return to the Summary Table.
Figure 8-175. PGOOD_SEL_1 Register
7 6 5 4 3 2 1 0
PGOOD_SEL_BUCK4 PGOOD_SEL_BUCK3 PGOOD_SEL_BUCK2 PGOOD_SEL_BUCK1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-138. PGOOD_SEL_1 Register Field Descriptions

Bit Field Type Reset Description
7-6 PGOOD_SEL_BUCK4 R/W 0h PGOOD signal source control from BUCK4
(Default from NVM memory)
0h = Masked
1h = Powergood threshold voltage
2h = Powergood threshold voltage AND current limit
3h = Powergood threshold voltage AND current limit
5-4 PGOOD_SEL_BUCK3 R/W 0h PGOOD signal source control from BUCK3
(Default from NVM memory)
0h = Masked
1h = Powergood threshold voltage
2h = Powergood threshold voltage AND current limit
3h = Powergood threshold voltage AND current limit
3-2 PGOOD_SEL_BUCK2 R/W 0h PGOOD signal source control from BUCK2
(Default from NVM memory)
0h = Masked
1h = Powergood threshold voltage
2h = Powergood threshold voltage AND current limit
3h = Powergood threshold voltage AND current limit
1-0 PGOOD_SEL_BUCK1 R/W 0h PGOOD signal source control from BUCK1
(Default from NVM memory)
0h = Masked
1h = Powergood threshold voltage
2h = Powergood threshold voltage AND current limit
3h = Powergood threshold voltage AND current limit

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8.7.1.115 PGOOD_SEL_2 Register (Offset = 79h) [Reset = 00h]

PGOOD_SEL_2 is shown in Figure 8-176 and described in Table 8-139.
Return to the Summary Table.
Figure 8-176. PGOOD_SEL_2 Register
7 6 5 4 3 2 1 0
RESERVED PGOOD_SEL_BUCK5
R/W-0h R/W-0h

Table 8-139. PGOOD_SEL_2 Register Field Descriptions

Bit Field Type Reset Description
7-2 RESERVED R/W 0h
1-0 PGOOD_SEL_BUCK5 R/W 0h PGOOD signal source control from BUCK5
(Default from NVM memory)
0h = Masked
1h = Powergood threshold voltage
2h = Powergood threshold voltage AND current limit
3h = Powergood threshold voltage AND current limit

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8.7.1.116 PGOOD_SEL_3 Register (Offset = 7Ah) [Reset = 00h]

PGOOD_SEL_3 is shown in Figure 8-177 and described in Table 8-140.
Return to the Summary Table.
Figure 8-177. PGOOD_SEL_3 Register
7 6 5 4 3 2 1 0
PGOOD_SEL_LDO4 PGOOD_SEL_LDO3 PGOOD_SEL_LDO2 PGOOD_SEL_LDO1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-140. PGOOD_SEL_3 Register Field Descriptions

Bit Field Type Reset Description
7-6 PGOOD_SEL_LDO4 R/W 0h PGOOD signal source control from LDO4
(Default from NVM memory)
0h = Masked
1h = Powergood threshold voltage
2h = Powergood threshold voltage AND current limit
3h = Powergood threshold voltage AND current limit
5-4 PGOOD_SEL_LDO3 R/W 0h PGOOD signal source control from LDO3
(Default from NVM memory)
0h = Masked
1h = Powergood threshold voltage
2h = Powergood threshold voltage AND current limit
3h = Powergood threshold voltage AND current limit
3-2 PGOOD_SEL_LDO2 R/W 0h PGOOD signal source control from LDO2
(Default from NVM memory)
0h = Masked
1h = Powergood threshold voltage
2h = Powergood threshold voltage AND current limit
3h = Powergood threshold voltage AND current limit
1-0 PGOOD_SEL_LDO1 R/W 0h PGOOD signal source control from LDO1
(Default from NVM memory)
0h = Masked
1h = Powergood threshold voltage
2h = Powergood threshold voltage AND current limit
3h = Powergood threshold voltage AND current limit

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8.7.1.117 PGOOD_SEL_4 Register (Offset = 7Bh) [Reset = 00h]

PGOOD_SEL_4 is shown in Figure 8-178 and described in Table 8-141.
Return to the Summary Table.
Figure 8-178. PGOOD_SEL_4 Register
7 6 5 4 3 2 1 0
PGOOD_WIND PGOOD_POL PGOOD_SEL_ PGOOD_SEL_ PGOOD_SEL_ RESERVED PGOOD_SEL_
OW NRSTOUT_SO NRSTOUT TDIE_WARN VCCA
C
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-141. PGOOD_SEL_4 Register Field Descriptions

Bit Field Type Reset Description
7 PGOOD_WINDOW R/W 0h Type of voltage monitoring for PGOOD signal:
(Default from NVM memory)
0h = Only undervoltage is monitored
1h = Both undervoltage and overvoltage are monitored
6 PGOOD_POL R/W 0h PGOOD signal polarity select:
(Default from NVM memory)
0h = PGOOD signal is high when monitored inputs are valid
1h = PGOOD signal is low when monitored inputs are valid
5 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT_SOC pin:
_SOC (Default from NVM memory)
0h = Masked
1h = nRSTOUT_SOC pin low state forces PGOOD signal to low
4 PGOOD_SEL_NRSTOUT R/W 0h PGOOD signal source control from nRSTOUT pin:
(Default from NVM memory)
0h = Masked
1h = nRSTOUT pin low state forces PGOOD signal to low
3 PGOOD_SEL_TDIE_WAR R/W 0h PGOOD signal source control from thermal warning
N (Default from NVM memory)
0h = Masked
1h = Thermal warning affecting to PGOOD signal
2-1 RESERVED R/W 0h
0 PGOOD_SEL_VCCA R/W 0h PGOOD signal source control from VCCA monitoring
(Default from NVM memory)
0h = Masked
1h = VCCA OV/UV threshold affecting PGOOD signal

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8.7.1.118 PLL_CTRL Register (Offset = 7Ch) [Reset = 00h]

PLL_CTRL is shown in Figure 8-179 and described in Table 8-142.
Return to the Summary Table.
Figure 8-179. PLL_CTRL Register
7 6 5 4 3 2 1 0
RESERVED EXT_CLK_FREQ
R/W-0h R/W-0h

Table 8-142. PLL_CTRL Register Field Descriptions

Bit Field Type Reset Description
7-2 RESERVED R/W 0h
1-0 EXT_CLK_FREQ R/W 0h Frequency of the external clock (SYNCCLKIN):
See electrical specification for input clock frequency tolerance.
(Default from NVM memory)
0h = 1.1 MHz
1h = 2.2 MHz
2h = 4.4 MHz
3h = Reserved

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8.7.1.119 CONFIG_1 Register (Offset = 7Dh) [Reset = C0h]

CONFIG_1 is shown in Figure 8-180 and described in Table 8-143.
Return to the Summary Table.
Figure 8-180. CONFIG_1 Register
7 6 5 4 3 2 1 0
NSLEEP2_MAS NSLEEP1_MAS EN_ILIM_FSM_ I2C2_HS I2C1_HS RESERVED TSD_ORD_LEV TWARN_LEVE
K K CTRL EL L
R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-143. CONFIG_1 Register Field Descriptions

Bit Field Type Reset Description
7 NSLEEP2_MASK R/W 1h Masking for NSLEEP2 pin(s) and NSLEEP2B bit:
(Default from NVM memory)
0h = NSLEEP2(B) affects FSM state transitions.
1h = NSLEEP2(B) does not affect FSM state transitions.
6 NSLEEP1_MASK R/W 1h Masking for NSLEEP1 pin(s) and NSLEEP1B bit:
(Default from NVM memory)
0h = NSLEEP1(B) affects FSM state transitions.
1h = NSLEEP1(B) does not affect FSM state transitions.
5 EN_ILIM_FSM_CTRL R/W 0h (Default from NVM memory)
0h = Buck/LDO regulators ILIM interrupts do not affect FSM triggers.
1h = Buck/LDO regulators ILIM interrupts affect FSM triggers.
4 I2C2_HS R/W 0h Select I2C2 speed (input filter)
(Default from NVM memory)
0h = Standard, fast or fast+ by default, can be set to Hs-mode by
Hs-mode controller code.
1h = Forced to Hs-mode
3 I2C1_HS R/W 0h Select I2C1 speed (input filter)
(Default from NVM memory)
0h = Standard, fast or fast+ by default, can be set to Hs-mode by
Hs-mode controller code.
1h = Forced to Hs-mode
2 RESERVED R/W 0h
1 TSD_ORD_LEVEL R/W 0h Thermal shutdown threshold level.
(Default from NVM memory)
0h = 140C
1h = 145C
0 TWARN_LEVEL R/W 0h Thermal warning threshold level.
(Default from NVM memory)
0h = 130C
1h = 140C

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8.7.1.120 CONFIG_2 Register (Offset = 7Eh) [Reset = 00h]

CONFIG_2 is shown in Figure 8-181 and described in Table 8-144.
Return to the Summary Table.
Figure 8-181. CONFIG_2 Register
7 6 5 4 3 2 1 0
BB_EOC_RDY RESERVED BB_VEOC BB_ICHR BB_CHARGER
_EN
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-144. CONFIG_2 Register Field Descriptions

Bit Field Type Reset Description
7 BB_EOC_RDY R 0h Backup end of charge indication
0h = Charging active or not enabled
1h = Charger has reached termination voltage set by BB_VEOC
register
6-4 RESERVED R/W 0h
3-2 BB_VEOC R/W 0h End of charge voltage for backup battery charger:
(Default from NVM memory)
0h = 2.5V
1h = 2.8V
2h = 3.0V
3h = 3.3V
1 BB_ICHR R/W 0h Backup battery charging current:
(Default from NVM memory)
0h = 100uA
1h = 500uA
0 BB_CHARGER_EN R/W 0h Backup battery charging:
0h = Disabled
1h = Enabled

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8.7.1.121 ENABLE_DRV_REG Register (Offset = 80h) [Reset = 00h]

ENABLE_DRV_REG is shown in Figure 8-182 and described in Table 8-145.
Return to the Summary Table.
Figure 8-182. ENABLE_DRV_REG Register
7 6 5 4 3 2 1 0
RESERVED ENABLE_DRV
R/W-0h R/W-0h

Table 8-145. ENABLE_DRV_REG Register Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R/W 0h
0 ENABLE_DRV R/W 0h Control for EN_DRV pin:
FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin.
Otherwise EN_DRV pin is low.
0h = Low
1h = High

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8.7.1.122 MISC_CTRL Register (Offset = 81h) [Reset = 00h]

MISC_CTRL is shown in Figure 8-183 and described in Table 8-146.
Return to the Summary Table.
Figure 8-183. MISC_CTRL Register
7 6 5 4 3 2 1 0
SYNCCLKOUT_FREQ_SEL SEL_EXT_CLK AMUXOUT_EN CLKMON_EN LPM_EN NRSTOUT_SO NRSTOUT
C
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-146. MISC_CTRL Register Field Descriptions

Bit Field Type Reset Description
7-6 SYNCCLKOUT_FREQ_S R/W 0h SYNCCLKOUT enable/frequency select:
EL 0h = SYNCCLKOUT off
1h = 1.1 MHz
2h = 2.2 MHz
3h = 4.4 MHz
5 SEL_EXT_CLK R/W 0h Selection of external clock:
0h = Forced to internal RC oscillator.
1h = Automatic external clock used when available, interrupt is
generated if the external clock is expected (SEL_EXT_CLK = 1), but
it is not available or the clock frequency is not within the valid range.
4 AMUXOUT_EN R/W 0h Control bandgap voltage to AMUXOUT pin.
0h = Disabled
1h = Enabled
3 CLKMON_EN R/W 0h Control of internal clock monitoring.
0h = Disabled
1h = Enabled
2 LPM_EN R/W 0h Low power mode control.
LPM_EN sets device in a low power mode. Intended use case is
for the PFSM to set LPM_EN upon entering a deep sleep state.
The end objective is to disable the digital oscillator to reduce power
consumption.
The following functions are disabled when LPM_EN=1.
-TSD cycling of all sensors/thresholds
-regmap/SRAM CRC continuous checking
-SPMI WD NVM_ID request/response polling
-Disable clock monitoring
0h = Low power mode disabled
1h = Low power mode enabled
1 NRSTOUT_SOC R/W 0h Control for nRSTOUT_SOC signal:
0h = Low
1h = High
0 NRSTOUT R/W 0h Control for nRSTOUT signal:
0h = Low
1h = High

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8.7.1.123 ENABLE_DRV_STAT Register (Offset = 82h) [Reset = 08h]

ENABLE_DRV_STAT is shown in Figure 8-184 and described in Table 8-147.
Return to the Summary Table.
Figure 8-184. ENABLE_DRV_STAT Register
7 6 5 4 3 2 1 0
RESERVED SPMI_LPM_EN FORCE_EN_D NRSTOUT_SO NRSTOUT_IN EN_DRV_IN
RV_LOW C_IN
R/W-0h R/W-0h R/W-1h R-0h R-0h R-0h

Table 8-147. ENABLE_DRV_STAT Register Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R/W 0h
4 SPMI_LPM_EN R/W 0h This bit is read/write for PFSM and read-only for I2C/SPI
SPMI low power mode control.
SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI
WD (Bus heartbeat). PMICs enters SPMI_LPM_EN=1 at similar
times to prevent SPMI WD failures. Therefore to mitigate clock
variations, setting SPMI_LPM_EN=1 must be done early in the
sequence.
The following functions are disabled when SPMI_LPM_EN=1.
-SPMI WD NVM_ID request/response polling
0h = SPMI low power mode disabled
1h = SPMI low power mode enabled
3 FORCE_EN_DRV_LOW R/W 1h This bit is read/write for PFSM and read-only for I2C/SPI
0h = ENABLE_DRV bit can be written by I2C/SPI
1h = ENABLE_DRV bit is forced low and cannot be written high by
I2C/SPI
2 NRSTOUT_SOC_IN R 0h Level of NRSTOUT_SOC pin:
0h = Low
1h = High
1 NRSTOUT_IN R 0h Level of NRSTOUT pin:
0h = Low
1h = High
0 EN_DRV_IN R 0h Level of EN_DRV pin:
0h = Low
1h = High

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8.7.1.124 RECOV_CNT_REG_1 Register (Offset = 83h) [Reset = 00h]

RECOV_CNT_REG_1 is shown in Figure 8-185 and described in Table 8-148.
Return to the Summary Table.
Figure 8-185. RECOV_CNT_REG_1 Register
7 6 5 4 3 2 1 0
RESERVED RECOV_CNT
R-0h R-0h

Table 8-148. RECOV_CNT_REG_1 Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R 0h
3-0 RECOV_CNT R 0h Recovery counter status. Counter value is incremented each time
PMIC goes through warm reset.

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8.7.1.125 RECOV_CNT_REG_2 Register (Offset = 84h) [Reset = 00h]

RECOV_CNT_REG_2 is shown in Figure 8-186 and described in Table 8-149.
Return to the Summary Table.
Figure 8-186. RECOV_CNT_REG_2 Register
7 6 5 4 3 2 1 0
RESERVED RECOV_CNT_ RECOV_CNT_THR
CLR
R/W-0h R/WSelfClrF-0h R/W-0h

Table 8-149. RECOV_CNT_REG_2 Register Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R/W 0h
4 RECOV_CNT_CLR R/WSelfClrF 0h Recovery counter clear. Write 1 to clear the counter. This bit is
automatically set back to 0.
3-0 RECOV_CNT_THR R/W 0h Recovery counter threshold value for immediate power-down of all
supply rails.
(Default from NVM memory)

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8.7.1.126 FSM_I2C_TRIGGERS Register (Offset = 85h) [Reset = 00h]

FSM_I2C_TRIGGERS is shown in Figure 8-187 and described in Table 8-150.
Return to the Summary Table.
Figure 8-187. FSM_I2C_TRIGGERS Register
7 6 5 4 3 2 1 0
TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_
7 6 5 4 3 2 1 0
R/W-0h R/W-0h R/W-0h R/W-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h R/WSelfClrF-0h

Table 8-150. FSM_I2C_TRIGGERS Register Field Descriptions

Bit Field Type Reset Description
7 TRIGGER_I2C_7 R/W 0h Trigger for PFSM program.
6 TRIGGER_I2C_6 R/W 0h Trigger for PFSM program.
5 TRIGGER_I2C_5 R/W 0h Trigger for PFSM program.
4 TRIGGER_I2C_4 R/W 0h Trigger for PFSM program.
3 TRIGGER_I2C_3 R/WSelfClrF 0h Trigger for PFSM program.
This bit is automatically cleared. Writing this bit 1 creates PFSM
trigger pulse.
2 TRIGGER_I2C_2 R/WSelfClrF 0h Trigger for PFSM program.
This bit is automatically cleared. Writing this bit 1 creates PFSM
trigger pulse.
1 TRIGGER_I2C_1 R/WSelfClrF 0h Trigger for PFSM program.
This bit is automatically cleared. Writing this bit 1 creates PFSM
trigger pulse.
0 TRIGGER_I2C_0 R/WSelfClrF 0h Trigger for PFSM program.
This bit is automatically cleared. Writing this bit 1 creates PFSM
trigger pulse.

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8.7.1.127 FSM_NSLEEP_TRIGGERS Register (Offset = 86h) [Reset = 00h]

FSM_NSLEEP_TRIGGERS is shown in Figure 8-188 and described in Table 8-151.
Return to the Summary Table.
Figure 8-188. FSM_NSLEEP_TRIGGERS Register
7 6 5 4 3 2 1 0
RESERVED NSLEEP2B NSLEEP1B
R/W-0h R/W-0h R/W-0h

Table 8-151. FSM_NSLEEP_TRIGGERS Register Field Descriptions

Bit Field Type Reset Description
7-2 RESERVED R/W 0h
1 NSLEEP2B R/W 0h Parallel register bit for NSLEEP2 function:
0h = NSLEEP2 low
1h = NSLEEP2 high
0 NSLEEP1B R/W 0h Parallel register bit for NSLEEP1 function:
0h = NSLEEP1 low
1h = NSLEEP1 high

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8.7.1.128 BUCK_RESET_REG Register (Offset = 87h) [Reset = 00h]

BUCK_RESET_REG is shown in Figure 8-189 and described in Table 8-152.
Return to the Summary Table.
Figure 8-189. BUCK_RESET_REG Register
7 6 5 4 3 2 1 0
RESERVED BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-152. BUCK_RESET_REG Register Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R/W 0h
4 BUCK5_RESET R/W 0h Reset signal for Buck logic.
Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1'
DURING DEVICE OPERATION.
3 BUCK4_RESET R/W 0h Reset signal for Buck logic.
Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1'
DURING DEVICE OPERATION.
2 BUCK3_RESET R/W 0h Reset signal for Buck logic.
Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1'
DURING DEVICE OPERATION.
1 BUCK2_RESET R/W 0h Reset signal for Buck logic.
Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1'
DURING DEVICE OPERATION.
0 BUCK1_RESET R/W 0h Reset signal for Buck logic.
Warning: This bit is for debug only. DO NOT SET THIS BIT TO '1'
DURING DEVICE OPERATION.

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8.7.1.129 SPREAD_SPECTRUM_1 Register (Offset = 88h) [Reset = 00h]

SPREAD_SPECTRUM_1 is shown in Figure 8-190 and described in Table 8-153.
Return to the Summary Table.
Figure 8-190. SPREAD_SPECTRUM_1 Register
7 6 5 4 3 2 1 0
RESERVED SS_EN SS_DEPTH
R/W-0h R/W-0h R/W-0h

Table 8-153. SPREAD_SPECTRUM_1 Register Field Descriptions

Bit Field Type Reset Description
7-3 RESERVED R/W 0h
2 SS_EN R/W 0h Spread spectrum enable.
(Default from NVM memory)
0h = Spread spectrum disabled
1h = Spread spectrum enabled
1-0 SS_DEPTH R/W 0h Spread spectrum modulation depth.
(Default from NVM memory)
0h = No modulation
1h = +/- 6.3%
2h = +/- 8.4%
3h = RESERVED

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8.7.1.130 FREQ_SEL Register (Offset = 8Ah) [Reset = 00h]

FREQ_SEL is shown in Figure 8-191 and described in Table 8-154.
Return to the Summary Table.
Figure 8-191. FREQ_SEL Register
7 6 5 4 3 2 1 0
RESERVED BUCK5_FREQ_ BUCK4_FREQ_ BUCK3_FREQ_ BUCK2_FREQ_ BUCK1_FREQ_
SEL SEL SEL SEL SEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-154. FREQ_SEL Register Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R/W 0h
4 BUCK5_FREQ_SEL R/W 0h Buck5 switching frequency:
This bit is Read/Write or Read-Only for I2C/SPI access depending on
NVM configuration. See Technical Reference Manual / User's Guide
for details.
(Default from NVM memory)
0h = 2.2 MHz
1h = 4.4 MHz
3 BUCK4_FREQ_SEL R/W 0h Buck4 switching frequency:
This bit is Read/Write or Read-Only for I2C/SPI access depending on
NVM configuration. See Technical Reference Manual / User's Guide
for details.
(Default from NVM memory)
0h = 2.2 MHz
1h = 4.4 MHz
2 BUCK3_FREQ_SEL R/W 0h Buck3 switching frequency:
This bit is Read/Write or Read-Only for I2C/SPI access depending on
NVM configuration. See Technical Reference Manual / User's Guide
for details.
(Default from NVM memory)
0h = 2.2 MHz
1h = 4.4 MHz
1 BUCK2_FREQ_SEL R/W 0h Buck2 switching frequency:
This bit is Read/Write or Read-Only for I2C/SPI access depending on
NVM configuration. See Technical Reference Manual / User's Guide
for details.
(Default from NVM memory)
0h = 2.2 MHz
1h = 4.4 MHz
0 BUCK1_FREQ_SEL R/W 0h Buck1 switching frequency:
This bit is Read/Write or Read-Only for I2C/SPI access depending on
NVM configuration. See Technical Reference Manual / User's Guide
for details.
(Default from NVM memory)
0h = 2.2 MHz
1h = 4.4 MHz

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8.7.1.131 FSM_STEP_SIZE Register (Offset = 8Bh) [Reset = 00h]

FSM_STEP_SIZE is shown in Figure 8-192 and described in Table 8-155.
Return to the Summary Table.
Figure 8-192. FSM_STEP_SIZE Register
7 6 5 4 3 2 1 0
RESERVED PFSM_DELAY_STEP
R/W-0h R/W-0h

Table 8-155. FSM_STEP_SIZE Register Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R/W 0h
4-0 PFSM_DELAY_STEP R/W 0h Step size for PFSM sequence counter.
Step size is 50ns * 2PFSM_DELAY_STEP.
(Default from NVM memory)

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8.7.1.132 USER_SPARE_REGS Register (Offset = 8Eh) [Reset = 00h]

USER_SPARE_REGS is shown in Figure 8-193 and described in Table 8-156.
Return to the Summary Table.
Figure 8-193. USER_SPARE_REGS Register
7 6 5 4 3 2 1 0
RESERVED USER_SPARE_ USER_SPARE_ USER_SPARE_ USER_SPARE_
4 3 2 1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-156. USER_SPARE_REGS Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3 USER_SPARE_4 R/W 0h (Default from NVM memory)
2 USER_SPARE_3 R/W 0h (Default from NVM memory)
1 USER_SPARE_2 R/W 0h (Default from NVM memory)
0 USER_SPARE_1 R/W 0h (Default from NVM memory)

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8.7.1.133 ESM_MCU_START_REG Register (Offset = 8Fh) [Reset = 00h]

ESM_MCU_START_REG is shown in Figure 8-194 and described in Table 8-157.
Return to the Summary Table.
Figure 8-194. ESM_MCU_START_REG Register
7 6 5 4 3 2 1 0
RESERVED ESM_MCU_ST
ART
R/W-0h R/W-0h

Table 8-157. ESM_MCU_START_REG Register Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R/W 0h
0 ESM_MCU_START R/W 0h Control bit to start the ESM_MCU:
0h = ESM_MCU not started. Device clears ENABLE_DRV bit when
bit ESM_MCU_EN=1
1h = ESM_MCU started.

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8.7.1.134 ESM_MCU_DELAY1_REG Register (Offset = 90h) [Reset = 00h]

ESM_MCU_DELAY1_REG is shown in Figure 8-195 and described in Table 8-158.
Return to the Summary Table.
Figure 8-195. ESM_MCU_DELAY1_REG Register
7 6 5 4 3 2 1 0
ESM_MCU_DELAY1
R/W-0h

Table 8-158. ESM_MCU_DELAY1_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_MCU_DELAY1 R/W 0h These bits configure the duration of the ESM_MCU delay-1 time-
interval (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_MCU_START=0.

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8.7.1.135 ESM_MCU_DELAY2_REG Register (Offset = 91h) [Reset = 00h]

ESM_MCU_DELAY2_REG is shown in Figure 8-196 and described in Table 8-159.
Return to the Summary Table.
Figure 8-196. ESM_MCU_DELAY2_REG Register
7 6 5 4 3 2 1 0
ESM_MCU_DELAY2
R/W-0h

Table 8-159. ESM_MCU_DELAY2_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_MCU_DELAY2 R/W 0h These bits configure the duration of the ESM_MCU delay-2 time-
interval (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_MCU_START=0.

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8.7.1.136 ESM_MCU_MODE_CFG Register (Offset = 92h) [Reset = 00h]

ESM_MCU_MODE_CFG is shown in Figure 8-197 and described in Table 8-160.
Return to the Summary Table.
Figure 8-197. ESM_MCU_MODE_CFG Register
7 6 5 4 3 2 1 0
ESM_MCU_MO ESM_MCU_EN ESM_MCU_EN RESERVED ESM_MCU_ERR_CNT_TH
DE DRV
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-160. ESM_MCU_MODE_CFG Register Field Descriptions

Bit Field Type Reset Description
7 ESM_MCU_MODE R/W 0h This bit selects the mode for the ESM_MCU:
These bits can be only be written when control bit
ESM_MCU_START=0.
0h = Level Mode
1h = PWM Mode
6 ESM_MCU_EN R/W 0h ESM_MCU enable configuration bit:
These bits can be only be written when control bit
ESM_MCU_START=0.
0h = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all
other interrupt bits are cleared
1h = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if:
- bit ESM_MCU_START=1, and
- (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and
- ESM_MCU_RST_INT=0, and
- all other interrupt bits are cleared
5 ESM_MCU_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for
ESM_MCU:
These bits can be only be written when control bit
ESM_MCU_START=0.
0h = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1
1h = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1
4 RESERVED R/W 0h
3-0 ESM_MCU_ERR_CNT_T R/W 0h Configuration bits for the threshold of the ESM_MCU error-counter.
H The ESM_MCU starts the Error Handling Procedure (see
Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] >
ESM_MCU_ERR_CNT_TH[3:0].
These bits can be only be written when control bit
ESM_MCU_START=0.

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8.7.1.137 ESM_MCU_HMAX_REG Register (Offset = 93h) [Reset = 00h]

ESM_MCU_HMAX_REG is shown in Figure 8-198 and described in Table 8-161.
Return to the Summary Table.
Figure 8-198. ESM_MCU_HMAX_REG Register
7 6 5 4 3 2 1 0
ESM_MCU_HMAX
R/W-0h

Table 8-161. ESM_MCU_HMAX_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_MCU_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold
(tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_MCU_START=0.

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8.7.1.138 ESM_MCU_HMIN_REG Register (Offset = 94h) [Reset = 00h]

ESM_MCU_HMIN_REG is shown in Figure 8-199 and described in Table 8-162.
Return to the Summary Table.
Figure 8-199. ESM_MCU_HMIN_REG Register
7 6 5 4 3 2 1 0
ESM_MCU_HMIN
R/W-0h

Table 8-162. ESM_MCU_HMIN_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_MCU_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold
(tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_MCU_START=0.

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8.7.1.139 ESM_MCU_LMAX_REG Register (Offset = 95h) [Reset = 00h]

ESM_MCU_LMAX_REG is shown in Figure 8-200 and described in Table 8-163.
Return to the Summary Table.
Figure 8-200. ESM_MCU_LMAX_REG Register
7 6 5 4 3 2 1 0
ESM_MCU_LMAX
R/W-0h

Table 8-163. ESM_MCU_LMAX_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_MCU_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold
(tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_MCU_START=0.

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8.7.1.140 ESM_MCU_LMIN_REG Register (Offset = 96h) [Reset = 00h]

ESM_MCU_LMIN_REG is shown in Figure 8-201 and described in Table 8-164.
Return to the Summary Table.
Figure 8-201. ESM_MCU_LMIN_REG Register
7 6 5 4 3 2 1 0
ESM_MCU_LMIN
R/W-0h

Table 8-164. ESM_MCU_LMIN_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_MCU_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold
(tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_MCU_START=0.

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8.7.1.141 ESM_MCU_ERR_CNT_REG Register (Offset = 97h) [Reset = 00h]

ESM_MCU_ERR_CNT_REG is shown in Figure 8-202 and described in Table 8-165.
Return to the Summary Table.
Figure 8-202. ESM_MCU_ERR_CNT_REG Register
7 6 5 4 3 2 1 0
RESERVED ESM_MCU_ERR_CNT
R-0h R-0h

Table 8-165. ESM_MCU_ERR_CNT_REG Register Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R 0h
4-0 ESM_MCU_ERR_CNT R 0h Status bits to indicate the value of the ESM_MCU Error-Counter. The
device clears these bits when ESM_MCU_START bit is 0, or when
the device resets the MCU.

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8.7.1.142 ESM_SOC_START_REG Register (Offset = 98h) [Reset = 00h]

ESM_SOC_START_REG is shown in Figure 8-203 and described in Table 8-166.
Return to the Summary Table.
Figure 8-203. ESM_SOC_START_REG Register
7 6 5 4 3 2 1 0
RESERVED ESM_SOC_ST
ART
R/W-0h R/W-0h

Table 8-166. ESM_SOC_START_REG Register Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R/W 0h
0 ESM_SOC_START R/W 0h Control bit to start the ESM_SoC:
0h = ESM_SoC not started. Device clears ENABLE_DRV bit when
bit ESM_SOC_EN=1
1h = ESM_SoC started

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8.7.1.143 ESM_SOC_DELAY1_REG Register (Offset = 99h) [Reset = 00h]

ESM_SOC_DELAY1_REG is shown in Figure 8-204 and described in Table 8-167.
Return to the Summary Table.
Figure 8-204. ESM_SOC_DELAY1_REG Register
7 6 5 4 3 2 1 0
ESM_SOC_DELAY1
R/W-0h

Table 8-167. ESM_SOC_DELAY1_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_SOC_DELAY1 R/W 0h These bits configure the duration of the ESM_SoC delay-1 time-
interval (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_SOC_START=0.

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8.7.1.144 ESM_SOC_DELAY2_REG Register (Offset = 9Ah) [Reset = 00h]

ESM_SOC_DELAY2_REG is shown in Figure 8-205 and described in Table 8-168.
Return to the Summary Table.
Figure 8-205. ESM_SOC_DELAY2_REG Register
7 6 5 4 3 2 1 0
ESM_SOC_DELAY2
R/W-0h

Table 8-168. ESM_SOC_DELAY2_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_SOC_DELAY2 R/W 0h These bits configure the duration of the ESM_SoC delay-2 time-
interval (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_SOC_START=0.

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8.7.1.145 ESM_SOC_MODE_CFG Register (Offset = 9Bh) [Reset = 00h]

ESM_SOC_MODE_CFG is shown in Figure 8-206 and described in Table 8-169.
Return to the Summary Table.
Figure 8-206. ESM_SOC_MODE_CFG Register
7 6 5 4 3 2 1 0
ESM_SOC_MO ESM_SOC_EN ESM_SOC_EN RESERVED ESM_SOC_ERR_CNT_TH
DE DRV
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-169. ESM_SOC_MODE_CFG Register Field Descriptions

Bit Field Type Reset Description
7 ESM_SOC_MODE R/W 0h This bit selects the mode for the ESM_SoC:
These bits can be only be written when control bit
ESM_SOC_START=0.
0h = Level Mode
1h = PWM Mode
6 ESM_SOC_EN R/W 0h ESM_SoC enable configuration bit:
These bits can be only be written when control bit
ESM_SOC_START=0.
0h = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all
other interrupt bits are cleared
1h = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if:
- bit ESM_SOC_START=1, and
- (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and
- ESM_SOC_RST_INT=0, and
- all other interrupt bits are cleared.
5 ESM_SOC_ENDRV R/W 0h Configuration bit to select ENABLE_DRV clear on ESM-error for
ESM_SoC:
These bits can be only be written when control bit
ESM_SOC_START=0
0h = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1
1h = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1.
4 RESERVED R/W 0h
3-0 ESM_SOC_ERR_CNT_T R/W 0h Configuration bits for the threshold of the ESM_SoC error-counter
H The ESM_SoC starts the Error Handling Procedure (see
Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] >
ESM_SOC_ERR_CNT_TH[3:0].
These bits can be only be written when control bit
ESM_SOC_START=0.

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8.7.1.146 ESM_SOC_HMAX_REG Register (Offset = 9Ch) [Reset = 00h]

ESM_SOC_HMAX_REG is shown in Figure 8-207 and described in Table 8-170.
Return to the Summary Table.
Figure 8-207. ESM_SOC_HMAX_REG Register
7 6 5 4 3 2 1 0
ESM_SOC_HMAX
R/W-0h

Table 8-170. ESM_SOC_HMAX_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_SOC_HMAX R/W 0h These bits configure the the maximum high-pulse time-threshold
(tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_SOC_START=0.

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8.7.1.147 ESM_SOC_HMIN_REG Register (Offset = 9Dh) [Reset = 00h]

ESM_SOC_HMIN_REG is shown in Figure 8-208 and described in Table 8-171.
Return to the Summary Table.
Figure 8-208. ESM_SOC_HMIN_REG Register
7 6 5 4 3 2 1 0
ESM_SOC_HMIN
R/W-0h

Table 8-171. ESM_SOC_HMIN_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_SOC_HMIN R/W 0h These bits configure the the minimum high-pulse time-threshold
(tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_SOC_START=0.

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8.7.1.148 ESM_SOC_LMAX_REG Register (Offset = 9Eh) [Reset = 00h]

ESM_SOC_LMAX_REG is shown in Figure 8-209 and described in Table 8-172.
Return to the Summary Table.
Figure 8-209. ESM_SOC_LMAX_REG Register
7 6 5 4 3 2 1 0
ESM_SOC_LMAX
R/W-0h

Table 8-172. ESM_SOC_LMAX_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_SOC_LMAX R/W 0h These bits configure the the maximum low-pulse time-threshold
(tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_SOC_START=0.

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8.7.1.149 ESM_SOC_LMIN_REG Register (Offset = 9Fh) [Reset = 00h]

ESM_SOC_LMIN_REG is shown in Figure 8-210 and described in Table 8-173.
Return to the Summary Table.
Figure 8-210. ESM_SOC_LMIN_REG Register
7 6 5 4 3 2 1 0
ESM_SOC_LMIN
R/W-0h

Table 8-173. ESM_SOC_LMIN_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 ESM_SOC_LMIN R/W 0h These bits configure the the minimum low-pulse time-threshold
(tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter).
These bits can be only be written when control bit
ESM_SOC_START=0.

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8.7.1.150 ESM_SOC_ERR_CNT_REG Register (Offset = A0h) [Reset = 00h]

ESM_SOC_ERR_CNT_REG is shown in Figure 8-211 and described in Table 8-174.
Return to the Summary Table.
Figure 8-211. ESM_SOC_ERR_CNT_REG Register
7 6 5 4 3 2 1 0
RESERVED ESM_SOC_ERR_CNT
R-0h R-0h

Table 8-174. ESM_SOC_ERR_CNT_REG Register Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R 0h
4-0 ESM_SOC_ERR_CNT R 0h Status bits to indicate the value of the ESM_SoC Error-Counter. The
device clears these bits when ESM_SOC_START bit is 0, or when
the device resets the SoC.

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8.7.1.151 REGISTER_LOCK Register (Offset = A1h) [Reset = 00h]

REGISTER_LOCK is shown in Figure 8-212 and described in Table 8-175.
Return to the Summary Table.
Figure 8-212. REGISTER_LOCK Register
7 6 5 4 3 2 1 0
RESERVED REGISTER_LO
CK_STATUS
R/W-0h R/W-0h

Table 8-175. REGISTER_LOCK Register Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R/W 0h
0 REGISTER_LOCK_STAT R/W 0h Unlocking registers: write 0x9B to this address.
US Locking registers: write anything else than 0x9B to this address.
Written 8 bit data to this address is not stored, only lock status can
be read.
REGISTER_LOCK_STATUS bit shows the lock status:
0h = Registers are unlocked
1h = Registers are locked

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8.7.1.152 MANUFACTURING_VER Register (Offset = A6h) [Reset = 00h]

MANUFACTURING_VER is shown in Figure 8-213 and described in Table 8-176.
Return to the Summary Table.
Figure 8-213. MANUFACTURING_VER Register
7 6 5 4 3 2 1 0
SILICON_REV
R-0h

Table 8-176. MANUFACTURING_VER Register Field Descriptions

Bit Field Type Reset Description
7-0 SILICON_REV R 0h SILICON_REV[7:6] - Reserved
SILICON_REV[5:3] - ALR
SILICON_REV[2:0] - Metal

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8.7.1.153 CUSTOMER_NVM_ID_REG Register (Offset = A7h) [Reset = 00h]

CUSTOMER_NVM_ID_REG is shown in Figure 8-214 and described in Table 8-177.
Return to the Summary Table.
Figure 8-214. CUSTOMER_NVM_ID_REG Register
7 6 5 4 3 2 1 0
CUSTOMER_NVM_ID
R/W-0h

Table 8-177. CUSTOMER_NVM_ID_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 CUSTOMER_NVM_ID R/W 0h Customer defined value if customer programmed part
Same value as in TI_NVM_ID register if TI programmed part

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8.7.1.154 SOFT_REBOOT_REG Register (Offset = ABh) [Reset = 00h]

SOFT_REBOOT_REG is shown in Figure 8-215 and described in Table 8-178.
Return to the Summary Table.
Figure 8-215. SOFT_REBOOT_REG Register
7 6 5 4 3 2 1 0
RESERVED SOFT_REBOO
T
R/W-0h R/WSelfClrF-0h

Table 8-178. SOFT_REBOOT_REG Register Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R/W 0h
0 SOFT_REBOOT R/WSelfClrF 0h Write 1 to request a soft reboot.
This bit is automatically cleared.

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8.7.1.155 RTC_SECONDS Register (Offset = B5h) [Reset = 00h]

RTC_SECONDS is shown in Figure 8-216 and described in Table 8-179.
Return to the Summary Table.
Figure 8-216. RTC_SECONDS Register
7 6 5 4 3 2 1 0
RESERVED SECOND_1 SECOND_0
R/W-0h R/W-0h R/W-0h

Table 8-179. RTC_SECONDS Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-4 SECOND_1 R/W 0h Second digit of seconds (range is 0 up to 5)
3-0 SECOND_0 R/W 0h First digit of seconds (range is 0 up to 9)

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8.7.1.156 RTC_MINUTES Register (Offset = B6h) [Reset = 00h]

RTC_MINUTES is shown in Figure 8-217 and described in Table 8-180.
Return to the Summary Table.
Figure 8-217. RTC_MINUTES Register
7 6 5 4 3 2 1 0
RESERVED MINUTE_1 MINUTE_0
R/W-0h R/W-0h R/W-0h

Table 8-180. RTC_MINUTES Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-4 MINUTE_1 R/W 0h Second digit of minutes (range is 0 up to 5)
3-0 MINUTE_0 R/W 0h First digit of minutes (range is 0 up to 9)

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8.7.1.157 RTC_HOURS Register (Offset = B7h) [Reset = 00h]

RTC_HOURS is shown in Figure 8-218 and described in Table 8-181.
Return to the Summary Table.
Figure 8-218. RTC_HOURS Register
7 6 5 4 3 2 1 0
PM_NAM RESERVED HOUR_1 HOUR_0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-181. RTC_HOURS Register Field Descriptions

Bit Field Type Reset Description
7 PM_NAM R/W 0h Only used in PM_AM mode (otherwise it is set to 0)
0h = AM
1h = PM
6 RESERVED R/W 0h
5-4 HOUR_1 R/W 0h Second digit of hours(range is 0 up to 2)
3-0 HOUR_0 R/W 0h First digit of hours (range is 0 up to 9)

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8.7.1.158 RTC_DAYS Register (Offset = B8h) [Reset = 00h]

RTC_DAYS is shown in Figure 8-219 and described in Table 8-182.
Return to the Summary Table.
Figure 8-219. RTC_DAYS Register
7 6 5 4 3 2 1 0
RESERVED DAY_1 DAY_0
R/W-0h R/W-0h R/W-0h

Table 8-182. RTC_DAYS Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-4 DAY_1 R/W 0h Second digit of days (range is 0 up to 3)
3-0 DAY_0 R/W 0h First digit of days (range is 0 up to 9)

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8.7.1.159 RTC_MONTHS Register (Offset = B9h) [Reset = 00h]

RTC_MONTHS is shown in Figure 8-220 and described in Table 8-183.
Return to the Summary Table.
Figure 8-220. RTC_MONTHS Register
7 6 5 4 3 2 1 0
RESERVED MONTH_1 MONTH_0
R/W-0h R/W-0h R/W-0h

Table 8-183. RTC_MONTHS Register Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R/W 0h
4 MONTH_1 R/W 0h Second digit of months (range is 0 up to 1)
3-0 MONTH_0 R/W 0h First digit of months (range is 0 up to 9)

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8.7.1.160 RTC_YEARS Register (Offset = BAh) [Reset = 00h]

RTC_YEARS is shown in Figure 8-221 and described in Table 8-184.
Return to the Summary Table.
Figure 8-221. RTC_YEARS Register
7 6 5 4 3 2 1 0
YEAR_1 YEAR_0
R/W-0h R/W-0h

Table 8-184. RTC_YEARS Register Field Descriptions

Bit Field Type Reset Description
7-4 YEAR_1 R/W 0h Second digit of years (range is 0 up to 9)
3-0 YEAR_0 R/W 0h First digit of years (range is 0 up to 9)

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8.7.1.161 RTC_WEEKS Register (Offset = BBh) [Reset = 00h]

RTC_WEEKS is shown in Figure 8-222 and described in Table 8-185.
Return to the Summary Table.
Figure 8-222. RTC_WEEKS Register
7 6 5 4 3 2 1 0
RESERVED WEEK
R/W-0h R/W-0h

Table 8-185. RTC_WEEKS Register Field Descriptions

Bit Field Type Reset Description
7-3 RESERVED R/W 0h
2-0 WEEK R/W 0h First digit of day of the week (range is 0 up to 6)

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8.7.1.162 ALARM_SECONDS Register (Offset = BCh) [Reset = 00h]

ALARM_SECONDS is shown in Figure 8-223 and described in Table 8-186.
Return to the Summary Table.
Figure 8-223. ALARM_SECONDS Register
7 6 5 4 3 2 1 0
RESERVED ALR_SECOND_1 ALR_SECOND_0
R/W-0h R/W-0h R/W-0h

Table 8-186. ALARM_SECONDS Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-4 ALR_SECOND_1 R/W 0h Second digit of alarm programmation for seconds (range is 0 up to 5)
3-0 ALR_SECOND_0 R/W 0h First digit of alarm programmation for seconds (range is 0 up to 9)

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8.7.1.163 ALARM_MINUTES Register (Offset = BDh) [Reset = 00h]

ALARM_MINUTES is shown in Figure 8-224 and described in Table 8-187.
Return to the Summary Table.
Figure 8-224. ALARM_MINUTES Register
7 6 5 4 3 2 1 0
RESERVED ALR_MINUTE_1 ALR_MINUTE_0
R/W-0h R/W-0h R/W-0h

Table 8-187. ALARM_MINUTES Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-4 ALR_MINUTE_1 R/W 0h Second digit of alarm programmation for minutes (range is 0 up to 5)
3-0 ALR_MINUTE_0 R/W 0h First digit of alarm programmation for minutes (range is 0 up to 9)

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8.7.1.164 ALARM_HOURS Register (Offset = BEh) [Reset = 00h]

ALARM_HOURS is shown in Figure 8-225 and described in Table 8-188.
Return to the Summary Table.
Figure 8-225. ALARM_HOURS Register
7 6 5 4 3 2 1 0
ALR_PM_NAM RESERVED ALR_HOUR_1 ALR_HOUR_0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-188. ALARM_HOURS Register Field Descriptions

Bit Field Type Reset Description
7 ALR_PM_NAM R/W 0h Only used in PM_AM mode for alarm programmation (otherwise it is
set to 0)
0h = AM
1h = PM
6 RESERVED R/W 0h
5-4 ALR_HOUR_1 R/W 0h Second digit of alarm programmation for hours(range is 0 up to 2)
3-0 ALR_HOUR_0 R/W 0h First digit of alarm programmation for hours (range is 0 up to 9)

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8.7.1.165 ALARM_DAYS Register (Offset = BFh) [Reset = 00h]

ALARM_DAYS is shown in Figure 8-226 and described in Table 8-189.
Return to the Summary Table.
Figure 8-226. ALARM_DAYS Register
7 6 5 4 3 2 1 0
RESERVED ALR_DAY_1 ALR_DAY_0
R/W-0h R/W-0h R/W-0h

Table 8-189. ALARM_DAYS Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R/W 0h
5-4 ALR_DAY_1 R/W 0h Second digit of alarm programmation for days (range is 0 up to 3)
3-0 ALR_DAY_0 R/W 0h First digit of alarm programmation for days (range is 0 up to 9)

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8.7.1.166 ALARM_MONTHS Register (Offset = C0h) [Reset = 00h]

ALARM_MONTHS is shown in Figure 8-227 and described in Table 8-190.
Return to the Summary Table.
Figure 8-227. ALARM_MONTHS Register
7 6 5 4 3 2 1 0
RESERVED ALR_MONTH_ ALR_MONTH_0
1
R/W-0h R/W-0h R/W-0h

Table 8-190. ALARM_MONTHS Register Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R/W 0h
4 ALR_MONTH_1 R/W 0h Second digit of alarm programmation for months (range is 0 up to 1)
3-0 ALR_MONTH_0 R/W 0h First digit of alarm programmation for months (range is 0 up to 9)

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8.7.1.167 ALARM_YEARS Register (Offset = C1h) [Reset = 00h]

ALARM_YEARS is shown in Figure 8-228 and described in Table 8-191.
Return to the Summary Table.
Figure 8-228. ALARM_YEARS Register
7 6 5 4 3 2 1 0
ALR_YEAR_1 ALR_YEAR_0
R/W-0h R/W-0h

Table 8-191. ALARM_YEARS Register Field Descriptions

Bit Field Type Reset Description
7-4 ALR_YEAR_1 R/W 0h Second digit of alarm programmation for years (range is 0 up to 9)
3-0 ALR_YEAR_0 R/W 0h First digit of alarm programmation for years (range is 0 up to 9)

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8.7.1.168 RTC_CTRL_1 Register (Offset = C2h) [Reset = 00h]

RTC_CTRL_1 is shown in Figure 8-229 and described in Table 8-192.
Return to the Summary Table.
Figure 8-229. RTC_CTRL_1 Register
7 6 5 4 3 2 1 0
RTC_V_OPT GET_TIME SET_32_COUN RESERVED MODE_12_24 AUTO_COMP ROUND_30S STOP_RTC
TER
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-192. RTC_CTRL_1 Register Field Descriptions

Bit Field Type Reset Description
7 RTC_V_OPT R/W 0h RTC date / time register selection:
0h = Read access directly to dynamic registers (RTC_SECONDS,
RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS,
RTC_YEAR, RTC_WEEKS)
1h = Read access to static shadowed registers: (see GET_TIME bit).
6 GET_TIME R/W 0h When writing a 1 into this register, the content of the dynamic
registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS,
RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is
transferred into static shadowed registers.
Each update of the shadowed registers needs to be done by re-
asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1)
Note: Shadowed registers, linked to the GET_TIME feature, are a
parallel set of calendar static registers, at the same I2C addresses
as the dynamic registers.
Note: The GET_TIME feature loads the RTC counter in the shadow
registers and make the content of the shadow registers available and
stable for reading.
Note: The GET_TIME bit has to be set to 0 and again to 1 to get a
new timing value.
Note: If the time reading is done without GET_TIME, the read value
comes directly from the RTC counter and software has to manage
the counter change during the reading.
Time reading remains always at the same address, with or without
using the GET_TIME feature.
5 SET_32_COUNTER R/W 0h Note: This bit must only be used when the RTC is frozen.
0h = No action
1h = Set the 32kHz counter with RTC_COMP_MSB_REG/
RTC_COMP_LSB_REG value
4 RESERVED R/W 0h
3 MODE_12_24 R/W 0h Note: It is possible to switch between the two modes at any time
without disturbed the RTC, read or write are always performed with
the current mode.
0h = 24 hours mode
1h = 12 hours mode (PM-AM mode)
2 AUTO_COMP R/W 0h AUTO_COMP
0h = No auto compensation
1h = Auto compensation enabled
1 ROUND_30S R/W 0h Note: This bit is a toggle bit, the micro-controller can only write one
and RTC clears it.
If the micro-controller sets the ROUND_30S bit and then read it, the
micro-controller reads one until the rounding to the closest minute is
performed at the next second.
0h = No update
1h = When a one is written, the time is rounded to the closest minute
0 STOP_RTC R/W 0h STOP_RTC
0h = RTC is frozen
1h = RTC is running

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8.7.1.169 RTC_CTRL_2 Register (Offset = C3h) [Reset = 00h]

RTC_CTRL_2 is shown in Figure 8-230 and described in Table 8-193.
Return to the Summary Table.
Figure 8-230. RTC_CTRL_2 Register
7 6 5 4 3 2 1 0
FIRST_START STARTUP_DEST FAST_BIST LP_STANDBY_ XTAL_SEL XTAL_EN
UP_DONE SEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-193. RTC_CTRL_2 Register Field Descriptions

Bit Field Type Reset Description
7 FIRST_STARTUP_DONE R/W 0h This bit controls if pre-configured NVM defaults are loaded to RTC
domain reg bits during NVM read
0h = pre-configured NVM defaults are loaded to RTC domain bits
1h = pre-configured NVM defaults are not loaded to RTC domain bits
6-5 STARTUP_DEST R/W 0h FSM start-up destination select.
(Default from NVM memory)
0h = STANDBY/LP_STANDBY based on LP_STANDBY_SEL
1h = Reserved
2h = MCU_ONLY
3h = ACTIVE
4 FAST_BIST R/W 0h FAST_BIST
(Default from NVM memory)
0h = Logic and analog BIST is run at BOOT BIST.
1h = Only analog BIST is run at BOOT BIST.
3 LP_STANDBY_SEL R/W 0h Control to enter low power standby state:
(Default from NVM memory)
0h = LDOINT is enabled in standby state.
1h = Low power standby state is used as standby state (LDOINT is
disabled).
2-1 XTAL_SEL R/W 0h Crystal oscillator type select
(Default from NVM memory)
0h = 6 pF
1h = 9 pF
2h = 12.5 pF
3h = Reserved
0 XTAL_EN R/W 0h Crystal oscillator enable.
(Default from NVM memory)
0h = Crystal oscillator is disabled
1h = Crystal oscillator is enabled

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8.7.1.170 RTC_STATUS Register (Offset = C4h) [Reset = 80h]

RTC_STATUS is shown in Figure 8-231 and described in Table 8-194.
Return to the Summary Table.
Figure 8-231. RTC_STATUS Register
7 6 5 4 3 2 1 0
POWER_UP ALARM TIMER RESERVED RUN RESERVED
R/W1C-1h R/W1C-0h R/W1C-0h R/W-0h R-0h R/W-0h

Table 8-194. RTC_STATUS Register Field Descriptions

Bit Field Type Reset Description
7 POWER_UP R/W1C 1h Indicates that a reset occurred (bit cleared to 0 by writing 1) and that
RTC data are not valid anymore.
Note: POWER_UP is set by a reset, is cleared by writing one in this
bit.
Note: The POWER_UP (RTC_STATUS) and RESET_STATUS
(RTC_RESET_STATUS) register bits indicate the same information.
6 ALARM R/W1C 0h Indicates that an alarm interrupt has been generated (bit clear by
writing 1).
5 TIMER R/W1C 0h Indicates that an timer interrupt has been generated (bit clear by
writing 1).
4-2 RESERVED R/W 0h
1 RUN R 0h Note: This bit shows the real state of the RTC, indeed because
of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz
clock, the action of this bit is delayed.
0h = RTC is frozen
1h = RTC is running
0 RESERVED R/W 0h

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8.7.1.171 RTC_INTERRUPTS Register (Offset = C5h) [Reset = 00h]

RTC_INTERRUPTS is shown in Figure 8-232 and described in Table 8-195.
Return to the Summary Table.
Figure 8-232. RTC_INTERRUPTS Register
7 6 5 4 3 2 1 0
RESERVED IT_ALARM IT_TIMER EVERY
R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-195. RTC_INTERRUPTS Register Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3 IT_ALARM R/W 0h Enable one interrupt when the alarm value is reached
(TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES,
ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS,
ALARM_YEARS) by the TC registers
NOTE: To prevent mis-firing of the ALARM interrupt, set the
IT_ALARM = 0 prior to configuring the ALARM registers
0h = interrupt disabled
1h = interrupt enabled
2 IT_TIMER R/W 0h Enable periodic interrupt
NOTE: To prevent mis-firing of the TIMER interrupt, set the
IT_TIMER = 0 prior to configuring the periodic time value
0h = interrupt disabled
1h = interrupt enabled
1-0 EVERY R/W 0h Interrupt period
0h = every second
1h = every minute
2h = every hour
3h = every day

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8.7.1.172 RTC_COMP_LSB Register (Offset = C6h) [Reset = 00h]

RTC_COMP_LSB is shown in Figure 8-233 and described in Table 8-196.
Return to the Summary Table.
Figure 8-233. RTC_COMP_LSB Register
7 6 5 4 3 2 1 0
COMP_LSB_RTC
R/W-0h

Table 8-196. RTC_COMP_LSB Register Field Descriptions

Bit Field Type Reset Description
7-0 COMP_LSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into
the 32kHz counter every hour [LSB]

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8.7.1.173 RTC_COMP_MSB Register (Offset = C7h) [Reset = 00h]

RTC_COMP_MSB is shown in Figure 8-234 and described in Table 8-197.
Return to the Summary Table.
Figure 8-234. RTC_COMP_MSB Register
7 6 5 4 3 2 1 0
COMP_MSB_RTC
R/W-0h

Table 8-197. RTC_COMP_MSB Register Field Descriptions

Bit Field Type Reset Description
7-0 COMP_MSB_RTC R/W 0h This register contains the number of 32kHz periods to be added into
the 32kHz counter every hour [MSB]

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8.7.1.174 RTC_RESET_STATUS Register (Offset = C8h) [Reset = 00h]

RTC_RESET_STATUS is shown in Figure 8-235 and described in Table 8-198.
Return to the Summary Table.
Figure 8-235. RTC_RESET_STATUS Register
7 6 5 4 3 2 1 0
RESERVED RESET_STATU
S_RTC
R/W-0h R/W-0h

Table 8-198. RTC_RESET_STATUS Register Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R/W 0h
0 RESET_STATUS_RTC R/W 0h This bit can only be set to one and is cleared when a manual reset
or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR
level) occur. If this bit is reset it means that the RTC has lost its
configuration.
Note: The RESET_STATUS (RTC_RESET_STATUS) and
POWER_UP (RTC_STATUS) register bits indicate the same
information.

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8.7.1.175 SCRATCH_PAD_REG_1 Register (Offset = C9h) [Reset = 00h]

SCRATCH_PAD_REG_1 is shown in Figure 8-236 and described in Table 8-199.
Return to the Summary Table.
Figure 8-236. SCRATCH_PAD_REG_1 Register
7 6 5 4 3 2 1 0
SCRATCH_PAD_1
R/W-0h

Table 8-199. SCRATCH_PAD_REG_1 Register Field Descriptions

Bit Field Type Reset Description
7-0 SCRATCH_PAD_1 R/W 0h Scratchpad for temporary data storage. The register is reset only
when VRTC is disabled. The data is maintained when VINT regulator
is disabled, for example during LP_STANDBY state.

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8.7.1.176 SCRATCH_PAD_REG_2 Register (Offset = CAh) [Reset = 00h]

SCRATCH_PAD_REG_2 is shown in Figure 8-237 and described in Table 8-200.
Return to the Summary Table.
Figure 8-237. SCRATCH_PAD_REG_2 Register
7 6 5 4 3 2 1 0
SCRATCH_PAD_2
R/W-0h

Table 8-200. SCRATCH_PAD_REG_2 Register Field Descriptions

Bit Field Type Reset Description
7-0 SCRATCH_PAD_2 R/W 0h Scratchpad for temporary data storage. The register is reset only
when VRTC is disabled. The data is maintained when VINT regulator
is disabled, for example during LP_STANDBY state.

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8.7.1.177 SCRATCH_PAD_REG_3 Register (Offset = CBh) [Reset = 00h]

SCRATCH_PAD_REG_3 is shown in Figure 8-238 and described in Table 8-201.
Return to the Summary Table.
Figure 8-238. SCRATCH_PAD_REG_3 Register
7 6 5 4 3 2 1 0
SCRATCH_PAD_3
R/W-0h

Table 8-201. SCRATCH_PAD_REG_3 Register Field Descriptions

Bit Field Type Reset Description
7-0 SCRATCH_PAD_3 R/W 0h Scratchpad for temporary data storage. The register is reset only
when VRTC is disabled. The data is maintained when VINT regulator
is disabled, for example during LP_STANDBY state.

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8.7.1.178 SCRATCH_PAD_REG_4 Register (Offset = CCh) [Reset = 00h]

SCRATCH_PAD_REG_4 is shown in Figure 8-239 and described in Table 8-202.
Return to the Summary Table.
Figure 8-239. SCRATCH_PAD_REG_4 Register
7 6 5 4 3 2 1 0
SCRATCH_PAD_4
R/W-0h

Table 8-202. SCRATCH_PAD_REG_4 Register Field Descriptions

Bit Field Type Reset Description
7-0 SCRATCH_PAD_4 R/W 0h Scratchpad for temporary data storage. The register is reset only
when VRTC is disabled. The data is maintained when VINT regulator
is disabled, for example during LP_STANDBY state.

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8.7.1.179 PFSM_DELAY_REG_1 Register (Offset = CDh) [Reset = 00h]

PFSM_DELAY_REG_1 is shown in Figure 8-240 and described in Table 8-203.
Return to the Summary Table.
Figure 8-240. PFSM_DELAY_REG_1 Register
7 6 5 4 3 2 1 0
PFSM_DELAY1
R/W-0h

Table 8-203. PFSM_DELAY_REG_1 Register Field Descriptions

Bit Field Type Reset Description
7-0 PFSM_DELAY1 R/W 0h Generic delay1 for PFSM use.
The step size is defined by PFSM_DELAY_STEP bits.
(Default from NVM memory)

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8.7.1.180 PFSM_DELAY_REG_2 Register (Offset = CEh) [Reset = 00h]

PFSM_DELAY_REG_2 is shown in Figure 8-241 and described in Table 8-204.
Return to the Summary Table.
Figure 8-241. PFSM_DELAY_REG_2 Register
7 6 5 4 3 2 1 0
PFSM_DELAY2
R/W-0h

Table 8-204. PFSM_DELAY_REG_2 Register Field Descriptions

Bit Field Type Reset Description
7-0 PFSM_DELAY2 R/W 0h Generic delay2 for PFSM use.
The step size is defined by PFSM_DELAY_STEP bits.
(Default from NVM memory)

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8.7.1.181 PFSM_DELAY_REG_3 Register (Offset = CFh) [Reset = 00h]

PFSM_DELAY_REG_3 is shown in Figure 8-242 and described in Table 8-205.
Return to the Summary Table.
Figure 8-242. PFSM_DELAY_REG_3 Register
7 6 5 4 3 2 1 0
PFSM_DELAY3
R/W-0h

Table 8-205. PFSM_DELAY_REG_3 Register Field Descriptions

Bit Field Type Reset Description
7-0 PFSM_DELAY3 R/W 0h Generic delay3 for PFSM use.
The step size is defined by PFSM_DELAY_STEP bits.
(Default from NVM memory)

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8.7.1.182 PFSM_DELAY_REG_4 Register (Offset = D0h) [Reset = 00h]

PFSM_DELAY_REG_4 is shown in Figure 8-243 and described in Table 8-206.
Return to the Summary Table.
Figure 8-243. PFSM_DELAY_REG_4 Register
7 6 5 4 3 2 1 0
PFSM_DELAY4
R/W-0h

Table 8-206. PFSM_DELAY_REG_4 Register Field Descriptions

Bit Field Type Reset Description
7-0 PFSM_DELAY4 R/W 0h Generic delay4 for PFSM use.
The step size is defined by PFSM_DELAY_STEP bits.
(Default from NVM memory)

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8.7.1.183 WD_ANSWER_REG Register (Offset = 401h) [Reset = 00h]

WD_ANSWER_REG is shown in Figure 8-244 and described in Table 8-207.
Return to the Summary Table.
Figure 8-244. WD_ANSWER_REG Register
7 6 5 4 3 2 1 0
WD_ANSWER
R/W-0h

Table 8-207. WD_ANSWER_REG Register Field Descriptions

Bit Field Type Reset Description
7-0 WD_ANSWER R/W 0h MCU answer byte. The MCU must write the expected reference
Answer-x into this register.
Each watchdog question requires four answer bytes:
- Three answer bytes (Answer-3, Answer-2, Answer-1) must be
written in Window-1.
- The fourth (final) answer-byte (Answer-0) must be written in
Window-2.
The number of written answer bytes is tracked with the
WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT
register.
These bits only apply for Watchdog in Q&A mode.

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8.7.1.184 WD_QUESTION_ANSW_CNT Register (Offset = 402h) [Reset = 30h]

WD_QUESTION_ANSW_CNT is shown in Figure 8-245 and described in Table 8-208.
Return to the Summary Table.
Figure 8-245. WD_QUESTION_ANSW_CNT Register
7 6 5 4 3 2 1 0
RESERVED WD_ANSW_CNT WD_QUESTION
R-0h R-3h R-0h

Table 8-208. WD_QUESTION_ANSW_CNT Register Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h
5-4 WD_ANSW_CNT R 3h Current, received watchdog-answer count state.
These bits only apply for Watchdog in Q&A mode.
3-0 WD_QUESTION R 0h Watchdog question.
The MCU must read (or calculate ) the current watchdog question
value to generate correct answers.
These bits only apply for Watchdog in Q&A mode.

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8.7.1.185 WD_WIN1_CFG Register (Offset = 403h) [Reset = 7Fh]

WD_WIN1_CFG is shown in Figure 8-246 and described in Table 8-209.
Return to the Summary Table.
Figure 8-246. WD_WIN1_CFG Register
7 6 5 4 3 2 1 0
RESERVED WD_WIN1
R/W-0h R/W-7Fh

Table 8-209. WD_WIN1_CFG Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-0 WD_WIN1 R/W 7Fh These bits are for programming the duration of Watchdog Window-1
(see Watchdoc chapter).
These bits can be only be written when the watchdog is in the Long
Window.

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8.7.1.186 WD_WIN2_CFG Register (Offset = 404h) [Reset = 7Fh]

WD_WIN2_CFG is shown in Figure 8-247 and described in Table 8-210.
Return to the Summary Table.
Figure 8-247. WD_WIN2_CFG Register
7 6 5 4 3 2 1 0
RESERVED WD_WIN2
R/W-0h R/W-7Fh

Table 8-210. WD_WIN2_CFG Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h
6-0 WD_WIN2 R/W 7Fh These bits are for programming the duration of Watchdog Window-2
(see Watchdog chapter).
These bits can be only be written when the watchdog is in the Long
Window.

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8.7.1.187 WD_LONGWIN_CFG Register (Offset = 405h) [Reset = FFh]

WD_LONGWIN_CFG is shown in Figure 8-248 and described in Table 8-211.
Return to the Summary Table.
Figure 8-248. WD_LONGWIN_CFG Register
7 6 5 4 3 2 1 0
WD_LONGWIN
R/W-FFh

Table 8-211. WD_LONGWIN_CFG Register Field Descriptions

Bit Field Type Reset Description
7-0 WD_LONGWIN R/W FFh These bits are for programming the duration of Watchdog Long
Window (see Watchdog chapter).
These bits can be only be written when the watchdog is in the Long
Window.
(Default from NVM memory)

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8.7.1.188 WD_MODE_REG Register (Offset = 406h) [Reset = 02h]

WD_MODE_REG is shown in Figure 8-249 and described in Table 8-212.
Return to the Summary Table.
Figure 8-249. WD_MODE_REG Register
7 6 5 4 3 2 1 0
RESERVED WD_PWRHOL WD_MODE_SE WD_RETURN_
D LECT LONGWIN
R/W-0h R/W-0h R/W-1h R/W-0h

Table 8-212. WD_MODE_REG Register Field Descriptions

Bit Field Type Reset Description
7-3 RESERVED R/W 0h
2 WD_PWRHOLD R/W 0h Device sets WD_PWRHOLD if hardware condition on pin
DISABLE_WDOG (mapped to GPIO8 pin) is applied at start-up (see
Watchdog chapter).
MCU can write this bit to 1.
MCU needs to clear this bit to get out of the Long Window:
0h = watchdog goes out of the Long Window and starts the first
watchdog-sequence when the configured Long Window time-interval
elapses
1h = watchdog stays in Long Window
1 WD_MODE_SELECT R/W 1h Watchdog mode-select:
MCU can set this to required value only when watchdog is in the
Long Window.
0h = Trigger Mode
1h = Q&A mode.
0 WD_RETURN_LONGWIN R/W 0h MCU can set this bit to put the watchdog from operating back to the
Long Window (see Watchdog chapter):
0h = Watchdog continues operating
1h = Watchdog returns to Long-Window after completion of the
current watchdog-sequence.

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8.7.1.189 WD_QA_CFG Register (Offset = 407h) [Reset = 0Ah]

WD_QA_CFG is shown in Figure 8-250 and described in Table 8-213.
Return to the Summary Table.
Figure 8-250. WD_QA_CFG Register
7 6 5 4 3 2 1 0
WD_QA_FDBK WD_QA_LFSR WD_QUESTION_SEED
R/W-0h R/W-0h R/W-Ah

Table 8-213. WD_QA_CFG Register Field Descriptions

Bit Field Type Reset Description
7-6 WD_QA_FDBK R/W 0h Feedback configuration bits for the watchdog question. These bits
control the sequence of the generated questions and respective
reference answers (see Watchdog chapter).
These bits are only used for the watchdog in Q&A mode.
These bits can be only be written when the watchdog is in the Long
Window.
5-4 WD_QA_LFSR R/W 0h LFSR-equation configuration bits for the watchdog question (see
Watchdog chapter).
These bits are only used for the watchdog in Q&A mode.
These bits can be only be written when the watchdog is in the Long
Window.
3-0 WD_QUESTION_SEED R/W Ah The watchdog question-seed value (see Watchdog chapter).
The MCU updates the question-seed value to generate a set of new
questions.
These bits can be only be written when the watchdog is in the Long
Window.

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8.7.1.190 WD_ERR_STATUS Register (Offset = 408h) [Reset = 00h]

WD_ERR_STATUS is shown in Figure 8-251 and described in Table 8-214.
Return to the Summary Table.
Figure 8-251. WD_ERR_STATUS Register
7 6 5 4 3 2 1 0
WD_RST_INT WD_FAIL_INT WD_ANSW_ER WD_SEQ_ERR WD_ANSW_EA WD_TRIG_EAR WD_TIMEOUT WD_LONGWIN
R RLY LY _TIMEOUT_INT
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 8-214. WD_ERR_STATUS Register Field Descriptions

Bit Field Type Reset Description
7 WD_RST_INT R/W1C 0h Latched status bit to indicate that the device went through
warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] +
WD_RST_TH[2:0]).
Write 1 to clear.
6 WD_FAIL_INT R/W1C 0h Latched status bit to indicate that the watchdog has cleared the
ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0].
Write 1 to clear.
5 WD_ANSW_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an
incorrect answer-byte.
Write 1 to clear.
This bit only applies for Watchdog in Q&A mode.
4 WD_SEQ_ERR R/W1C 0h Latched status bit to indicate that the watchdog has detected an
incorrect sequence of the answer-bytes.
Write 1 to clear.
This bit only applies for Watchdog in Q&A mode.
3 WD_ANSW_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the final
answer-byte in Window-1.
Write 1 to clear.
This bit only applies for Watchdog in Q&A mode.
2 WD_TRIG_EARLY R/W1C 0h Latched status bit to indicate that the watchdog has received the
watchdog-trigger in Window-1.
Write 1 to clear.
This bit only applies for Watchdog in Trigger mode.
1 WD_TIMEOUT R/W1C 0h Latched status bit to indicate that the watchdog has detected a time-
out event in the started watchdog sequence.
Write 1 to clear.
0 WD_LONGWIN_TIMEOU R/W1C 0h Latched status bit to indicate that device went through warm reset
T_INT due to elapse of Long Window time-interval.
Write 1 to clear interrupt.

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8.7.1.191 WD_THR_CFG Register (Offset = 409h) [Reset = FFh]

WD_THR_CFG is shown in Figure 8-252 and described in Table 8-215.
Return to the Summary Table.
Figure 8-252. WD_THR_CFG Register
7 6 5 4 3 2 1 0
WD_RST_EN WD_EN WD_FAIL_TH WD_RST_TH
R/W-1h R/W-1h R/W-7h R/W-7h

Table 8-215. WD_THR_CFG Register Field Descriptions

Bit Field Type Reset Description
7 WD_RST_EN R/W 1h Watchdog reset configuration bit:
This bit can be only be written when the watchdog is in the Long
Window.
0h = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0]
+ WD_RST_TH[2:0])
1h = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] +
WD_RST_TH[2:0]).
6 WD_EN R/W 1h Watchdog enable configuration bit:
This bit can be only be written when the watchdog is in the Long
Window.
(Default from NVM memory)
0h = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all
other interrupt status bits are cleared
1h = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if:
- watchdog is out of the Long Window
- WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0]
- WD_FIRST_OK=1
- all other interrupt status bits are cleared.
5-3 WD_FAIL_TH R/W 7h Configuration bits for the 1st threshold of the watchdog fail counter:
Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] >
WD_FAIL_TH[2:0].
These bits can be only be written when the watchdog is in the Long
Window.
2-0 WD_RST_TH R/W 7h Configuration bits for the 2nd threshold of the watchdog fail counter:
Device goes through warm reset when WD_FAIL_CNT[3:0] >
(WD_FAIL_TH[2:0] + WD_RST_TH[2:0]).
These bits can be only be written when the watchdog is in the Long
Window.

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8.7.1.192 WD_FAIL_CNT_REG Register (Offset = 40Ah) [Reset = 20h]

WD_FAIL_CNT_REG is shown in Figure 8-253 and described in Table 8-216.
Return to the Summary Table.
Figure 8-253. WD_FAIL_CNT_REG Register
7 6 5 4 3 2 1 0
RESERVED WD_BAD_EVE WD_FIRST_OK RESERVED WD_FAIL_CNT
NT
R-0h R-0h R-1h R-0h R-0h

Table 8-216. WD_FAIL_CNT_REG Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R 0h
6 WD_BAD_EVENT R 0h Status bit to indicate that the watchdog has detected a bad event in
the current watchdog sequence.
The device clears this bit at the end of the watchdog sequence.
5 WD_FIRST_OK R 1h Status bit to indicate that the watchdog has detected a good event.
The device clears this bit when the watchdog goes to the Long
Window.
4 RESERVED R 0h
3-0 WD_FAIL_CNT R 0h Status bits to indicate the value of the Watchdog Fail Counter.
The device clears these bits when the watchdog goes to the Long
Window.

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The following sections provides more detail on the proper utilization of the PMIC. Each orderable part number
has unique default non-volatile memory settings and the relevant user's guide for that orderable are available
in the TPS6593-Q1 product folder . Reference these user's guides for specific application information. More
generic topics and some examples are outlined here.
To help with new designs, a variety of tools and documents are available in the product folder. Some examples
are:
• Evaluation module and user guide which allow testing of various orderable part numbers, including multi-
PMIC operation
• GUI to communicate with the PMIC
• Schematic and layout checklist
9.2 Typical Application
The PMIC is generally used to power a processor. The number of regulators needed, the required sequencing,
the load current requirements, and the voltage characteristics are all critical in determining the number of PMICs
used in the system as well as the external components used with it. The following section provides a generic
case. For specific cases, refer to the relevant user's guide based on the orderable part number.
9.2.1 Powering a Processor
In this example, a single PMIC is used to power a generic processor. For this case, the PMIC is used in 2+1+1+1
buck phase configuration where BUCK1 and BUCK2 are used in parallel to supply higher currents.

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TPS6593-Q1 Processor Supplies

BUCK1 0.8V
3.3V VCCA
(3.5A max)
POWER DOMAINS
BUCK2 0.8V
(3.5A max) VDD CORE
BUCK3 0.85V
(3.5A max) MCU
BUCK4 0.8V (AVS)
(4A max) CPU (AVS)
BUCK5 1.1V
(2A max) VDD DDR
LDO1 1.8V
(500mA max) VDDA
LDO2 1.8V
(500mA max) 1.8V PHYs
LDO3 0.8V
(500mA max) 0.8V PLLs and DLLs
GPIOs

LDO4 1.8V
(300mA max) 3.3V VDDSHVx

VIO_IN
I2C I2C
nRSTOUT PORz

EN 3.3V System
Load Switch

LPDDR4
1.8V
1.1V

Figure 9-1. Example Power Map

9.2.1.1 Design Requirements

The design requirements for the sample processor in Figure 9-1 are outlined below:
• VDD CORE rail requires 0.8 V, 5 A
• MCU rail requires 0.85 V, 2 A
• CPU (AVS) rail requires 0.8 V, 3 A and the ability to support Adaptive Voltage Scaling
• LPDDR4 is used, which requires 1.1 V, 1 A and 1.8 V, 200 mA
• 1.8V PHYs and 0.8V PLLs and DLLs which are noise sensitive
• VDDA supplies the most noise sensitive components of the processor, requires 100 mA, and requires extra
low noise
9.2.1.2 Detailed Design Procedure
Based on the above requirements, the PMIC has been configured with the connections outlined in Figure 9-1.
BUCK1 and BUCK2 are used in multiphase operation to support the 5 A current. LDO2 and LDO3 are used to
power 1.8 V PHYs and 0.8 V PLLs and DLLs because they are lower noise than a buck regulator and it isolates
them from the noise of VDD CORE and the LPDDR4 1.8 V supply. LDO4 is used to power VDDA because it has
better noise performance.
Using this configuration information, components can be chosen to use with the PMIC.

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9.2.1.2.1 VCCA
The VCCA pin provides power to the LDOVINT regulator and other internal functions. This VCCA pin is always
connected in parallel with the buck input pins (PVIN_Bx pins). The VCCA pin can be connected to an optional
0.47-µF bypass capacitor close to the pin.
Table 9-1. Recommended VCCA Components
EIA SIZE
COMPONENT MANUFACTURER PART NUMBER VALUE SIZE (mm) USED for VALIDATION
CODE
Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 Yes
Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7R 0402 1.0 × 0.5 —

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9.2.1.2.2 Internal LDOs

The internal LDOs, VOUT_LDOVINT and VOUT_LDOVRTC, require external 2.2 µF capacitors for stabilization.
The recommended components are shown below.
Table 9-2. Recommended Internal LDO Components
COMPONE MANUFACTURE USED for
PART NUMBER VALUE EIA SIZE CODE SIZE (mm)
NT R VALIDATION
2.2 µF, 6.3 V,
Capacitor Murata GCM188R70J225KE22 0603 1.6 × 0.8 —
X7R
CGA3E1X7S1C225M080 2.2 µF, 6.3 V,
Capacitor TDK 0603 1.6 × 0.8 —
AC X7R

9.2.1.2.3 Crystal Oscillator

A crystal oscillator can be used for application requiring a high accuracy real-time clock module. The
OSC32KCAP pin is bypassed with a 100-nF bypass capacitor for noise rejection. For the OSC32KIN and
OSC32KOUT pins, a simplified oscillator schematic is shown in Figure 9-2 to determine what external load
capacitors are needed for the crystal.

Figure 9-2. Crystal Oscillator Component Selection

CIN1 and CIN2 are both 12-pF for this device. CPCB1 and CPCB2 depend on the board but is generally around
1-pF. The crystal oscillator chosen must have a required load capacitance of either 6-pF, 9-pF, or 12.5-pF and
the value of the XTAL_SEL bit in the RTC_CTRL_2 register must be updated based on the oscillator chosen. To
achieve the required load capacitance (CL) for the oscillator, Equation 25 is used. This equation assumes that
the crystal series capacitance is negligible.

CL = (CL1 + CPCB1 + CIN1) × (CL2 + CPCB2 + CIN2) / ((CL1 + CPCB1 + CIN1) + (CL2 + CPCB2 + CIN2)) (25)

Assuming CL1 = CL2, this simplifies to CL1 = 2 × CL - CPCB - CIN. Simplifying this into the standard capacitor
values typically available results in the following general capacitor recommendations. If more precise matching is
desired, complete the exercise without series capacitance neglected and with exact PCB parasitic capacitance.
Too much capacitance results in a lower than expected oscillator frequency, while not enough capacitance has
the opposite impact.

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Table 9-3. Approximate Crystal Oscillator Load Capacitors

Crystal CL (pF) Component CL1 = CL2 (pF)
6 0
9 6
12.5 12.5

The recommended components using a 9-pF oscillator as an example are in Table 9-4. If an alternate load
capacitance crystal is used, the values of the load capacitors must be adjusted to match based on the above.
Table 9-4. Recommended Crystal Oscillator Components for 9-pF Crystal
EIA size
Component MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation
code
Capacitor Murata GCM155R71C104JA55D 100-nF, 16-V, X7R 0402 1.0 x 0.5 Yes
Capacitor TDK CGA2B1X7R1C104K050BC 100-nF, 16-V, X7R 0402 1.0 x 0.5 -
Crystal NDK NX3215SD-32.768K-STD- 32.768-kHz, ±20 3.2 x 1.5 x 0.9 Yes
MUS-6 ppm, 9-pF
Crystal Abracon ABS07AIG-32.768kHz-9-T 32.768-kHz, ±20 3.2 x 1.5 x 0.9 -
ppm, 9-pF
Capacitor Murata GCM1555C1H6R0CA16 6-pF, 50-V, 0402 1.0 x 0.5 Yes
C0G/NP0
Capacitor TDK CGA2B2C0G1H060D050BA 6-pF, 50-V, 0402 1.0 x 0.5 -
C0G/NP0

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9.2.1.2.4 Buck Input Capacitors

For optimal performance, every buck needs an input capacitor, and the capacitor value and voltage rating must
be at least 10-µF, 10-V and must be placed as close to the buck input pins as possible. If the board size allows a
larger foot print, a 22-µF, 10-V capacitor is recommended. See Table 9-5 for the recommended input capacitors,
and the Section 9.4 for more information about component placement.
Table 9-5. Recommended Buck Input Capacitors
MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation
TDK CGA4J1X7S1C106K125AC 10 µF, 16 V, X7R 0805 2.0 × 1.25 × 1.25 Yes
Murata GCM21BR71A106KE22 10 µF, 10 V, X7R 0805 2.0 × 1.25 × 1.25 -

9.2.1.2.5 Buck Output Capacitors

The buck converters have seven potential NVM configurations which can impact the output capacitor selection.
Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The
actual minimal capacitance requirements to achieve a specific accuracy or ripple target varies depending on
the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below.
The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic
emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter.
It is recommended to place all large capacitors near the inductor. See Section 9.4 for more information about
component placement. Use ceramic local output capacitors, X7R or X7T types; do not use Y5V or F. DC bias
voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current
flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and
reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently
low ESR and ESL to perform these functions. Minimum effective output capacitance (including the DC voltage
roll-off, tolerances, aging and temperature effects) is defined in Electrical Characteristics table for different buck
configurations. The output voltage ripple is caused by the charging and discharging of the output capacitor and
also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value
used for selection process is at the switching frequency of the part.
To achieve better ripple and transient performance, additional high pass filter caps are recommended to
compensate for the parasitic impedance due to board routing and provide faster transient response to a load
step. These caps are placed close to the point of load and are also the input capacitors of the load. These
capacitors are referred to as POL caps later in this document. POL capacitor usage varies based on the
application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps
are recommended, as their high performance can help reduce the total number of capacitors required which
simplifies board layout design and saves board area. They also help to reduce the total cost of the solution.
Note that the output capacitor may be the limiting factor in the output voltage ramp and the maximum total output
capacitance listed in electrical characteristics must not be exceeded. At shutdown the output capacitors are
discharged to 0.15-V level using forced-PWM operation. This discharge of the output capacitors can cause an
increase of the input voltage if the load current is small and the output capacitor is large. Below 0.15-V level the
output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to
settle VOUT down as a consequence of the increased time constant.
Figure 9-3 is an example power distribution network (PDN) of local and POL caps at the output of a buck for
optimal ripple and transient performance. Table 9-6 lists the local and POL capacitors used to validate the buck
transient and ripple performance specified in the parametric table for each of the seven configurations. Table 9-7
lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10-µF.
It is recommended to simulate and validate that the capacitor network chosen for a particular design meets the
desired requirements as these are provided as guidelines.

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Figure 9-3. Example Power Distribution Network (PDN) of Local and POL Capacitors

Table 9-6. Local and POL Capacitors used for Buck Use Case Validation
LPCB per
Configuration COUT L CL / phase RPCB per phase1 CPOL1 (total) CPOL2 (total)
phase2
4.4 MHz VOUT Less than 1.9 V, Low Load Low 470 nH 22 uF x 1 8 mΩ 2.5 nH 1 uF x 1
Step, Single Phase with low COUT
Low 220 nH 47 µF × 2 8 mΩ 2.5 nH 10 µF × 4
4.4 MHz VOUT Less than 1.9 V, Multiphase
High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2
4.4 MHz VOUT Less than 1.9 V, Single Low 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4
Phase with high COUT
High 220 nH 47 µF × 4 8 mΩ 2.5 nH 10 µF × 2

4.4 MHz VOUT Less than 1.9 V, Single Low 220 nH 22 µF × 1 8 mΩ 2.5 nH 10 µF × 2
Phase with low COUT High 220 nH 47 µF × 1 8 mΩ 2.5 nH 10 µF × 4

4.4 MHz VOUT Greater than 1.7 V, Single Low 470 nH 47 µF × 1 27 mΩ 6 nH 10 µF × 4

Phase Only (VIN Greater than 4.5 V) High 470 nH 47 µF × 2 27 mΩ 6 nH 10 µF × 2

2.2 MHz Full VOUT Range and VIN Greater Low 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4
than 4.5 V, Single Phase Only High 1000 nH 47 µF × 3 8 mΩ 2.5 nH 10 µF × 4 680 µF × 1

2.2 MHz VOUT Less than 1.9 V Multiphase Low 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4
or Single Phase High 470 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 4 680 µF × 1

2.2 MHz Full VOUT and Full VIN Range, Low 1000 nH 47 µF × 3 4.1 mΩ 1.3 nH 10 µF × 2
Single Phase Only High 1000 nH 100 µF × 4 4.1 mΩ 1.3 nH 10 µF × 2
DDR VTT Termination, 2.2 MHz Single 10 µF × 1 + 22 µF x
- 470 nH 22 µF × 1 27 mΩ 6 nH
Phase Only 1

1. RPCB is the PCB wiring resistance between local and POL capacitors including both positive and negative
paths. For multi-phase outputs the total resistance is divided by the number of phases.
2. LPCB is the PCB wiring inductance between local and POL capacitors including both positive and negative
paths. For multi-phase outputs the total inductance is divided by the number of phases.
Power input and output wiring parasitic resistance and inductance must be minimized.
Table 9-7. Recommended Buck Converter Output Capacitor Components
MANUFACTURER PART NUMBER VALUE EIA Size Code SIZE (mm) Used for Validation
Murata NFM15HC105D0G(1) 1 µF, 4 V, X7S 0402 1.0 × 0.5 Yes
TDK YFF18AC0J105M(1) 1 µF, 6.3 V 0603 1.6 × 0.8 -
Murata NFM18HC106D0G(1) 10 µF, 4 V, X7S 0603 1.6 × 0.8 Yes
TDK YFF18AC0G475M(1) 4.7 µF, 6.3 V 0603 1.6 × 0.8 -
Murata GCM31CR71A226KE02 22 µF, 10 V, X7R 1206 3.2 × 1.6 Yes
Murata GCM21BD7CGA5L1X7R0J226MT0J226M 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 -
TDK CGA5L1X7R0J226MT 22 µF, 6.3 V, X7R 1206 3.2 × 1.6 -
TDK CGA4J1X7T0J226MT 22 µF, 6.3 V, X7T 0805 2.0 × 1.25 × 1.25 -
Murata GCM32ER70J476ME19 47 µF, 6.3 V, X7R 1210 3.2 × 2.5 Yes
Murata GCM31CD70G476M 47 µF, 4 V, X7T 1206 3.2 × 1.6 -
TDK CGA6P1X7S1A476MT 47 µF, 10 V, X7S 1210 3.2 × 2.5 -
TDK CGA5L1X7T0G476MT 47 µF, 4 V, X7T 1206 3.2 × 1.6 -
Murata GCM32ED70G107MEC4 100 µF, 4 V, X7S 1210 3.2 × 2.5 Yes
TDK CGA6P1X7T0G107MT 100 µF, 4 V, X7T 1210 3.2 × 2.5 -
Kemet T510X687K006ATA023(2) 680 µF, 6.3 V 2917 7.4 × 5.0 Yes

Murata GCM188D70E226ME36D 22uF, 2.5 V, X7T 0603 1.6 × 0.8 Yes

(1) Low ESL 3-terminal cap.

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(2) Dependent on availability; may switch to 470 µF.

9.2.1.2.6 Buck Inductors

Inductor must be chosen based on the buck configuration. See Table 9-6 for the appropriate nominal inductance.
Recommended inductors based on these requirements are shown below.
Table 9-8. Recommended Buck Converter Inductors
MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation
TDK TFM322512ALMA1R0MTAA 1000 nH, 4 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes
Murata DFE322520FD-1R0M=P2 1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0 -
TDK TFM322512ALMAR47MTAA 470 nH, 5.3 A Max, 150 °C 3.2 × 2.5 × 1.2 Yes
TDK TFM252012ALMAR47MTAA 470 nH, 4.9 A Max, 150 °C 2.5 x 2.0 x 1.2 -
Murata DFE2HCAHR47MJ0 470 nH, 4.5 A Max, 150 °C 2.5 × 2.0 × 1.2 Yes

TDK TFM322512ALMAR22MTAA 220 nH, 7.6 A Max, 150 °C 3.2 x 2.5 x 1.2 Yes
TDK TFM201610ALMAR24MTAA 220 nH, 5 A Max, 150 °C 2.0 x 1.6 x 1.2 -
Murata DFE2MCAHR24MJ0 240 nH, 4.2 A Max, 150 °C 2.0 x 1.6 x 1.2 -

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9.2.1.2.7 LDO Input Capacitors

All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF capacitor
for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V, 10-V, or 16-V capacitor
can be used. For optimal performance, the input capacitors must be placed as close to the LDO input pins
as possible. See the Section 9.4 for more information about component placement. See Table 9-9 for the
recommended input capacitors.
Table 9-9. Recommended LDO Input Capacitors(1)
MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation
TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 x 0.8 Yes
Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 x 0.8 -

(1) Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP.

9.2.1.2.8 LDO Output Capacitors

All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the
input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note: this requirement excludes
any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional
capacitance placed near the load can be supported, but the end application or system must be evaluated
for stability. See Table 9-10 for the specific part number of the recommended output capacitors. For BOM
optimization purposes, the same capacitor part number was used for LDO input and LDO output.
Table 9-10. Recommended LDO Output Capacitors
MANUFACTURER PART NUMBER VALUE EIA size code SIZE (mm) Used for Validation
TDK CGA3E1X7S1C225M080AC 2.2-µF, 16-V, X7S 0603 1.6 × 0.8 Yes
Murata GCM188R70J225KE22 2.2-µF, 16-V, X7R 0603 1.6 × 0.8 —

9.2.1.2.9 Digital Signal Connections

The VIO_IN pin requires a 0.47 µF bypass capacitor close to the pin. See Table 9-11 for the recommended
bypass capacitors.
Table 9-11. Recommended VIO_IN Capacitor
EIA size
Component MANUFACTURER PART NUMBER VALUE SIZE (mm) Used for Validation
code
Capacitor Murata GCM155C71A474KE36 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 Yes
Capacitor TDK CGA2B3X7S1A474K050BB 0.47 µF, 10 V, X7S 0402 1.0 x 0.5 -

For I2C pull-up resistor values, please refer to the I2C standard for the chosen use-case (standard mode, Fast
mode, Fast mode+, High-Speed mode with Cb = 100pF or 400pF)

Product Folder Links: TPS6593-Q1

TPS6593-Q1
www.ti.com SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023

9.2.2 Application Curves

100 100

80 80
Efficiency (%)

Efficiency (%)
60 60

40 40

VPVIN_Bn = 3.3 V, FPWM mode Fsw = 2.2 MHz, FPWM mode

20 VPVIN_Bn = 3.3 V, Auto mode 20 Fsw = 2.2 MHz, Auto mode
VPVIN_Bn = 5 V, FPWM mode Fsw = 4.4 MHz, FPWM mode
VPVIN_Bn = 5 V, Auto mode Fsw = 4.4 MHz, Auto mode
0 0
0.01 0.05 0.1 0.5 1 5 10 20 0.01 0.05 0.1 0.5 1 5 10 20
IOUT_Bn (A) IOUT_Bn (A)

VVOUT_Bn = 1.8 V Fsw = 2.2 MHz 4-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V 4-Phase
Figure 9-4. BUCK Efficiency at 3.3 V or 5 V Input Voltage Figure 9-5. BUCK Efficiency with Fsw = 2.2 MHz or 4.4 MHz
95 95

90 90

85 85
Efficiency (%)

Efficiency (%)
80 Fsw = 2.2 MHz, 1 Phase 80 Fsw = 2.2 MHz, 1 Phase
Fsw = 2.2 MHz, 2 Phase Fsw = 2.2 MHz, 2 Phase
75 Fsw = 2.2 MHz, 3 Phase 75 Fsw = 2.2 MHz, 3 Phase
Fsw = 2.2 MHz, 4 Phase Fsw = 2.2 MHz, 4 Phase
Fsw = 4.4 MHz, 1 Phase Fsw = 4.4 MHz, 1 Phase
70 Fsw = 4.4 MHz, 2 Phase 70 Fsw = 4.4 MHz, 2 Phase
Fsw = 4.4 MHz, 3 Phase Fsw = 4.4 MHz, 3 Phase
Fsw = 4.4 MHz, 4 Phase Fsw = 4.4 MHz, 4 Phase
65 65
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
IOUT_Bn (A) IOUT_Bn (A)

Data valid for all bucks up to IOUT_Bn Data valid for all bucks up to IOUT_Bn
VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1.8 V Auto Mode
Figure 9-6. BUCK Efficiency in Varied Phase Configuration, 3.3 Figure 9-7. BUCK Efficiency in Varied Phase Configuration, 5 V
V Input Input
100 100

80 80
Efficiency (%)

Efficiency (%)

60 60

40 40
VOUT_Bn = 0.8 V, F sw = 4.4 MHz VOUT_Bn = 0.8 V, F sw = 4.4 MHz
VOUT_Bn = 0.8 V, F sw = 2.2 MHz VOUT_Bn = 0.8 V, F sw = 2.2 MHz
VOUT_Bn = 1.2 V, F sw = 4.4 MHz VOUT_Bn = 1.2 V, F sw = 4.4 MHz
20 VOUT_Bn = 1.2 V, F sw = 2.2 MHz 20 VOUT_Bn = 1.2 V, F sw = 2.2 MHz
VOUT_Bn = 1.8 V, F sw = 4.4 MHz VOUT_Bn = 1.8 V, F sw = 4.4 MHz
VOUT_Bn = 1.8 V, F sw = 2.2 MHz VOUT_Bn = 1.8 V, F sw = 2.2 MHz
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4
IOUT_Bn (A) IOUT_Bn (A)

Data valid for all bucks up to IOUT_Bn Data valid for all bucks up to IOUT_Bn
VPVIN_Bn = 3.3 V Single-Phase Forced-PWM Mode VPVIN_Bn = 5 V Single-Phase Forced-PWM Mode
Figure 9-8. BUCK Efficiency with different VOUT_Bn, 3.3 V Input Figure 9-9. BUCK Efficiency with different VOUT_Bn, 5 V Input

Product Folder Links: TPS6593-Q1

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9.2.2 Application Curves (continued)

90 100
-40oC
25oC
85 85oC 80
125oC
Efficiency (%)

Efficiency (%)
80 60

75 40

-40oC
70 20 25oC
85oC
125oC
65 0
0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4
IOUT_Bn (A) IOUT_Bn (A)

Data valid for all bucks up to IOUT_Bn Data valid for all bucks up to IOUT_Bn
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Single-Phase
Figure 9-10. BUCK Efficiency at different TA, Auto Mode Figure 9-11. BUCK Efficiency at different TA, Forced-PWM Mode
1.01 1.01
1 Phase 1 Phase
1.0075 2 Phase 1.0075 2 Phase
3 Phase 3 Phase
1.005 4 Phase 1.005 4 Phase
VVOUT_Bn (V)

VVOUT_Bn (V)
1.0025 1.0025

1 1

0.9975 0.9975

0.995 0.995

0.9925 0.9925

0.99 0.99
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V

Figure 9-12. Buck Temperature Drift, Auto Mode, Fsw = 2.2 MHz Figure 9-13. Buck Temperature Drift, Auto Mode, Fsw = 4.4 MHz
1.01 1.01
1 Phase 1 Phase
1.0075 2 Phase 1.0075 2 Phase
3 Phase 3 Phase
1.005 4 Phase 1.005 4 Phase
VVOUT_Bn (V)

VVOUT_Bn (V)

1.0025 1.0025

1 1

0.9975 0.9975

0.995 0.995

0.9925 0.9925

0.99 0.99
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V

Figure 9-14. Buck Temperature Drift, Forced-PWM Mode, Fsw = Figure 9-15. Buck Temperature Drift, Forced-PWM Mode, Fsw =
2.2 MHz 4.4 MHz

Product Folder Links: TPS6593-Q1

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9.2.2 Application Curves (continued)

1.01 1.01
Fsw = 2.2 MHz, FPWM mode Fsw = 2.2 MHz, FPWM mode
1.008 Fsw = 2.2 MHz, Auto mode 1.008 Fsw = 2.2 MHz, Auto mode
1.006 Fsw = 4.4 MHz, FPWM mode 1.006 Fsw = 4.4 MHz, FPWM mode
Fsw = 4.4 MHz, Auto mode Fsw = 4.4 MHz, Auto mode
1.004 1.004
VVOUT_Bn (V)

VVOUT_Bn (V)
1.002 1.002
1 1
0.998 0.998
0.996 0.996
0.994 0.994
0.992 0.992
0.99 0.99
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
IOUT_Bn (A) IOUT_Bn (A)

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V 4-Phase VPVIN_Bn = 5 V VVOUT_Bn = 1 V 4-Phase

Figure 9-16. Buck Load Regulation with 3.3 V Input Figure 9-17. Buck Load Regulation with 5 V Input
1.01 1.01
1 Phase 1 Phase
1.008 2 Phase 1.008 2 Phase
3 Phase 3 Phase
1.006 1.006
4 Phase 4 Phase
1.004 1.004
VVOUT_Bn (V)

1.002 VVOUT_Bn (V) 1.002

1 1
0.998 0.998
0.996 0.996
0.994 0.994
0.992 0.992
0.99 0.99
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
IOUT_Bn (A) IOUT_Bn (A)

Data valid for all bucks up to IOUT_Bn Data valid for all bucks up to IOUT_Bn
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode
Figure 9-18. Buck Load Regulation, with Fsw = 2.2 MHz Figure 9-19. Buck Load Regulation, with Fsw = 4.4 MHz
1.01 1.01
1 Phase 1 Phase
1.008 2 Phase 1.008 2 Phase
3 Phase 3 Phase
1.006 1.006
4 Phase 4 Phase
1.004 1.004
VVOUT_Bn (V)

VVOUT_Bn (V)

1.002 1.002
1 1
0.998 0.998
0.996 0.996
0.994 0.994
0.992 0.992
0.99 0.99
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
VPVIN_Bn (V) VPVIN_Bn (V)

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V Auto Mode
Figure 9-20. Buck Line Regulation, with Fsw = 2.2 MHz Figure 9-21. Buck Line Regulation, with Fsw = 4.4 MHz

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9.2.2 Application Curves (continued)

VVOUT_Bn (10mV/div)

VSW_Bn (2V/div) VSW_Bn (2V/div)

Time (40µs/div) Time (200ns/div)

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA
Figure 9-22. Buck Output Ripple - Single Phase, Auto Mode Figure 9-23. Buck Output Ripple - Single Phase, Fsw = 2.2 MHz,
Forced-PWM Mode

VVOUT_Bn (10mV/div)

VSW_Bn (2V/div) VSW_Bn (2V/div)

Time (200ns/div) Time (40µs/div)

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA
Figure 9-24. Buck Output Ripple - Single Phase, Fsw = 4.4 MHz, Figure 9-25. Buck Output Ripple - 2-Phase, Auto Mode
Forced-PWM Mode

VVOUT_Bn (10mV/div) VVOUT_Bn (10mV/div)

VSW_Bn (2V/div) VSW_Bn (2V/div)

Time (200ns/div) Time (200ns/div)

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA
Figure 9-26. Buck Output Ripple - 2-Phase, Fsw = 2.2 MHz, Figure 9-27. Buck Output Ripple - 2-Phase, Fsw = 4.4 MHz,
Forced-PWM Mode Forced-PWM Mode

Product Folder Links: TPS6593-Q1

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9.2.2 Application Curves (continued)

VVOUT_Bn (10mV/div) VVOUT_Bn (5mV/div)

VSW_Bn (2V/div) VSW_Bn (2V/div)

Time (200ns/div)
Time (40µs/div) VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA Figure 9-29. Buck Output Ripple - 3-Phase, Fsw = 2.2 MHz,
Figure 9-28. Buck Output Ripple - 3-Phase, Auto Mode Forced-PWM Mode

VVOUT_Bn (5mV/div) VVOUT_Bn (10mV/div)

VSW_Bn (2V/div) VSW_Bn (2V/div)

Time (40µs/div)
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 10 mA
Time (200ns/div)
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA Figure 9-31. Buck Output Ripple - 4-Phase, Auto Mode

Figure 9-30. Buck Output Ripple - 3-Phase, Fsw = 4.4 MHz,

Forced-PWM Mode

VVOUT_Bn (10mV/div) VVOUT_Bn (10mV/div)

VSW_Bn (2V/div) VSW_Bn (2V/div)

Time (200ns/div) Time (200ns/div)

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA
Figure 9-32. Buck Output Ripple - 4-Phase, Fsw = 2.2 MHz, Figure 9-33. Buck Output Ripple - 4-Phase, Fsw = 4.4 MHz,
Forced-PWM Mode Forced-PWM Mode

Product Folder Links: TPS6593-Q1

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SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023 www.ti.com

9.2.2 Application Curves (continued)

VVOUT_Bn (10mV/div) VVOUT_Bn (10mV/div)

VSW_Bn (2V/div)

Time (2µs/div) Time (2µs/div)

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA
Figure 9-34. Buck Transient from PWM mode to PFM mode, 2.2 Figure 9-35. Buck Transient from PWM mode to PFM mode, 4.4
MHz, Single Phase MHz, Single Phase

VVOUT_Bn (10mV/div) VVOUT_Bn (10mV/div)

VSW_Bn (2V/div) VSW_Bn (2V/div)

Time (2µs/div) Time (2µs/div)

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V ILOAD = 200 mA
Figure 9-36. Buck Transient from PFM mode to PWM mode, 2.2 Figure 9-37. Buck Transient from PFM mode to PWM mode, 4.4
MHz, Single Phase MHz, Single Phase

VVOUT_Bn (20mV/div) VVOUT_Bn (20mV/div)

ILOAD (2A/div) ILOAD (2A/div)

Time (20µs/div) Time (20µs/div)

ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V
Figure 9-38. Buck Load Step Transient - 4-Phase, 2.2 MHz, Auto Figure 9-39. Buck Load Step Transient - 4-Phase, 4.4 MHz, Auto
Mode Mode

Product Folder Links: TPS6593-Q1

TPS6593-Q1
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9.2.2 Application Curves (continued)

VVOUT_Bn (20mV/div) VVOUT_Bn (20mV/div)

ILOAD (2A/div) ILOAD (2A/div)

Time (20µs/div) Time (20µs/div)

ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs ILOAD = 0.1 A → 7 A → 0.1 A, TR = TF = 1 μs
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V
Figure 9-40. Buck Load Step Transient - 4-Phase, 2.2 MHz, Figure 9-41. Buck Load Step Transient - 4-Phase, 4.4 MHz,
Forced-PWM Mode Forced-PWM Mode

VVOUT_Bn (20mV/div) VVOUT_Bn (20mV/div)

ILOAD (2A/div) ILOAD (2A/div)

Time (20µs/div) Time (20µs/div)

ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V
Figure 9-42. Buck Load Step Transient - 3-Phase, 2.2 MHz, Auto Figure 9-43. Buck Load Step Transient - 3-Phase, 4.4 MHz, Auto
Mode Mode

VVOUT_Bn (20mV/div) VVOUT_Bn (20mV/div)

ILOAD (2A/div) ILOAD (2A/div)

Time (20µs/div) Time (20µs/div)

ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs ILOAD = 0.1 A → 5.25 A → 0.1 A, TR = TF = 1 μs

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V

Figure 9-44. Buck Load Step Transient - 3-Phase, 2.2 MHz, Figure 9-45. Buck Load Step Transient - 3-Phase, 4.4 MHz,
Forced-PWM Mode Forced-PWM Mode

Product Folder Links: TPS6593-Q1

TPS6593-Q1
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9.2.2 Application Curves (continued)

VVOUT_Bn (20mV/div) VVOUT_Bn (20mV/div)

ILOAD (1A/div) ILOAD (1A/div)

Time (20µs/div) Time (20µs/div)

ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V
Figure 9-46. Buck Load Step Transient - 2-Phase, 2.2 MHz, Auto Figure 9-47. Buck Load Step Transient - 2-Phase, 4.4 MHz, Auto
Mode Mode

VVOUT_Bn (20mV/div) VVOUT_Bn (20mV/div)

ILOAD (1A/div) ILOAD (1A/div)

Time (20µs/div) Time (20µs/div)

ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs ILOAD = 0.1 A → 3.5 A → 0.1 A, TR = TF = 1 μs
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V
Figure 9-48. Buck Load Step Transient - 2-Phase, 2.2 MHz, Figure 9-49. Buck Load Step Transient - 2-Phase, 4.4 MHz,
Forced-PWM Mode Forced-PWM Mode

VVOUT_Bn (20mV/div) VVOUT_Bn (20mV/div)

ILOAD (1A/div) ILOAD (1A/div)

Time (20µs/div) Time (20µs/div)

ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V
Figure 9-50. Buck Load Step Transient - Buck4, 2.2 MHz, Auto Figure 9-51. Buck Load Step Transient - Buck4, 4.4 MHz, Auto
Mode Mode

Product Folder Links: TPS6593-Q1

TPS6593-Q1
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9.2.2 Application Curves (continued)

VVOUT_Bn (20mV/div) VVOUT_Bn (20mV/div)

ILOAD (1A/div) ILOAD (1A/div)

Time (20µs/div) Time (20µs/div)

ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs ILOAD = 0.1 A → 2 A → 0.1 A, TR = TF = 1 μs

VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V

Figure 9-52. Buck Load Step Transient - Buck4, 2.2 MHz, Figure 9-53. Buck Load Step Transient - Buck4, 4.4 MHz,
Forced-PWM Mode Forced-PWM Mode

VVOUT_Bn (20mV/div) VVOUT_Bn (20mV/div)

ILOAD (0.4A/div)
ILOAD (0.4A/div)

Time (20µs/div) Time (20µs/div)

ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V
Figure 9-54. Buck Load Step Transient - Buck5, 2.2 MHz, Auto Figure 9-55. Buck Load Step Transient - Buck5, 4.4 MHz, Auto
Mode Mode

VVOUT_Bn (20mV/div) VVOUT_Bn (20mV/div)

ILOAD (0.4A/div) ILOAD (0.4A/div)

Time (20µs/div) Time (20µs/div)

ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs ILOAD = 0.1 A → 1 A → 0.1 A, TR = TF = 1 μs
VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V VPVIN_Bn = 3.3 V VVOUT_Bn = 1 V
Figure 9-56. Buck Load Step Transient - Buck5, 2.2 MHz, Figure 9-57. Buck Load Step Transient - Buck5, 4.4 MHz,
Forced-PWM Mode Forced-PWM Mode

Product Folder Links: TPS6593-Q1

TPS6593-Q1
SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023 www.ti.com

9.2.2 Application Curves (continued)

1.81 3.005
VIN(LDOn) = 3.3 V VIN(LDOn) = 3.3 V
1.808 VIN(LDOn) = 5 V 3.004 VIN(LDOn) = 5 V
1.806 3.003
1.804 3.002
VOUT(LDOn) (V)

VOUT(LDOn) (V)
1.802 3.001
1.8 3
1.798 2.999
1.796 2.998
1.794 2.997
1.792 2.996
1.79 2.995
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Load (A) Load (A)

VIN(LDOn) = 3.3 V VOUT(LDOn) = 1.8 V VIN(LDOn) = 3.3 V VOUT(LDOn) = 3.0 V

Figure 9-58. LDO1/2/3 Load Regulation, Vout = 1.8 V Figure 9-59. LDO1/2/3 Load Regulation, Vout = 3 V
0.808 1.82
TA = -40oC TA = -40oC
0.806 TA = 0oC 1.815 TA = 0oC
TA = 20oC TA = 20oC
0.804 TA = 80oC 1.81 TA = 80oC
TA = 125oC TA = 125oC
VOUT(LDOn) (V)

VOUT(LDOn) (V)
0.802 1.805

0.8 1.8

0.798 1.795

0.796 1.79

0.794 1.785

0.792 1.78
1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3
VIN(LDOn) (V) VIN(LDOn) (V)

VOUT(LDOn) = 0.8 V IOUT(LDOn) = 500 mA VOUT(LDOn) = 1.8 V IOUT(LDOn) = 50 mA

Figure 9-60. LDO1/2/3 Line Regulation over Temperature, Vout = Figure 9-61. LDO1/2/3 Line Regulation over Temperature, Vout =
0.8 V 1.8 V
3.4 3.4

3.2 3.2

3 3

2.8 2.8
VOUT(LDOn) (V)

VOUT(LDOn) (V)

2.6 2.6

2.4 2.4

2.2 2.2

2 2

1.8 1.8

1.6 1.6
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time (ms) Time (ms)

VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA VIN(LDOn) = 3.3 V IOUT(LDOn) = 50 mA

Figure 9-62. LDO1/2/3 Transition from 3.3 V in Bypass Mode to Figure 9-63. LDO1/2/3 Transition from 1.8 V in Linear Mode to
1.8 V Linear Mode 3.3 V in Bypass Mode

Product Folder Links: TPS6593-Q1

TPS6593-Q1
www.ti.com SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023

9.2.2 Application Curves (continued)

1.81
VIN(LDOn) = 3.3 V
1.808 VIN(LDOn) = 5 V
VVOUT_Bn (20mV/div)
1.806
1.804

VOUT(LDOn) (V)
1.802
1.8

ILOAD (0.2A/div) 1.798

1.796
1.794
1.792
Time (20µs/div)
1.79
ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs 0 0.05 0.1 0.15 0.2 0.25 0.3
Load (A)
VIN(LDOn) = 3.3 V VOUT(LDOn) = 1 V
VIN(LDO4) = 3.3 V VOUT(LDO4) = 1.8 V
Figure 9-64. LDO1/2/3 Load Step Transient
Figure 9-65. LDO4 Load Regulation, Vout = 1.8 V
3.005 1.82
VIN(LDOn) = 3.3 V TA = -40oC
3.004 VIN(LDOn) = 5 V 1.815 TA = 0oC
3.003 TA = 20oC
1.81 TA = 80oC
3.002 TA = 125oC

VOUT(LDOn) (V)
VOUT(LDOn) (V)

1.805
3.001
3 1.8
2.999 1.795
2.998
1.79
2.997
1.785
2.996
2.995 1.78
0 0.05 0.1 0.15 0.2 0.25 0.3 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3
Load (A) VIN(LDOn) (V)

VIN(LDO4) = 3.3 V VOUT(LDO4) = 3.0 V VOUT(LDO4) = 1.8 V IOUT(LDO4) = 300 mA

Figure 9-66. LDO4 Load Regulation, Vout = 3 V Figure 9-67. LDO4 Line Regulation over Temperature, Vout = 1.8
V

VVOUT_Bn (20mV/div)

ILOAD (0.2A/div)

Time (20µs/div)
ILOAD = 0.1 A → 0.4 A → 0.1 A, TR = TF = 1 μs
VIN(LDO4) = 3.3 V VOUT(LDO4) = = 1 V
Figure 9-68. LDO4 Load Step Transient

Product Folder Links: TPS6593-Q1

TPS6593-Q1
SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023 www.ti.com

9.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 3.0 V and 5.5 V. This input supply
must be well regulated and can withstand maximum input current and keep a stable voltage without voltage drop
even at load transition condition. The resistance of the input supply rail must be low enough that the input current
transient does not cause too high drop in the device supply voltage that can cause false UVLO fault triggering. If
the input supply is located more than a few inches from the device, additional bulk capacitance may be required
in addition to the ceramic bypass capacitors.
9.4 Layout
9.4.1 Layout Guidelines
The high frequency and large switching currents of the TPS6593-Q1 device make the choice of layout important.
Good power supply results only occur when care is given to correct design and layout. Layout affects noise
pickup and generation and can cause a good design to perform with less-than-expected results.
With a range of buck output currents from a few milliampere to 10 A and over, good power supply layout is
much more difficult than most general PCB design. Use the following steps as a reference to ensure the buck
regulators are stable and maintain correct voltage and current regulation across its intended operating voltage
and current range.
1. Place CIN as close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the VIN trace wide
and thick to avoid IR drops. The DCR of the trace from the source to the pin must be less than 2 mΩ. The
trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the
trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as
possible. The input capacitance provides a low-impedance voltage source for the switching converter. The
inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic
inductance on these traces must be kept as small as possible for correct device operation. The parasitic
inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric
layer between top layer and ground plane.
2. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output
voltage. This output filter must be placed as close as possible to the device keeping the switch node small,
for best EMI behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and
capacitor placement must be made as close as possible without compromising PVIN_Bx. Route the traces
between the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop.
3. Input for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA
directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs.
Place the decoupling capacitor as close as possible to the VCCA pin.
4. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device
to the respective sense pins on the processor. If the processor does not support remote voltage sensing,
then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the
negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended
trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals
such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid capacitive
and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a
quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a
differential pair is recommended. If series resistors are used for load current measurement, place them after
connection of the voltage feedback.
5. PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers,
which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx.
For the LDO regulators, the feedback connection is internal. Therefore, it is important to keep the PCB
resistance between LDO output and target load in the range of the acceptable voltage drop for LDOs. Similar
to the buck regulators, the input capacitor at the PVIN_LDOx pins and the VCCA pin must be placed as
close as possible to the PMIC. The impedance from the source of the PVIN_LDOx pins and the VCCA pin
must be low and the DCR less than 2 mΩ. The output capacitor at the VOUT_LDOx, VOUT_LDOVINT and
VOUT_LDOVRTC pins must be as close (0.5mm) to the PMIC as possible. The ground connection of these

Product Folder Links: TPS6593-Q1

TPS6593-Q1
www.ti.com SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023

capacitors, especially for the capacitor at the VOUT_LDOVINT pin, must have a low impedance of less than
2 mΩ to the ground (Thermal Pad) of the TPS6593-Q1. For the ground connection of this capacitor at the
VOUT_LDOVINT pin, use multiple vias (at least three) directly at the ground landing pad of the capacitor. See
illustration below:

Figure 9-69. Ground connection of capacitor at VOUT_LDOVINT pin

Due to the overall small solution size, the thermal performance of the PCB layout is important. Many system-
dependent parameters, such as thermal coupling, airflow, added heat sinks and convection surfaces, and the
presence of other heat-generating components affect the power dissipation limits of a given component. Proper
PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces
come with the ability to sink dissipated heat. The capability to sink dissipated heat can be improved further
on multi-layer PCB designs with vias to different planes. Improved heat-sinking capability results in reduced
junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device
junction temperature, TJ. TI strongly recommends to perform a careful system-level 2D or full 3D dynamic
thermal analysis at the beginning product design process, by using a thermal modeling analysis software.
Overall recommendation for the PCB is to use at least 12 layers with 60 to 90 mil thickness, and with following
weights for the Copper layers:
• 0.5oz for signal layers
• at least 1.5oz for top layer and other plane layers
A more complete list of layout recommendations can be found in the Schematic and layout checklist.

Product Folder Links: TPS6593-Q1

TPS6593-Q1
SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023 www.ti.com

9.4.2 Layout Example

Figure 9-70. Example PMIC Layout

This example shows a top and bottom layout of the key power components and the crystal oscillator based on
the EVM. Most of the digital routing is neglected in this image, see the EVM design files EVM design files for
full details. The highest priority must be on the buck input capacitors, followed by the inductors, and the output
capacitor on the VOUT_LDOVINT pin. Ensure that there are sufficient vias for high current pathways.

Product Folder Links: TPS6593-Q1

TPS6593-Q1
www.ti.com SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023

10 Device and Documentation Support

10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Device Nomenclature
The following acronyms and terms are used in this data sheet. For a detailed list of terms, acronyms, and
definitions, see the TI glossary.
ADC Analog-to-Digital Converter
DAC Digital-to-Analog Converter
APE Application Processor Engine
AVS Adaptive Voltage Scaling
DVS Dynamic Voltage Scaling
GPIO General-Purpose Input and Output
LDO Low-Dropout voltage linear regulator
PM Power Management
PMIC Power-Management Integrated Circuit
PSRR Power Supply Rejection Ratio
RTC Real-Time Clock
NA Not Applicable
NVM Non-Volatile Memory
ESR Equivalent Series Resistance
DCR DC Resistance of an inductor
PDN Power Delivery Network
PMU Power Management Unit
PFM Pulse Frequency Modulation
PWM Pulse Width Modulation
EMC Electromagnetic Compatibility
PLL Phase Locked Loop
SPI Serial Peripheral Interface
SPMI System Power Management Interface
I2C Inter-Integrated Circuit
PFSM Pre-configured Finite State Machine
UV Undervoltage
OV Overvoltage
POR Power On Reset
UVLO Undervoltage Lockout
OVP Overvoltage Protection
EPC Embedded Power Controller

Product Folder Links: TPS6593-Q1

TPS6593-Q1
SLVSE83B – DECEMBER 2020 – REVISED SEPTEMBER 2023 www.ti.com

FSD First Supply Detection

ESM Error Signal Monitor
MCU Micro Controller Unit
SoC System on Chip
BIST Built-In Self-Test
LBIST Logic Built-In Self-Test
CRC Cyclic Redundancy Check
VMON Voltage Monitor
PGOOD Power Good (signal which indicates that the monitored power supply rail(s) is (are) in range)
10.3 Documentation Support
10.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.6 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: TPS6593-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 30-Jan-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS65930400RWERQ1 ACTIVE VQFNP RWE 56 2000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 125 TPS6593 Samples
0400-Q1
TPS65931211RWERQ1 ACTIVE VQFNP RWE 56 2000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 125 TPS6593 Samples
1211-Q1
TPS6593C3A0RWERQ1 ACTIVE VQFNP RWE 56 2000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 125 TPS6593 Samples
C3A0-Q1

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 30-Jan-2024

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 28-Mar-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65930400RWERQ1 VQFNP RWE 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2
TPS65931211RWERQ1 VQFNP RWE 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2
TPS6593C3A0RWERQ1 VQFNP RWE 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 28-Mar-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65930400RWERQ1 VQFNP RWE 56 2000 350.0 350.0 43.0
TPS65931211RWERQ1 VQFNP RWE 56 2000 350.0 350.0 43.0
TPS6593C3A0RWERQ1 VQFNP RWE 56 2000 350.0 350.0 43.0

Pack Materials-Page 2
GENERIC PACKAGE VIEW
RWE 56 VQFNP - 0.9 mm max height
8 x 8, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224587/A

www.ti.com
PACKAGE OUTLINE
RWE0056C SCALE 2.000
VQFNP - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

8.1 A
B
7.9

0.05 (0.1)
0.00
PIN 1 ID

DETAIL A
8.1 TYPICAL
7.9
DETAIL A
SCALE 20.000

( 7.75)

(0.15)

0.15 0.1

DETAIL B
DETAIL B
SCALE 20.000

0.9 TYPICAL
12 MAX C
0.8

SEATING PLANE
(0.2) 0.08 C
SEE DETAIL A (R0.2)

SEE DETAIL B
4X
45 X 0.6 MAX
15 28

14
29 PIN 1 ID
OPTIONAL

SYMM 57
4X 5.5 0.05
6.5

1 42
52X 0.5 0.3
56 56X
43 0.2
SYMM
PIN 1 ID 0.5 0.1 C B A
OPTIONAL 56X 0.05 C
0.3
4224586/B 03/2021
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
EXAMPLE BOARD LAYOUT
RWE0056C VQFNP - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 5.5)
SYMM
56X (0.6)
56 43
56X (0.25)
1
42

52X (0.5)

(7.8)
SYMM 57

(1.32) TYP

(R0.05) (2.5)
TYP TYP

( 0.2) TYP
VIA
29
14

15 28
(1.32)
TYP
(2.5)
TYP
(7.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK
METAL
OPENING

EXPOSED SOLDER MASK EXPOSED METAL UNDER

METAL OPENING METAL SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224586/B 03/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
EXAMPLE STENCIL DESIGN
RWE0056C VQFNP - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(7.8)

(0.66) TYP (1.32)

TYP
56 43
56X (0.6)
56X (0.25)
1
42

52X (0.5)

(1.32) TYP

SYMM 57 (0.66) TYP

(7.8)

METAL
TYP
16X
( 1.12)
(R0.05) TYP

14 29

15 28
SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 57:

66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X

4224586/B 03/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

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