TPS65994AE

SLVSG37 – JUNE 2021

TPS65994AE Dual Port USB Type-C® and USB PD Controller with Integrated Source
Power Switches
• USB type-C connector system software interface
1 Features (USCI) support
• USB Power Delivery (PD) controller • Power management
– USB PD 3.0 compliant – Power supply from 3.3 V or VBUS source
– Fast role swap support – 3.3-V LDO output for dead battery support
– Physical layer and policy engine • QFN package (0.4-mm pitch)
– Configurable at Boot and host-controlled
• USB Type-C specification compliant
2 Applications
– Cable attach and orientation detection • Notebook PCs
– Default, 1.5-A or 3-A power advertisement • Desktop computers
– Integrated VCONN switch • Docking Station DFP port
• Integrated VBUS sourcing port power switch • Monitor
– Two 5-V, 3-A, 29-mΩ sourcing switches • Industrial PC
– Adjustable current limiting
– Undervoltage and overvoltage protection 3 Description
– Fast turn-on mode to support fast-role swap The TPS65994AE is a stand-alone USB Type-C
• UL recognized component (E169910) and Power Delivery (PD) controller providing cable
• High-voltage gate drivers for two sinking paths plug and orientation detection for two USB Type-C
– Reverse current protection connectors. Upon cable attachment, the TPS65994AE
– Slew rate control performs cable detection according to the USB Type-
– Overvoltage protection C specification. It also communicates on the CC wire
• Alternate mode support using the USB PD protocol. When cable detection and
– DisplayPort source USB PD negotiation are complete, the TPS65994AE
– Thunderbolt™ enables the appropriate power path and configures
alternate mode settings for external multiplexers.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TPS65994AE QFN (RSL) 6.0 mm x 6.0 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

5A
5A

5-20 V
3.3V

PP_EXT PP_EXT
LDO
Control Control
USB
CC1/2 2 CC
Type-C
TPS65994 VCONN
Connector
5V VBUS
3A

VBUS
3A

Type-C Rp/Rd & state CC1/2 2 CC

EC EC Host machine, VCONN
Interface VCONN switches, USB
USB PD policy engine, Type-C
TBT TBT Host
protocol and physical Connector
Controller Interface layer

I2C GND
I2C slaves
Master
2 ADCIN pins
(I2C addr & 10 GPIO
config)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.2 Functional Block Diagram......................................... 19
2 Applications..................................................................... 1 8.3 Feature Description...................................................20
3 Description.......................................................................1 8.4 Device Functional Modes..........................................39
4 Revision History.............................................................. 2 9 Application and Implementation.................................. 41
5 Pin Configuration and Functions...................................3 9.1 Application Information............................................. 41
6 Specifications.................................................................. 5 9.2 Typical Application.................................................... 41
6.1 Absolute Maximum Ratings........................................ 5 10 Power Supply Recommendations..............................49
6.2 ESD Ratings............................................................... 5 10.1 3.3-V Power............................................................ 49
6.3 Recommended Operating Conditions.........................6 10.2 1.5-V Power............................................................ 49
6.4 Recommended Capacitance.......................................6 10.3 Recommended Supply Load Capacitance..............49
6.5 Thermal Information....................................................6 11 Layout........................................................................... 50
6.6 Power Supply Characteristics..................................... 7 11.1 Layout Guidelines................................................... 50
6.7 Power Consumption....................................................7 11.2 Layout Example...................................................... 50
6.8 PP_5V Power Switch Characteristics......................... 8 11.3 Component Placement............................................50
6.9 PP_EXT Power Switch Characteristics.......................9 11.4 Routing PP_5V, VBUS, VIN_3V3, LDO_3V3,
6.10 Power Path Supervisory......................................... 10 LDO_1V5 ................................................................... 51
6.11 CC Cable Detection Parameters.............................10 11.5 Routing CC and GPIO .......................................... 54
6.12 CC VCONN Parameters......................................... 12 12 Device and Documentation Support..........................56
6.13 CC PHY Parameters...............................................12 12.1 Device Support....................................................... 56
6.14 Thermal Shutdown Characteristics......................... 13 12.2 Documentation Support.......................................... 56
6.15 ADC Characteristics................................................13 12.3 Support Resources................................................. 56
6.16 Input/Output (I/O) Characteristics........................... 13 12.4 Trademarks............................................................. 56
6.17 I2C Requirements and Characteristics................... 14 12.5 Electrostatic Discharge Caution..............................56
6.18 Typical Characteristics ........................................... 16 12.6 Glossary..................................................................56
7 Parameter Measurement Information.......................... 17 13 Mechanical, Packaging, and Orderable
8 Detailed Description......................................................18 Information.................................................................... 56
8.1 Overview................................................................... 18

4 Revision History
DATE REVISION NOTES
June 2021 * Initial Release

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5 Pin Configuration and Functions

LDO_3V3

VIN_3V3

PA_CC1

PA_CC2
ADCIN2

ADCIN1

GPIO6

GPIO3

GPIO7

PP5V

PP5V
GND
36

35

34

33

32

31

30

29

28

27

26

25
LDO_1V5 37 24 PA_VBUS

GPIO1 38 23 PA_VBUS

I2C2s_IRQ 39 22 PA_VBUS

I2C_EC_SDA 40 21 PA_VBUS

I2C2s_SCL 41 20 PP5V
Thermal
I2C_EC_SCL 42 19 PA_GATE_VBUS
Pad
I2C_EC_IRQ 43 (GND) 18 PB_GATE_VBUS

I2C2s_SDA 44 17 PP5V

GPIO0 45 16 PB_VBUS

GPIO5 46 15 PB_VBUS

I2C3m_IRQ 47 14 PB_VBUS

I2C3m_SDA 48 10 13 PB_VBUS
11

12
1

9
I2C3m_SCL

GPIO4

VSYS
PB_GATE_VSYS

PA_GATE_VSYS

PB_CC1

PB_CC2

GPIO9

GPIO2

GPIO8

PP5V

PP5V

Figure 5-1. RSL Package 48-pin QFN Top View

Table 5-1. Pin Functions

PIN
TYPE RESET Description
NAME NO.
ADCIN1 33 I Hi-Z Configuration input. Connect to a resistor divider to LDO_3V3.
ADCIN2 35 I Hi-Z Configuration input. Connect to a resistor divider to LDO_3V3.
GND 36 — — Ground. Connect to ground plane.

General purpose digital I/O. Tie to PP5V or ground when unused. May be
GPIO0 45 I/O Hi-Z
used as DisplayPort HPD signal for Port B.
General purpose digital I/O. Tie to PP5V or ground when unused. May be
GPIO1 38 I/O Hi-Z
used as DisplayPort HPD signal for Port A.
GPIO2 9 I/O Hi-Z General purpose digital I/O. Tie to PP5V or ground when unused.
GPIO3 28 I/O Hi-Z General purpose digital I/O. Tie to PP5V or ground when unused.
General purpose digital I/O. May be used as an ADC input. Tie to PP5V or
GPIO4 2 I/O Hi-Z
ground when unused.
General purpose digital I/O. May be used as an ADC input. Tie to PP5V or
GPIO5 46 I/O Hi-Z
ground when unused.
GPIO6 29 I/O Hi-Z General purpose digital I/O. Tie to PP5V or ground when unused.
GPIO7 27 I/O Hi-Z General purpose digital I/O. Tie to PP5V or ground when unused.
GPIO8 10 I/O Hi-Z General purpose digital I/O. Tie to PP5V or ground when unused.

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Table 5-1. Pin Functions (continued)

PIN
TYPE RESET Description
NAME NO.
GPIO9 8 O Hi-Z General purpose digital output. Tie to PP5V or ground when unused.
I2C slave serial clock input. Tie to pullup voltage through a resistor. May be
I2C_EC_SCL 42 I Hi-Z
grounded if unused. Connect to Embedded Controller (EC).
I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a
I2C_EC_SDA 40 I/O Hi-Z
resistor. May be grounded if unused. Connect to Embedded Controller (EC).
I2C slave interrupt. Active low. Connect to external voltage through a pull-up
I2C_EC_IRQ 43 O Hi-Z resistor. Connect to Embedded Controller (EC). This can be re-configured to
GPIO10. May be grounded if unused.
I2C slave serial clock input. Tie to pull-up voltage through a resistor. May be
I2C2s_SCL 41 I Hi-Z
grounded if unused.
I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a
I2C2s_SDA 44 I/O Hi-Z
resistor. May be grounded if unused.
I2C slave interrupt. Active low. Connect to external voltage through a pull-up
I2C2s_IRQ 39 O Hi-Z resistor. Tie to PP5V or ground when unused. This can be re-configured to
GPIO11.
I2C master serial clock. Open-drain output. Tie to pullup voltage through a
I2C3m_SCL 1 O Hi-Z
resistor when used or unused.
I2C master serial data. Open-drain input/output. Tie to pullup voltage through
I2C3m_SDA 48 I/O Hi-Z
a resistor when used or unused.
I2C master interrupt. Active low. Connect to external voltage through a pull-up
I2C3m_IRQ 47 I Hi-Z resistor. Tie to PP5V or ground when unused. This can be re-configured to
GPIO12.
Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This
LDO_1V5 37 O —
pin cannot source current to external circuits.
Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with
LDO_3V3 34 O —
capacitance CLDO_3V3 to GND.
I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to
PA_CC1 31 I/O Hi-Z
GND (CPx_CCy).
I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to
PA_CC2 30 I/O Hi-Z
GND (CPx_CCy).
PA_GATE_VSYS 5 O Hi-Z Connect to the PortA N-ch MOSFET that has source tied to VSYS.
PA_GATE_VBUS 19 O Hi-Z Connect to the N-ch MOSFET that has source tied to PA_VBUS.
5-V to 20-V input or 5-V output from PP5V. Bypass with capacitance CVBUS to
PA_VBUS 21,22,23,24 I/O —
GND.
I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to
PB_CC1 6 I/O Hi-Z
GND (CPx_CCy).
I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to
PB_CC2 7 I/O Hi-Z
GND (CPx_CCy).
PB_GATE_VSYS 4 O Hi-Z Connect to the Port B N-ch MOSFET that has source tied to VSYS.
PB_GATE_VBUS 18 O Hi-Z Connect to the N-ch MOSFET that has source tied to PB_VBUS.
5-V to 20-V input or 5-V output from PP5V. Bypass with capacitance CVBUS to
PB_VBUS 13,14,15,16 I/O —
GND.
11,12,17,20,25,
PP5V I — 5-V System Supply to VBUS, supply for Px_CCy pins as VCONN.
26
High-voltage sinking node in the system. It is used to implement reverse-
VSYS 3 I — current-protection (RCP) for the external sinking paths controlled by
PA_GATE_VSYS and PB_GATE_VSYS.
VIN_3V3 32 I — Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
PP5V –0.3 6
VIN_3V3 –0.3 4 V
ADCIN1, ADCIN2 –0.3 4
VSYS, PA_VBUS, PB_VBUS (4) –0.3 28
Input voltage range (2) PA_CC1, PA_CC2, PB_CC1, PB_CC2 –0.5 6
GPIO0-GPIO9, I2C_EC_IRQ, I2C2s_IRQ,
-0.3 6 V
I2C3m_IRQ,
I2C_EC_SDA, I2C_EC_SCL,I2C2s_SDA,
I2C2s_SCL, I2C3m_SDA, I2C3m_SCL –0.3 4

LDO_1V5(3) –0.3 2
Output voltage range (2) V
LDO_3V3(3) –0.3 4
PA_GATE_VBUS, PA_GATE_VSYS,
Output voltage range (2) –0.3 40 V
PB_GATE_VBUS, PB_GATE_VSYS (3)
VGS VPx_GATE_VBUS - VPx_VBUS, VPx_GATE_SYS - VVSYS –0.5 12 V
Source or sink current PA_VBUS, PB_VBUS internally limited
Positive source current on PA_CC1, PA_CC2,
1
PB_CC1, PB_CC2
Positive sink current on PA_CC1, PA_CC2,
PB_CC1, PB_CC2 while VCONN switch is 1
Source current enabled A
GPIO0-GPIO9 0.005
positive sink current for I2C_EC_SDA,
I2C_EC_SCL, I2C2s_SDA, I2C2s_SCL, internally limited
I2C3m_SDA, I2C3m_SCL,
positive source current for LDO_3V3, LDO_1V5 internally limited
TJ Operating junction temperature –40 175 °C
TSTG Storage temperature –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.
(3) Do not apply voltage to these pins.
(4) For Px_VBUS a TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such
as TVS2200. For Px_VBUS a Schottky diode is recommended to ensure the MIN voltage is not violated.

6.2 ESD Ratings

PARAMETER TEST CONDITIONS VALUE UNIT
Human body model (HBM), per ANSI/
±1000
ESDA/JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge Charged device model (CDM), per V
JEDEC specificationJESD22-C101, all ±500
pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN_3V3 3.0 3.6
VI Input voltage range (1) PP5V (2) 4.9 5.5 V
PA_VBUS, PB_VBUS (3) 4 22
VI Input voltage range (1) VSYS 0 22 V
I2Cx_SDA, I2Cx_SCL, ADCIN1,
0 3.6
ADCIN2
GPIOx, I2C_EC_IRQ, I2C2s_IRQ,
VIO I/O voltage range (1) 0 5.5 V
I2C3m_IRQ,
PA_CC1, PA_CC2, PB_CC1,
0 5.5
PB_CC2
PA_VBUS, PB_VBUS 3 A
IO Output current (from PP5V) PA_CC1, PA_CC2, PB_CC1,
315 mA
PB_CC2
IO Output current (from LDO_3V3) GPIOx 1 mA
sum of current from LDO_3V3 and
IO Output current (from VBUS LDO) 5 mA
GPIO0-9.
IPP_5Vx ≤ 1.5 A, IPP_5Vy ≤ 3.0 A,
–40 105
IPP_CABLEx ≤ 315 mA
TA Ambient operating temperature °C
IPP_5Vx ≤ 3.0 A, IPP_CABLEx ≤ 315
–40 85
mA
TJ Operating junction temperature –40 125 °C

(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
(2) Maximum current sourced from PP5V to PA_VBUS or PB_VBUS. Resistance from Px_VBUS to Type-C connector less than or equal
30 mΩ. Short all PP5V bumps together.
(3) All PA_VBUS bumps should be shorted together. All PB_VBUS bumps should be shorted together.

6.4 Recommended Capacitance

over operating free-air temperature range (unless otherwise noted)
PARAMETER(1) VOLTAGE RATING MIN NOM MAX UNIT
CVIN_3V3 Capacitance on VIN_3V3 6.3 V 5 10 µF
CLDO_3V3 Capacitance on LDO_3V3 6.3 V 5 10 25 µF
CLDO_1V5 Capacitance on LDO_1V5 4V 4.5 12 µF
CPx_VBUS Capacitance on VBUS(3) 25 V 1 4.7 10 µF
CPP5V Capacitance on PP5V 10 V 120 µF
Capacitance on VSYS Sink from
CVSYS 25 V 47 100 µF
VBUS
CPx_CCy Capacitance on Px_CCy pins(2) 6.3 V 200 320 480 pF

(1) Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by
50% at the required operating voltage, then the required external capacitor value would be 10 µF.
(2) This includes all capacitance to the Type-C receptacle.
(3) The device can be configured to quickly disable PP_EXT upon certain events. When such a configuration is used, a capacitance on
the higher side of this range is recommended.

6.5 Thermal Information

TPS65994AE
THERMAL METRIC(1) QFN (RSL) UNIT
48 PINS
RθJA Junction-to-ambient thermal resistance 26.8 °C/W

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6.5 Thermal Information (continued)

TPS65994AE
THERMAL METRIC(1) QFN (RSL) UNIT
48 PINS
RθJC (top) Junction-to-case (top) thermal resistance 15.4 °C/W
RθJB Junction-to-board thermal resistance 8.5 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
Junction-to-board characterization
ψJB 8.5 °C/W
parameter
Junction-to-case (bottom GND pad)
RθJC (bottom) 1.8 °C/W
thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.6 Power Supply Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN_3V3, Px_VBUS
rising, VPx_VBUS=0 2.56 2.66 2.76
voltage required on VIN_3V3 for
VVIN3V3_UVLO falling, VPx_VBUS=0 2.44 2.54 2.64 V
power on
hysteresis 0.12
rising 3.6 3.9
VVBUS_UVLO UVLO comparator for Px_VBUS falling 3.5 3.8 V
hysteresis 0.1
LDO_3V3, LDO_1V5
VVIN_3V3 = 0V, ILDO_3V3 ≤ 5 mA,
VLDO_3V3 voltage on LDO_3V3 VPA_VBUS ≥ 3.9V or VPB_VBUS ≥ 2.7 3.4 3.6 V
3.9V
RLDO_3V3 Rdson of VIN_3V3 to LDO_3V3 ILDO_3V3=50mA 1.5 Ω
up to maximum internal loading
V_LDO_1V5 Output voltage of LDO_1V5 1.55 V
condition.

6.7 Power Consumption

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V, no loading on GPIO pins
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVIN_3V3,ActSrc current into VIN_3V3 Active Source mode: VPP5V=5.0V, VVIN_3V3=3.3V 4.5 12 mA
Active Sink mode: 22V ≥ VPA_VBUS ≥ 4.0V, 22V ≥ VPB_VBUS
IVIN_3V3,ActSnk current into VIN_3V3 4.8 12 mA
≥ 4.0V, VVIN_3V3=3.3V
IVSYS current into VSYS 10 µA
Idle Source mode: VPA_VBUS=5.0V, VPB_VBUS=5.0V,
IVIN_3V3,IdlSrc current into VIN_3V3 1.1 mA
VVIN_3V3=3.3V
Idle Sink mode: 22V ≥ VPA_VBUS ≥ 4.0V, 22V ≥ VPB_VBUS ≥
IVIN_3V3,IdlSnk current into VIN_3V3 1.1 mA
4.0V, VVIN_3V3=3.3V
Power drawn into PP5V
Modern Standby Sink Mode: VPP5V = 5V, VVIN_3V3=3.3V,
PMstbySnk and VIN_3V3 in Modern 3.7 mW
VPA_VBUS=5.0V, VPB_VBUS=0V
Standby Sink Mode
Power drawn into PP5V
Modern Standby Source Mode: VPP5V = 5V, VVIN_3V3=3.3V,
PMstbySrc and VIN_3V3 in Modern 4.5 mW
IPx_VBUS=0
Standby Source Mode
Sleep mode: VPA_VBUS=0V, VPB_VBUS=0V, VVIN_3V3=3.3V, TJ
IVIN_3V3,Sleep current into VIN_3V3 67 µA
≤ 25oC

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6.8 PP_5V Power Switch Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILOAD = 3 A, TJ≤25oC 36 40
RPP_5V Resistance from PP5V to Px_VBUS mΩ
ILOAD = 3 A, TJ≤125oC 36 52
VPP5V = 0V, VPx_VBUS
IPP5V_REV Px_VBUS to PP5V leakage current = 5.5V, PP_5V disabled, 0 3 µA
TJ≤85oC, measure IPP5V
VPP5V = 5.5V, VPx_VBUS
IPP5V_FWD PP5V to Px_VBUS leakage current = 0V, PP_5V disabled, 0 15 µA
TJ≤85oC, measure IPx_VBUS
ILIM5V Current limit setting Configure to setting 0 1.15 1.36 A
ILIM5V Current limit setting configure to setting 1 1.61 1.90 A
ILIM5V Current limit setting configure to setting 2 2.3 2.70 A
ILIM5V Current limit setting configure to setting 3 3.04 3.58 A
ILIM5V Current limit setting configure to setting 4 3.22 3.78 A
RCP clears and PP_5Vx starts
turning on when VPx_VBUS – VPP5V
VPP_5V_RCP 10 15 20 mV
< VPP_5V_RCP. Measure VPx_VBUS –
VPP5V
Px_VBUS to GND through
tiOS_PP_5V response time to VBUS short circuit 1.15 µs
10mΩ, CPx_VBUS=0
Enable PP_5Vx, ramp
response time to VPx_VBUS >
tPP_5V_ovp VPx_VBUS from 4V to 20V at 4.5 µs
VOVP4RCP
100 V/ms
response time to VPP5V <
R = 100 Ω, no external
tPP_5V_uvlo VPP5V_UVLO, PP_VBUS is deemed off L 4 µs
capacitance on Px_VBUS
when VPx_VBUS < 0.8V
VPP5V=5.5V, enable
response time to VPP5V <
tPP_5V_rcp PP_5Vx, ramp VPx_VBUS 0.7 µs
VPx_VBUS+VPP_5V_RCP
from 4V to 21.5V at 10 V/µs
Initial VPx_VBUS = 0V, 2µF
≤ CPx_VBUS ≤ 20µF, 0 ≤
Time allowed to enable the pass FET
tFRS_on IPx_VBUS ≤ 0.5 A, FET 54 150 µs
in PP_5Vx with 3A current limit.
is deemed enabled when
VPx_VBUS > 4.75V.
tILIM Current clamping deglitch time 5 ms
from enable signal to Px_VBUS at RL = 100Ω, VPP5V = 5V,
tON 2.6 3.5 4.4 ms
90% of final value CL=0
from disable signal to Px_VBUS at RL = 100Ω, VPP5V = 5V,
tOFF 0.30 0.45 0.6 ms
10% of final value CL=0
Px_VBUS from 10% to 90% of final RL = 100Ω, VPP5V = 5V,
tRISE 1.2 1.7 2.2 ms
value CL=0
Px_VBUS from 90% to 10% of initial RL = 100Ω, VPP5V = 5V,
tFALL 0.06 0.1 0.14 ms
value CL=0

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6.9 PP_EXT Power Switch Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0 ≤ VPx_GATE_VSYS-VVSYS ≤
6 V, 0 V ≤ VVSYS ≤ 22 V,
8.5 10 11.5 µA
VPx_VBUS > 4 V, measure
IPx_GATE_VSYS
IPx_GATE_ON Gate driver sourcing current
0 ≤ VPx_GATE_VBUS-
VPx_VBUS ≤ 6 V, 4 V ≤
8.5 10 11.5 µA
VPx_VBUS ≤ 22 V, measure
IPx_GATE_VBUS
0 ≤ VVSYS ≤ 22 V,
IPx_GATE_VSYS < 4 µA,
6 12 V
measure VPx_GATE_VSYS –
VVSYS, VPx_VBUS > 4 V.
VGATE_ON sourcing voltage (ON)
4 V ≤ VPx_VBUS ≤ 22
V, IPx_GATE_VBUS < 4 µA,
6 12 V
measure VPx_GATE_VBUS –
VPx_VBUS.
setting 0, 4 V ≤ VPx_VBUS ≤
2 6 10 mV
22 V, VVIN_3V3 ≤ 3.63 V
setting 1, 4 V ≤ VPx_VBUS ≤
4 8 12 mV
comparator mode RCP threshold, 22 V, VVIN_3V3 ≤ 3.63 V
VRCP
VVSYS - VPx_VBUS. setting 2, 4 V ≤ VPx_VBUS ≤
6 10 14 mV
22 V, VVIN_3V3 ≤ 3.63 V
setting 3, 4 V ≤ VPx_VBUS ≤
8 12 16 mV
22 V, VVIN_3V3 ≤ 3.63 V
normal turnoff: VVSYS = 5V,
13 µA
VPx_GATE_VSYS=6V
IPx_GATE_OFF Sinking strength normal turnoff: VPx_VBUS
= 5V, VPx_GATE_VBUS=6V, 13 µA
VVSYS = 5 V
fast turnoff: VVSYS = 5V,
85 Ω
VPx_GATE_VSYS=6V,
RPx_GATE_FSD Sinking strength fast turnoff: VPx_VBUS = 5V,
VPx_GATE_VBUS=6V, VVSYS = 85 Ω
5V
VVIN_3V3=0V,
RPx_GATE_OFF_UVLO Sinking strength in UVLO (safety) VPx_VBUS=3.0V, 1.5 MΩ
VPx_GATE_VSYS=0.1V
Time allowed to disable the external
VPx_VBUS=20V, Gate is off
tPx_GATE_VBUS_OFF FET via Px_GATE_VBUS in normal 260 µs
when VGS < 1 V
shutdown mode.(1)
Time allowed to disable the external OVP: VOVP4RCP= setting
FET via Px_GATE_VBUS in fast 57, VPx_VBUS=20V initially,
tPx_GATE_VBUS_OVP 3 µs
shutdown mode (VOVP4RCP then raised to 23V in 50ns,
exceeded).(1) Gate is off when VGS < 1 V
RCP: VRCP= setting 0,
Time allowed to disable the external VPx_VBUS=5V, VVSYS=5V
tPx_GATE_VBUS_RCP FET via Px_GATE_VBUS in fast initially, then raised to 5.5V 1.2 µs
shutdown mode (VRCP exceeded).(1) in 50ns, Gate is off when
VGS < 1 V
Time allowed to disable the external
VVSYS=20V, Gate is off
tPx_GATE_VSYS_OFF FET via Px_GATE_VSYS in normal 0.25 ms
when VGS < 1 V
shutdown mode(1)

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6.9 PP_EXT Power Switch Characteristics (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVSYS=VVBUS=20V initially,
Time allowed to disable the external
then VVBUS raised to 23V
tPx_GATE_VSYS_FSD FET via Px_GATE_VSYS in fast 0.25 μs
in 50ns, Gate is off when
shutdown mode (OVP or FRS)(1)
VGS< 1 V
measure time from when
tPx_GATE_VBUS_ON time to enable Px_GATE_VBUS (1) 0.25 ms
VGS=0V until VGS>3V

(1) These values depend upon the characteristics of the external N-ch MOSFET. The typical values were measured when
Px_GATE_VSYS and Px_GATE_VBUS were used to drive two CSD17571Q2 in common drain back-to-back configuration.

6.10 Power Path Supervisory

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VBUS over voltage protection typical
OVP detected when
VOVP4RCP threshold for RCP programmable 5.25 22.9 V
VPx_VBUS > VOVP4RCP
range (setting 0 to setting 63).
Tolernance of VOVP4RCP threshold -5 5 %
VBUS over voltage protection range
VOVPLSB 280 mV
for RCP
VOVP4RCPH hysteresis 1.75 2 2.25 %
setting 0 1 1 1 V/V
ratio of OVP4RCP input
used for OVP4VSYS setting 1 0.925 0.95 0.975 V/V
rOVP
comparator. rOVP*VOVP4VSYS = setting 2 0.875 0.90 0.925 V/V
VOVP4RCP
setting 3 0.85 0.875 0.9 V/V
VBUS over voltage protection range OVP detected when
VOVP4VSYS 5 27.5 V
for VSYS protection rOVP*VPx_VBUS > VOVP4RCP
VBUS falling, % of
VOVP4VSYS hysteresis 2 %
VOVP4VSYS
rising 3.9 4.1 4.3
VPP5V_UVLO Voltage required on PP5V falling 3.8 4.0 4.2 V
hysteresis 0.1
VPx_VBUS = 22V, measure
IDSCH VBUS discharge current (1) 4 13 mA
IPx_VBUS

(1) The discharge is enabled automatically when needed to meet USB specifications. It is not always enabled.

6.11 CC Cable Detection Parameters

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Type-C Source (Rp pull-up)
Unattached Px_CCy open circuit VLDO_3V3_UVLO < VLDO_3V3 < 3.6 V,
VOC_3.3 1.85 V
voltage while Rp enabled, no load RCC = 47 kΩ
Attached Px_CCy open circuit VPP5V_UVLO < VPP5V < 5.5 V, RCC =
VOC_5 2.95 V
voltage while Rp enabled, no load 47 kΩ
VPx_CCy = 5.5V, VPx_CCx = 0V,
VLDO_3V3_UVLO < VLDO_3V3 < 3.6
10
V, VPP5V = 3.8 V , measure current
Unattached reverse current on into Px_CCy
IRev µA
Px_CCy VPx_CCy = 5.5V, VPx_CCx = 0V,
VLDO_3V3_UVLO < VLDO_3V3 < 3.6
10
V, VPP5V = 0, -10oC≤TJ≤85oC,
measure current into Px_CCy

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6.11 CC Cable Detection Parameters (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0 < VPx_CCy < 1.0 V, measure
IRpDef current source - USB Default 64 80 96 µA
IPx_CCy
4.75 V < VPP5V < 5.5 V, 0 <
IRp1.5 current source - 1.5A 166 180 194 µA
VPx_CCy < 1.5 V, measure IPx_CCy
4.75 V < VPP5V < 5.5 V, 0 <
IRp3.0 current source - 3.0A 304 330 356 µA
VPx_CCy < 2.45 V, measure IPx_CCy
Type-C Sink (Rd pull-down)
Open/Default detection threshold
rising 0.2 0.24 V
when Rd applied to Px_CCy
VSNK1 Open/Default detection threshold
falling 0.16 0.20 V
when Rd applied to Px_CCy
hysteresis 0.04 V
Default/1.5A detection threshold falling 0.62 0.68 V
VSNK2 Default/1.5A detection threshold rising 0.63 0.66 0.69 V
hysteresis 0.01 V
1.5A/3.0A detection threshold
falling 1.17 1.25 V
when Rd applied to Px_CCy
VSNK3 1.5A/3.0A detection threshold
rising 1.22 1.3 V
when Rd applied to Px_CCy
hysteresis 0.05 V
0.25 V ≤ VPx_CCy ≤ 2.1 V, measure
RSNK Rd pulldown resistance 4.1 6.1 kΩ
resistance on Px_CCy
0V ≤ VPx_CCy ≤ 5.5 V, measure
RVCONN_DIS VCONN discharge resistance 4.1 6.1 kΩ
resistance on Px_CCy
VVIN_3V3=0V, 64 µA < IPx_CCy<96
0.25 1.32
µA
VVIN_3V3=0V, 166 µA <
VCLAMP Dead battery Rd clamp 0.65 1.32 V
IPx_CCy<194 µA
VVIN_3V3=0V, 304 µA < IPx_CCy<
1.20 2.18
356 µA
VPx_VBUS = 0, VVIN_3V3=3.3V,
VPx_CCy=5 V, measure resistance 500 kΩ
resistance from Px_CCy to GND on Px_CCy
ROpen
when configured as open. VPx_VBUS = 5V, VVIN_3V3 = 0,
VPx_CCy=5 V, measure resistance 500 kΩ
on Px_CCy
Fast Role swap request voltage
VFRS detection threshold on Px_CCy 495 515 535 mV
(falling)
VFRS hysteresis 0.01 V
VPx_CCy must be below VFRS for
Fast role swap signal detection
tFRS_DET at least this long before the FRS 30 35 µs
time
signal is detected
response time of the Fast role
tFRS_Resp VPx_CCy rises from 0.24V to 0.64V 0.6 µs
swap comparator (rising)
Common (Source and Sink)
deglitch time for comparators on
tCC 3.2 ms
Px_CCy

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6.12 CC VCONN Parameters

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VPP5V=5V, IL = 250 mA,
RPP_CABLE Rdson of the VCONN path measure resistance from PP5V 0.4 0.7 Ω
to Px_CCy
setting 0, VPP5V=5V,
ILIMVC short circuit current limit 350 410 470 mA
RL=10mΩ , measure IPx_CCy
setting 1, VPP5V=5V,
ILIMVC short circuit current limit 540 605 670 mA
RL=10mΩ , measure IPx_CCy
VCONN disabled, TJ ≤ 85oC,
VPx_CCy = 5.5 V, VPP5V=0 V,
Reverse leakage current
ICC2PP5V VPx_VBUS=5V, LDO forced to 0 10 µA
through VCONN FET
draw from VBUS, measure
IPx_CCy
tVCILIM Current clamp deglitch time 1.28 ms
from disable signal to Px_CCy
tPP_CABLE_off IL = 250 mA, VPP5V = 5V, CL=0 100 171 300 µs
at 10% of final value
VPP5V=5V, for short circuit RL =
tiOS_PP_CABLE response time to short circuit 2 µs
10mΩ.

6.13 CC PHY Parameters

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V or VPx_ VBUS ≥ 3.9 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Transmitter
VTXHI Transmit high voltage on Px_CCy Standard External load 1.05 1.125 1.2 V
VTXLO Transmit low voltage on Px_CCy Standard External load -75 75 mV
Transmit output impedance while
ZDRIVER measured at 750 kHz 33 75 Ω
driving the CC line using Px_CCy
Rise time. 10 % to 90 % amplitude
points on Px_CCy, minimum is
tRise CPx_CCy= 520 pF 300 ns
under an unloaded condition.
Maximum set by TX mask
Fall time. 90 % to 10 % amplitude
points on Px_CCy, minimum is
tFall CPx_CCy= 520 pF 300 ns
under an unloaded condition.
Maximum set by TX mask
Receiver
Does not include pull-up or
receiver input impedance on
ZBMCRX pulldown resistance from cable 10 MΩ
Px_CCy
detect. Transmitter is Hi-Z.
Receiver capacitance on Capacitance looking into the CC
CCC 120 pF
Px_CCy(1) pin when in receiver mode
Rising threshold on Px_CCy for
VRX_SNK_R sink mode (rising) 499 525 551 mV
receiver comparator
Rising threshold on Px_CCy for
VRX_SRC_R source mode (rising) 784 825 866 mV
receiver comparator
Falling threshold on Px_CCy for
VRX_SNK_F sink mode (falling) 230 250 270 mV
receiver comparator
Falling threshold on Px_CCy for
VRX_SRC_F source mode (falling) 523 550 578 mV
receiver comparator

(1) CCC includes only the internal capacitance on a Px_CCy pin when the pin is configured to be receiving BMC data. External
capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications (cReceiver). Therefore, TI
recommends adding CPx_CCy externally.

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6.14 Thermal Shutdown Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Temperature rising 145 160 175 °C
TSD_MAIN Temperature shutdown threshold
hysteresis 15 °C
Temperature controlled shutdown Temperature rising 135 150 165 °C
threshold. The power paths for
each port sourcing from PP5V
TSD_PP5V
have local sensors that disables hysteresis 5 °C
them when this temperature is
exceeded.

6.15 ADC Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.6V max scaling, voltage
14 mV
divider of 3
LSB least significant bit 25.2V max scaling, voltage
98 mV
divider of 21
4.07A max scaling 16.5 mA
0.05V ≤ VADCINx ≤ 3.6V, VADCINx
≤ VLDO_3V3
–2.7 2.7
0.05V ≤ VGPIOx ≤ 3.6V, VGPIOx
GAIN_ERR Gain error ≤ VLDO_3V3 %

2.7V ≤ VLDO_3V3 ≤ 3.6V –2.4 2.4

0.6V ≤ VPx_VBUS ≤ 22V –2.1 2.1
0.05V ≤ VADCINx ≤ 3.6V, VADCINx
≤ VLDO_3V3
–4.1 4.1
0.05V ≤ VGPIOx ≤ 3.6V, VGPIOx
VOS_ERR Offset error(1) ≤ VLDO_3V3 mV

2.7V ≤ VLDO_3V3 ≤ 3.6V -4.1 4.1

0.6V ≤ VPx_VBUS ≤ 22V -4.1 4.1

(1) The offset error is specified after the voltage divider.

6.16 Input/Output (I/O) Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GPIO0-8 (Inputs)
GPIO_VIH GPIOx high-Level input voltage VLDO_3V3 = 3.3V 1.3 V
GPIO_VIL GPIOx low-level input voltage VLDO_3V3 = 3.3V 0.54 V
GPIO_HYS GPIOx input hysteresis voltage VLDO_3V3 = 3.3V 0.09 V
GPIO_ILKG GPIOx leakage current VGPIOx = 3.45 V –1 1 µA
GPIO_RPU GPIOx internal pull-up pull-up enabled 50 100 150 kΩ
GPIO_RPD GPIOx internal pull-down pull-down enabled 50 100 150 kΩ
GPIO_DG GPIOx input deglitch 20 ns
GPIO0-9 (Outputs)
GPIO_VOH GPIOx output high voltage VLDO_3V3 = 3.3V, IGPIOx= -2mA 2.9 V
GPIO_VOL GPIOx output low voltage VLDO_3V3 = 3.3V, IGPIOx=2mA 0.4 V
ADCIN1, ADCIN2
ADCIN_ILKG ADCINx leakage current VADCINx ≤ VLDO_3V3 –1 1 µA

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6.16 Input/Output (I/O) Characteristics (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
time from LDO_3V3 going
tBOOT high until ADCINx is read for 10 ms
configuration

6.17 I2C Requirements and Characteristics

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I2C_EC_IRQ , I2C2s_IRQ
OD_VOL_IRQ Low level output voltage IOL = 2 mA 0.4 V
OD_LKG_IRQ Leakage Current Output is Hi-Z, VI2Cx_IRQ = 3.45 V –1 1 µA
I2C3m_IRQ
IRQ_VIH High-Level input voltage VLDO_3V3 = 3.3V 1.3 V
IRQ_VIH_THRESH High-Level input voltage threshold VLDO_3V3 = 3.3V 0.72 1.3 V
IRQ_VIL low-level input voltage VLDO_3V3 = 3.3V 0.54 V
IRQ_VIL_THRESH low-level input voltage threshold VLDO_3V3 = 3.3V 0.54 1.08 V
IRQ_HYS input hysteresis voltage VLDO_3V3 = 3.3V 0.09 V
IRQ_DEG input deglitch 20 ns
IRQ_ILKG I2C3m_IRQ leakage current VI2C3m_IRQ = 3.45 V –1 1 µA
SDA and SCL Common Characteristics (Master, Slave)
VIL Input low signal VLDO_3V3=3.3V, 0.54 V
VIH Input high signal VLDO_3V3=3.3V, 1.3 V
VHYS Input hysteresis VLDO_3V3=3.3V 0.165 V
VOL Output low voltage IOL=3 mA 0.36 V
ILEAK Input leakage current Voltage on pin = VLDO_3V3 –3 3 µA
IOL Max output low current VOL=0.4 V 15 mA
IOL Max output low current VOL=0.6 V 20 mA
VDD = 1.8V, 10 pF ≤ Cb ≤ 400 pF 12 80 ns
tf Fall time from 0.7*VDD to 0.3*VDD
VDD = 3.3V, 10 pF ≤ Cb ≤ 400 pF 12 150 ns
tSP I2C pulse width surpressed 50 ns
CI pin capacitance (internal) 10 pF
Capacitive load for each bus line
Cb 400 pF
(external)
tHD;DAT Serial data hold time VDD = 1.8V or 3.3V 0 ns
SDA and SCL Standard Mode Characteristics (Slave)
fSCLS Clock frequency VDD = 1.8V or 3.3V 100 kHz
Transmitting Data, VDD = 1.8V or
tVD;DAT Valid data time 3.45 µs
3.3V, SCL low to SDA output valid
Transmitting Data, VDD = 1.8V or
tVD;ACK Valid data time of ACK condition 3.3V, ACK signal from SCL low to 3.45 µs
SDA (out) low
SDA and SCL Fast Mode Characteristics (Slave)
fSCLS Clock frequency VDD = 1.8V or 3.3V 100 400 kHz
Transmitting data, VDD = 1.8V,
tVD;DAT Valid data time 0.9 µs
SCL low to SDA output valid
Transmitting data, VDD = 1.8V or
tVD;ACK Valid data time of ACK condition 3.3V, ACK signal from SCL low to 0.9 µs
SDA (out) low

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6.17 I2C Requirements and Characteristics (continued)

Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SDA and SCL Fast Mode Plus Characteristics (Slave)
VDD = 1.8V or 3.3V, master
fSCLS Clock frequency (1) controls SCL frequency such that: 400 1000 kHz
tLOW > tVD;ACK + tSU;DAT, TJ ≤ 65oC
Transmitting data, VDD = 1.8V or
tVD;DAT Valid data time 3.3V, SCL low to SDA output valid, 0.55 µs
TJ ≤ 65oC
Transmitting data, VDD = 1.8V or
tVD;ACK Valid data time of ACK condition 3.3V, ACK signal from SCL low to 0.55 µs
SDA (out) low, TJ ≤ 65oC
SDA and SCL Fast Mode Characteristics (Master)
fSCLM Clock frequency for master(3) VDD = 3.3V 390 410 kHz
Start or repeated start
tHD;STA VDD = 3.3V 0.6 µs
condition hold time
tLOW Clock low time VDD = 3.3V 1.3 µs
tHIGH Clock high time VDD = 3.3V 0.6 µs
Start or repeated start
tSU;STA VDD = 3.3V 0.6 µs
condition setup time
tSU;DAT Serial data setup time Transmitting data, VDD = 3.3V 100 ns
tSU;STO Stop condition setup time VDD = 3.3V 0.6 µs
Bus free time between stop and
tBUF VDD = 3.3V 1.3 µs
start
Transmitting data, VDD = 3.3V,
tVD;DAT Valid data time 0.9 µs
SCL low to SDA output valid
Transmitting data, VDD = 3.3V,
tVD;ACK Valid data time of ACK condition ACK signal from SCL low to SDA 0.9 µs
(out) low

(1) Fast Mode Plus is only recommended during boot when the device is in PTCH mode.
(2) The master or slave connected to the device follows I2C specifications.
(3) Actual frequency is dependent upon bus capacitance.

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6.18 Typical Characteristics

50 0.575

47.5 0.55
0.525
45
0.5
42.5

RPP_CABLE (:)
RPP_5V (m:)

0.475
40
0.45
37.5
0.425
35 0.4
32.5 0.375
30 0.35

27.5 0.325
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
TJ (oC) TJ (oC) TypG
TypG

Figure 6-1. PP_5Vx Rdson vs. Temperature Figure 6-2. PP_CABLEx Rdson vs. Temperature

5.9 5.82
5.85 VPx_VBUS = 4V 5.815
5.8 VPx_VBUS = 22V
5.75 5.81
VRCP setting 0 (mV)

5.7 VOVP4RCP (mV) 5.805

5.65
5.6 5.8
5.55 5.795
5.5
5.79
5.45
5.4 5.785
5.35
5.78
5.3
5.25 5.775
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
TJ (oC) TJ (oC) TypG
TypG

Figure 6-3. VRCP vs. Temperature Figure 6-4. VOVP4RCP (Setting 2) vs. Temperature

9 11

8.8
Px_GATE_VBUS
8.6 10.5 Px_GATE_VSYS
VPx_GATE_ON (V)

8.4
IPx_GATE_ON

Px_GATE_VSYS: VVSYS=0V
Px_GATE_VSYS: VVSYS=22V
8.2 Px_GATE_VBUS: 4V < VVBUS < 22V 10

7.8 9.5

7.6

7.4 9
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
TJ (oC) TJ (oC) TypG
TypG

Figure 6-5. VPx_GATE_ON vs. Temperature Figure 6-6. IPX_GATE_ON vs. Temperature

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7 Parameter Measurement Information

tf tr tSU;DAT

70 % 70 %
SDA
30 % 30 % cont.
tHD;DAT tVD;DAT
tf
tHIGH
tr
70 % 70 % 70 % 70 %
SCL 30 % 30 %
30 % 30 % cont.
tHD;STA tLOW
9th clock
S 1 / fSCL
1st clock cycle

tBUF

SDA

tVD;ACK
tSU;STA tHD;STA tSP tSU;STO

70 %
SCL 30 %
Sr P S
9th clock 002aac938

Figure 7-1. I2C Slave Interface Timing

ILIM5V, ILIMVC

tiOS_PP_5V, tiOS_PP_CABLE

Figure 7-2. Short-Circuit Response Time for Internal Power Paths PP_5Vx and PP_CABLEx

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8 Detailed Description
8.1 Overview
The TPS65994AE is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug
and orientation detection for two USB Type-C and PD receptacles. The TPS65994AE communicates with the
cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port power
switch for sourcing, controls a high current port power switch for sinking and negotiates alternate modes for each
port. The TPS65994AE may also control an attached super-speed multiplexer to simultaneously support USB
data and DisplayPort video.
Each Type-C port controlled by the TPS65994AE is functionally identical and supports the full range of the USB
Type-C and PD standards.
The TPS65994AE is divided into several main sections: the USB-PD controller, the cable plug and orientation
detection circuitry, the port power switches, the power management circuitry and the digital core.
The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD
data is output through either the Px_CC1 pin or the Px_CC2 pin, depending on the orientation of the reversible
USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and
more detailed circuitry, see the USB-PD Physical Layer section.
The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug
insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and
orientation detection, a description of its features and more detailed circuitry, see the Cable Plug and Orientation
Detection.
The port power switches provide power to the Px_VBUS pin and also to the Px_CC1 or Px_CC2 pins based
on the detected plug orientation. For a high-level block diagram of the port power switches, a description of its
features and more detailed circuitry, see the Power Paths.
The digital core provides the engine for receiving, processing and sending all USB-PD packets as well as
handling control of all other TPS65994AE functionality. A portion of the digital core contains ROM memory which
contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section of the
ROM, called boot code, is capable of initializing the TPS65994AE, loading of device configuration information
and loading any code patches into volatile memory in the digital core. For a high-level block diagram of the
digital core, a description of its features and more detailed circuitry, see the Digital Core section.
The digital core of the TPS65994AE also interprets and uses information provided by the analog-to-digital
converter ADC (see the ADC), is configurable to read the status of general purpose inputs and trigger events
accordingly, and controls general outputs which are configurable as push-pull or open-drain types with integrated
pull-up or pull-down resistors. The TPS65994AE has two I2C slave ports to be controlled by host processors ,
and one I2C master to write to and read from external slave devices such as multiplexor, retimer, or an optional
external EEPROM memory (see the I2C Interface).
The TPS65994AE also integrates a thermal shutdown mechanism and runs off of accurate clocks provided by
the integrated oscillator.

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8.2 Functional Block Diagram

PA_GATE_VBUS

PB_GATE_VBUS
PA_GATE_VSYS

PB_GATE_VSYS
PB_VBUS

3A
PP5V

PA_VBUS

3A

LDO_3V3

VSYS
LDO_1V5
VIN_3V3 Power Supervisor

GND

PB_CC1
ADCIN1

ADCIN2 Cable Detect, Cable Power, & USB PD PHY PB_CC2

I2C_EC_SDA/SCL/IRQ 3

I2C2s_SDA/SCL/IRQ 3 Core & Other Digital

PA_CC1
I2C3m_SDA/SCL/IRQ 3

GPIO0-9 10 Cable Detect, Cable Power, & USB PD PHY PA_CC2

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8.3 Feature Description

8.3.1 USB-PD Physical Layer
Figure 8-1 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and
orientation detection block. This block is duplicated for the second TPS65994AE port.
IVCON Fast
current
limit

PP5V

Px_CC1 Gate Control and

Current Limit
LDO_3V3

IRp

±
RSNK

Px_CC1
Digital USB-PD PHY
Core (Rx/Tx)

LDO_3V3 Px_CC2

IRp

RSNK

Px_CC1 Gate Control and

Current Limit

Fast
current
limit

Figure 8-1. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry

USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output
on the same pin (Px_CC1 or Px_CC2) that is DC biased due to the Rp (or Rd) cable attach mechanism.

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8.3.1.1 USB-PD Encoding and Signaling

Figure 8-2 illustrates the high-level block diagram of the baseband USB-PD transmitter. Figure 8-3 illustrates the
high-level block diagram of the baseband USB-PD receiver.

4b5b BMC
Data to PD_TX
Encoder Encoder

CRC

Figure 8-2. USB-PD Baseband Transmitter Block Diagram

BMC SOP 4b5b Data

from PD_RX
Decoder Detect Decoder

CRC

Figure 8-3. USB-PD Baseband Receiver Block Diagram

8.3.1.2 USB-PD Bi-Phase Marked Coding

The USB-PD physical layer implemented in the TPS65994AE is compliant to the USB-PD Specifications. The
encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark
Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in
the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity
(limited to 1/2 bit over an arbitrary packet, so a very low DC level). Figure 8-4 illustrates Biphase Mark Coding.
0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1
Data in

BMC

Figure 8-4. Biphase Mark Coding Example

The USB PD baseband signal is driven onto the Px_CC1 or Px_CC2 pin with a tri-state driver. The tri-state driver
is slew rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When sending
the USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end tolerates
the loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver clocks the
final bit of EOP.
8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal edge
at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning, the
masks are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The boundaries
of the Rx outer mask are specified to accommodate a change in signal amplitude due to the ground offset
through the cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly, the
boundaries of the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time masks
are superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge rate
that has minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits on the
rise and fall times. Refer to the USB-PD Specifications for more details.
8.3.1.4 USB-PD BMC Transmitter
The TPS65994AE transmits and receives USB-PD data over one of the Px_CCy pins for a given CC pin pair
(one pair per USB Type-C port). The Px_CCy pins are also used to determine the cable orientation and maintain

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the cable/device attach detection. Thus, a DC bias exists on the Px_CCy pins. The transmitter driver overdrives
the Px_CCy DC bias while transmitting, but returns to a Hi-Z state allowing the DC voltage to return to the
Px_CCy pin when not transmitting. While either Px_CC1 or Px_CC2 may be used for transmitting and receiving,
during a given connection only the one that mates with the CC pin of the plug is used; so there is no dynamic
switching between Px_CC1 and Px_CC2. Figure 8-5 shows the USB-PD BMC TX and RX driver block diagram.

LDO_3V3

PD_TX Level Shifter Driver

Px_CC1

PD_RX Level Shifter Px_CC2

Digitally
Adjustable
VREF (VRXHI, VRXLO)
USB-PD Modem

Figure 8-5. USB-PD BMC TX/Rx Block Diagram

Figure 8-6 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere
between the minimum and maximum threshold for detecting a Sink attach. This means that the DC bias can be
above or below the VOH of the transmitter driver.
VOH

DC Bias DC Bias

VOL

DC Bias VOH DC Bias

VOL

Figure 8-6. TX Driver Transmission with DC Bias

The transmitter drives a digital signal onto the Px_CCy lines. The signal peak, VTXHI, is set to meet the TX
masks defined in the USB-PD Specifications. Note that the TX mask is measured at the far-end of the cable.
When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by the
driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts the
noise ingression in the cable.
Figure 8-7 shows the simplified circuit determining ZDRIVER. It is specified such that noise at the receiver is
bounded.

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RDRIVER ZDRIVER
Driver
CDRIVER

Figure 8-7. ZDRIVER Circuit

8.3.1.5 USB-PD BMC Receiver

The receiver block of the TPS65994AE receives a signal that follows the allowed Rx masks defined in the USB
PD specification. The receive thresholds and hysteresis come from this mask.
Figure 8-8 shows an example of a multi-drop USB-PD connection (only the CC wire). This connection has
the typical Sink (device) to Source (host) connection, but also includes cable USB-PD Tx/Rx blocks. Only one
system can be transmitting at a time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also
specifies the capacitance that can exist on the wire as well as a typical DC bias setting circuit for attach
detection.
Source Sink
System Pullup for System
Attach
Connector Cable Connector
Detection
CC wire
Tx Tx

CRECEIVER
CRECEIVER

Rx Rx

CCablePlug_CC CCablePlug_CC

RD for
Attach
Detection

Rx Rx
Tx Tx

623¶ 3' 623¶¶ 3'

communication only communication only
(eMarker #1) (eMarker #2)

Figure 8-8. Example USB-PD Multi-Drop Configuration

8.3.1.6 Squelch Receiver

The TPS65994AE has a squelch receiver to monitor for the bus idle condition as defined by the USB PD
specification.
8.3.2 Power Management
The TPS65994AE power management block receives power and generates voltages to provide power to the
TPS65994AE internal circuitry. These generated power rails are LDO_3V3 and LDO_1V5. LDO_3V3 may also
be used as a low power output for external EEPROM memory. The power supply path is shown in Figure 8-9.

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PB_VBUS
RLDO_3V3

VIN_3V3 PA_VBUS

VREF

LDO_3V3 LDO

VREF

LDO_1V5 LDO

Figure 8-9. Power Supplies

The TPS65994AE is powered from either VIN_3V3, PA_VBUS, or PB_VBUS. The normal power supply input
is VIN_3V3. When powering from VIN_3V3, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3-V
circuitry and I/Os. A second LDO steps the voltage down from LDO_3V3 to LDO_1V5 to power the 1.5-V core
digital circuitry. When VIN_3V3 power is unavailable and power is available on PA_VBUS, or PB_VBUS it is
referred to as the dead-battery startup condition. In a dead-battery startup condition, the TPS65994AE opens the
VIN_3V3 switch until the host clears the dead-battery flag via I2C. Therefore, the TPS65994AE is powered from
the VBUS input with the higher voltage during the dead-battery startup condition and until the dead-battery flag
is cleared. When powering from a VBUS input, the voltage on PA_VBUS, or PB_VBUS is stepped down through
an LDO to LDO_3V3.
8.3.2.1 Power-On And Supervisory Functions
A power-on reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a
good supply is present.
8.3.2.2 VBUS LDO
The TPS65994AE contains an internal high-voltage LDO which is capable of converting Px_VBUS to 3.3 V
for powering internal device circuitry. The VBUS LDO is only used when VIN_3V3 is low (the dead-battery
condition). The VBUS LDO is powered from either PA_VBUS, or PB_VBUS ; the one with the highest voltage.
8.3.3 Power Paths
The TPS65994AE has internal sourcing power paths: PP_5V1, PP_5V2, PP_CABLE1, and PP_CABLE2. It also
has control for external power paths: PP_EXT1, and PP_EXT2. Each power path is described in detail in this
section.
8.3.3.1 Internal Sourcing Power Paths
Figure 8-10 shows the TPS65994AE internal sourcing power paths. The TPS65994AE features four internal
5-V sourcing power paths. The path from PP5V to PA_VBUS is called PP_5V1 , and the path from PP5V to
PB_VBUS is called PP_5V2. The path from PP5V to PA_CCx is called PP_CABLE1 , and the path from PP5V to
PB_CCy is called PP_CABLE2. Each path contains current clamping protection, overvoltage protection, UVLO
protection and temperature sensing circuitry. PP_5V1 and PP_5V2 may each conduct up to 3 A continuously,
while PP_CABLE1 and PP_CABLE2 may conduct up to 315 mA continuously. When disabled, the blocking FET
protects the PP5V rail from high-voltage that may appear on Px_VBUS.

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3A
Fast current clamp, ILIM5V
PA_VBUS

Temp
Sensor

PP_VBUS1 Gate Control and Sense

PP_5V1

PP_CABLE1
TSD_PP5V PA_CC1 Gate Control

Fast current limit, IVCON

PA_CC1

PA_CC2 Gate Control

PP5V Temp
Sensor

PA_CC2

3A
Fast current clamp, ILIM5V

PB_VBUS

Temp
Sensor

PP_VBUS2 Gate Control and Sense

PP_5V2

TSD_PP5V PP_CABLE2
PB_CC1 Gate Control

Fast current limit, IVCON

PB_CC1

PB_CC2 Gate Control

Temp
Sensor

PB_CC2

Figure 8-10. Port Power Switches

8.3.3.1.1 PP_5Vx Current Clamping

The current through the internal PP_5Vx paths are current limited to ILIM5V. The ILIM5V value is configured by
application firmware. When the current through the switch exceeds ILIM5V, the current limiting circuit activates
within tiOS_PP_5V and the path behaves as a constant current source. If the duration of the overcurrent event
exceeds tILIM, the PP_5V switch is disabled.
8.3.3.1.2 PP_5Vx Local Overtemperature Shut Down (OTSD)
When PP_5Vx clamps the current, the temperature of the switch will begin to increase. When the local
temperature sensors of PP_5Vx or PP_CABLEx detect that TJ>TSD_PP5V the PP_5Vx switch is disabled and
the affected port enters the USB Type-C ErrorRecovery state.

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8.3.3.1.3 PP_5Vx Current Sense

The current from PP5V to Px_VBUS is sensed through the switch and passed to the internal ADC.
8.3.3.1.4 PP_5Vx OVP
The overvoltage protection level is automatically configured based on the expected maximum VBUS voltage,
which depends upon the USB PD contract. When the voltage on a port's Px_VBUS pin exceeds the configured
value (VOVP4RCP) while PP_5Vx is enabled, then PP_5Vx is disabled within tPP_5V_ovp and the affected port
enters into the Type-C ErrorRecovery state.
8.3.3.1.5 PP_5Vx UVLO
If the PP5V pin voltage falls below its undervoltage lock out threshold (VPP5V_UVLO) while PP_5Vx is enabled,
then PP_5Vx is disabled within tPP_5V_uvlo and the port that had PP_5Vx enabled enters into the Type-C
ErrorRecovery state.
8.3.3.1.6 PP_5Vx Reverse Current Protection
If VPx_VBUS - VPP5V > VPP_5V_RCP, then the PP_5Vx path is automatically disabled within tPP_5V_rcp. If the RCP
condition clears, then the PP_5Vx path is automatically enabled within tON.
8.3.3.1.7 Fast Role Swap
The TPS65994AE supports Fast Role Swap as defined by USB PD. The PP_5Vx path has a fast turn-on mode
that application firmware selectively enables to support Fast Role Swap. When enabled it is engaged when
VPx_VBUS - VPP5V<VPP_5V_RCP, and turns on the switch within tFRS_on.
8.3.3.1.8 PP_CABLE Current Clamp
When enabled and providing VCONN power the TPS65994AE PP_CABLE power switches clamp the current to
IVCON. When the current through the PP_CABLEx switch exceeds IVCON, the current clamping circuit activates
within tiOS_PP_CABLE and the switch behaves as a constant current source. The switches do not have reverse
current blocking when the switch is enabled and current is flowing to either Px_CC1 or Px_CC2.

8.3.3.1.9 PP_CABLE Local Overtemperature Shut Down (OTSD)

When PP_CABLEx clamps the current, the temperature of the switch will begin to increase. When the local
temperature sensors of PP_5Vx or PP_CABLEx detect that TJ>TSD_PP5V the PP_CABLEx switch is disabled and
latched off within tPP_CABLE_off. The port then enters the USB Type-C ErrorRecovery state.
8.3.3.1.10 PP_CABLE UVLO
If the PP5V pin voltage falls below its undervoltage lock out threshold (VPP5V_UVLO), then both PP_CABLE1 and
PP_CABLE2 switches are automatically disabled within tPP_CABLE_off.
8.3.3.2 Sink Path Control
The sink-path control includes overvoltage protection (OVP), and reverse current protection (RCP).

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3A

PP_EXT1

PP_EXT2

3A

PB_GATE_VBUS

PA_GATE_VBUS
PB_GATE_VSYS

PA_GATE_VSYS
PB_VBUS

PA_VBUS
VSYS

PP_EXT2 Gate Control and

Sense

PP_EXT1 Gate Control and Sense

Figure 8-11. Sink Path Control

The following figure shows the Px_GATE_VSYS gate driver in more detail.

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Px_GATE_VSYS

VSYS
switch enabled when
gate driver is disabled and
VVIN_3V3 < VVIN_3V3_UVLO
VPx_GATE_ON

RPx_GATE_FSD
Regular enable/
disable
Fast
disable
IPx_GATE_OFF IPx_GATE_ON
Charge Px_VBUS
RPx_GATE_OFF_UVLO Pump
GND

Figure 8-12. Details of the Px_GATE_VSYS gate driver.

8.3.3.2.1 Overvoltage Protection (OVP)

The application firmware enables the OVP and configures it based on the expected Px_VBUS voltage. If the
voltage on Px_VBUS surpasses the configured threshold VOVP4VSYS = VOVP4RCP/rOVP, then Px_GATE_VSYS is
automatically disabled within tPx_GATE_VSYS_FSD to protect the system. If the voltage on Px_VBUS surpasses the
configured threshold VOVP4RCP then Px_GATE_VBUS is automatically disabled within tPx_GATE_VBUS_OVP. When
VPx_VBUS falls below VOVP4RCP - VOVP4RCPHPx_GATE_VBUS is automatically re-enabled within
tPx_GATE_VBUS_ON since the OVP condition has cleared. This allows two sinking power paths to be enabled
simultaneously and Px_GATE_VBUS will be disabled when necessary to ensure that VPx_VBUS remains below
VOVP4RCP.
While the TPS65994AE is in the BOOT mode in a dead-battery scenario (that is VIN_3V3 is low) it
handles an OVP condition slightly differently. As long as the OVP condition is present Px_GATE_VBUS and
Px_GATE_VSYS are disabled. Once the OVP condition clears, both Px_GATE_VBUS and Px_GATE_VSYS
are re-enabled (unless ADCINx are configured in SafeMode). Since this is a dead-battery condition, the
TPS65994AE will be drawing approximately IVIN_3V3,ActSnk from PA_VBUS or PB_VBUS during this time to help
discharge it.

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VBUS
Power Path Supervisor

VOVP4RCP

VOVP4VSYS = VOVP4RCP / rOVP

Figure 8-13. Diagram for OVP Comparators

8.3.3.2.2 Reverse-Current Protection (RCP)

The VSYS gate control circuit monitors the VSYS and Px_VBUS voltages and detects reverse current when the
VVSYS surpasses VPx_VBUS by more than VRCP. When the reverse current condition is detected, Px_GATE_VBUS
is disabled within tPx_GATE_VBUS_RCP. When the reverse current condition is cleared, Px_GATE_VBUS is re-
enabled within tPx_GATE_VBUS_ON. This limits the amount of reverse current that may flow from VSYS to Px_VBUS
through the external N-ch MOSFETs.
In reverse current protection mode, the power switch controlled by Px_GATE_VBUS is allowed to behave
resistively until the current reaches VRCP/ RON and then blocks reverse current from VSYS to Px_VBUS , where
RON is the resistance of the external back-to-back N-ch MOSFET. Figure 8-14 shows the behavior of the switch.

1/RON

-VRC P

V=VPx_VBUS VVSYS
VRC P/RON

Figure 8-14. Switch I-V Curve for RCP on External Switches

8.3.3.2.3 VBUS UVLO

The TPS65994AE monitors Px_VBUS voltage and detects when it falls below VVBUS_UVLO. When the UVLO
condition is detected, Px_GATE_VBUS is disabled within tPx_GATE_VBUS_RCP. When the UVLO condition is
cleared, Px_GATE_VBUS is re-enabled within tPx_GATE_VBUS_ON.
8.3.3.2.4 Discharging VBUS to Safe Voltage
The TPS65994AE has an integrated active pull-down (IDSCH) on Px_VBUS for discharging from high voltage to
VSAFE0V (0.8 V). This discharge is applied when it is in an Unattached Type-C state.

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8.3.4 Cable Plug and Orientation Detection

Figure 8-15 shows the plug and orientation detection block at each Px_CCy pin (PA_CC1, PA_CC2, PB_CC1,
PB_CC2). Each pin has identical detection circuitry.

IRp De f IRp1.5 IRp3.0

VREF1
Px_CCy

VREF2

VREF3 RSNK

Figure 8-15. Plug and Orientation Detection Block

8.3.4.1 Configured as a Source

When configured as a source, the TPS65994AE detects when a cable or a Sink is attached using the Px_CC1
and Px_CC2 pins. When in a disconnected state, the TPS65994AE monitors the voltages on these pins to
determine what, if anything, is connected. See USB Type-C Specification for more information.
Table 8-1 shows the Cable Detect States for a Source.
Table 8-1. Cable Detect States for a Source
Px_CC1 Px_CC2 CONNECTION STATE RESULTING ACTION
Continue monitoring both Px_CCy pins for attach. Power is not applied to Px_VBUS
Open Open Nothing attached
or VCONN.
Monitor Px_CC1 for detach. Power is applied to Px_VBUS but not to VCONN
Rd Open Sink attached
(Px_CC2).
Monitor Px_CC2 for detach. Power is applied to Px_VBUS but not to VCONN
Open Rd Sink attached
(Px_CC1).
Powered Cable-No UFP Monitor Px_CC2 for a Sink attach and Px_CC1 for cable detach. Power is not
Ra Open
attached applied to Px_VBUS or VCONN (Px_CC1).
Powered Cable-No UFP Monitor Px_CC1 for a Sink attach and Px_CC2 for cable detach. Power is not
Open Ra
attached applied to Px_VBUS or VCONN (Px_CC1).
Provide power on Px_VBUS and VCONN (Px_CC1) then monitor Px_CC2 for a Sink
Ra Rd Powered Cable-UFP Attached
detach. Px_CC1 is not monitored for a detach.
Provide power on Px_VBUS and VCONN (Px_CC2) then monitor Px_CC1 for a Sink
Rd Ra Powered Cable-UFP attached
detach. Px_CC2 is not monitored for a detach.
Debug Accessory Mode
Rd Rd Sense either Px_CCy pin for detach.
attached

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Table 8-1. Cable Detect States for a Source (continued)

Px_CC1 Px_CC2 CONNECTION STATE RESULTING ACTION
Audio Adapter Accessory
Ra Ra Sense either Px_CCy pin for detach.
Mode attached

When a TPS65994AE port is configured as a Source, a current IRpDef is driven out each Px_CCy pin and each
pin is monitored for different states. When a Sink is attached to the pin a pull-down resistance of Rd to GND
exists. The current IRpDef is then forced across the resistance Rd generating a voltage at the Px_CCy pin. The
TPS65994AE applies IRpDef until it closes the switch from PP5V to Px_VBUS, at which time application firmware
may change to IRp1.5A or IRp3.0A.
When the Px_CCy pin is connected to an active cable VCONN input, the pull-down resistance is different (Ra).
In this case the voltage on the Px_CCy pin will be lower and the TPS65994AE recognizes it as an active cable.
The voltage on Px_CCy is monitored to detect a disconnection depending upon which Rp current source is
active. When a connection has been recognized and the voltage on Px_CCy subsequently rises above the
disconnect threshold for tCC, the system registers a disconnection.
8.3.4.2 Configured as a Sink
When a TPS65994AE port is configured as a Sink, the TPS65994AE presents a pull-down resistance RSNK on
each Px_CCy pin and waits for a Source to attach and pull-up the voltage on the pin. The Sink detects an
attachment by the presence of VBUS. The Sink determines the advertised current from the Source based on the
voltage on the Px_CCy pin.
8.3.4.3 Configured as a DRP
When a TPS65994AE port is configured as a DRP, the TPS65994AE alternates the port's Px_CCy pins between
the pull-down resistance, RSNK, and pull-up current source, IRp.
8.3.4.4 Fast Role Swap Signal Detection
The TPS65994AE cable plug block contains additional circuitry that may be used to support the Fast Role Swap
(FRS) behavior defined in the USB Power Delivery Specification. The circuitry provided for this functionality is
detailed in Figure 8-16.

Px_CC1

To Cable Detect and

Ori entation

Px_CC2

To Digital Core

VFRS

Figure 8-16. Fast Role Swap Detection and Signaling

When a TPS65994AE port is operating as a sink with FRS enabled, the TPS65994AE monitors the CC pin
voltage. If the CC voltage falls below VFRS for tFRS_DET a fast role swap signal is detected and indicated
to the digital core. When this signal is detected the TPS65994AE ceases operating as a sink (disables
Px_GATE_VSYS and Px_GATE_VBUS) and begins operating as a source.

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8.3.5 Default Behavior Configuration (ADCIN1, ADCIN2)

Note
This functionality is firmware controlled and subject to change.

The ADCINx inputs to the internal ADC control the behavior of the TPS65994AE in response to PA_VBUS or
PB_VBUS being supplied when VIN_3V3 is low (that is the dead-battery scenario). The ADCINx pins must be
externally tied to the LDO_3V3 pin via a resistive divider as shown in the following figure. At power-up the ADC
converts the ADCINx voltage and the digital core uses these two values to determine start-up behavior. The
available start-up configurations include options for I2C slave address of I2C_EC_SCL/SDA, sink path control in
dead-battery, and default configuration.

LDO_3V3

Mux an d
ADC
Divi ders

ADCINx

Figure 8-17. ADCINx Resistor Divider

The device behavior is determined in several ways depending upon the decoded value of the ADCIN1 and
ADCIN2 pins. The following table shows the decoded values for different resistor divider ratios. See Pin
Strapping to Configure Default Behavior for details on how the ADCINx configurations determine default device
behavior. See I2C Address Setting for details on how ADCINx decoded values affects default I2C slave address.
Table 8-2. Decoding of ADCIN1 and ADCIN2 Pins
DIV = RDOWN / (RUP + RDOWN)(1) Without using RUP
ADCINx decoded value
MIN Target MAX or RDOWN

0 0.0114 0.0228 tie to GND 0

0.0229 0.0475 0.0722 N/A 1
0.0723 0.1074 0.1425 N/A 2
0.1425 0.1899 0.2372 N/A 3
0.2373 0.3022 0.3671 N/A 4
0.3672 0.5368 0.7064 tie to LDO_1V5 5
0.7065 0.8062 0.9060 N/A 6
0.9061 0.9530 1.0 tie to LDO_3V3 7

(1) External resistor tolerance of 1% is recommended. Resistor values must be chosen to yield a DIV value centered nominally between
listed MIN and MAX values. For convenience, the Target column shows this value.

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8.3.6 ADC
The TPS65994AE ADC is shown in Figure 8-18. The ADC is an 8-bit successive approximation ADC. The input
to the ADC is an analog input mux that supports multiple inputs from various voltages and currents in the device.
The output from the ADC is available to be read and used by application firmware.

Voltage
Px_VBUS
Divi der 2

LDO_3V3 Voltage
Divi der 1
8 bits
Input ADC
GPIO4
Mux
ADCIN1 Buffers &
Voltage
ADCIN2
Divi der 1
GPIO5

I_Px_VBUS I-to-V

Figure 8-18. SAR ADC

8.3.7 DisplayPort Hot-Plug Detect (HPD)

The TPS65994AE supports the DisplayPort alternate mode as a DP source . It is recommended to use the
virtual HPD functionality through I2C. However, the TPS65994AE also supports the HPD converter functions on
GPIO pins (See Table 8-3). The core will translate PD messaging events onto the HPD pin.

PD Con tro ller VBUS

(PD to HPD converter)

CC1
Disp layPort
Typ e-C Conn ector
Transmitter System CC2

HPD GPIO1 / HPD_Tx GND

detecto r

PD Con tro ller VBUS

(HPD to PD converter)

CC1
Disp layPort
Typ e-C Conn ector
Receiver S ystem CC2

HPD HPD_Rx GND

driver

Figure 8-19. Illustration of how a PD-to-HPD Converter Passes the HPD Signal Along in a DisplayPort
System

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8.3.8 Digital Interfaces

The TPS65994AE contains several different digital interfaces which may be used for communicating with other
devices. The available interfaces include two I2C Slaves and one I2C Master, and additional GPIOs.
8.3.8.1 General GPIO
GPIOn pins can be mapped to USB Type-C, USB PD, and application-specific events to control other ICs,
interrupt a host processor, or receive input from another IC. This buffer is configurable to be a push-pull output, a
weak push-pull, or open drain output. When configured as an input, the signal can be a de-glitched digital input
or an analog input to the ADC (only a subset of the GPIO's are ADC inputs see table below). The push-pull
output is a simple CMOS output with independent pull-down control allowing open-drain connections. The weak
push-pull is also a CMOS output, but with GPIO_RPU resistance in series with the drain. The supply voltage to
the output buffer is LDO_3V3 and LDO_1V5 to the input buffer. When interfacing with non 3.3-V I/O devices the
output buffer may be configured as an open drain output and an external pull-up resistor attached to the GPIO
pin. The pull-up and pull-down output drivers are independently controlled from the input and are enabled or
disabled via application code in the digital core.
Table 8-3. GPIO Functionality Table
Pin Name Type Special Functionality
GPIO0 I/O HPD_Tx for Port B
GPIO1 I/O HPD_Tx for Port A
GPIO2 I/O
GPIO3 I/O
GPIO4 I/O ADC Input,
GPIO5 I/O ADC Input,
GPIO6 I/O
GPIO7 I/O
GPIO8 I/O
GPIO9 O PROCHOT#
I2C_EC_IRQ(GPIO10) O IRQ for I2C_EC, or used as a general-purpose output
I2C2s_IRQ(GPIO11) O IRQ for I2C2, or used as a general-purpose output
I2C3m_IRQ(GPIO12) I IRQ for I2C3, or used as a general-purpose input

8.3.8.2 I2C Interface

The TPS65994AE features three I2C interfaces that each use an I2C I/O driver like the one shown in Figure 8-20.
This I/O consists of an open-drain output and in input comparator with de-glitching.

50ns
I2C_DI
Deglitch

I2C_SDA/SCL
I2C_DO

Figure 8-20. I2C Buffer

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8.3.9 Digital Core

Figure 8-21 shows a simplified block diagram of the digital core.

GPIO0-9

I2C_EC_SDA

I2C
I2C to I2C_EC_SCL Por t 1
System Co ntr ol (slave)

I2C_EC_IRQ

I2C2s_SDA

I2C
I2C to I2C2s_SCL Por t 2
Thunde rbolt Con troll er (slave)
Digital Cor e CBL_DET
I2C2s_IRQ USB PD P hy
Bias CTL
and USB-PD

I2C3m_SDA

I2C to I2C3m_SCL
Thunde rbolt Retimer I2C
Por t 3
(master)
I2C3m_IRQ

OSC
ADC Read

Thermal Temp
Shu tdo wn Sen se ADC

Figure 8-21. Digital Core Block Diagram

8.3.10 I2C Interface

The TPS65994AE has two I2C slave interface ports: I2C_EC and I2C2s. I2C port I2C_EC is comprised of the
I2C_EC_SDA, I2C_EC_SCL, and I2C_EC_IRQ pins. I2C I2C2s is comprised of the I2C2s_SDA, I2C2s_SCL,
and I2C2s_IRQ pins. These interfaces provide general status information about the TPS65994AE, as well as the
ability to control the TPS65994AE behavior, supporting communications to/from a connected device and/or cable
supporting BMC USB-PD, and providing information about connections detected at the USB-C receptacle.
When the TPS65994AE is in 'APP ' mode it is recommended to use Standard Mode or Fast Mode (that is a clock
speed no higher than 400 kHz). However, in the 'BOOT' mode when a patch bundle is loaded Fast Mode Plus
may be used (see fSCLS).
The TPS65994AE has one I2C master interface port: I2C3m. I2C3m is comprised of the I2C3m_SDA,
I2C3m_SCL, and I2C3m_IRQ1 pins. This interface can be used to read from or write to external slave devices.
During boot the TPS65994AE attempts to read patch and Application Configuration data from an external
EEPROM with a 7-bit slave address of 0x50. The EEPROM should be at least 32 kilo-bytes.
Table 8-4. I2C Summary
I2C Bus Type Typical Usage
I2C_EC Slave Connect to an Embedded Controller (EC). Used to load the patch and application configuration.
I2C2s Slave Connect to a TBT controller or second master.

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Table 8-4. I2C Summary (continued)

I2C Bus Type Typical Usage
Connect to a TBT retimer, USB Type-C mux, I2C EEPROM, or other slave. Use the LDO_3V3 pin as
I2C3m Master
the pull-up voltage. Multi-master configuration is not supported.

8.3.10.1 I2C Interface Description

The TPS65994AE supports Standard and Fast mode I2C interfaces. The bidirectional I2C bus consists of the
serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up
resistor. Data transfer may be initiated only when the bus is not busy.
A master sending a Start condition, a high-to-low transition on the SDA input and output, while the SCL input is
high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit
(MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred
during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period
as changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a
Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this
event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 8-22 shows the start and stop conditions of the transfer. Figure 8-23 shows the SDA and SCL signals for
transferring a bit. Figure 8-24 shows a data transfer sequence with the ACK or NACK at the last clock pulse.

SDA

SCL

S P
Start Condition Stop Condition

Figure 8-22. I2C Definition of Start and Stop Conditions

SDA

SCL

Data Line Change

Figure 8-23. I2C Bit Transfer

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Data Output
by Transmitter

Nack
Data Output
by Receiver

SCL From Ack

Master
1 2 8 9
S
Start Clock Pulse for
Condition Acknowledgement

Figure 8-24. I2C Acknowledgment

8.3.10.2 I2C Clock Stretching

The TPS65994AE features clock stretching for the I2C protocol. The TPS65994AE slave I2C port may hold the
clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data.
The master communicating with the slave must not finish the transmission of the current bit and must wait until
the clock line actually goes high. When the slave is clock stretching, the clock line remains low.
The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for
standard 100-kbps I2C) before pulling the clock low again.
Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.
8.3.10.3 I2C Address Setting
The host should only use I2C_EC_SCL/SDA for loading a patch bundle. Once the boot process is complete,
each port has a unique slave address on the I2C_EC_SCL/SDA bus as selected by the ADCINx pins. The slave
address used by each port on the I2C2s bus are determined from the application configuration. The Port A slave
address should be used for pushing the patch bundle since the Port B slave address is not available during the
BOOT mode.
Table 8-5. I2C Default Slave Address for I2C_EC_SCL/SDA.
I2C address index Slave Address
Available During
(decoded from ADCIN1 Port
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOOT
and ADCIN2)(1)
#1 A 0 1 0 0 0 0 0 R/W Yes
#1 B 0 1 0 0 1 0 0 R/W No
#2 A 0 1 0 0 0 0 1 R/W Yes
#2 B 0 1 0 0 1 0 1 R/W No
#3 A 0 1 0 0 0 1 0 R/W Yes
#3 B 0 1 0 0 1 1 0 R/W No
#4 A 0 1 0 0 0 1 1 R/W Yes
#4 B 0 1 0 0 1 1 1 R/W No

(1) See Table 8-2 details about ADCIN1 and ADCIN2 decoding.

8.3.10.4 Unique Address Interface

The Unique Address Interface allows for complex interaction between an I2C master and a single TPS65994AE.
The I 2C Slave sub-address is used to receive or respond to Host Interface protocol commands. Figure 8-25 and
Figure 8-26 show the write and read protocol for the I2C slave interface, and a key is included in Figure 8-27
to explain the terminology used. The TPS65994AE Host interface utilizes a different unique address to identify
each of the two USB Type-C ports controlled by the TPS65994AE. The key to the protocol diagrams is in the
SMBus Specification and is repeated here in part.

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1 7 1 1 8 1 8 1 8 1

S Unique Address Wr A Register Number A Byte Count = N A Data Byte 1 A

8 1 8 1

Data Byte 2 A Data Byte N A P

Figure 8-25. I2C Unique Address Write Register Protocol

1 7 1 1 8 1 1 7 1 1 8 1

S Unique Address Wr A Register Number A Sr Unique Address Rd A Byte Count = N A

8 1 8 1 8 1

Data Byte 1 A Data Byte 2 A Data Byte N A P

Figure 8-26. I2C Unique Address Read Register Protocol

1 7 1 1 8 1 1

S Slave Address Wr A Data Byte A P

x x
S Start Condition

SR Repeated Start Condition

Rd Read (bit value of 1)

Wr Write (bit value of 0)

x Field is required to have the value x

Acknowledge (this bit position may be 0 for an ACK or
A
1 for a NACK)
P Stop Condition

Master-to-Slave

Slave-to-Master

Continuation of protocol

Figure 8-27. I2C Read/Write Protocol Key

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8.4 Device Functional Modes

8.4.1 Pin Strapping to Configure Default Behavior

During the boot procedure, the device will read the ADCINx pins and set the configurations based on the table
below. Then it will attempt to load a configuration from an external EEPROM on the I2C3m bus. If no EEPROM
is detected, then the device will wait for an EC to load a configuration.
When an external EEPROM is used, each device is connected to a unique EEPROM, it cannot be shared for
multiple devices. The external EEPROM shall be at 7-bit slave address 0x50.

Table 8-6. Device Configuration using ADCIN1 and ADCIN2

ADCIN1 decoded ADCIN2 decoded
I2C address Index (1) Dead Battery Configuration
value (2) value (2)
7 5 #1
5 5 #2 AlwaysEnableSink: The device always enables the sink path
regardless of the amount of current the attached source is
2 0 #3 offering. USB PD is disabled until configuration is loaded.
1 7 #4
7 4 #1
4 4 #2 SinkRequires_3.0A: The device only enables the sink path if the
attached source is offering at least 3.0A. USB PD is disabled
3 0 #3 until configuration is loaded.
2 7 #4
7 6 #1
6 6 #2 SinkRequires_1.5A: The device only enables the sink path if the
attached source is offering at least 1.5A. USB PD is disabled
6 5 #3 until configuration is loaded.
6 7 #4
7 3 #1 NegotiateHighVoltage: The device always enables the sink path
during the initial implicit contract regardless of the amount of
3 3 #2
current the attached source is offering. The PD controller will
4 0 #3 enter the 'APP ' mode, enable USB PD PHY and negotiate a
3 7 #4 contract for the highest power contract that is offered up to 20 V.
This cannot be used when a patch is loaded from EEPROM.
7 0 #1 SafeMode: The device does not enable the sink path. USB
0 0 #2 PD is disabled until configuration is loaded. Note that the
configuration could put the device into a source-only mode.
6 0 #3 This is recommended when the application loads the patch from
5 7 #4 EEPROM.

(1) See Table 8-5 to see the exact meaning of I2C Address Index.
(2) See Table 8-2 for how to configure a given ADCINx decoded value.

8.4.2 Power States

The TPS65994AE may operate in one of three different power states: Active, Idle, or Sleep. The Modern
Standby mode is a special case of the Idle mode. The functionality available in each state is summarized in
the following table. The device will automatically transition between the three power states based on the circuits
that are active and required, see the following figure. In the Sleep State the TPS65994AE will detect a Type-C
connection. Transitioning between the Active mode to the Idle mode requires a period of time (T) without any of
the following activity:
• Incoming USB PD message.
• Change in CC status.
• GPIO input event.
• I2C transactions.
• Voltage alert.
• Fault alert.

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Figure 8-28. Flow Diagram For Power States

Table 8-7. Power Consumption States

Modern Modern
Active Source Active Sink Idle Source Idle Sink
Standby Standby Sink Sleep Mode(3)
Mode(1) Mode(6) Mode(2) Mode(7)
Source Mode(4) Mode(5)
PP_5V1 enabled disabled enabled disabled enabled disabled disabled
PP_5V2 enabled disabled enabled disabled disabled disabled disabled
PP_EXT 1 disabled enabled disabled enabled disabled disabled disabled
PP_EXT2 disabled enabled disabled enabled disabled disabled disabled
PP_CABLE1 enabled enabled enabled enabled disabled disabled disabled
PP_CABLE2 enabled enabled enabled enabled disabled disabled disabled
external
PA_CC1 Rd Rp 3.0A Rd Rp 3.0A Rd Rp 3.0A open
termination
external
PA_CC2 open open open open open open open
termination
external
PB_CC1 Rd Rp 3.0A Rd Rp 3.0A open open open
termination
external
PB_CC2 open open open open open open open
termination

(1) This mode is used for: IVIN_3V3,ActSrc.

(2) This mode is used for: IVIN_3V3,IdlSrc
(3) This mode is used for: IVIN_3V3,Sleep
(4) This mode is used for: PMstbySrc
(5) This mode is used for: PMstbySnk
(6) This mode is used for: IVIN_3V3,ActSnk
(7) This mode is used for: IVIN_3V3,IdlSnk

8.4.3 Thermal Shutdown

The TPS65994AE features a central thermal shutdown as well as independent thermal sensors for each
internal power path. The central thermal shutdown monitors the overall temperature of the die and disables
all functions except for supervisory circuitry when die temperature goes above a rising temperature of TSD_MAIN.
The temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back below this value,
the device resumes normal operation.
The power path thermal shutdown monitors the temperature of each internal PP5V-to-VBUS power path and
disables both power paths and the VCONN power path when either exceeds TSD_PP5V. Once the temperature
falls by at least T SDH_PP5V the path can be configured to resume operation or remain disabled until re-enabled by
firmware.

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The TPS65994AE firmware implements a host interface over I2C to allow for the configuration and control of all
device options.Initial device configuration is configured through a configuration bundle loaded on to the device
during boot.The bundle may be loaded through the I2C_EC port or it may be loaded over I2C3m from an
external EEPROM.The TPS65994AE configuration bundle and host interface allow the device to be customized
for each specific application. The configuration bundle can be generated through the Application Customization
Tool.
9.2 Typical Application
9.2.1 Type-C VBUS Design Considerations
USB Type-C and PD allows for voltages up to 20 V with currents up to 5 A. This introduces power levels
that could damage components touching or hanging off of VBUS. Under normal conditions, all high power PD
contracts should start at 5 V and then transition to a higher voltage. However, there are some devices that are
not compliant to the USB Type-C and Power Delivery standards and could have 20 V on VBUS. This could
cause a 20-V hot plug that can ring above 30 V. Adequate design considerations are recommended below for
these non-compliant devices.
9.2.1.1 Design Requirements
Table 9-1 shows VBUS conditions that can be introduced to a USB Type-C and PD Sink. The system should be
able to handle these conditions to ensure that the system is protected from non-compliant and/or damaged USB
PD sources. A USB Sink should be able to protect from the following conditions being applied to its VBUS. The
Section 9.2.1.2 section explains how to protect from these conditions.
Table 9-1. VBUS Conditions
CONDITION VOLTAGE APPLIED
Abnormal VBUS Hot Plug 4 V - 21.5 V
VBUS Transient Spikes 4 V - 43 V

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9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Type-C Connector VBUS Capacitors
C_VBUS C_VBUS
VBUS A4 VBUS B9
10 nF 10 nF
35V 35V

GND
Type-C GND
Connector

C_VBUS C_VBUS
VBUS A9 VBUS B4
10 nF 10 nF
35V 35V

GND GND

Figure 9-1. Type-C Connector VBUS Capacitors

The first level of protection starts at the Type-C connector and the VBUS pin capacitors. These capacitors help
filter out high frequency noise but can also help absorb short voltage transients. Each VBUS pin should have
a 10-nF capacitor rated at or above 25 V and placed as close to the pin as possible. The GND pin on the
capacitors should have very short path to GND on the connector. The derating factor of ceramic capacitors
should be taken into account as they can lose more than 50% of their effective capacitance when biased. Adding
the VBUS capacitors can help reduce voltage spikes by 2 V to 3 V.
9.2.1.2.2 VBUS Schottky and TVS Diodes
Schottky diodes are used on VBUS to help absorb large GND currents when a Type-C cable is removed while
drawing high current. The inductance in the cable will continue to draw current on VBUS until the energy stored
is dissipated. Higher currents could cause the body diodes on IC devices connected to VBUS to conduct. When
the current is high enough it could damage the body diodes of IC devices. Ideally, a VBUS Schottky diode
should have a lower forward voltage so it can turn on before any other body diodes on other IC devices.
Schottky diodes on VBUS also help during hard shorts to GND which can occur with a faulty Type-C cable or
damaged Type-C PD device. VBUS could ring below GND which could damage devices hanging off of VBUS.
The Schottky diode will start to conduct once VBUS goes below the forward voltage. When the TPS65994AE is
the only device connected to VBUS, place the Schottky Diode close to the VBUS pin of the TPS65994AE. The
two figures below show a short condition with and without a Schottky diode on VBUS. In Figure 9-3 the test is
with TVS2200 but without Schottky diode and in Figure 9-4 is with both TVS2200 and the Schottky diode. As the
graphs are almost identical and the voltage ring below ground are within 300mV of one another, a TVS diode
such as the TVS2200 can be used in lieu of a Schottky diode.
TVS Diodes help suppress and clamp transient voltages. Most TVS diodes can fully clamp around 10 ns and
can keep the VBUS at their clamping voltage for a period of time. Looking at the clamping voltage of TVS diodes
after they settle during a transient will help decide which TVS diode to use. The peak power rating of a TVS
diode must be able to handle the worst case conditions in the system. A TVS diode can also act as a “pseudo
schottky diode” as they will also start to conduct when VBUS goes below GND.

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9.2.1.2.3 VBUS Snubber Circuit

VBUS
4.7 …F

1 …F

3.48Ÿ

GND

Figure 9-2. VBUS Snubber

Another method of clamping the USB Type-C VBUS is to use a VBUS RC Snubber. An RC Snubber is a great
solution because in general it is much smaller than a TVS diode, and typically more cost effective as well. An RC
Snubber works by modifying the characteristic of the total RLC response in the USB Type-C cable hot-plug from
being under-damped to critically-damped or over-damped. So rather than clamping the over-voltage directly, it
changes the hot-plug response from under-damped to critically-damped, so the voltage on VBUS does not ring
at all; so the voltage is limited, but without requiring a clamping element like a TVS diode.
However, the USB Type-C and Power Delivery specifications limit the range of capacitance that can be used
on VBUS for the RC snubber. VBUS capacitance must have a minimum 1 µF and a maximum of 10 µF. The
RC snubber values chosen support up to 4 m USB Type-C cable (maximum length allowed in the USB Type-C
specification) being hot plugged, is to use 4.7-μF capacitor in series with a 3.48-Ω resistor. In parallel with
the RC Snubber a 1μF capacitor is used, which always ensures the minimum USB Type-C VBUS capacitance
specification is met. This circuit can be seen in Figure 9-2.
9.2.1.3 Application Curves

Figure 9-3. Px_VBUS Short with TVS2200, but Figure 9-4. Px_VBUS Short with TVS2200 and
Without Schottky Diode Schottky Diode

9.2.2 Notebook Design Supporting PD Charging

The TPS65994AE works very well in single port Notebooks that support PD charging. The internal power
path for the TPS65994AE source System 5 V from PP5V to the VBUS pins. Additionally, the TPS65994AE
can control an external Common Drain N-FET power path to sink power into the system. The TPS65994AE
offers full reverse-current protection on the external power path through the N-FET gate driver. The System
5-V connected to PP5V on the TPS65994AE also supplies power to VCONN of Type-C e-marked cables and
Type-C accessories. An embedded controller EC is used for additional control of the TPS65994AE and to relay
information back to the operating system. An embedded controller enables features such as entering and exiting
sleep modes, changing source and sink capabilities depending on the state of the battery, UCSI support, control
alternate modes, and so forth.

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9.2.2.1 USB and DisplayPort notebook Supporting PD Charging

USB SSTX/RX USB3.1 Source
SSTX/RX
TUSB1046 I2C SS Mux Control
SBU1/2
DP ML DP1.4 Source

USB2.0 Source

Port A Type C
Receptacle

SSTX/RX

SBU1/2
PA_HV_GATE
USB2.0
GPIO SS Mux Control*
CC1/2 PA_CC1/2

VBUS System 5V
PP5V
VIN BAT

BQ Battery +
TPS65994 VIN_3V3 System 3.3V Charger
Port B Type C I2C
Receptacle
VBUS PP5V

CC1/2 PB_CC1/2
I2C3m SS Mux Control*

USB2.0 I2C_EC EC
PB_HV_GATE
SBU1/2
I2C MASTER
SSTX/RX

USB2.0 Source

DP ML DP1.4 Source
SBU1/2
TUSB1046 I2C SS Mux Control
SSTX/RX
USB SSTX/RX USB3.1 Source

Figure 9-5. USB and DisplayPort Architecture

9.2.2.1.1 Design Requirements

Table 9-2 summarizes the Power Design parameters for an USB Type-C PD Notebook.
Table 9-2. Power Design Parameters
POWER DESIGN PARAMETERS VALUE CURRENT PATH
PP5V Input Voltage, Current 5 V, 2 A VBUS Source & VCONN Source
NFET PP_EXT Voltage, Current 5 V – 20 V, 3 A (5 A Max) VBUS Sink
VIN_3V3 Voltage, Current 3.3 V, 50 mA Internal TPS65994AE Circuitry

9.2.2.1.2 Detailed Design Procedure

9.2.2.1.2.1 USB Power Delivery Source Capabilities
Most Type-C dongles (video and data) draw less than 900 mA and supplying 1.5 A on each Type-C port is
sufficient for a notebook supporting USB and DisplayPort. Table 9-3 shows the PDO for the Type-C port.

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Table 9-3. Source PDOs

SOURCE PDO PDO TYPE VOLTAGE CURRENT
PDO1 Fixed 5V 1.5 A

9.2.2.1.2.2 USB Power Delivery Sink Capabilities

Most notebooks support buck/boost charging which allows them to charge the battery from 5 V to 20 V. USB
PD sources must also follow the Source Power Rules defined by the USB Power Delivery specification. It is
recommended for notebooks to support all the voltages in the Source Power Rules to ensure compatibility with
most PD chargers/adapters.
Table 9-4. Sink PDOs
SINK PDO PDO TYPE VOLTAGE CURRENT
PDO1 Fixed 5V 3A
PDO2 Fixed 9V 3A
PDO3 Fixed 15 V 3A
PDO4 Fixed 20 V 3 A (5 A Max)

9.2.2.1.2.3 USB and DisplayPort Supported Data Modes

Table 9-5 summarizes the data capabilities of the notebook supporting USB3 and DisplayPort.
Table 9-5. Data Capabilities
PROTOCOL DATA DATA ROLE
USB Data USB3.1 Gen2 Host
DisplayPort DP1.4 Host DFP_D (Pin Assignment C, D, and E)

9.2.2.1.2.4 TUSB1046 Super Speed Mux GPIO Control

The TUSB1046 requires GPIO control in GPIO control mode to determine whether if there is USB or DisplayPort
data connection. Table 9-6 summarizes the TPS65994AE GPIO Events and the control pins for the TUSB1046.
Note that the pin strapping on the TUSB1046 will set the GPIO control mode and the required equalizer settings.
For more details refer to the TUSB1046 datasheet.
Table 9-6. GPIO Events for Super Speed Mux
TPS65994AE GPIO EVENT TUSB1046 CONTROL
Cable_Orientation_Event_Port1 FLIP
USB3_Event_Port1 CTL0
DP_Mode_Selection_Event_Port1 CTL1

9.2.2.2 Thunderbolt Notebook Supporting PD Charging

A Thunderbolt system is capable of sourcing USB, DisplayPort, and Thunderbolt data. There is an I2C
connection between the TPS65994AE and the Thunderbolt controller. The TPS65994AE will determine the
connection on the Type-C port and will generate an interrupt to the Thunderbolt controller to generate the
appropriate data output. An external mux for SBU may be needed to mux the LSTX/RX and AUX_P/N signal
from the Thunderbolt controller to the Type-C Connector. The TPD6S300 provides additional protection such as
short to VBUS on the CC and SBU pins and ESD for the USB2 DN/P. See Figure 9-6 for a block diagram of the
system.

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PB_TX0/1/RX0/1

SBU Mux Control

LSTX/RX PA_LSTX/RX
SBU1/2 TS3DS10224
AUXP/N PA_DPSRC_AUX_P/N

USB2.0 Source

U1_TBT_I2C_SDA
Port A Type C Thunderbolt
U2_TBT_I2C_SCL
Receptacle Controller I2C Master
J4_TBTA_I2C_IRQZ
SSTX/RX E2_TBTB_I2C_IRQZ

SBU1/2
PA_HV_GATE GPIO SBU Mux Control
USB2.0 TPD6S300 TBT RESETN RESETN

CC1/2 PA_CC1/2

VBUS System 5V
PP5V
VIN BAT

BQ Battery + Thunderbolt Controller

TPS65994 VIN_3V3 System 3.3V Charger (AR)
Port B Type C I2C
Receptacle
VBUS PP5V

CC1/2 PB_CC1/2
Thunderbolt
I2C2s
Controller I2C Master
USB2.0 TPD6S300
I2C_EC
EC
PB_HV_GATE
SBU1/2
I2C MASTER
SSTX/RX

USB2.0 Source

AUXP/N PB_DPSRC_AUX_P/N
SBU1/2 TS3DS10224
LSTX/RX PB_LSTX/RX

SBU Mux Control

PB_TX0/1/RX0/1

Figure 9-6. Thunderbolt Architecture

9.2.2.2.1 Design Requirements

Table 9-7 summarizes the Power Design parameters for an USB Type-C PD Thunderbolt Notebook.
Table 9-7. Power Design Parameters
POWER DESIGN PARAMETERS VALUE CURRENT PATH
PP5V Input Voltage, Current 5 V, 3.5 A VBUS Source & VCONN Source
NFET PP_EXT Voltage, Current 5 V – 20 V, 3 A (5 A Max) VBUS Sink
VIN_3V3 Voltage, Current 3.3 V, 50 mA Internal TPS65994AE Circuitry

9.2.2.2.2 Detailed Design Procedure

9.2.2.2.2.1 USB Power Delivery Source Capabilities
All Type-C Ports that support Thunderbolt must support sourcing 5 V at 3 A (15 W). See the Table 9-8 for the
PDO information.
Table 9-8. Source PDOs
SOURCE PDO PDO TYPE VOLTAGE CURRENT
PDO1 Fixed 5V 3A

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9.2.2.2.2.2 USB Power Delivery Sink Capabilities

Most notebooks support buck/boost charging which allows them to charge the battery from 5 V to 20 V. USB
PD sources must also follow the Source Power Rules defined by the USB Power Delivery specification. It is
recommended for notebooks to support all the voltages in the Source Power Rules to ensure compatibility with
most PD chargers/adapters.
Table 9-9. Sink PDOs
SINK PDO PDO TYPE VOLTAGE CURRENT
PDO1 Fixed 5V 3A
PDO2 Fixed 9V 3A
PDO3 Fixed 15 V 3A
PDO4 Fixed 20 V 3 A (5 A Max)

9.2.2.2.2.3 Thunderbolt Supported Data Modes

Thunderbolt Controllers are capable of generating USB3, DisplayPort and Thunderbolt Data. The Thunderbolt
controller is also capable of muxing the appropriate super speed signal to the Type-C connector. Thunderbolt
systems do not need a super speed mux for the Type-C connector. Table 9-10 summarizes the data capabilities
of each Type-C port supporting Thunderbolt.
Table 9-10. Data Capabilities
PROTOCOL DATA DATA ROLE
USB Data USB3.1 Gen2 Host
DisplayPort DP1.4 Host DFP_D (Pin Assignment C, D, and E)
Thunderbolt PCIe/DP Host/Device

9.2.2.2.2.4 I2C Design Requirements

The I2C connection from the TPS65994AE and the Thunderbolt control allows the Thunderbolt controller to read
the current data status from the TPS65994AE when there is a connection on the Type-C port. The Thunderbolt
controller has an interrupt assigned for the TPS65994AE and the Thunderbolt controller will read the I2C address
corresponding to the Type-C port. The I2C2s on the TPS65994AE is always connected to the Thunderbolt
controller.
9.2.2.2.2.5 TS3DS10224 SBU Mux for AUX and LSTX/RX
The SBU signals must be muxed from the Type-C connector to the Thunderbolt controller. The AUX for
DisplayPort and LSTX/RX for Thunderbolt are connected to the TS3DS10224 and then muxed to the SBU
pins. The SBU mux is controlled through GPIOs from the TPS65994AE. Table 9-11 shows the TPS65994AE
GPIO events and the control signals from the TS3DS10224.
Table 9-11. GPIO Events for SBU Mux
TPS65994AE GPIO EVENT TS3DS10224 CONTROL
Cable_Orientation_Event_Port1 SAO, SBO
DP_Mode_Selection_Event_Port1 ENA
TBT_Mode_Selection_Event_Por1 ENB
N/A SAI tied to VCC
N/A SBI tied to GND

Table 9-12 shows the connections for the AUX, LSTXRX, and SBU pins for the TS3DS10224.
Table 9-12. TS3DS10224 Pin Connections
TS3DS10224 PIN SIGNAL
INA+ SBU1
INA- SBU2

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Table 9-12. TS3DS10224 Pin Connections (continued)

TS3DS10224 PIN SIGNAL
OUTB0+ LSTX
OUTB0- LSRX
OUTB1+ LSRX
OUTB1- LSTX
OUTA0+ AUX_P
OUTA0- AUX_N
OUTA1+ AUX_N
OUTA1- AUX_P

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10 Power Supply Recommendations

10.1 3.3-V Power
10.1.1 VIN_3V3 Input Switch
The VIN_3V3 input is the main supply of the TPS65994AE device. The VIN_3V3 switch (see Power
Management) is a uni-directional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards
from LDO_3V3 to VIN_3V3. This switch is on when the 3.3 V supply is available. The recommended capacitance
CVIN_3V3 (see the Recommended Capacitance in the Specifications section) should be connected from the
VIN_3V3 pin to the GND pin ).
10.1.2 VBUS 3.3-V LDO
The 3.3 V LDO from Px_VBUS to LDO_3V3 steps down voltage from the PA_VBUS pin to LDO_3V3 which
allows the TPS65994AE device to be powered from VBUS when VIN_3V3 is unavailable. This LDO steps down
any recommended voltage on the PA_VBUS pin. When VBUS reaches 20 V, which is allowable by USB PD, the
internal circuitry of the TPS65994AE device operates without triggering thermal shutdown; however, a significant
external load on the LDO_3V3 pin or any GPIOx pin can increase temperature enough to trigger thermal
shutdown. Keep the total load on LDO_3V3 within the limits from the Recommended Operating Conditions in
the Specifications section. Connect the recommended capacitance CPx_VBUS (see Recommended Capacitance
in the Specifications section) from the VBUS pin to the GND pin.
10.2 1.5-V Power
The internal circuitry is powered from 1.5 V. The 1.5-V LDO steps the voltage down from LDO_3V3 to 1.5 V. The
1.5-V LDO provides power to all internal low-voltage digital circuits which includes the digital core, and memory.
The 1.5-V LDO also provides power to all internal low-voltage analog circuits. Connect the recommended
capacitance CLDO_1V5 (see the Recommended Capacitance in the Specifications section) from the LDO_1V5 pin
to the GND pin.
10.3 Recommended Supply Load Capacitance
The Recommended Capacitance in the Specifications section lists the recommended board capacitances for the
various supplies. The typical capacitance is the nominally rated capacitance that must be placed on the board as
close to the pin as possible. The maximum capacitance must not be exceeded on pins for which it is specified.
The minimum capacitance is minimum capacitance allowing for tolerances and voltage derating ensuring proper
operation.

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11 Layout
11.1 Layout Guidelines
Proper routing and placement will maintain signal integrity for high speed signals and improve the heat
dissipation from the power paths. The combination of power and high speed data signals are easily routed if the
following guidelines are followed. It is a best practice to consult with board manufacturing to verify manufacturing
capabilities.
11.1.1 Top TPS65994AE Placement and Bottom Component Placement and Layout
When the TPS65994AE is placed on top and its components on bottom the solution size will be at its smallest.
11.2 Layout Example
Follow the differential impedances for Super and High Speed signals defined by their specifications (DisplayPort
- AUXN/P and USB2.0). All I/O will be fanned out to provide an example for routing out all pins, not all designs
will utilize all of the I/O on the TPS65994AE.

Figure 11-1. Example Schematic

11.3 Component Placement

Top and bottom placement is used for this example to minimize solution size. The TPS65994AE is placed on
the top side of the board and the majority of its components are placed on the bottom side. When placing the
components on the bottom side, it is recommended that they are placed directly under the TPS65994AE. When
placing the VBUS and PPHV capacitors it is easiest to place them with the GND terminal of the capacitors to
face outward from the TPS65994AE or to the side since the drain connection pads on the bottom layer should
not be connected to anything and left floating. All other components that are for pins on the GND pad side of the
TPS65994AE should be placed where the GND terminal is underneath the GND pad.
The CC capacitors should be placed on the same side as the TPS65994AE close to the respective CC1 and
CC2 pins. Do NOT via to another layer in between the CC pins to the CC capacitor, placing a via after the CC
capacitor is recommended.

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The ADCIN1/2 voltage divider resistors can be placed where convenient. In this layout example they are placed
on the opposite layer of the TPS65994AE close to the LDO_3V3 pin to simplify routing.
The figures below show the placement in 2-D and 3-D.

Figure 11-3. Bottom View Layout (Flipped)

Figure 11-2. Top View Layout

Figure 11-4. Top View 3-D Figure 11-5. Bottom View 3-D

11.4 Routing PP_5V, VBUS, VIN_3V3, LDO_3V3, LDO_1V5

On the top side, create pours for PP_5V and VBUS1/2. Connect PP5V from the top layer to the bottom layer
using at least 7 8-mil hole and 16-mil diameter vias. See Figure 11-6 and Figure 11-7 for top and bottom layer via
placement and copper pours respectively.

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Figure 11-6. VBUS1 and VBUS2 Copper Pours and Via Placement (Top)

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Figure 11-7. PP5V Copper Pours and Via Placement (Bottom)

Next, VIN_3V3, LDO_3V3, and LDO_1V5 will be routed to their respective decoupling capacitors. This is
highlighted in Figure 8. Connect the bottom side VIN_3V3, LDO_1V5, and LDO_3V3 capacitors with traces
through a via. The vias should have a straight connection to the respective pins.
As shown in Figure 11-5 (3D view) these decoupling capacitors are in the bottom layer.

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Figure 11-8. VIN_3V3, LDO_3V3, and LDO_1V5 Routing

11.5 Routing CC and GPIO

Routing the CC lines with a 10-mil trace will ensure the needed current for supporting powered Type-C cables
through VCONN. For more information on VCONN refer to the Type-C specification. For capacitor GND pin use
a 16-mil trace if possible.
Most of the GPIO signals can be fanned out on the top or bottom layer using either a 6-mil trace or a 8-mil trace.
The following images highlight how the CC lines and GPIOs are routed out.

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Figure 11-9. Top Layer GPIO Routing

Table 11-1. Routing Widths

ROUTE WIDTH (mil minimum)
PA_CC1, PA_CC2, PB_CC1, PB_CC2 8
VIN_3V3, LDO_3V3, LDO_1V5 6
Component GND 10
GPIO 4

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12 Device and Documentation Support

12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
• USB-PD Specifications
• USB Power Delivery Specification
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
Thunderbolt™ is a trademark of Intel.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS65994AERSLR ACTIVE VQFN RSL 48 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS65994 Samples
AE

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Nov-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65994AERSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Nov-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65994AERSLR VQFN RSL 48 2500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RSL0048B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

6.1 A
B 5.9

PIN 1 INDEX AREA

6.1
5.9

1 MAX

SEATING PLANE
0.05 0.08 C
0.00
4.4
13 24
44X 0.4
12 23

49 SYMM
4.4 4.5
4.3

1 36
48X 0.25
0.15
PIN 1 IDENTIFICATION
48 37 0.1 C A B
(OPTIONAL)
SYMM
48X 0.5
0.3
0.05 C
4219205/A 02/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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 EXAMPLE BOARD LAYOUT
RSL0048B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

(5.8)

( 4.4)
SYMM

48 37
48X (0.6)
48X (0.2)
1
36

44X (0.4)

10X (1.12) 49 SYMM

(5.8)

6X (0.83) 12 25

(R0.05) TYP

13 24 (Ø0.2) VIA
6X (0.83) 10X (1.12) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 12X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND METAL UNDER
METAL
SOLDER MASK

EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK

OPENING METAL OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS 4219205/A 02/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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 EXAMPLE STENCIL DESIGN
RSL0048B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

(5.8)
SYMM

48 37
48X (0.6)
48X (0.2)
1 49
36

44X (0.4)
16X
( 0.92)

8X (0.56) SYMM
(5.8)

8X (1.12) 12 25

(R0.05) TYP

13 24
METAL TYP
8X (1.12) 8X (0.56)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
70% PRINTED COVERAGE BY AREA
SCALE: 12X

4219205/A 02/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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