CD4070B,

Data sheet acquired from Harris Semiconductor

CD4077B
SCHS055E
CMOS Quad Exclusive-OR
January 1998 - Revised September 2003 and Exclusive-NOR Gate

Features Ordering Information

• High-Voltage Types (20V Rating) TEMP. RANGE
• CD4070B - Quad Exclusive-OR Gate PART NUMBER (oC) PACKAGE
[ /Title
(CD40 • CD4077B - Quad Exclusive-NOR Gate CD4070BE -55 to 125 14 Ld PDIP
70B, • Medium Speed Operation
CD4070BF3A -55 to 125 14 Ld CERDIP
CD407 - tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
CD4070BM -55 to 125 14 Ld SOIC
7B) • 100% Tested for Quiescent Current at 20V
/Sub- • Standardized Symmetrical Output Characteristics CD4070BMT -55 to 125 14 Ld SOIC
ject • 5V, 10V and 15V Parametric Ratings CD4070BM96 -55 to 125 14 Ld SOIC
(CMO • Maximum Input Current of 1µA at 18V Over Full
S Quad Package Temperature Range CD4070BNSR -55 to 125 14 Ld SOP

Exclu- - 100nA at 18V and 25oC CD4070BPW -55 to 125 14 Ld TSSOP

sive- • Noise Margin (Over Full Package Temperature Range)
CD4070BPWR -55 to 125 14 Ld TSSOP
OR - 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
and • Meets All Requirements of JEDEC Standard No. 13B,
CD4077BE -55 to 125 14 Ld PDIP

Exclu- “Standard Specifications for Description of ‘B’ Series CD4077BF3A -55 to 125 14 Ld CERDIP
sive- CMOS Devices
CD4077BM -55 to 125 14 Ld SOIC
NOR
Gate) Applications CD4077BMT -55 to 125 14 Ld SOIC
/Autho • Logical Comparators
CD4077BM96 -55 to 125 14 Ld SOIC
r () • Adders/Subtractors
CD4077BNSR -55 to 125 14 Ld SOP
/Key- • Parity Generators and Checkers
words CD4077BPW -55 to 125 14 Ld TSSOP
(Har- Description CD4077BPWR -55 to 125 14 Ld TSSOP
ris The Harris CD4070B contains four independent Exclusive- NOTE: When ordering, use the entire part number. The suffixes 96
Semi- OR gates. The Harris CD4077B contains four independent and R denote tape and reel. The suffix T denotes a small-quantity
con- Exclusive-NOR gates. reel of 250.
ductor, The CD4070B and CD4077B provide the system designer
CD400 with a means for direct implementation of the Exclusive-OR
and Exclusive-NOR functions, respectively.
0,
metal
gate,
CMOS
, pdip,
cerdip,
mil,

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
 CD4070B, CD4077B

Pinouts
CD4070B CD4077B
(PDIP, CERDIP, SOIC, SOP, TSSOP) (PDIP, CERDIP, SOIC, SOP, TSSOP)
TOP VIEW TOP VIEW

A 1 14 VDD A 1 14 VDD

B 2 13 H B 2 13 H

J=A⊕B 3 12 G J=A⊕B 3 12 G

K=C⊕D 4 11 M = G ⊕ H K=C⊕D 4 11 M = G ⊕ H

C 5 10 L = E ⊕ F C 5 10 L = E ⊕ F

D 6 9 F D 6 9 F

VSS 7 8 E VSS 7 8 E

Functional Diagrams
CD4070B CD4077B

1 1
A 3 A 3
2 J 2 J
B
J=A⊕B B
K=C⊕D 5 J =A ⊕B 5
C 4
C
6
4
K K=C ⊕D 6 K
M=G⊕ H D D

L=E⊕F 8
E
8
10 M=G ⊕H E 10
9 L
=E⊕F
9 L
VSS = 7 F L F
VDD = 14 12 12
G 11 G 11
M 13 M
13 H
H

2
 CD4070B, CD4077B

VDD
VDD
VDD p
VDD p
B†
B† p
p 2(5,9,12) n
n n
2(5,9,12) n
n VSS p
VSS p p
p VDD J
VDD p J
p n 3(4,10,11)
n 3(4,10,11) A†
p n
A†
n 1(6,8,13) n
1(6,8,13) n
VSS
VDD VSS VDD
VSS VSS

† INPUTS PROTECTED † INPUTS PROTECTED

BY CMOS PROTECTION BY CMOS PROTECTION
NETWORK NETWORK

VSS VSS

FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B
(1 OF 4 IDENTICAL GATES) (1 OF 4 IDENTICAL GATES)

CD4070B TRUTH TABLE (1 OF 4 GATES) CD4077B TRUTH TABLE (1 OF 4 GATES)

A B J A B J

0 0 0 0 0 1

1 0 1 1 0 0

0 1 1 0 1 0

1 1 0 1 1 1

NOTE: NOTE:
1 = High Level 1 = High Level
0 = Low Level 0 = Low Level
J=A⊕B J=A⊕B

3
 CD4070B, CD4077B

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V Package Thermal Impedance, θJA (see Note 1):
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76oC/W
Operating Conditions PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W
Maximum Junction Temperature (Hermetic Package or Die) . 175oC
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
LIMITS AT INDICATED TEMPERATURES (oC)

CONDITIONS 25

VO VIN VDD
PARAMETER (V) (V) (V) -55 -40 85 125 MIN TYP MAX UNITS

Quiescent Device Current - 0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 µA

IDD Max
- 0, 10 10 0.5 0.5 15 15 - 0.01 0.5 µA

- 0, 15 15 1 1 30 30 - 0.01 1 µA

- 0, 20 20 5 5 150 150 - 0.02 5 µA

Output Low (Sink) Current 0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - mA
IOL Min
0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - mA

1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - mA

Output High (Source) Current 4.6 0, 5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
IOH Min
2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - mA

9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - mA

13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - mA

Output Voltage: Low Level, - 0, 5 5 0.05 0.05 0.05 0.05 - 0 0.05 V

VOL Max
- 0, 10 10 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0, 15 15 0.05 0.05 0.05 0.05 - 0 0.05 V

Output Voltage: High Level, - 0, 5 5 4.95 4.95 4.95 4.95 4.95 5 - V

VOH Min
- 0, 10 10 9.95 9.95 9.95 9.95 9.95 10 - V

- 0, 15 15 14.95 14.95 14.95 14.95 14.95 15 - V

Input Low Voltage, 0.5, 4.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V
VIL Max
1, 9 - 10 3 3 3 3 - - 3 V

1.5, 13.5 - 15 4 4 4 4 - - 4 V

Input High Voltage, 0.5, 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V
VIH Min
1, 9 - 10 7 7 7 7 7 - - V

1.5, 13.5 - 15 11 11 11 11 11 - - V

Input Current, IIN Max - 0, 18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 µA

4
 CD4070B, CD4077B

AC Electrical Specifications TA = 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ

TEST CONDITIONS LIMITS ON ALL TYPES

PARAMETER SYMBOL VDD (V) TYP MAX UNITS

Propagation Delay Time tPHL, tPLH 5 140 280 ns

10 65 130 ns

15 50 100 ns

Transition Time tTHL, tTLH 5 100 200 ns

10 50 100 ns

15 40 80 ns

Input Capacitance CIN Any Input 5 7.5 pF

Typical Performance Curves

TA = 25oC TA = 25oC
IOL, OUTPUT LOW (SINK) CURRENT (mA)

30 GATE TO SOURCE VOLTAGE (VGS) = 15V IOL, OUTPUT LOW (SINK) CURRENT (mA) 15
GATE TO SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10
10V 10V
15 7.5

10 5
5V 5V
5 2.5

0 0
0 5 10 15 0 5 10 15
VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS

VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)
-15 -10 -5 0
IOH, OUTPUT HIGH (SOURCE) CURRENT (mA)

-15 -10 -5 0
0 0
TA = 25oC
IOH, OUTPUT HIGH (SINK) CURRENT (mA)
TA = 25oC
-5
GATE TO SOURCE VOLTAGE (VGS) = -5V
GATE TO SOURCE VOLTAGE (VGS) = -5V
-10 -5
-15
-10V
-20
-10V -10
-25
-15V -30
-15V -15

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS

5
Typical Performance Curves (Continued)

tPHL, tPLH, PROPAGATION DELAY TIME (ns)

TA = 25oC
TA = 25oC
tTHL, tTLH, TRANSITION TIME (ns)

300
200
SUPPLY VOLTAGE (VDD) = 5V
150 200 SUPPLY VOLTAGE (VDD) = 5V

100 10V
100
50 15V 10V

15V
0 0
0 20 40 60 80 100 110 0 20 40 60 80 100
CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF)

FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
LOAD CAPACITANCE FUNCTION OF LOAD CAPACITANCE

105
tPHL, tPLH, PROPAGATION DELAY TIME (ns)

TA = 25oC TA = 25oC
LOAD CAPACITANCE CL = 50pF V
PD, POWER DISSIPATION (µW)

104 15
)=
300 D
E (V D 10V
103 AG
O LT CL = 50pF
YV
P PL
200
102 SU 10V
CL = 15pF

10 5V
100
1

0 10-1
0 5 10 15 20 10-1 1 10 102 103 104
VDD, SUPPLY VOLTAGE (V) fI, INPUT FREQUENCY (kHz)

FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF SUPPLY VOLTAGE FUNCTION OF INPUT FREQUENCY

6
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
CD4070BE ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4070BEE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4070BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD4070BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD4070BF3AS2534 OBSOLETE CDIP J 14 TBD Call TI Call TI
CD4070BM ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BM96 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BME4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BMG4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BMT ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BMTE4 ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BMTG4 ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BNSR ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BPW ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4070BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BE ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4077BEE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD4077BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD4077BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
CD4077BM ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BM96 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BME4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BMG4 ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BMT ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BMTE4 ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BMTG4 ACTIVE SOIC D 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BNSR ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BPW ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4077BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
JM38510/17203BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
CD4070BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4070BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4070BPWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
CD4077BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4077BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4077BPWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4070BM96 SOIC D 14 2500 346.0 346.0 33.0
CD4070BNSR SO NS 14 2000 346.0 346.0 33.0
CD4070BPWR TSSOP PW 14 2000 346.0 346.0 29.0
CD4077BM96 SOIC D 14 2500 346.0 346.0 33.0
CD4077BNSR SO NS 14 2000 346.0 346.0 33.0
CD4077BPWR TSSOP PW 14 2000 346.0 346.0 29.0

Pack Materials-Page 2
 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 1-May-2025

PACKAGING INFORMATION

Orderable Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
part number (1) (2) (3) Ball material Peak reflow (6)
(4) (5)

CD4070BE Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD4070BE
CD4070BF Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD4070BF
CD4070BF3A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD4070BF3A
CD4070BM Obsolete Production SOIC (D) | 14 - - Call TI Call TI -55 to 125 CD4070BM
CD4070BM96 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CD4070BM
CD4070BMT Obsolete Production SOIC (D) | 14 - - Call TI Call TI -55 to 125 CD4070BM
CD4070BNSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CD4070B
CD4070BPW Obsolete Production TSSOP (PW) | 14 - - Call TI Call TI -55 to 125 CM070B
CD4070BPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CM070B
CD4077BE Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD4077BE
CD4077BF Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD4077BF
CD4077BF3A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD4077BF3A
CD4077BM Obsolete Production SOIC (D) | 14 - - Call TI Call TI -55 to 125 CD4077BM
CD4077BM96 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CD4077BM
CD4077BMT Obsolete Production SOIC (D) | 14 - - Call TI Call TI -55 to 125 CD4077BM
CD4077BNSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CD4077B
CD4077BPW Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -55 to 125 CM077B
JM38510/17203BCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
17203BCA

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 1-May-2025

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD4070B, CD4070B-MIL, CD4077B, CD4077B-MIL :

• Catalog : CD4070B, CD4077B

• Military : CD4070B-MIL, CD4077B-MIL

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Apr-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD4070BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4070BNSR SOP NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4070BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4077BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4077BNSR SOP NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Apr-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4070BM96 SOIC D 14 2500 356.0 356.0 35.0
CD4070BNSR SOP NS 14 2000 356.0 356.0 35.0
CD4070BPWR TSSOP PW 14 2000 356.0 356.0 35.0
CD4077BM96 SOIC D 14 2500 356.0 356.0 35.0
CD4077BNSR SOP NS 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 23-Apr-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD4070BE N PDIP 14 25 506 13.97 11230 4.32
CD4070BEE4 N PDIP 14 25 506 13.97 11230 4.32
CD4077BE N PDIP 14 25 506 13.97 11230 4.32
CD4077BPW PW TSSOP 14 90 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1

2X
5.1 3.9
4.9
NOTE 3

4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220202/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220202/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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