MP7612

Octal 12-Bit DAC ArrayTM

D/A Converter with Output Amplifier
and Serial Data/Address
...the analog plus company TM µP Control Logic

FEATURES APPLICATIONS April 1996-4

• Eight Independent 12-Bit DACs with Output Amplifiers • Data Acquisition Systems
• Low Power 320 mW (typ.) • ATE
• Serial Digital Data and Address Port (3-Wire • Process Control
Standard) • Self-Diagnostic Systems
• 12-Bit Resolution, 11 Bit Accuracy • Logic Analyzers
• Extremely Well Matched DACs • Digital Storage Scopes
• Extremely Low Analog Ground Current (<60µA/Channel) • PC Based Controller/DAS
• +10 V Output Swing with +11.4 V Supplies
• Zero Volt Output Preset (Data = 10 .. 00)
• Rugged Construction – Latch-Up Free
• Parallel Version: MP7613

GENERAL DESCRIPTION sinking and sourcing 5mA, and the output voltage settles to
12-bits in less than 30µs (typ.).
The MP7612 is equipped with a serial data (3-wire standard)
The MP7612 provides eight independent 12-bit resolution
Digital-to-Analog Converters with voltage output amplifiers and µ-processor logic interface to reduce pin count, package size,
a 3-wire standard serial digital address and data port. and board space.
Built using an advanced linear BiCMOS, these devices offer
Typical DAC matching for B grade versions is 0.7 LSB across rugged solutions that are latch-up free, and take advantage of
all codes. Accuracy of +0.75 LSB for DNL and +1 LSB for INL is EXAR’s patented thin-film resistor process which exhibits excel-
also achieved for B grades. The output amplifier is capable of lent long term stability and reliability.

SIMPLIFIED BLOCK DIAGRAM

VRP VRP
– D Q 12
+ VRN DAC0 +
LAT0 – VO0
XR XE
VRN
RST
XE0
XE0 - XE7

LD
Not Used 8 VRP
12 8
12
4 to 16 Decoder D Q DAC7 VO7
+
LAT7 –
LAT XR XE
SDI D Q 4
VRN
EN
XE7
LD
EN D0 to D11 A0 to A3
CLK D Q Tri-State Buffer
LAT 16-Bit Shift Register SDO
VRP LD

VEE VEE VCC VCC AGND AGND VREF DGND DVDD

Rev. 3.00

1996
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538  (510) 668-7000  FAX (510) 668-7010
MP7612
ORDERING INFORMATION

Package Temperature Res. INL DNL FSE

Type Range Part No. (Bits) (LSB) (LSB) (LSB)

PLCC –40 to +85°C MP7612BP 12
1
0.75
6

PLCC –40 to +85°C MP7612AP 12
2
1
8
SOIC –40 to +85°C MP7612BS 12
1
0.75
6
SOIC –40 to +85°C MP7612AS 12
2
1
8

PIN CONFIGURATIONS

AGND 1 28 DGND
1
VO0 2 27 N/C
VO1 3 26 N/C
VO2 4 25 DVDD
VO3 5 24 DGND
VEE 6 23 N/C
See the following page for VCC 7 22 SDO
pin descriptions VREF 8 21 SDI
VCC 9 20 CLK
VEE 10 19 LD
VO4 11 18 N/C
VO5 12 17 RST
VO6 13 16 N/C
VO7 14 15 AGND

44 Pin PLCC 28 Pin SOIC (Jedec, 0.346”)

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 MP7612
PIN DESCRIPTION
SOIC PLCC
Pin # Pin # Symbol Description
1 2 AGND Analog Ground
2 3 VO0 DAC 0 Output
3 4 VO1 DAC 1 Output
4 5 VO2 DAC 2 Output
5 6 VO3 DAC 3 Output
6 7 VEE Analog Negative Power Supply (–12 V)
7 9 VCC Analog Positive Power Supply (+12 V)
8 12 VREF Voltage Reference Input (+5 V)
9 13 VCC Analog Positive Power Supply (+12 V)
10 15 VEE Analog Negative Power Supply (–12 V)
11 18 VO4 DAC 4 Output
12 19 VO5 DAC 5 Output
13 20 VO6 DAC 6 Output
14 21 VO7 DAC 7 Output
15 24 AGND Analog Ground
16 N/C No Connection
17 26 RST Reset all DACs to 0 V Output
18 N/C No Connection
19 29 LD Load Signal; Load Data to Selected DAC
20 31 CLK Serial Data Clock
21 32 SDI Serial Data Input
22 34 SDO Shift Register Serial Output
23 N/C No Connection
24 37 DGND Digital Ground
25 40 DVDD Digital Positive Power Supply (+5 V)
26 N/C No Connection
27 1, 8, 10, 11, 14, N/C No Connection
16, 17, 22, 23,
25, 27, 28, 30,
33, 35, 36, 38,
39, 41, 42, 43
28 44 DGND Digital Ground

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MP7612
ELECTRICAL CHARACTERISTICS
VCC = +12 V, VEE = –12 V, VREF = 5 V, DVDD = 5.0 V, T = 25°C, Output Load = 5kΩ (unless otherwise noted)

25°C Tmin to Tmax

Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments

STATIC PERFORMANCE

Resolution (All Grades) N 12 Bits

Integral Non-Linearity INL LSB End Point Linearity Spec

(Relative Accuracy)
A
2
2
B
1
1

Differential Non-Linearity DNL LSB

A
1
1
B
0.75
0.75

Positive Full Scale Error +FSE LSB

A 6
8
8
B 4
6
6

Negative Full Scale Error –FSE LSB

A 6
8
8
B 4
6
6

Bipolar Zero Offset ZOFS LSB

A
4
4
B
3
3

INL Matching ∆INL LSB

A
2
2
B
1.5
1.5

All Channels Maximum Error ME LSB

with DAC 0 adjusted to
minimum error
A
4
4
B
2
2

Bipolar Zero Matching ∆ZOFS LSB

A
4
4
B
3
3

Full Scale Error Matching FSE LSB

A
4
4
B
3
3

DYNAMIC PERFORMANCE

Voltage Settling from LD tsd 30 50 50 µsec ZS to FS (20 V Step)

to VDAC Out1
Channel-to-Channel Crosstalk1, 6 CT 0.04 LSB DC
Digital Feedthrough1, 6 Q –70 dB CLK and Data to VOUTi
Power Supply Rejection Ratio PSRR 5 ppm/% ∆VEE & ∆VCC = +5%, ppm of FS

REFERENCE INPUTS

Impedance of VREF REF 350 700 1.05k 350 1.05k Ω See Application Hints for driving
the reference input
VREF Voltage1, 2 VREF 3.5 6 V

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 MP7612
ELECTRICAL CHARACTERISTICS (CONT’D)

25°C Tmin to Tmax

Parameter Symbol Min Typ Max Min Max Units Test Conditions/Comments

DIGITAL INPUTS3

Logic High VIH 2.4 V

Logic Low VIL 0.8 V
Input Current IL +10 µA
Input Capacitance1 CL 8 pF

ANALOG OUTPUTS

Output Swing –VEE +1.4 VCC –1.4 V

Output Drive Current –5 5 mA
Output Impedance RO 1 Ω
Output Short Circuit Current ISC 25 mA +FS to AGND
30 mA +FS to VEE
40 mA –FS to AGND
55 mA –FS to VCC

DIGITAL OUTPUTS

Output High Voltage VOH 4.5 V

Output Low Voltage VOL 0.5 V

POWER SUPPLIES

VCC Voltage5 VCC VREF+1.5 12 12.75 VREF+1.5 12.75 V

VEE Voltage5 VEE –12.75 –12 –5 –12.75 –5 V
DVDD Voltage DVDD 4.5 5 5.5 4.5 5.5 V
Positive Supply Current ICC 8 10 10 mA Bipolar zero
Negative Supply Current IEE 15 20 20 mA Bipolar zero
Digital Supply Current IDD 2 2 mA Bipolar zero
Power Dissipation PDISS 320 420 450 mW Bipolar zero

ANALOG GROUND CURRENT

Per Channel1 IAGND ±60 µA See Application Notes

DIGITAL TIMING
SPECIFICATIONS1,4 VIL = 0, VIH = 5.0, CL = 20 pF

Input Clock Pulse Width tCH, tCL 35 ns

Data Setup Time tDS 15 ns
Data Hold Time tDH 15 ns
CLK to SDO Propagation Delay tPD 40 ns
DAC Register Load Pulse Width tLD 35 ns
Preset Pulse Width tPR 50 ns
Clock Edge to Load Time tCKLD1 140 ns Note: tLD and tCKLD2 cannot both
tCKLD2 0 be min. since tCKLD1=tCKLD2+tLD
LD Falling Edge to SDO tHZ1 50 ns
Tri-state Enable
LD Rising Edge to SDO tHZ2 50 ns
Tri-state Disable
LD Rising Edge to CLK Enable tLDCK 50 ns
LD Set-up Time with Respect tLDSU 30 ns
to CLK

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MP7612
ELECTRICAL CHARACTERISTICS (CONT’D)

NOTES:
1 Guaranteed; not tested.
2 Specified values guarantee functionality.
3 Digital inputs should not go below digital GND or exceed DVDD supply voltage.
4 See Figures 2 and 3. All digital input signals are specified with tR = tF = 10 ns 10% to 90% and timed from a 50% voltage level.
5 For power supply values < 2VREF, the output swing is limited as specified in Analog Outputs.
6 Digital feedthrough and channel-to-channel crosstalk are heavily dependent on the board layout and environment.

Specifications are subject to change without notice

ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2

VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . +16.5 V Analog Inputs & Outputs . . . . . . . Indefinite Shorts to
VCC, VEE, DVDD, AGND, DGND (provided that power
dissipation of the package spec is not exceeded)
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –16.5 V
Operating Temperature Range
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V Extended Industrial . . . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature . . . –65°C to 150°C
VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V Lead Temperature (Soldering, 10 sec) . . . . . +300°C
(Functionality guaranteed for 0.5 V only)
Package Power Dissipation Rating @ 75°C
Digital Input & Output Voltage to DGND –0.5 to DVDD SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . . . . 1150mW
+0.5V Derates above 75°C . . . . . . . . . . . . . . . . . 15mW/°C
NOTES:
1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100µs.

APPLICATION NOTES
Refer to Section 8 in the 1995 Data Acquisition products Databook for Applications Information
NOTE: When using these DACs to drive remote devices, the accuracy of the output can be improved by utilizing a remote analog
ground connection. The difference between the DGND and AGND should be limited to 300 mV to assure normal operation. If there
is any chance that the AGND to DGND can be greater than 1 V, we recommend two back-to-back diodes be used between DGND
and AGND to clamp the voltage and prevent damage to the DAC. Using a buffer between the remote ground location and AGND may
help reduce noise induced from long lead or trace lengths.

Rev. 3.00
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 MP7612
MSB
SDI 1
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D0
(Data In) 0

1
CLK
0

1
LD
0
DAC Register
Loaded
1
SDO Previous Data A3 (1)
0

VOUT

Notes: (1) Because A3 is available immediately after 16th clock edge of DATA Shift-in, only 15 clock cycles are needed to
complete the readback.

Figure 1. Serial Data Timing and Loading

tDS
1
SDI
0
tDH tHZ1 tHZ2
1 HIGH Z
SDO
0
tCH tPD tLDSU tLDCK
1
CLK
0 tCKLD2
tCL tCKLD1
1
LD
0
tLD
+FS
VOUT
–FS tSD
+1/2 LSB Band
Notes: (1) CLK should be high during the falling edge of LD to insure proper function of the shift register.

Figure 2. Serial Data Input Timing (RST = “1”)

tPR
RST 1
0

VOUT
VOUT = 0 V

Note: Reset settling time is <tSD +1/2 LSB Error Band

Figure 3. Reset Operation

Rev. 3.00
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MP7612
The MP7612 is equipped with a serial data (3-wire standard) The LD signal going low also disables the serial data (SDI), out-
µ-processor logic interface to reduce pin count, package size, put (SDO 3-stated) and the CLK input. This design tremen-
and board wire (space). If the LD signal is high, the CLK signal dously reduces digital noise and glitch transients into the DACs
loads the digital input bits (SDI) into the shift register (4 bits ad- due to free running CLK and SDI. Note also that the preset sig-
dress A3 to A0 plus 12 bits data DB11 to DB0 for the MP7612). nal (RST) resets all analog outputs to 0 volt regardless of digital
The LD signal going low loads the data into the selected DAC. inputs.

Function A3 A2 A1 A0 LD CLK RST SDI SDO

Shift Data In X X X X 1 0→1 1 Data Input Data Output

and Out Repeat Valid Valid
Stop Shifting X X X X 0 X 1 X Hi-Z
Data In and
Out
Load DACs
0 0 0 0 No Operation
DAC 0 0 0 0 1 1→0 X 1 X Hi-Z
DAC 1 0 0 1 0 1→0 X 1 X Hi-Z
DAC 2 0 0 1 1 1→0 X 1 X Hi-Z
DAC 3 0 1 0 0 1→0 X 1 X Hi-Z
DAC 4 0 1 0 1 1→0 X 1 X Hi-Z
DAC 5 0 1 1 0 1→0 X 1 X Hi-Z
DAC 6 0 1 1 1 1→0 X 1 X Hi-Z
DAC 7 1 0 0 0 1→0 X 1 X Hi-Z
No Operation X
X
X
1 1 1 0 No Operation X 1 X Hi-Z
1 1 1 1 No Operation X 1 X Hi-Z

Reset all DACs X X X X X X 0 X X

to 0 V

Table 1. Digital Function Truth Table

Serial In/Serial Out
Note: For timing information see Electrical Characteristics

Rev. 3.00
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 MP7612
Output Voltage = 2 • Vr (–1 + 2•D )
Hex Code Binary Code (Vr = +5 V) 4096

000 000000000000 10 • (–1 + 0) = –10

4094
7FF 011111111111 10 • (–1 + ) = –4.88 mV
4096

800 100000000000 10 • (–1 + 4096 ) = 0

4096

801 100000000001 10 • (–1 + 4098 ) = 4.88 mV

4096

FFF 111111111111 10 • (–1 + 8190 ) = 9.99512

4096

Table 2. MP7612
Ideal DAC Output vs. Input Code

Note: See Electrical Characteristics for real system accuracy

SERIAL INTERFACE DIAGRAMS

Rev. 3.00
9
MP7612
VRI1 VOI1 VRI2 VOI2 VRIn VOIn
1 8 1 8 1 8

IC(1) IC(2) IC(n)

µPC SDI LD SDO SDI LD SDO SDI LD SDO

Data

LD
CLK

Figure 4. Simplified Diagram

VRI1 VOI1 VRI2 VOI2 VRIm VOIm

1 8 1 8 1 8

IC(1) IC(2) IC(n)

µPC SDI LD SDO SDI LD SDO SDI LD SDO

Data Out
Data
n #1 #2 #n
CS or LD
CLK

Figure 5. Simplified Diagram

VRI1 VOI1 VRI2 VOI2 VRIn VOIn

1
Decoder
Address

SDO 2
n
Address IC(1) IC(2) IC(n)

µPC 2n SDI LD SDO1 SDI LD SDO2 SDI LD SDOm

WR
(SDI) Data In
CLK

Figure 6. Simplified Diagram

Rev. 3.00
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 MP7612
16 16 Address Bus
A0 to A15
3

E1 A0 to A2
MC6800 74LS138
02 E3 Address
Decoder
R/W E2

8 8 Data Bus
DBO to DB7

LD CLK
DB7
SDI
RST

From SYSTEM RESET

NOTES
1. Execute consecutive memory write instructions while manipulating the data between WRITEs so that each
WRITE presents the next bit.
2. The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE to
memory location 2000, R/W, and 02. A WRITE to address 4000 transfers data from input shift register to DAC
register.

Figure 7. MC6800 Interface

8 Address Bus
8 3
8085
E1 A0 to A2
ALE 8212 +5
74LS138
E3 Address
Decoder
WR E2

8 Data Bus

SOD

LD CLK
SDI
RST

From SYSTEM RESET

NOTES:
1. Clock generated by WR and decoding address 8000.
2. Data is clocked in the DAC shift register by executing memory write instructions. The clock input is generated
by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory write instruction
to address 4000.
3. Serial data must be present in the right justified format in registers H & L of the microprocessor.

Figure 8. 8085 Interface

Rev. 3.00
11
MP7612
PERFORMANCE CHARACTERISTICS

11 V

0V

–11 V
VOUT
2.5mV

0V

–2.5mV
VOUT Settling 50µs/Division

Graph 1. Typical Output Settling Characteristic

VREF = 5 V, RL = 5K, CL = 500pF

Graph 1 shows the typical output settling characteristic of the MP7610 Family for a RESET !ZS!FS!ZS series
of code transitions. The top graph shows the output voltage transients, while the bottom graph shows the differ-
ence between the output and the ideal output.

Graph 2. Linearity with

VREF = 5 V, All DACs, All Codes

Rev. 3.00
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 MP7612

Graph 3. DAC 0 INL vs. VREF Graph 4. DAC 0 DNL vs. VREF

Graph 5. DAC 0 Linearity with Graph 6. DAC 0 Linearity with

VREF = 5 V, VOUT =
10 VREF = 4.5 V, VOUT =
9

Graph 7. DAC 0 Linearity with Graph 8. DAC 0 Linearity with

VREF = 4 V, VOUT =
8 VREF = 3.5 V, VOUT =
7

Rev. 3.00
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MP7612

VOUT 50
VO

MP7610 5k 500pF CL I
Family 2mA

CL = 500pF, 5nF, 50nF, 500nF

Figure 9. Circuit for Determining Typical Analog Output Pulse Response

2.0mA

0.0

400mV

VO

–400mV

200mV
CL = 500pF
CL = 5nF CL = 50nF CL = 500nF
VOUT

–200mV
0s 1.0µs 2.0µs 3.0µs 4.0µs 5.0µs 6.0µs

Graph 9. Typical Response of the MP7610 Family Analog Output to

a Current Pulse with CL=500pF, 5nF, 50nF, 500nF
(See Figure 9. above)

Rev. 3.00
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 MP7612

44 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC)

D C
Seating Plane
D1 45° x H1
45° x H2 A2

2 1 44

B1

D D1 B D
D3 2

R
D3
A1
A

INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX

A 0.165 0.180 4.19 4.57

A1 0.090 0.120 2.29 3.05
A2 0.020 –––. 0.51 –––
B 0.013 0.021 0.33 0.53
B1 0.026 0.032 0.66 0.81
C 0.008 0.013 0.19 0.32
D 0.685 0.695 17.40 17.65
D1 0.650 0.656 16.51 16.66
D2 0.590 0.630 14.99 16.00
D3 0.500 typ. 12.70 typ.
e 0.050 BSC 1.27 BSC
H1 0.042 0.056 1.07 1.42
H2 0.042 0.048 1.07 1.22
R 0.025 0.045 0.64 1.14

Note: The control dimension is the inch column

Rev. 3.00
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MP7612

28 LEAD SMALL OUTLINE

(350 MIL JEDEC SOIC)

28 15

E H

1
14

C
A
Seating
Plane α
e B
A1

INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX

A 0.093 0.104 2.35 2.65

A1 0.004 0.012 0.10 0.30
B 0.013 0.020 0.33 0.51
C 0.009 0.013 0.23 0.32
D 0.706 0.718 17.93 18.24
E 0.340 0.350 8.64 8.89
e 0.050 BSC 1.27 BSC
H 0.460 0.485 11.68 12.32
L 0.016 0.050 0.40 1.27

α 0° 8° 0° 8°
Note: The control dimension is the millimeter column

Rev. 3.00
16
 MP7612

Notes

Rev. 3.00
17
MP7612

Notes

Rev. 3.00
18
 MP7612

Notes

Rev. 3.00
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MP7612

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.

Copyright 1993 EXAR Corporation

Datasheet April 1996
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Rev. 3.00
20