a 16-Bit High Speed

Current-Output DAC
DAC16
FEATURES FUNCTIONAL BLOCK DIAGRAM
ⴞ1 LSB Differential Linearity (max)
Guaranteed Monotonic Over Temperature Range IREF
BUFFER DAC16
ⴞ2 LSB Integral Linearity (max)
500 ns Settling Time REF GND
CCOMP

5 mA Full-Scale Output VCC

TTL/CMOS Compatible AGND DAC IOUT
VEE
Low Power: 190 mW (typ)
DGND
Available in Die Form
DB0 (LSB) DB15 (MSB)

TE
APPLICATIONS
Communications
ATE
Data Acquisition Systems
High Resolution Displays

GENERAL DESCRIPTION LE
The DAC16 is a 16-bit high speed current-output digital-to-
analog converter with a settling time of 500 ns. A unique com-
bination of low distortion, high signal-to-noise ratio, and high
speed make the DAC16 ideally suited to performing waveform
PERCENT OF FULL-SCALE – %
0.1

VLOGIC = +5V
TURNING OFF

VLOGIC = 0V
TURNING ON
synthesis and modulation in communications, instrumentation,
and ATE systems. Input reference current is buffered, with full- 0.01
SO
scale output current of 5 mA. The 16-bit parallel digital input
bus is TTL/CMOS compatible. Operating from +5 V and
–15 V supplies, the DAC16 consumes 190 mW (typ) and is
available in a 24-lead epoxy DIP, epoxy surface-mount small IFS = 4mA
TA = 258C
outline (SOL), and in die form.

0.001
0 100 200 300 400 500 600 700 800
SETTLING TIME – ns

Figure 1. DAC16 Settling Time Accuracy vs. Percent of

B

Full Scale
O

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
DAC16–SPECIFICATIONS(@ V = +5.0 V, VEE = –15.0 V, IREF = 0.5 mA, CCOMP = 47 ␮F, TA = Full Operating Tem-
CC
ELECTRICAL CHARACTERISTICS perature Range unless otherwise noted. See Note 1 for supply variations.)
Parameter Conditions Min Typ Max Units

Integral Linearity “G” INL TA = +25°C –2 ± 1.2 +2 LSB

Integral Linearity “G” INL –4 ± 1.6 +4 LSB
Differential Linearity “G” DNL TA = +25°C –1 ± 0.5 +1 LSB
Differential Linearity “G” DNL –1 ± 0.7 +1.5 LSB
Integral Linearity “F” INL TA = +25°C –4 ± 1.4 +4 LSB
Integral Linearity “F” INL –6 ±2 +6 LSB
Differential Linearity “F” DNL TA = +25°C –1 ± 0.5 +1.5 LSB
Differential Linearity “F” DNL –1.5 ± 0.6 +2 LSB
Zero Scale Error ZSE 1 LSB
Zero Scale Drift TCZSE 0.025 ppm/°C
Gain Error GE ± 0.225 % FS
Gain Drift TCGE 5 ppm/°C

TE
REFERENCE2
Reference Input Current IREF Note 2 350 625 µA
OUTPUT CHARACTERISTICS
Output Current IOUT Note 2 2.8 5.0 mA
Output Capacitance COUT 10 pF
Settling Time tS 0.003% of Full Scale 500 ns
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Logic Input Current
VINH
VINL
IINH
IINH
LE
TA = +25°C
TA = +25°C
VIN = 5.0 V, DB0–DB10
VIN = 5.0 V, DB11–DB15
2.4
0.8
7.5
100
V
V
µA
µA
Logic Input Current IINL VIN = 0 V, DB0–DB15 1 µA
Input Capacitance CIN 8 pF
SO
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSS VCC = 4.5 V to 5.5 V, VEE = –13 V to –17 V 20 ppm/V
Positive Supply Current ICC All Bits HIGH 15 22 mA
Positive Supply Current ICC All Bits LOW 6 7.5 mA
Negative Supply Current IEE 7.5 10 mA
Power Dissipation PDISS 188 260 mW
NOTES
1
All supplies can be varied ± 5% and operation is guaranteed. Device is tested with nominal supplies.
B

2
Operation is guaranteed over this reference range, but linearity is neither tested not guaranteed (see Figures 7 and 8).
Specifications subject to change without notice.

WAFER TEST LIMITS (@ V CC = +5.0 V, VEE = –15.0 V, IREF = 0.5 mA, CCOMP = 47 ␮F, TA = +25ⴗC unless otherwise noted.)
O

DAC16G
Parameter Symbol Conditions Limit Units

Integral Nonlinearity INL ±3 LSB max

Differential Nonlinearity DNL ±1 LSB max
Zero Scale Error ZSE ±1 LSB max
Gain Error GE ± 12 % FS max
Logic Input High Voltage VINH 2.4 V min
Logic Input Low Voltage VINL 0.8 V max
Logic Input Current IIN 75 µA max
Positive Supply Current ICC 20 mA max
Negative Supply Current IEE 10 mA max
Power Dissipation PDISS 250 mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

–2– REV. B
 DAC16
ABSOLUTE MAXIMUM RATINGS CAUTION
(TA = +25°C unless otherwise noted) 1. Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +25.0 V
stress rating only and functional operation at or above this
VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7.0 V
specification is not implied. Exposure to the above maximum
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –18.0 V
rating conditions for extended periods may affect device
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +0.3 V
reliability.
REF GND to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +1.0 V
IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA 2. Digital inputs and outputs are protected; however, perma-
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 8 mA nent damage may occur on unprotected units from high en-
Digital Input Voltage to DGND . . . . . . . . . . . . . . . . . . . ≤VCC ergy electrostatic fields. Keep units in conductive foam or
Operating Temperature Range packaging at all times until ready to use. Use proper anti-
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C static handling procedures.
GS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C 3. Remove power before inserting or removing units from their
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C sockets.
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

TE
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW PIN CONFIGURATION
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C 24-Lead DIP (P, S)
Package Type θJA1 θJC Units
IREF 1 24 CCOMP
24-Lead Plastic DIP (P) 62 32 °C/W DGND 2 23 IOUT
24-Lead Plastic SOL (S) 70 22 °C/W VCC 3 22 AGND

NOTE DB15 (MSB) 4 21 REF GND

1

device in socket.

DICE CHARACTERISTICS
VCC DGND IREF CCOMP IOUT AGND
LE
θJA is specified for worst case mounting conditions, i.e., θJA is specified for DB14 5
DB13 6
DB12 7
DB11 8
DB10 9
DAC16
20

17

16
VEE

TOP VIEW 19 DB0 (LSB)

(Not to Scale) 18 DB1

DB2
DB3
DB9 10 15 DB4
DB8 11 14 DB5
REF GND
SO
DB7 12 13 DB6
DB15 (MSB)
VEE

DB14 DB0 (LSB)

PIN DESCRIPTION
DB13 Pin
DB12
(P, S) Name Description
DB1 1 IREF Reference Current Input
DB11
DB2 2 DGND Digital Ground
B

DB10
3 VCC +5 V Digital Supply
DB3 4–19 DB15–DB0 16-Bit Digital Input Bus. DB15 is the MSB.
20 VEE –15 V Analog Supply
DB9 DB8 DB7 DB6 DB5 DB4
21 REF GND Reference Current Return
O

Die Size 0.129 x 0.153 inch, 19,737 sq. mils 22 AGND Analog Ground/Output Reference
(3.277 x 3.886 mm, 12.73 sq. mm) 23 IOUT Current Output
The DAC16 Contains 330 Transistors. 24 CCOMP Current Ladder Compensation
Substrate is VEE Polarity.

ORDERING GUIDE

Model Grade DNL (max) Temperature Ranges Package Descriptions Package Options

DAC16GS ±1 0°C to +70°C 24-Lead SOL R-24

DAC16FP ±2 –40°C to +85°C 24-Lead PDIP N-24
DAC16FS ±2 –40°C to +85°C 24-Lead SOL R-24
DAC16GBC ±1 +25°C Die

REV. B –3–
DAC16
+5V minimizing the deleterious effects of digital feedthrough
10kV
while allowing the user to tailor the digital interface to
1 24 NC the speed requirements and bus configuration of the
2 23 application.
3 22
Equivalent Circuit Analysis
4 21
An equivalent circuit for static operation of the DAC16 is
5 20 –15V
illustrated in Figure 4. IREF is the current applied to the
6 19
DAC16 and is set externally to the device by VREF and
7 18
RREF. The output capacitance of the DAC16 is approxi-
8 17
mately 10 pF and is code independent. Its output resis-
9 16
tance RO is code dependent and is given by:
10 15

11 14

12
1 = 1 + DB9 + DB10 + X
13
RO 8 kΩ 288 kΩ 144 kΩ 72 kΩ
where
Figure 2. Burn-In Diagram

TE
DB9 = State of Data Bit 9 = 0 or 1;
OPERATION DB10 = State of Data Bit 10 = 0 or 1; and
Novel DAC Architecture
The DAC16 was designed with a compound DAC architecture X = Decimal representation of the 5 MSBs (DB11–DB15)
to achieve high accuracy, excellent linearity, and low transition = 0 to 31.
errors. As shown in Figure 3, the DAC’s five most-significant IOUT
bits utilize 31 identical segmented current sources to obtain

LE
optimal high speed settling at major code transitions. The lower
nine bits utilize an inverted R-2R ladder network which is laser-
trimmed to ensure excellent differential nonlinearity. The middle
two bits (DB9 and DB10) arc binary-weighted and scaled from
the MSB segments. Note that the flow of output current is into
IDAC RO CO IOUT = 8 • IREF
RO = SEE TEXT
CO = 10pF

Figure 4. Equivalent Circuit for the DAC16

65,535 Digital Code
65,536

the DAC16—there is no signal inversion. As shown, the switches Table I provides the relationship between the input digital
for each current source are essentially diodes. It is for this rea- code and the output resistance of the DAC16.
son that the output voltage compliance of the DAC16 is limited
SO
to a few millivolts. The DAC16 was designed to operate with an Table I. DAC16 Output Resistance vs. Digital Code
operational amplifier configured as an I–V converter; therefore,
the DAC16’s output must be connected to the sum node of an Hex Digital Code Scale Output Resistance
operational amplifier for proper operation. Exceeding the output
FFFF Zero 8 kΩ
voltage compliance of the DAC16 will introduce linearity errors.
BFFF 1/4 4.2 kΩ
The reference current buffer assures full accuracy and fast set-
7FFF 1/2 2.9 kΩ
tling by controlling the MSB reference node. The 16-bit paral-
3FFF 3/4 2.2 kΩ
lel digital input is TTL/CMOS compatible and unbuffered,
0 Full – 1 LSB 1.8 kΩ
B

IOUT
O

DB0 – DB8
AGND

DB11 – DB15 DB10 DB9 8kV 8kV 4kV

4kV 4kV 4kV 4kV DB0 – DB15
SWITCH DETAIL
18kV SW SW SW SW SW10 SW9 SW8 SW7 SW6 SW0
IREF +5V

FROM
SWITCH
DECODER
31 CURRENT SOURCES 62.5mA 31.25mA 9 CURRENT SOURCES
125mA EACH 15.63mA EACH

CCOMP

Figure 3. DAC16 Architecture

–4– REV. B
 Typical Performance Characteristics–DAC16
Digital Input Considerations This input capacitance can be used in conjunction with an ex-
The threshold of the DAC16’s digital input circuitry is set at ternal R-C circuit for digital signal deskewing, if required. In
1.4 V, independent of supply voltage. Hence, the digital inputs applications where some of the DAC16’s digital inputs are
can interface with any type of 5 V logic. Illustrated in Figure 5 is not used, the recommended procedure to turn off one or more
the equivalent circuit of the digital inputs. Note that the indi- inputs is to connect each input line to +5 V as shown in
vidual input capacitance is approximately 7 pF. Figure 6.
+5V +0.7V
+5V
R2
DBX Q1 75kV DAC16

Q2 Q3 DB0
R1 TO DAC
20kV SWITCH DB1
R3
28kV

–15V –0.7V

Figure 5. Equivalent Circuit of a DAC16 Digital Input Figure 6. Handling Unused DAC16 Digital Inputs

TE
4 2.0 1.0
VCC = +5V VCC = +5V
DIFFERENTIAL NONLINEARITY – LSB

3 VEE = –15V 1.5 VEE = –15V

INTEGRAL NONLINEARITY – LSB

VCC = +5V
2
TA = +258C
LE 1.0
TA = +258C 0.8 VEE = –15V
IREF = 0.5mA

ZERO SCALE – LSB

1 +INL 0.5
+DNL 0.6
0 0

–1 –0.5 0.4
–INL
–DNL
–2 –1.0
0.2
SO
–3 –1.5

–4 –2.0 0
0.2 0.3 0.4 0.5 0.6 0.7 0.2 0.3 0.4 0.5 0.6 0.7 –40 –20 0 20 40 60 80
REFERENCE CURRENT – mA REFERENCE CURRENT – mA TEMPERATURE – 8C

Figure 7. Integral Nonlinearity vs. IREF Figure 8. Differential Nonlinearity Figure 9. Zero Scale Output vs.
vs. IREF Temperature
B

15 4 1.5
VCC = +5V
DIFFERENTIAL NONLINEARITY – LSB

VCC = +5V
INTEGRAL NONLINEARITY – LSB

10 VEE = –15V 1.0 VEE = –15V

+INL
IREF = 0.5mA IREF = 0.5mA
2
GAIN ERROR – LSB

5 0.5
+DNL
–INL
0 0 0

–5 –0.5
VCC = +5V
–2 VEE = –15V –DNL
–10 IREF = 0.5mA –1.0

–15 –4 –1.5
–40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80
TEMPERATURE – 8C TEMPERATURE – 8C TEMPERATURE – 8C

Figure 10. Gain Error vs. Figure 11. Integral Nonlinearity Figure 12. Differential Nonlinearity
Temperature vs. Temperature vs. Temperature

REV. B –5–
DAC16–Typical Performance Characteristics
20 20 50

VEE = –15V VCC = +5V

ICC, LOGIC BITS = HIGH
VCC = +5V VEE = –15V
40

LOGIC BIT CURRENT – mA

SUPPLY CURRENT – mA

15 15 TA = +258C VIN = +5V

DB0 – DB4

30

I CC – mA
10 10
IEE , LOGIC BITS = LOW
20
IEE , LOGIC BITS = HIGH
5 5
10

ICC, LOGIC BITS = LOW DB5 – DB15

0 0 0
–40 –20 0 20 40 60 80 0 1 2 3 4 5 –40 –20 0 20 40 60 80
TEMPERATURE – 8C LOGIC INPUT VOLTAGE – V TEMPERATURE – 8C
ALL DATA BITS

Figure 13. Supply Current vs. Figure 14. VCC Supply Current vs. Figure 15. Digital Input Current vs.
Temperature Logic Input Voltage, All Data Bits Temperature

TE
1.5 6
130
VCC = +5V, VEE = –15V WORST CASE + INL VCC = +5V, VEE = –15V
5
DIFFERENTIAL NONLINEARITY – LSB

TA = +258C, IREF = 0.5mA TA = +258C, IREF = 0.5mA

INTEGRAL NONLINEARITY – LSB

1.0 4 120
WORST CASE + DNL WORST CASE
3 + GAIN ERROR

GAIN ERROR – LSB

0.5 TYPICAL + INL 110
TYPICAL + DNL 2

–0.5

–1.0
0

TYPICAL – DNL
1

–1

–2
LE TYPICAL – INL

WORST CASE – INL

VCC = +5V, VEE = –15V

–10

–20
0
TYPICAL
GAIN ERROR

WORST CASE
WORST CASE – DNL –3 – GAIN ERROR
TA = +258C, IREF = 0.5mA
–1.5 –4 –30
0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
SO
0 200 400 600 800 1000 1200
BURN-IN TIME – Hours BURN-IN TIME – Hours BURN-IN TIME – Hours

Figure 16. Differential Nonlinearity Figure 17. Integral Nonlinearity vs Figure 18. Gain Error vs. Time
vs. Time Accelerated by Burn-In Time Accelerated by Burn-In Accelerated by Burn-In

APPLICATIONS The DAC16 includes two ground connections in order to mini-

mize system accuracy degradation arising from grounding er-
B

Power Supplies, Bypassing, and Grounding

All precision converter products require careful application of rors. The two ground pins are designated DGND (Pin 2) and
good grounding practices to maintain full-rated performance. As AGND (Pin 22). The DGND pin is the return for the digital
is always the case with analog circuits operating in digital envi- circuit sections of the DAC and serves as their input threshold
ronments, digital noise is prevalent; therefore, special care must reference point. Thus, DGND should be connected to the same
O

be taken to ensure that the DAC16’s inherent precision is main- ground as the circuitry that drives the digital inputs.
tained. This means that particularly good engineering judgment Pin 22, AGND, serves as the reference point for the 9-bit
should be exercised when addressing the power supply, ground- lower-order DAC as well as the common for the reference am-
ing, and bypassing issues using the DAC16. plifier, REFGND (Pin 21). This pin should also serve as the
The DAC16 was designed to operate from +5 V and –15 V reference point for all analog circuitry associated with the
supplies. The +5 V supply primarily powers the digital portion DAC16. Therefore, to minimize any errors, it is recommended
of the DAC16 and can consume 20 mA, maximum. Although that AGND connection on the DAC16 be connected to a high
very little +5 V supply current is used by the reference amplifier, quality analog ground. If the system contains any analog signal
large amounts of digital noise present on the +5 V supply can path carrying a significant amount of current, then that path
introduce analog errors. It is, therefore, very important that the should have its own return connection to Pin 22.
+5 V supply be well filtered and regulated. The –15 V supply It is often advisable to maintain separate analog and digital
provides most of the current for the reference amplifier and all grounds throughout a complete system, tying them common to
of the current for the internal DAC. Although the maximum one place only. If the common tie point is remote and an acci-
current in this supply is 10 mA, it must provide a low imped- dental disconnection of that one common tie point were to oc-
ance path for the DAC switch currents. Therefore, it too must cur due to card removal with power on, a large differential
be well filtered and regulated. voltage between the two commons could develop. To protect
devices that interface to both digital and analog parts of the

–6– REV. B
 DAC16
system, such as the DAC16, it is recommended that common +5V
10mF
ground tie points be provided at each such device. If only one
system ground can be connected directly to the DAC16, it is
recommended that the analog common be used. If the system’s FB
0.1mF
AGND has suitable low impedance, then the digital signal cur-
rents flowing in it should not seriously affect the ground noise.
The amount of digital noise introduced by connecting the two VCC
DAC16
grounds together at the device will not adversely affect system VEE AGND
performance due to loss of digital noise immunity.
0.1mF
Generous bypassing of the DAC’s supplies goes a long way in
reducing supply-line induced errors. Even with well-filtered, FB
10mF
well-regulated supplies, local bypassing consisting of 10 µF tan-
talum electrolytic shunted by a 0.1 µF ceramic is recommended.
–15V
The decoupling capacitors should be connected between the
DAC’s supply pins (Pin 3 for +5 V, Pin 20 for –15 V) and Figure 20. Using a Ferrite Bead as a High Frequency Filter

TE
the analog ground (Pin 22). Figure 19 shows how the DGND,
Reference Amplifier Considerations
AGND, and bypass connections should be made to the DAC16.
The reference input current buffer is a high performance ampli-
+5V DB0 – DB15 fier optimized for high accuracy and linearity. The design of the
reference amplifier ensures fast settling times by tightly control-
ling the node common to all the current sources internal to the
10mF VCC
DAC16 DAC with an external compensation capacitor (CCOMP). Since
0.1mF IOUT
AGND DGND VEE the primary design goal of the DAC16 is to achieve 16-bit per-

TO OTHER TO
0.1mF

10mF

–15V
LE formance, proper operation of the reference amplifier requires a
47 µF tantalum electrolytic capacitor shunted by a 0.1 µF
ceramic capacitor, as shown in Figure 21. Increasing the capaci-
tance at this node above the recommended values does not fur-
ther reduce the analog transition current noise spikes at the
ANALOG POWER
CIRCUITS GROUND output of the reference amplifier. Reducing the value of com-
pensation, however, is not recommended as DAC linearity will
Figure 19. Recommended Grounding and Bypassing
SO
degrade as a result. In most systems, the VEE supply offers suffi-
Scheme for the DAC16 ciently low impedance to maintain a quiet return point for the
Using the Right Capacitors reference amplifier. If this is not the case, the AGND point can
Probably the most important external components associated also be used for the compensation capacitor return, as shown in
with high speed design are the capacitors used to bypass the Figure 21.
power supplies and to provide compensation. Both selection
and placement of these capacitors can be critical and, to a large CCOMP DAC16
IOUT
extent, dependent upon the specifics of the system configura- 0.1mF VEE AGND
tion. The dominant consideration in selection of bypass and
B

47mF
compensation capacitors for the DAC16 is minimization of se-
ries resistance and inductance. Many capacitors begin to look –15V
inductive at 20 MHz and above—the very frequencies where re-
jection of interference is needed. Ceramic and film-type capaci- Figure 21a. Recommended Compensation Scheme to VEE
O

tors generally feature lower series inductance than tantalum or

electrolytic types. A few general rules are of universal use when
approaching the issue of compensation or bypassing. CCOMP DAC16
IOUT
0.1mF AGND
Bypass capacitors should be installed on the printed circuit 47mF
board with the shortest possible leads consistent with reliable
construction. This helps to minimize series inductance in the
leads. Chip capacitors are optimal in this respect. Where illus- Figure 21b. Recommended Compensation Scheme to AGND
trated in the applications section, large tantalum electrolytic
capacitors are shunted by low self-inductance ceramic capaci- In applications where 16-bit multiplying performance is
tors. This technique reduces the self-resonance of the electrolytic required, the DAC16 might appear to be a viable solution.
while shifting the resonant frequency of the ceramics out-of-band. However, the compensation capacitor network would have to
be removed in these applications. The DAC16’s reference am-
Some series inductance between the DAC supply pins and the plifier was specifically designed for low frequency operation,
power supply plane often helps to filter out high frequency with a compensation capacitor network. In fact, this network
power supply noise. This inductance can be generated using a serves not only as a charge reservoir for the DAC’s internal
small ferrite bead as shown in Figure 20. current sources but also as a wideband noise filter for the

REV. B –7–
DAC16
reference amplifier. Completely removing the compensation thermally well-matched. Thin-film resistor networks work well
network would introduce large linearity errors, reference amplifier here. In this circuit, the parallel combination of R1 and R2
instability, wideband reference amplifier noise, and poor settling forms a 3 Hz low-pass filter with C1. The only noise source that
time. remains is the thermal noise of R2 which can be a significantly
Because the DAC exhibits an internal current scaling factor of lower noise generator than the voltage reference.
eight times (8×), the reference amplifier requires only 500 µA Input Coding
input current from the user-supplied precision reference for a The unipolar digital input coding of the DAC16 employs nega-
4 mA full-scale output current. In applications that do not re- tive logic to control the output current; that is, an all zero input
quire such high output currents, good accuracy can be achieved code (0000H) yields an output current 1 LSB below full scale.
with input reference currents in the range of 350 µA ≤ IREF Conversely, an all 1s input code (FFFFH) yields a zero analog
≤ 625 µA. The best signal-to-noise ratios, of course, will be current output. An expression for the DAC16’s transfer equa-
achieved with a 625 µA reference current which yields a maxi- tion can be expressed by:
mum 5 mA output current. Figure 22 illustrates how to form
the reference input current with a REF02 and a 10 kΩ precision  65,535 – Digital Code 
IOUT = 8 × IREF ×  
resistor.  65,536 

TE
+15V
Table II provides the relationship between the digital input
codes and the output current of the DAC16.
RREF
10kV Table II. Unipolar Code Table
IREF
0.1mF REF02 DAC16 IOUT
REF GND Digital Input DAC16 Output
Word (Hex) Current IOUT Comment
VREF
IREF =
8 × (2 – 1)/2 × IREF
16 16

Reducing Voltage Reference Noise

RREF

Figure 22. Generating the DAC16’s Reference Input Current

LE
In data converters of 16-bit and greater resolution, noise is of
critical importance. Surprisingly, the integrated voltage refer-
0000
7FFE
7FFF
8000
FFFF
8 × (215 + 1)/216 × IREF
8 × (215/216) × IREF
8 × (215– 1)/216 × IREF
0
Full Scale
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
Zero Scale

ence circuit used may contribute the dominant share of a Since the DAC16 exhibits a small output voltage compliance on
system’s noise floor, thereby degrading system dynamic range the order of a few millivolts, a high accuracy operational ampli-
SO
and signal-to-noise ratio. To maximize system dynamic range fier must be used to convert the DAC’s output current to a volt-
and SNR, all external noise contributions should be effectively age. Refer to the section on selecting operation amplifiers for the
much less than 1/2 LSB. For example, in a 5 V DAC16 applica- DAC16. The circuit shown in Figure 24 illustrates a unipolar
tion, one LSB is equivalent to 76 µV. This means that the total output configuration. In symbolic form, the transfer equation
wideband noise contribution due to a voltage reference and all for this circuit can be expressed by:
other sources should be less than 38 µV rms. These noise levels
 65,535 – Digital Code 
are not easy targets to hit with standard off-the-shelf reference VO = R3 × 8 × IREF  
devices. For example, commercially available references might  65,536 
exhibit 5 µV rms noise from 0.1 Hz to 10 Hz: but, over a 100 kHz In this example, the reference input current was set to 500 µA
B

bandwidth, its 300 µV rms of noise can easily swamp out a which produces a full-scale output current of 4 mA – 1 LSB.
16-bit system. Such noisy behavior can degrade a DAC’s effec- The DAC’s output current was scaled by R3, a 1.25 kΩ resistor,
tive resolution by increasing its differential nonlinearity which, to produce a 5 V full-scale output voltage. Bear in mind that to
in turn, can lead to nonmonotonic behavior or analog errors. ensure the highest possible accuracy, matched thin-film resistor
O

The easiest way to reduce noise in the reference circuit is to networks are almost a necessity, not an option. The resistors
band-limit its noise before feeding it to the converter. In the used in the circuit must have close tolerance and tight thermal
case of the DAC16, the reference is not a voltage, but a current. tracking. Table III illustrates the relationship between the input
Illustrated in Figure 23 is a simple way of hand-limiting digital code and the circuit’s output voltage for the component
values shown.
+15V
Table III. Unipolar Output Voltage vs. Digital Input Code
R1 R2
5kV 5kV
IREF DAC16 Digital Input Word Decimal Number in Analog Output
0.1mF REF02 C1 (Hex) in DAC Decoder Voltage (V)
22mF REF GND
AGND
0000 65,535 4.999924
7FFE 32,769 2.500076
Figure 23. Filtering a Reference’s Wideband Noise 7FFF 32,768 2.500000
8000 32,767 2.499924
voltage reference noise by splitting RREF into two equal resistors
FFFF 0 0
and bypassing the common node with a capacitor. To minimize
thermally induced errors, R1 and R2 must be electrically and

–8– REV. B
 DAC16
DIGITAL INPUT WORD
DB0 – DB7 DB8 – DB15 R3
2.5kV
(5kV42)
CLK
74AC11377 74AC11377
EN +15V
0.1mF
+15V
8 8
10mF
R1 R2
5kV 5kV
0.1mF REF02 IREF IOUT
22mF OP97A VOUT
REF GND DAC16 0V TO +10V FS
0.1mF
CCOMP AGND
10mF
47mF 100nF 0.1mF
CERAMIC
+5V DIGITAL +5V
PIN 3, DAC16 10mF –15V
–15V
10mF 0.1mF RESISTORS:
CADDOCK T912–5K–010–02 (OR EQUIVALENT)
–15V 5kV, 0.01%, TC TRACK = 2 ppm/8C

TE
Figure 24. Unipolar Circuit Configuration

+5VREF
DIGITAL INPUT WORD
DB0 – DB7 DB8 – DB15 R3 R4
2.5kV 2.5kV
(5kV42) (5kV42)
CLK
74AC11377 74AC11377
EN +15V

0.1mF
+15
V

REF02
+5VREF
R1
5kV

22mF
R2
5kV
LE IREF

REF GND
8

DAC16
8

IOUT
OP97A
0.1mF

10mF

0.1mF
VOUT
65V FS
CCOMP AGND
10mF
100nF 0.1mF
SO
47mF
CERAMIC
DIGITAL +5V
+5V PIN 3, DAC16 10mF –15V
–15V
10mF 0.1mF RESISTORS:
CADDOCK T912–5K–010–02 (OR EQUIVALENT)
–15V 5kV , 0.01%, TC TRACK = 2 ppm/8C

Figure 25. Bipolar Circuit Configuration

Bipolar Configuration Table IV. Bipolar Output Operation vs. Digital Input Code
B

For applications that require a bipolar output voltage, the circuit

in Figure 24 can be modified slightly by adding a resistor from Digital Input Decimal Number in Analog Output
the reference to the inverting sum node of the output amplifier Word (Hex) DAC Decoder Voltage (V)
to level shift the output signal. The transfer equation for the cir- 0000 65,535 4.999848
cuit now becomes:
O

7FFE 32,769 152E-6

7FFF 32,768 0
 65,535 – Digital Code   R4 
VO = R4 × 8 × IREF   – VREF ×   8000 32,767 –152E-6
 65,536   R3  FFFF 0 –5.00000
The circuit has the form shown in Figure 25, and Table IV pro-
vides the relationship between the digital input code and the
circuit’s output voltage for the component values shown.

REV. B –9–
DAC16
DIGITAL INPUT WORD
DB0 – DB7 DB8 – DB15 R3
1.25kV
(2.49kV42)
CLK
74AC11377 74AC11377
EN +15V
0.1mF
+15V
8 8
10mF
R1 R2
5kV 5kV
0.1mF REF02 IREF IOUT
22mF OP27A VOUT
REF GND DAC16 0V TO +5V FS
0.1mF
CCOMP AGND
10mF
C1 C2 0.1mF
47mF 100nF
CERAMIC
DIGITAL +5V 10mF –15V
+5V PIN 3, DAC16 –15V RESISTORS:
10mF 0.1mF CADDOCK T912–5K–010–02 (OR EQUIVALENT)
–15V 5kV, 0.01%, TC TRACK = 2 ppm/8C

TE
Figure 26. DAC16 Noise Measurement Test Circuit

DAC16 Noise Performance at different speeds, then the DAC output current will momen-
The novel architecture employed in the DAC16 yields very low tarily take on some incorrect value. This effect is particularly
wideband noise. Figure 26 illustrates the circuit configuration troublesome at the “carry points,” where the DAC output is to
for evaluating the DAC16’s noise performance. An OP27 is change by only one LSB, but several of the larger current
used as the DAC16’s output I–V converter which is configured sources must be switched to realize this change. Data skew can
to produce a 5 V full-scale output voltage. The output of the
OP27 was then capacitively coupled to an OP37 stage config-
ured in a gain of 101. Note that the techniques for reducing
wideband noise of the voltage reference and the DAC’s internal
reference amplifier were used. As a result of these techniques,
LE allow the DAC output to move a substantial amount towards
full scale or zero (depending upon the direction of the skew)
when only a small transition is desired. The glitch-sensitive user
should be equally diligent about minimizing the data skew at the
DAC16’s inputs, particularly the five most significant bits. This
the DAC16 exhibited a full-scale output noise spectral density can be achieved by using the proper logic family and gate to
of 31 pA/√Hz at 1 kHz. drive the DAC inputs, and keeping the interconnect lines be-
SO
Digital Feedthrough and Data Skew tween the latches and the DAC inputs as short and as well
The DAC16 features a compound DAC architecture where the matched as possible. Logic families that were empirically deter-
5 most significant bits utilize 31 identical, segmented current mined to operate well with the DAC16 are devices from the
sources to obtain optimal high speed settling at major code tran- 74AC11xxx and 74ACT11xxx advanced CMOS logic families.
sitions. Although every effort has been made to equalize the These devices have been purposely designed with improved lay-
speeds at which the DAC switches operate, there exists finite out and tailored rise times for minimizing ground bounce and
skew in the MSB DAC switches. digital feedthrough.

As with any converter product, a high speed digital-to-analog Deglitching

B

converter is forced to exist on the frontier between the noisy en- The output glitch of the DAC16 at the major carry (7FFEH to
vironment of high speed digital logic and the sensitive analog 7FFFH) is a not-insignificant 360 pA-sec, manifested as a
domain. The problems of this interlace are particularly acute momentary output transition to the negative rail for approxi-
when demands of high speed (greater than 10 MHz switching mately 200 ns. Due to the inherent low-pass or time-sampled
nature of many systems, this behavior in the DAC16 is not
O

times) and high precision are combined. No amount of design

effort can perfectly isolate the analog portions of a DAC from noticeable and does not detract from overall performance. Some
the spectral components of a digital input signal with a 2 ns rise applications however may prove so sensitive to glitch impulse
time. Inevitably, once this digital signal is brought onto the chip, that reduction by an order of magnitude or more is required. In
some of its higher frequency components will find their way to order to realize low glitch impulses, some sort of sample-and-
the sensitive analog nodes, producing a digital feedthrough hold amplifier-based deglitching scheme must be used.
glitch. To minimize the exposure to this effect, the DAC16 was There are high speed SHAs available with specifications suffi-
designed to omit intentionally the on-board latches that are usu- cient to deglitch the DAC16; however, most are hybrid in topol-
ally included in many slower DACs. This not only reduces the ogy at costs which can be prohibitive. A high performance, low
overall level of digital activity on chip, it also avoids bringing a cost alternative shown in Figure 27 is a discrete SHA utilizing a
latch clock pulse onto the IC, whose opposite edge inevitably high speed monolithic op amp and high speed DMOS FET
produces a substantial glitch, even when the DAC is not sup- switches.
posed to be changing codes. This SHA circuit uses the inverting integrator structure. A
The DAC16 uses each digital input line to switch each current 300 MHz gain-bandwidth product op amp, the AD841, is the
segment in the DAC between the output diode-connected heart of this fast SHA. The time constant formed by the 200 Ω
transistor and the logic control transistor. If the input bits are resistor and the 100 pF capacitor determines the acquisition
not changed simultaneously, or if the different DAC bits switch time and also hand limits the output signal to eliminate slew-
induced distortion.

–10– REV. B
 DAC16
200V 200V
INPUT
+15V
14 13 11 12
IN4735 M1 M2
16 9
100pF
360V 360V
+5V

6 8
MC10124 M3 AD841
Q1 Q2 5
OUTPUT
T/H 249V 169V 169V 249V
–15V 510V 75V
–5V –5V –5V 500pF

20kV –15V
3 4
TO PIN 2 M4
SD5000
Q1, Q2 = MPS571 1
1.6kV 0.39mF
M1 – M4 = SD5000

TE
Figure 27. A High Performance Deglitching Circuit

A discrete drive circuit is used to achieve the best performance In high speed applications where resolution is more important
from the SD5000 quad DMOS switch. This switch-driving cell than absolute accuracy, operational amplifiers such as the
is composed of MPS571 RF NPN transistors and an MC10124 AD843 offer the requisite settling time. Although these amplifi-
TTL-to-ECL translator. Using this technique provides both ers are not specified for 16-bit performance, their settling times
high speed and highly symmetrical drive signals for the SD5000 are two to three times faster than the DAC16 and will introduce
switches. The switches arc arranged in a single-pole, double- negligible error to the overall circuit’s settling time. It is possible
LE
throw (SPDT) configuration. The 500 pF “flyback” capacitor is
switched to the op amp summing junction during the hold mode
to keep switching transients from feeding to the output. This ca-
pacitor is grounded during sample mode to minimize its effect
on acquisition time.
to estimate the 16-bit settling time of an operational amplifier if
its 12-bit settling time is known. Assuming that the op amp can
be modeled by a single-pole response, then the ratio of the op
amp’s 16-bit settling time to its 12-bit settling can be expressed
as:
Careful circuit layout of the high speed SHA section is almost as ts (16 − bit )
important as the design itself. Double-sided printed circuit = 1.33
ts (12 − bit )
SO
board, a compact layout, and short critical signal paths all ensure
best performance. Since many operational amplifier data sheets provide charts
Op Amp Selection illustrating 0.01% settling time versus output voltage step size,
When selecting the amplifier to be used for the DAC16’s I–V all that is required to estimate an op amp’s 16-bit settling time is
converter, there are two main application areas; those requiring to multiply the 12-bit settling time for the required full-scale
high accuracy, and those seeking high speed. In high accuracy voltage by 1.33. The circuit’s overall settling time can then be
applications, three parameters are of prime importance: (1) approximated by the root-sum-square method:
input offset voltage. VOS; (2) input bias current, –IB; and (3) off-
B

2 2
set voltage drift, TCVOS. In these applications where 16-bit t S = (t DAC ) + (tOA )
performance must be maintained with an external reference
at +5 V, an op amp’s input offset voltage must be less than 15 µV where
(≈0.1 LSB) with a bias current less than 6 nA. The op amp tDAC = DAC16’s specified full-scale settling time
O

must also exhibit high open-loop gain to keep the offset voltage
tOA = Op amp full-scale settling time
below this limit over the specified full-scale output range. Thus,
for a maximum output of 5 V, the op amp’s open loop gain As a design aid, Table VI illustrates a high speed operational
must be greater than 1300 V/mV. amplifier selector guide for devices compatible with the DAC16
for high speed applications. All these devices exhibit the requi-
For low frequency, high accuracy applications, Table IV lists
site settling time, input offset voltage, and input bias current
selected compatible operational amplifiers available from Analog
consistent with maximum performance.
Devices. These operational amplifiers satisfy all the above
requirements and in most all cases will not require offset voltage
Table VI. High Speed Operational Amplifiers for the DAC16
nulling.
Model tS to % VOS TCVOS IB AVOL
Table V. Precision Operational Amplifier the DAC16
OP467 200 ns –0.01 0.5 mV 3.5 µV/°C 0.5 µA 20 V/mV
Model VOS TCVOS IB AVOL AD817 70 ns –0.01 2 mV 10 µV/°C 6.6 µA 6 V/mV
AD829 90 ns –0.1 0.5 mV 0.3 µV/°C 7 µA 100 V/mV
OP177 10 µV 0.3 µV/°C 2 nA 12000 V/mV
AD841 110 ns –0.01 1 mV 35 µV/°C 5 µA 45 V/mV
OP77 25 µV 0.6 µV/°C 2.8 nA 2000 V/mV
AD843 135 ns –0.01 1 mV 12 µV/°C 0.001 µA 25 V/mV
OP27 25 µV 0.3 µV/°C 80 nA 1500 V/mV
AD845 350 ns –0.01 0.25 mV 5 µV/°C 0.001 µA 500 V/mV
OP97 25 µV 2 µV/°C 0.15 nA 2000 V/mV
AD847 120 ns –0.01 1 mV 15 µV/°C 5 µA 5.5 V/mV

REV. B –11–
DAC16
In using high speed op amps, the output capacitance of the The choice of amplifier depends entirely on the required system
DAC16 appears across the inputs of the op amp where it and the accuracy, the required temperature range, and the operating
op amp’s input capacitance will set an additional pole in the op frequency.
amp’s loop gain response. The pole is formed with the feedback CFB
resistance and the output resistance of the DAC. This additional
pole may adversely affect the transient response of the circuit DAC16 RFB
due to the added phase shift. Placing a small capacitor across the

C1883b–1–4/99
feedback resistance, as shown in Figure 28, compensates for the IDAC RO CO
additional pole. The value of the capacitor can be determined by
CIN
setting RFBCFB = RO (CO + CIN) and should be adjusted for opti- VOUT

mum transient response.

Figure 28. Compensating for the Feedback Pole

TE
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

24
24-Lead Epoxy DIP (P)

1.275 (32.30)
1.125 (28.60)
(N-24)

13 0.280 (7.11)
LE 24-Lead Epoxy SOL (S)

0.6141 (15.60)
0.5985 (15.20)
(R-24)

1 12 0.240 (6.10) 24 13
0.325 (8.25) 0.2992 (7.60)
PIN 1
0.300 (7.62) 0.2914 (7.40)
SO
0.060 (1.52)
0.210 0.015 (0.38) 0.4193 (10.65)
0.195 (4.95) 1 12
(5.33) 0.3937 (10.00)
0.150 0.115 (2.93)
MAX
0.200 (5.05) (3.81)
MIN
0.125 (3.18) 0.015 (0.381) PIN 1 0.1043 (2.65)
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.0291 (0.74)
0.008 (0.204) 0.0926 (2.35) 3 458
0.014 (0.356) (2.54) 0.045 (1.15) PLANE 0.0098 (0.25)
BSC

88
0.0118 (0.30) 0.0500 0.0192 (0.49) SEATING 08 0.0500 (1.27)
0.0125 (0.32)
0.0040 (0.10) (1.27) 0.0138 (0.35) PLANE
0.0091 (0.23) 0.0157 (0.40)
BSC
B
O

PRINTED IN U.S.A.

–12– REV. B