AD7541

August 1997 12-Bit, Multiplying D/A Converter

Features Description
• 12-Bit Linearity 0.01% The AD7541 is a monolithic, low cost, high performance,
12-bit accurate, multiplying digital-to-analog converter
• Pretrimmed Gain
(DAC).
• Low Gain and Linearity Tempcos
Intersil’ wafer level laser-trimmed thin-film resistors on
• Full Temperature Range Operation CMOS circuitry provide true 12-bit linearity with TTL/CMOS
compatible operation.
• Full Input Static Protection
Special tabbed-resistor geometries (improving time stability),
• TTL/CMOS Compatible full input protection from damage due to static discharge by
• +5V to +15V Supply Range diode clamps to V+ and ground, large IOUT1 and IOUT2 bus
lines (improving superposition errors) are some of the fea-
• 20mW Low Power Dissipation tures offered by Intersil AD7541.
• Current Settling Time 1µs to 0.01% of FSR Pin compatible with AD7521, this DAC provides accurate
• Four Quadrant Multiplication four quadrant multiplication over the full military temperature
range.

Ordering Information
PART NUMBER NONLINEARITY TEMP. RANGE (oC) PACKAGE PKG. NO.

AD7541JN 0.02% (11-Bit) 0 to 70 18 Ld PDIP E18.3

AD7541KN 0.01% (12-Bit) 0 to 70 18 Ld PDIP E18.3

AD7541LN 0.01% (12-Bit) Guaranteed 0 to 70 18 Ld PDIP E18.3

Monotonic

Pinout Functional Block Diagram

AD7541
(PDIP) VREF IN 10kΩ 10kΩ 10kΩ 10kΩ
TOP VIEW
(17)

20kΩ 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ

IOUT1 1 18 RFEEDBACK

IOUT2 2 17 VREF IN (3)

GND 3 16 V+

BIT 1 (MSB) 4 15 BIT 12 (LSB) SPDT

NMOS IOUT2 (2)
BIT 2 5 14 BIT 11 SWITCHES IOUT1 (1)
BIT 3 6 13 BIT 10
10kΩ
BIT 4 7 12 BIT 9 MSB BIT 2 BIT 3 RFEEDBACK
BIT 5 8 11 BIT 8 (4) (5) (6) (18)

BIT 6 9 10 BIT 7

NOTE: Switches shown for digital inputs “High”.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3107.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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 AD7541

Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V Thermal Resistance (Typical, Note 1) θJA (oC/W)
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+ Maximum Storage Temperature . . . . . . . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range
JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = 25oC, Unless Otherwise Specified

TA = 25oC TA MIN-MAX

PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS

SYSTEM PERFORMANCE

Resolution 12 - - 12 - Bits

Nonlinearity A, S, J -10V ≤ VREF ≤ +10V - - ±0.024 - ±0.024 % of FSR

VOUT1 = VOUT2 = 0V
B, T, K - - ±0.012 - ±0.012 % of FSR
See Figure 3
L (Note 5) - - ±0.012 - ±0.012 % of FSR

Monotonicity Guaranteed

Gain Error -10V ≤ VREF ≤ +10V (Note 5) - - ±0.3 - ±0.4 % of FSR

Output Leakage Current VOUT1 = VOUT2 = 0 - - ±50 - ±200 nA

(Either Output)

DYNAMIC CHARACTERISTICS

Power Supply Rejection V+ = 14.5V to 15.5V - - ±0.005 - ±0.01 % of FSR/% of

See Figure 5 (Note 5) ∆V+

Output Current Settling Time To 0.1% of FSR - - 1 - 1 µs

See Figure 9 (Note 6)

Feedthrough Error VREF = 20VP-P, 10kHz - - 1 - 1 mVP-P

All Digital Inputs Low
See Figure 8 (Note 6)
REFERENCE INPUTS

Input Resistance All Digital Inputs High 5 10 20 5 20 kΩ

IOUT1 at Ground

ANALOG OUTPUT

Voltage Compliance Both Outputs, See Maximum -100mV to V+

Ratings (Note 7)

Output Capacitance COUT1 All Digital Inputs High - - 200 - 200 pF

See Figure 7 (Note 6)
COUT2 - - 60 - 60 pF

COUT1 All Digital Inputs Low) - - 60 - 60 pF

See Figure 7 (Note 6)
COUT2 - - 200 - 200 pF

Output Noise (Both Outputs) See Figure 6 Equivalent to 10kΩ Johnson Noise

DIGITAL INPUTS

Low State Threshold, VIL (Notes 2, 6) - - 0.8 - 0.8 V

High State Threshold, VIH 2.4 - - 2.4 - V

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 AD7541

Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = 25oC, Unless Otherwise Specified (Continued)

TA = 25oC TA MIN-MAX

PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS

Input Current VIN = 0V or V+ (Note 6) - - ±1 - ±1 µA

Input Coding See Tables 1 and 2 (Note 6) Binary/Offset Binary

Input Capacitance (Note 6) - - 8 - 8 pF

POWER SUPPLY CHARACTERISTICS

Power Supply Voltage Range Accuracy Is Not Guaranteed +5 to +16 V

Over This Range

I+ All Digital Inputs High or Low - - 2.0 - 2.5 mA

(Excluding Ladder Network)

Total Power Dissipation (Including Ladder Network) - 20 - - - mW

NOTES:
2. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy
electrostatic fields. Keep unused units in conductive foam at all times.
3. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK .
4. Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes.
5. Using internal feedback resistor, RFEEDBACK .
6. Guaranteed by design or characterization and not production tested.
7. Accuracy not guaranteed unless outputs at ground potential.

Definition of Terms Detailed Description

Nonlinearity: Error contributed by deviation of the DAC The AD7541 is a 12-bit, monolithic, multiplying D/A converter.
transfer function from a “best fit straight line” function. Nor- A highly stable thin film R-2R resistor ladder network and
mally expressed as a percentage of full scale range. For a NMOS SPDT switches form the basis of the converter circuit.
multiplying DAC, this should hold true over the entire VREF CMOS level shifters provide low power TTL/CMOS compati-
range. ble operation. An external voltage or current reference and an
operational amplifier are all that is required for most voltage
Resolution: Value of the LSB. For example, a unipolar
output applications. A simplified equivalent circuit of the DAC
converter with n bits has a resolution of LSB = (VREF)/2-N. A
is shown on page 1, (Functional Diagram). The NMOS SPDT
bipolar converter of n bits has a resolution of
switches steer the ladder leg currents between IOUT1 and
LSB = (VREF)/2-(N-1). Resolution in no way implies linearity.
IOUT2 buses which must be held at ground potential. This
Settling Time: Time required for the output function of the configuration maintains a constant current in each ladder leg
DAC to settle to within 1/2 LSB for a given digital input independent of the input code. Converter errors are further
stimulus, i.e., 0 to Full Scale. eliminated by using wider metal interconnections between the
major bits and the outputs. Use of high threshold switches
Gain Error: Ratio of the DAC’s operational amplifier output reduces the offset (leakage) errors to a negligible level.
voltage to the nominal input voltage value.
Each circuit is laser-trimmed, at the wafer level, to better than
Feedthrough Error: Error caused by capacitive coupling 12-bits linearity. For the first four bits of the ladder, special
from VREF to output with all switches OFF. trim-tabbed geometries are used to keep the body of the
Output Capacitance: Capacitance from IOUT1 , and IOUT2 resistors, carrying the majority of the output current, undis-
terminals to ground. turbed. The resultant time stability of the trimmed circuits is
comparable to that of untrimmed units.
Output Leakage Current: Current which appears on
IOUT1, terminal when all digital inputs are LOW or on IOUT2 The level shifter circuits are comprised of three inverters with
terminal when all inputs are HIGH. a positive feedback from the output of the second to first
(Figure 1). This configuration results in TTL/COMS compati-
ble operation over the full military temperature range. With
the ladder SPDT switches driven by the level shifter, each
switch is binary weighted for an “ON” resistance proportional
to the respective ladder leg current. This assures a constant
voltage drop across each switch, creating equipotential ter-
minations for the 2R ladder resistor, resulting in accurate leg
currents.

10-11
 AD7541

V+ +15V
1 3
4 6 VREF
TO LADDER
±10V
BIT 1 (MSB) 17 16 RFEEDBACK
8 9 4 18
IOUT1
5 AD7541 1 - VOUT
DIGITAL CR1
TTL/CMOS A
2 5 7 INPUT I 6
INPUT 15 3 2 OUT2 +
IOUT2 IOUT1 BIT 12 (LSB)
GND

FIGURE 2. UNIPOLAR BINARY OPERATION (2-QUADRANT

FIGURE 1. CMOS SWITCH
MULTIPLICATION)

Typical Applications Zero Offset Adjustment

General Recommendations 1. Connect all digital inputs to GND.
Static performance of the AD7541 depends on IOUT1 and 2. Adjust the offset zero adjust trimpot of the output
IOUT2 (pin 1 and pin 2) potentials being exactly equal to operational amplifier for 0V ±0.5mV (Max) at VOUT .
GND (pin 3).
Gain Adjustment
The output amplifier should be selected to have a low input
1. Connect all digital inputs to VDD .
bias current (typically less than 75nA), and a low drift
(depending on the temperature range). The voltage offset of 2. Monitor VOUT for a -VREF (11/212) reading.
the amplifier should be nulled (typically less than ±200µV).
3. To increase VOUT , connect a series resistor, (0Ω to
The bias current compensation resistor in the amplifier’s 250Ω), in the IOUT1 amplifier feedback loop.
non-inverting input can cause a variable offset. Non-inverting
input should be connected to GND with a low resistance 4. To decrease VOUT , connect a series resistor, (0Ω to 250Ω),
wire. between the reference voltage and the VREF terminal.

Ground-loops must be avoided by taking all pins going to

TABLE 1. CODE TABLE - UNIPOLAR BINARY OPERATION
GND to a common point, using separate connections.
DIGITAL INPUT ANALOG OUTPUT
The V+ (pin 18) power supply should have a low noise level
and should not have any transients exceeding +17V. 111111111111 -VREF (1 - 1/212)
Unused digital inputs must be connected to GND or VDD for
proper operation. 100000000001 -VREF (1/2 + 1/212)

A high value resistor (~1MΩ) can be used to prevent static -VREF/2

100000000000
charge accumulation, when the inputs are open-circuited for
any reason.
011111111111 -VREF (1/2 - 1/212)
When gain adjustment is required, low tempco
(approximately 50ppm/oC) resistors or trim-pots should be 000000000001 -VREF (1/212)
selected.
000000000000 0
Unipolar Binary Operation
The circuit configuration for operating the AD7541 in
unipolar mode is shown in Figure 2. With positive and Bipolar (Offset Binary) Operation
negative VREF values the circuit is capable of 2-Quadrant
The circuit configuration for operating the AD7541 in the
multiplication. The “Digital Input Code/Analog Output Value”
bipolar mode is given in Figure 3. Using offset binary digital
table for unipolar mode is given in Table 1. A Schottky diode
input codes and positive and negative reference voltage
(HP5082-2811 or equivalent) prevents IOUT1 from negative
values Four-Quadrant multiplication can be realized. The
excursions which could damage the device. This precaution
“Digital Input Code/Analog Output Value” table for bipolar
is only necessary with certain high speed amplifiers.
mode is given in Table 2.

10-12
 AD7541

A “Logic 1” input at any digital input forces the corresponding Gain Adjustment
ladder switch to steer the bit current to IOUT1 bus. A “Logic
1. Connect all digital inputs to VDD .
0” input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one 2. Monitor VOUT for a -VREF (1 - 1/211) volts reading.
another. The current amplifier at IOUT2 changes the polarity
of IOUT2 current and the transconductance amplifier at 3. To increase VOUT , connect a series resistor, (0Ω to
IOUT1 output sums the two currents. This configuration dou- 250Ω), in the IOUT1 amplifier feedback loop.
bles the output range of the DAC. The difference current 4. To decrease VOUT , connect a series resistor, (0Ω to 250Ω),
resulting at zero offset binary code, (MSB = “Logic 1”, All between the reference voltage and the VREF terminal.
other bits = “Logic 0”), is corrected by using an external
resistive divider, from VREF to IOUT2 .
TABLE 2. CODE TABLE - BIPOLAR (OFFSET BINARY)
Offset Adjustment OPERATION

1. Adjust VREF to approximately +10V. DIGITAL INPUT ANALOG OUTPUT

2. Set R4 to zero. 111111111111 -VREF (1 - 1/211)

3. Connect all digital inputs to “Logic 1”.
100000000001 -VREF (1/211)
4. Adjust IOUT1 amplifier offset zero adjust trimpot for 0V
±0.1mV at IOUT2 amplifier output. 100000000000 0
5. Connect a short circuit across R2.
011111111111 VREF (1/211)
6. Connect all digital inputs to “Logic 0”.
7. Adjust IOUT2 amplifier offset zero adjust trimpot for 0V 000000000001 VREF (1 - 1/211)
±0.1mV at IOUT1 amplifier output.
000000000000 VREF
8. Remove short circuit across R2.
9. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.
10. Adjust R4 for 0V ±0.2mV at VOUT .

±10V
VREF
+15V

BIT 1 (MSB) 17 16
4 18
IOUT1
1
-
A1 VOUT
6
+
DIGITAL
INPUT AD7541
R1 10K

R2 10K
R3
390K
R5 10K

15 2 -
BIT 12 (LSB) IOUT2 R4
3 500Ω
A2
6
GND +

NOTE: R1 and R2 should be 0.01%, low-TCR resistors.

FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)

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 AD7541

Test Circuits
+15V
VREF

BIT 1 (MSB) 17 16 RFEEDBACK

4 18
IOUT1
12-BIT 5 1 -
BINARY
COUNTER AD7541
AD7541 HA2600
IOUT2 +
15 2 10K
3 0.01% 1MΩ
BIT 12
(LSB) GND
CLOCK
VREF
-
HA2600
+ LINEARITY
BIT 1 10K 0.01% ERROR X 100
(MSB)
14-BIT
BIT 12 REFERENCE
DAC
BIT 13
BIT 14

FIGURE 4. NONLINEARITY TEST CIRCUIT

+15V
UNGROUNDED
SINE WAVE 500K
GENERATION
40Hz 1.0VP-P
+10V
VREF -
5K 0.01% HA2600
BIT 1 (MSB) 17 16 RFEEDBACK 5K 0.01% + VERROR X 100
4 18
IOUT1
5 -
1
AD7541 HA2600
BIT 12 IOUT2
15 3 2 +
(LSB)
GND

FIGURE 5. POWER SUPPLY REJECTION TEST CIRCUIT

+11V (ADJUST FOR VOUT = 0V)

+15V

1K

100Ω 10K F = 1KHz

IOUT2 BW = 1Hz
17 16
15µF 4 2
5 QUAN
- VOUT TECH
AD7541 MODEL
IOUT1 101ALN 134D
15 3 1 + WAVE
ANALYZER
50K 1K
-50V
0.1µF

FIGURE 6. NOISE TEST CIRCUIT

10-14
 AD7541

Test Circuits (Continued)

+15V NC +15V +15V

VREF = 20VP-P 10kHz SINE WAVE

BIT 1 (MSB) 17 16 BIT 1 (MSB) 17 16

4 18 NC 4 18
5 5
AD7541 1K AD7541 IOUT1 3
1 1
IOUT2 6
17 2 100mVP-P 15 3 2 HA2600
3 SCOPE 2 VOUT
BIT 12 (LSB) 1MHz BIT 12 (LSB)
GND

FIGURE 7. OUTPUT CAPACITANCE TEST CIRCUIT FIGURE 8. FEEDTHROUGH ERROR TEST CIRCUIT

+15V
VREF
+10V EXTRAPOLATE 3t: 5% SETTLING
9t: 0.01% SETTLING
BIT 1 (MSB) 17 16
+5V 4
0V 5 OSCILLOSCOPE
AD7541 +100mV
DIGITAL INPUT 1
IOUT2
15 3 2
BIT 12 (LSB) 100Ω
GND

FIGURE 9. OUTPUT CURRENT SETTLING TIME TEST CIRCUIT

Dynamic Performance
The dynamic performance of the DAC, also depends on the code. These variations necessitate the use of compensation
output amplifier selection. For low speed or static applica- capacitors, when high speed amplifiers are used.
tions, AC specifications of the amplifier are not very critical.
A capacitor in parallel with the feedback resistor (as shown
For high-speed applications slew-rate, settling-time,
in Figure 10) provides the necessary phase compensation to
openloop gain and gain/phase-margin specifications of the
critically damp the output.
amplifier should be selected for the desired performance.
A small capacitor connected to the compensation pin of the
The output impedance of the AD7541 looking into IOUT1
amplifier may be required for unstable situations causing
varies between 10kΩ (RFEEDBACK alone) and 5kΩ
oscillations. Careful PC board layout, minimizing parasitic
(RFEED-BACK in parallel with the ladder resistance).
capacitances, is also vital.
Similarly the output capacitance varies between the
minimum and the maximum values depending on the input

+15V
VREF +10V

17 16 RFEEDBACK
BIT 1 (MSB) 4 18
BIT 2 5
AD7541 IOUT1 CC
1 -
IOUT2 A VOUT
BIT 12 (LSB) 15 3 2 +

GND

FIGURE 10. GENERAL DAC CIRCUIT WITH COMPENSATION CAPACITOR, CC

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 AD7541

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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