CMOS Low Cost,

10-Bit Multiplying DAC

AD7533
FEATURES GENERAL DESCRIPTION
Low cost 10-bit DAC The AD7533 is a low cost, 10-bit, 4-quadrant multiplying DAC
Low cost AD7520 replacement manufactured using an advanced thin-film-on-monolithic-
Linearity: ½ LSB, 1 LSB, or 2 LSB CMOS wafer fabrication process.
Low power dissipation
Pin and function equivalent to the AD7520 industry standard,
Full 4-quadrant multiplying DAC
the AD7533 is recommended as a lower cost alternative for old
CMOS/TTL direct interface
AD7520 sockets or new 10-bit DAC designs.
Latch free (protection Schottky not required)
Endpoint linearity AD7533 application flexibility is demonstrated by its ability to
interface to TTL or CMOS, operate on 5 V to 15 V power, and
provide proper binary scaling for reference inputs of either
APPLICATIONS positive or negative polarity.
Digitally controlled attenuators
Programmable gain amplifiers
Function generation
Linear automatic gain controls

FUNCTIONAL BLOCK DIAGRAM

10kΩ 10kΩ 10kΩ
VREF

20kΩ 20kΩ 20kΩ 20kΩ 20kΩ

S1 S2 S3 SN

IOUT2

IOUT1
10kΩ
RFB

BIT 1 (MSB) BIT 2 BIT 3 BIT 10 (LSB)

01134-001

DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)

Figure 1.

Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
AD7533

TABLE OF CONTENTS
Features .............................................................................................. 1 Circuit Description............................................................................7
Applications....................................................................................... 1 General Circuit Information........................................................7
General Description ......................................................................... 1 Equivalent Circuit Analysis .........................................................7
Functional Block Diagram .............................................................. 1 Operation............................................................................................8
Revision History ............................................................................... 2 Unipolar Binary Code ..................................................................8
Specifications..................................................................................... 3 Bipolar (Offset Binary) Code.......................................................8
Absolute Maximum Ratings............................................................ 4 Applications........................................................................................9
ESD Caution.................................................................................. 4 Outline Dimensions ....................................................................... 10
Terminology ...................................................................................... 5 Ordering Guide .......................................................................... 12
Pin Configurations and Function Descriptions ........................... 6

REVISION HISTORY
3/07—Rev. B to Rev. C 3/04—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 3 Changes to Specifications.................................................................2
Changes to Table 2............................................................................ 4 Changes to Absolute Maximum Ratings........................................3
Changes to Figure 13, Figure 14, and Figure 17 ........................... 9 Changes to Ordering Guide .............................................................3
Updated Outline Dimensions ....................................................... 10 Updated Outline Dimensions..........................................................7
Changes to Ordering Guide .......................................................... 12

1/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Absolute Maximum Ratings ....................................... 4
Added Pin Configurations
and Function Descriptions Section................................................ 6
Updated Outline Dimensions ....................................................... 10
Changes to Ordering Guide .......................................................... 12

Rev. C | Page 2 of 12
 AD7533

SPECIFICATIONS
VDD = 15 V, VOUT1 = VOUT2 = 0 V, VREF = 10 V, unless otherwise noted.

Table 1.
Parameter TA = 25°C TA = Operating Range Test Conditions
STATIC ACCURACY
Resolution 10 Bits 10 Bits
Relative Accuracy 1
AD7533JN, AD7533AQ, ±0.2% FSR maximum ±0.2% FSR maximum
AD7533SQ, AD7533JP
AD7533KN, AD7533BQ, ±0.1% FSR maximum ±0.1% FSR maximum
AD7533KP, AD7533TE
AD7533LN, AD7533CQ, AD7533UQ ±0.05% FSR maximum ±0.05% FSR maximum
DNL ±1 LSB maximum ±1 LSB maximum
Gain Error 2, 3 ±1% FS maximum ±1% FS maximum Digital input = VINH
Supply Rejection 4
∆Gain/∆VDD 0.001%/% maximum 0.001%/% maximum Digital inputs = VINH, VDD = 14 V to 17 V
Output Leakage Current
IOUT1 ±5 nA maximum ±200 nA maximum Digital inputs = VINL, VREF = ±10 V
IOUT2 ±5 nA maximum ±200 nA maximum Digital inputs = VINH, VREF = ±10 V
DYNAMIC ACCURACY
Output Current Settling Time 600 ns maximum4 800 ns 5 To 0.05% FSR; RLOAD = 100 Ω, digital
inputs = VINH to VINL or VINL to VINH
Feedthrough Error ±0.05% FSR maximum5 ±0.1% FSR maximum5 Digital inputs = VINL, VREF = ±10 V,
100 kHz sine wave
Propagation Delay 100 ns typical 100 ns typical
Glitch Impulse 100 nV-s typical 100 nV-s typical
REFERENCE INPUT
Input Resistance (VREF) 5 kΩ min, 20 kΩ maximum 5 kΩ min, 20 kΩ maximum 6 11 kΩ nominal
ANALOG OUTPUTS
Output Capacitance
CIOUT1 50 pF maximum5 100 pF maximum5 Digital inputs = VINH
CIOUT2 20 pF maximum5 35 pF maximum5
CIOUT1 30 pF maximum5 35 pF maximum5
CIOUT2 50 pF maximum5 100 pF maximum5 Digital inputs = VINL
DIGITAL INPUTS
Input High Voltage (VINH) 2.4 V minimum 2.4 V minimum
Input Low Voltage (VINL) 0.8 V maximum 0.8 V maximum
Input Leakage Current (IIN) ±1 μA maximum ±1 μA maximum VIN = 0 V and VDD
Input Capacitance (CIN) 8 pF maximum5 8 pF maximum5
POWER REQUIREMENTS
VDD 15 V ± 10% 15 V ± 10% Rated accuracy
VDD Ranges5 5 V to 16 V 5 V to 16 V Functionality with degraded performance
IDD 2 mA maximum 2 mA maximum Digital inputs = VINL or VINH D
25 μA maximum 50 μA maximum Digital inputs over VIN
1
FSR = full-scale range.
2
Full scale (FS) = VREF.
3
Maximum gain change from TA = 25°C to TMIN or TMAX is ±0.1% FSR.
4
AC parameter, sample tested to ensure specification compliance.
5
Guaranteed, not tested.
6
Absolute temperature coefficient is approximately −300 ppm/°C.

Rev. C | Page 3 of 12
AD7533

ABSOLUTE MAXIMUM RATINGS

TA = 25 °C unless otherwise noted.

Table 2. Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress
Parameter Rating
rating only; functional operation of the device at these or any
VDD to GND −0.3 V, +17 V
other conditions above those indicated in the operational
RFB to GND ±25 V
section of this specification is not implied. Exposure to absolute
VREF to GND ±25 V
maximum rating conditions for extended periods may affect
Digital Input Voltage Range −0.3 V to VDD + 0.3 V
device reliability.
IOUT1, IOUT2 to GND −0.3 V to VDD
Power Dissipation (Any Package)
To 75°C 450 mW ESD CAUTION
Derates above 75°C by 6 mW/°C
Operating Temperature Range
Plastic (JN, JP, KN, KP, LN Versions) −40°C to +85°C
Hermetic (AQ, BQ, CQ Versions) −40°C to +85°C
Hermetic (SQ, TE, UQ Versions) −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C

Rev. C | Page 4 of 12
 AD7533

TERMINOLOGY
Relative Accuracy Gain Error
Relative accuracy or endpoint nonlinearity is a measure of the Gain error is a measure of the output error between an ideal
maximum deviation from a straight line passing through the DAC and the actual device output. It is measured with all 1s in
endpoints of the DAC transfer function. It is measured after the DAC after offset error is adjusted out and is expressed in LSBs.
adjusting for ideal zero and full scale and is expressed in % of Gain error is adjustable to zero with an external potentiometer.
full-scale range or (sub) multiples of 1 LSB. Feedthrough Error
Resolution Error caused by capacitive coupling from VREF to output with all
Value of the LSB. For example, a unipolar converter with n bits switches off.
has a resolution of (2–n) (VREF). A bipolar converter of n bits has Output Capacitance
a resolution of [2–(n–1)] (VREF). Resolution in no way implies Capacity from IOUT1 and IOUT2 terminals to ground.
linearity.
Output Leakage Current
Settling Time Current that appears on IOUT1 terminal with all digital inputs
Time required for the output function of the DAC to settle to low or on IOUT2 terminal when all inputs are high.
within ½ LSB for a given digital input stimulus, that is, 0 to
full scale.

Rev. C | Page 5 of 12
AD7533

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

IOUT2
IOUT1

VREF
IOUT1 1 16 RFB

RFB
NC
IOUT2 2 15 VREF 3 2 1 20 19
GND 3 AD7533 14 VDD
BIT 1 (MSB) 4 TOP VIEW 13 BIT 10 (LSB) GND 4 18 VDD
BIT 2 5 (Not to Scale) 12 BIT 9 BIT 1 (MSB) 5 17 BIT 10 (LSB)
BIT 3 6 11 BIT 8
AD7533
NC 6 16 NC
TOP VIEW
BIT 4 7 BIT 7

01134-002
10 BIT 2 7 15 BIT 9
(Not to Scale)
BIT 5 8 9 BIT 6 BIT 3 8 14 BIT 8

Figure 2. 16-Lead PDIP Pin Configuration 9 10 11 12 13

NC = NO CONNECT

01134-005
BIT 4
BIT 5

BIT 6
BIT 7
NC
IOUT1 1 16 RFB
IOUT2 2 15 VREF Figure 5. 20-Terminal LCC Pin Configuration
GND 3 14 VDD
AD7533
BIT 1 (MSB) 4 TOP VIEW 13 BIT 10 (LSB)

IOUT2
IOUT1

VREF
RFB
NC
BIT 2 5 (Not to Scale) 12 BIT 9
BIT 3 6 11 BIT 8 3 2 1 20 19

BIT 4 7 10 BIT 7
01134-003

GND 4 PIN 1 18 VDD

BIT 5 8 9 BIT 6 INDENTFIER
BIT 1 (MSB) 5 17 BIT 10 (LSB)

NC 6
AD7533 16 NC
TOP VIEW
Figure 3. 16-Lead SOIC Pin Configuration (Not to scale)
BIT 2 7 15 BIT 9

BIT 3 8 14 BIT 8

IOUT1 1 16 RFB 9 10 11 12 13

BIT 4
BIT 5

BIT 6
BIT 7
NC
IOUT2 2 15 VREF

01134-006
GND 3 14 VDD
AD7533 NC = NO CONNECT
BIT 1 (MSB) 4 TOP VIEW 13 BIT 10 (LSB)
BIT 2 5 (Not to Scale) 12 BIT 9 Figure 6. 20-Lead PLCC Pin Configuration
BIT 3 6 11 BIT 8

BIT 4 7 10 BIT 7
01134-004

BIT 5 8 9 BIT 6

Figure 4. 16-Lead CERDIP Pin Configuration

Table 3. Pin Function Descriptions

Pin Number
16-Lead PDIP, SOIC, CERDIP 20-Lead LCC, PLCC Mnemonic Description
1 2 IOUT1 DAC Current Output.
2 3 IOUT2 DAC Analog Ground. This pin should normally be tied to the
analog ground of the system.
3 4 GND Ground.
4 to 13 5, 7 to 10, 12 to 15, 17 BIT 1 to BIT 10 MSB to LSB.
14 18 VDD Positive Power Supply Input. These parts can be operated from
a supply of 5 V to 16 V.
15 19 VREF DAC Reference Voltage Input Terminal.
16 20 RFB DAC Feedback Resistor Pin. Establish voltage output for the DAC
by connecting RFB to external amplifier output.
NA 1, 6, 11, 16 NC No Connect.

Rev. C | Page 6 of 12
 AD7533

CIRCUIT DESCRIPTION
V+
GENERAL CIRCUIT INFORMATION 1 3
TO LADDER
The AD7533 is a 10-bit multiplying DAC that consists of a 4 6

highly stable thin-film R-2R ladder and ten CMOS current DTL/TTL/ 250Ω
CMOS
switches on a monolithic chip. Most applications require the INPUT
8 9
addition of only an output operational amplifier and a voltage 2 5 7

01134-007
or current reference.
IOUT2 IOUT1
The simplified D/A circuit is shown in Figure 7. An inverted
Figure 8. CMOS Switch
R- 2R ladder structure is used, that is, the binarily weighted
currents are switched between the IOUT1 and IOUT2 bus lines, EQUIVALENT CIRCUIT ANALYSIS
thus maintaining a constant current in each ladder leg The equivalent circuits for all digital inputs high and digital
independent of the switch state. inputs low are shown in Figure 9 and Figure 10. In Figure 9 with
10kΩ 10kΩ 10kΩ
VREF all digital inputs low, the reference current is switched to IOUT2.
20kΩ 20kΩ 20kΩ 20kΩ 20kΩ
The current source ILEAKAGE is composed of surface and junction
leakages to the substrate, while the I/1024 current source represents
S1 S2 S3 SN
a constant 1-bit current drain through the termination resistor
IOUT2
on the R-2R ladder. The on capacitance of the output N channel
IOUT1 switch is 100 pF, as shown on the IOUT2 terminal. The off switch
10kΩ
RFB
capacitance is 35 pF, as shown on the IOUT1 terminal. Analysis of
the circuit for all digital inputs high, as shown in Figure 10, is
BIT 1 (MSB) BIT 2 BIT 3 BIT 10 (LSB)
01134-001

similar to Figure 9; however, the on switches are now on

DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
Terminal IOUT1. Therefore, there is the 100 pF at that terminal.
Figure 7. Functional Diagram

One of the CMOS current switches is shown in Figure 8. The RFB

geometries of Device 1, Device 2, and Device 3 are optimized to R
make the digital control inputs DTL/TTL/CMOS compatible IOUT1
R 10kΩ ILEAKAGE
over the full military temperature range. The input stage drives 35pF

two inverters (Device 4, Device 5, Device 6, and Device 7), IREF

which in turn drive the two output N channels. The on VREF IOUT2
R
I/1024 ILEAKAGE 100pF

01134-008
resistances of the switches are binarily sealed so that the voltage
drop across each switch is the same. For example, Switch 1 in
Figure 8 is designed for an on resistance of 20 Ω, Switch 2 for Figure 9. Equivalent Circuit—All Digital Inputs Low
40 Ω, and so on. For a 10 V reference input, the current through
Switch 1 is 0.5 mA, the current through Switch 2 is 0.25 mA, RFB
and so on, thus maintaining a constant 10 mV drop across each IREF R 10kΩ R
switch. It is essential that each switch voltage drop be equal if VREF IOUT1
R
the binarily weighted current division property of the ladder is I/1024 ILEAKAGE 100pF
to be maintained.
IOUT2
ILEAKAGE 35pF
01134-009

Figure 10. Equivalent Circuit—All Digital Inputs High

Rev. C | Page 7 of 12
AD7533

OPERATION
UNIPOLAR BINARY CODE BIPOLAR (OFFSET BINARY) CODE

Table 4. Unipolar Binary Operation Table 5. Unipolar Binary Operation

(2-Quadrant Multiplication) (4-Quadrant Multiplication)
Digital Input Analog Output Digital Input Analog Output
MSB LSB (VOUT as shown in Figure 11) MSB LSB (VOUT as shown in Figure 12)
1111111111 1111111111
+ VREF ⎛⎜
511 ⎞
− VREF ⎛⎜
1023 ⎞
⎟ ⎟
⎝ 1024 ⎠ ⎝ 512 ⎠
1000000001 1000000001
+ VREF ⎛⎜
1 ⎞
− VREF ⎛⎜
513 ⎞
⎟ ⎟
⎝ 1024 ⎠ ⎝ 512 ⎠
1000000000 1000000000 0
− VREF ⎛⎜
512 ⎞ ⎛ VREF ⎞
⎟=⎜ ⎟ 0111111111
− VREF ⎛⎜
⎝ 1024 ⎠ ⎝ 2 ⎠ 1 ⎞
⎟
0111111111 ⎝ 512 ⎠
− VREF ⎛⎜
511 ⎞
⎟ 0000000001
− VREF ⎛⎜
⎝ 1024 ⎠ 511 ⎞
⎟
0000000001 ⎝ 512 ⎠
− VREF ⎛⎜
1 ⎞
⎟ 0000000000
− VREF ⎛⎜
⎝ 1024 ⎠ 512 ⎞
⎟
0000000000 ⎝ 512 ⎠
− VREF ⎛⎜
0 ⎞
⎟=0
⎝ 1024 ⎠
Nominal LSB magnitude for the circuit of Figure 12 is given by

LSB = V REF ⎛⎜
Nominal LSB magnitude for the circuit of Figure 11 is given by 1 ⎞
⎟
⎝ 512 ⎠
LSB = V REF ⎛⎜
1 ⎞
⎟
⎝ 1024 ⎠
BIPOLAR
ANALOG INPUT
±10V VDD
BIPOLAR
ANALOG INPUT
±10V VDD R1 R4
1kΩ 20kΩ
VREF R2 R5
15 14 330Ω 20kΩ
R1 MSB
16
1kΩ 4 IOUT1 C1 R3
VREF R2 BIPOLAR 1 10kΩ
15 14 RFB 330Ω DIGITAL AD7533 A1
16 INPUT LSB 2 A2 VOUT
MSB 13
IOUT2
4 IOUT1 C1
UNIPOLAR 1 3
R6
DIGITAL AD7533 VOUT 5kΩ
INPUT LSB 2
13
IOUT2 GND
3
NOTES

01134-011
1. R3, R4, AND R5 SELECTED FOR MATCHING AND TRACKING.
2. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
3. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIERS.
GND
NOTES Figure 12. Bipolar Operation (4-Quadrant Multiplication)
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
01134-010

2. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED

WHEN USING HIGH SPEED AMPLIFIER.

Figure 11. Unipolar Binary Operation (2-Quadrant Multiplication)

Rev. C | Page 8 of 12
 AD7533

APPLICATIONS
BIPOLAR
ANALOG INPUT
±10V VDD

VREF
15 14 RFB 10kΩ 10kΩ
16
MSB
4 IOUT1 1/2 AD7512DIJN
1
MAGNITUDE
BITS AD7533 5kΩ VOUT
LSB 2
13
IOUT2 OP97 OP97
DIGITAL 3
INPUT GND

01134-012
SIGN BIT

Figure 13. 10-Bit and Sign Multiplying DAC

CALIBRATE 4.7kΩ
10V 1kΩ

SQUARE
6.8V OP97 WAVE
+15V
VDD (2) 10kΩ 10kΩ
NC 1% 1%
VREF Ct
15 14
16
MSB
DIGITAL 4 IOUT1
1
FREQUENCY
CONTROL AD7533 IOUT2
WORD LSB 2 TRIANGULAR
13 OP97 WAVE
3 1
f=N( )
8RtCt

01134-013
GND Rt = 10kΩ
0 < N ≤ (1 210)

Figure 14. Programmable Function Generator

+15V TEST INPUT

VREF +15V (0 TO – VREF )
VIN
RFB
16 14
MSB 15 14
IOUT2 4
BIT 1 16 AD790
2 MSB COMPARATOR
DIGITAL 4 IOUT1
AD7533 INPUT DIGITAL 1
FAIL/PASS
1 LSB “D” INPUT AD7533
IOUT1 13 (TEST LIMIT) LSB TEST
BIT 10 2
13
IOUT2
3 15
VREF –VIN 3
VOUT =
D

01134-016
GND where:
BIT 1 BIT 2 BIT 10
VOUT D= + + … 10 GND
21 22 2
01134-014

1023 Figure 17. Digitally Programmable Limit Detector

0<D≤
1024

Figure 15. Divider (Digitally Controlled Gain)

VREF

+15V .
R1
VOUT
15 14 RFB
16
BIT 1 MSB
4 IOUT1 R2
DIGITAL 1
INPUT AD7533 –VREFD
“D” LSB 2
13 IOUT2
BIT 10
3
R2 R1D
VOUT = VREF = –
R1 + R2 R1 + R2
GND
where:
BIT 1 BIT 2 BIT 10
D= + + … 10
21 22 2
01134-015

1023
0<D≤
1024

Figure 16. Modified Scale Factor and Offset

Rev. C | Page 9 of 12
AD7533

OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)

16 9 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
8
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC
0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001-AB

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

073106-B
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 18. 16-Lead Plastic Dual In-Line Package [PDIP]

(N-16)
Dimensions shown in inches and (millimeters)

10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)

BSC 45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013- AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
112906-B

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 19. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)
Dimensions shown in millimeters and (inches)

Rev. C | Page 10 of 12
 AD7533
0.005 (0.13) MIN 0.098 (2.49) MAX

16 9
0.310 (7.87)
1 0.220 (5.59)
8

PIN 1
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.840 (21.34) MAX
0.060 (1.52)
0.200 (5.08) 0.015 (0.38)
MAX
0.150
0.200 (5.08) (3.81)
0.125 (3.18) MIN
SEATING 0.015 (0.38)
0.023 (0.58) 0.070 (1.78) PLANE 15°
0.008 (0.20)
0.014 (0.36) 0.030 (0.76) 0°

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 20. 16-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-16)
Dimensions shown in inches and (millimeters)

0.200 (5.08)
0.075 (1.91) REF
0.100 (2.54) REF
0.100 (2.54) REF
0.064 (1.63) 0.095 (2.41) 0.015 (0.38)
0.075 (1.90) MIN
19 3
18 20 4
0.028 (0.71)
0.358 (9.09) 0.358 1
(9.09) 0.011 (0.28) 0.022 (0.56)
0.342 (8.69) BOTTOM
MAX 0.007 (0.18) VIEW
SQ SQ R TYP 0.050 (1.27)
14 8 BSC
0.075 (1.91) 13 9
REF
45° TYP
0.088 (2.24) 0.055 (1.40) 0.150 (3.81)
0.054 (1.37) 0.045 (1.14) BSC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

022106-A
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 21. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)

0.180 (4.57)
0.048 (1.22 ) 0.165 (4.19)
0.042 (1.07) 0.056 (1.42)
0.20 (0.51) 0.020 (0.50)
0.042 (1.07) MIN R
3 19
0.021 (0.53)
0.048 (1.22) 4 18
PIN 1 0.050 0.013 (0.33)
0.042 (1.07) IDENTIFIER 0.330 (8.38) BOTTOM
(1.27)
TOP VIEW BSC VIEW
0.032 (0.81) 0.290 (7.37) (PINS UP)
(PINS DOWN)
14
0.026 (0.66)
8
9 13
0.020 0.045 (1.14)
(0.51) 0.356 (9.04) R
R SQ 0.025 (0.64)
0.350 (8.89)
0.120 (3.04)
0.395 (10.03) 0.090 (2.29)
SQ
0.385 (9.78)

COMPLIANT TO JEDEC STANDARDS MO-047-AA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 22. 20-Lead Plastic Leaded Chip Carrier [PLCC]

(P-20)
Dimensions shown in inches and (millimeters)

Rev. C | Page 11 of 12
AD7533
ORDERING GUIDE
Nonlinearity
Model Temperature Range Package Description Package Option (% FSR max)
AD7533ACHIPS DIE
AD7533JN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.2
AD7533JNZ 1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.2
AD7533KN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.1
AD7533KNZ1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.1
AD7533LN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.05
AD7533LNZ1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.05
AD7533JP −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533JP-REEL −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533JPZ1 −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533JPZ-REEL1 −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533KP −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KP-REEL −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KPZ1 −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KPZ-REEL1 −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533KR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533KRZ1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533KRZ-REEL1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533AQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.2
AD7533BQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.1
AD7533CQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.05
AD7533SQ −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.2
AD7533UQ −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.05
AD7533UQ/883B −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.05
AD7533TE/883B −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1 ±0.1
1
Z = RoHS compliant part.

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