a 2.5 V to 5.

5 V, 500 ␮A, Quad Voltage Output

8-/10-/12-Bit DACs in 10-Lead microSOIC
AD5304/AD5314/AD5324*
FEATURES GENERAL DESCRIPTION
AD5304 The AD5304/AD5314/AD5324 are quad 8-, 10- and 12-bit
Four Buffered 8-Bit DACs in 10-Lead microSOIC buffered voltage output DACs in a 10-lead microSOIC package
AD5314 that operate from a single 2.5 V to 5.5 V supply consuming
Four Buffered 10-Bit DACs in 10-Lead microSOIC 500 µA at 3 V. Their on-chip output amplifiers allow rail-to-
AD5324 rail output swing to be achieved with a slew rate of 0.7 V/µs.
Four Buffered 12-Bit DACs in 10-Lead microSOIC A 3-wire serial interface is used which operates at clock rates
Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V up to 30 MHz and is compatible with standard SPI, QSPI,
2.5 V to 5.5 V Power Supply MICROWIRE and DSP interface standards.
Guaranteed Monotonic By Design Over All Codes The references for the four DACs are derived from one reference
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V pin. The outputs of all DACs may be updated simultaneously
Double-Buffered Input Logic using the software LDAC function. The parts incorporate a
Output Range: 0–V REF power-on-reset circuit that ensures that the DAC outputs power
Power-On-Reset to Zero Volts up to zero volts and remain there until a valid write takes place
Simultaneous Update of Outputs (LDAC Function) to the device. The parts contain a power-down feature that
Low Power, SPI™, QSPI™, MICROWIRE™, and reduces the current consumption of the device to 200 nA @ 5 V
DSP-Compatible 3-Wire Serial Interface (80 nA @ 3 V).
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40ⴗC to +105ⴗC The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
APPLICATIONS The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
Portable Battery-Powered Instruments to 1 µW in power-down mode.
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
FUNCTIONAL BLOCK DIAGRAM

VDD REFIN

LDAC

INPUT DAC STRING

REGISTER BUFFER VOUTA
REGISTER DAC A

SCLK INPUT DAC STRING

REGISTER REGISTER BUFFER VOUTB
DAC B
INTERFACE
SYNC LOGIC

INPUT DAC STRING

REGISTER REGISTER BUFFER VOUTC
DIN DAC C

INPUT DAC STRING

REGISTER REGISTER BUFFER VOUTD
DAC D

POWER-DOWN
POWER-ON LOGIC
RESET AD5304/AD5314/AD5324

GND

*Protected by U.S. Patent No. 5,969,657; other patents pending.

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD5304/AD5314/AD5324–SPECIFICATIONS (V
GND; CL = 200 pF to GND; All specifications TMIN to TMAX unless otherwise noted.)
DD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k⍀ to

B Version2
Parameter1 Min Typ Max Unit Conditions/Comments
3, 4
DC PERFORMANCE
AD5304
Resolution 8 Bits
Relative Accuracy ± 0.15 ±1 LSB
Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design Over All Codes
AD5314
Resolution 10 Bits
Relative Accuracy ± 0.5 ±4 LSB
Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design Over All Codes
AD5324
Resolution 12 Bits
Relative Accuracy ±2 ± 16 LSB
Differential Nonlinearity ± 0.2 ±1 LSB Guaranteed Monotonic by Design Over All Codes
Offset Error ± 0.4 ±3 % of FSR See Figures 2 and 3
Gain Error ± 0.15 ±1 % of FSR See Figures 2 and 3
Lower Deadband 20 60 mV Lower Deadband Exists Only If Offset Error Is Negative
Offset Error Drift5 –12 ppm of FSR/°C
Gain Error Drift5 –5 ppm of FSR/°C
DC Power Supply Rejection Ratio5 –60 dB ∆VDD = ± 10%
DC Crosstalk5 200 µV RL = 2 kΩ to GND or VDD
DAC REFERENCE INPUTS5
VREF Input Range 0.25 VDD V
VREF Input Impedance 37 45 kΩ Normal Operation
>10 MΩ Power-Down Mode
Reference Feedthrough –90 dB Frequency = 10 kHz
OUTPUT CHARACTERISTICS5
Minimum Output Voltage6 0.001 V This is a measure of the minimum and maximum drive
Maximum Output Voltage6 VDD – 0.001 V capability of the output amplifier.
DC Output Impedance 0.5 Ω
Short Circuit Current 25 mA VDD = 5 V
16 mA VDD = 3 V
Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V
5 µs Coming Out of Power-Down Mode. VDD = 3 V
LOGIC INPUTS5
Input Current ±1 µA
VIL, Input Low Voltage 0.8 V VDD = 5 V ± 10%
0.6 V VDD = 3 V ± 10%
0.5 V VDD = 2.5 V
VIH, Input High Voltage 2.4 V VDD = 5 V ± 10%
2.1 V VDD = 3 V ± 10%
2.0 V VDD = 2.5 V
Pin Capacitance 3 pF
POWER REQUIREMENTS
VDD 2.5 5.5 V
IDD (Normal Mode)7
VDD = 4.5 V to 5.5 V 600 900 µA VIH = VDD and VIL = GND
VDD = 2.5 V to 3.6 V 500 700 µA VIH = VDD and VIL = GND
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V 0.2 1 µA VIH = VDD and VIL = GND
VDD = 2.5 V to 3.6 V 0.08 1 µA VIH = VDD and VIL = GND
NOTES
1
See Terminology.
2
Temperature range: B Version: –40°C to +105°C; typical at 25°C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5304 (Code 8 to 248); AD5314 (Code 28 to 995); AD5324 (Code 115 to 3981).
5
Guaranteed by design and characterization, not production tested.
6
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage,
VREF = VDD and “Offset plus Gain” Error must be positive.
7
IDD specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
Specifications subject to change without notice.

–2– REV. B
 AD5304/AD5314/AD5324
(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless
AC CHARACTERISTICS1 otherwise noted.)
B Version3
2
Parameter Min Typ Max Unit Conditions/Comments
Output Voltage Settling Time VREF = VDD = 5 V
AD5304 6 8 µs 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
AD5314 7 9 µs 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
AD5324 8 10 µs 1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 1 nV-s
Digital Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p
Total Harmonic Distortion –70 dB VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology.
3
Temperature range: B Version: –40°C to +105°C; typical at 25°C.
Specifications subject to change without notice.

TIMING CHARACTERISTICS1, 2, 3 (V DD = 2.5 V to 5.5 V. All specifications TMIN to TMAX unless otherwise noted)
Limit at TMIN, TMAX
Parameter VDD = 2.5 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments
t1 40 33 ns min SCLK Cycle Time
t2 16 13 ns min SCLK High Time
t3 16 13 ns min SCLK Low Time
t4 0 0 ns min SYNC to SCLK Rising Edge Setup Time
t5 5 5 ns min Data Setup Time
t6 4.5 4.5 ns min Data Hold Time
t7 0 0 ns min SCLK Falling Edge to SYNC Rising Edge
t8 80 33 ns min Minimum SYNC High Time
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2.
3
See Figure 1.
Specifications subject to change without notice.

t1

SCLK
t2
t8 t3 t7
t4
SYNC
t6
t5

DIN DB15 DB0

Figure 1. Serial Interface Timing Diagram

REV. B –3–
AD5304/AD5314/AD5324
ABSOLUTE MAXIMUM RATINGS1, 2 PIN CONFIGURATION
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V VDD 1 10 SYNC

Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V VOUTA 2 AD5304/ 9 SCLK
AD5314/
VOUTA–D to GND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V VOUTB 3 AD5324 8 DIN
Operating Temperature Range VOUTC 4 TOP VIEW 7 GND
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C REFIN 5 (Not to Scale) 6 VOUTD
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
10-Lead microSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . (TJ max – TA)/θJA
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function
1 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND.
2 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
3 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
4 VOUTC Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to VDD.
6 VOUTD Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
7 GND Ground Reference Point for All Circuitry on the Part.
8 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input. The DIN input buffer is powered down after each write cycle.
9 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
10 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. If SYNC is
taken high before the sixteenth falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the device.

ORDERING GUIDE

Temperature Package Package Branding

Model Range Description Option Information
AD5304BRM –40°C to +105°C 10-Lead microSOIC RM-10 DBB
AD5314BRM –40°C to +105°C 10-Lead microSOIC RM-10 DCB
AD5324BRM –40°C to +105°C 10-Lead microSOIC RM-10 DDB

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD5304/AD5314/AD5324 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. B
 AD5304/AD5314/AD5324
TERMINOLOGY DIGITAL CROSSTALK
RELATIVE ACCURACY This is the glitch impulse transferred to the output of one DAC
For the DAC, relative accuracy or integral nonlinearity (INL) is at midscale in response to a full-scale code change (all 0s to all
a measure of the maximum deviation, in LSBs, from a straight 1s and vice versa) in the input register of another DAC. It is
line passing through the endpoints of the DAC transfer function. expressed in nV-secs.
Typical INL versus Code plots can be seen in Figures 4, 5, and 6.
DAC-TO-DAC CROSSTALK
DIFFERENTIAL NONLINEARITY This is the glitch impulse transferred to the output of one DAC
Differential Nonlinearity (DNL) is the difference between the due to a digital code change and subsequent output change of
measured change and the ideal 1 LSB change between any two another DAC. This includes both digital and analog crosstalk. It
adjacent codes. A specified differential nonlinearity of ± 1 LSB is measured by loading one of the DACs with a full-scale code
maximum ensures monotonicity. This DAC is guaranteed mono- change (all 0s to all 1s and vice versa) with the LDAC bit set low
tonic by design. Typical DNL versus Code plots can be seen in and monitoring the output of another DAC. The energy of the
Figures 7, 8, and 9. glitch is expressed in nV-secs.

OFFSET ERROR MULTIPLYING BANDWIDTH

This is a measure of the offset error of the DAC and the output The amplifiers within the DAC have a finite bandwidth. The
amplifier. It is expressed as a percentage of the full-scale range. multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
GAIN ERROR the output. The multiplying bandwidth is the frequency at which
This is a measure of the span error of the DAC. It is the devia- the output amplitude falls to 3 dB below the input.
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range. TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated
OFFSET ERROR DRIFT version using the DAC. The sine wave is used as the reference
This is a measure of the change in offset error with changes in for the DAC and the THD is a measure of the harmonics present
temperature. It is expressed in (ppm of full-scale range)/°C. on the DAC output. It is measured in dBs.
GAIN ERROR
GAIN ERROR DRIFT OUTPUT IDEAL PLUS
VOLTAGE OFFSET ERROR
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
ACTUAL

POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to NEGATIVE
OFFSET DAC CODE
a change in VDD for full-scale output of the DAC. It is measured ERROR
in dBs. VREF is held at 2 V and VDD is varied ± 10%.
DEADBAND CODES
DC CROSSTALK
AMPLIFIER
This is the dc change in the output level of one DAC at midscale FOOTROOM
in response to a full-scale code change (all 0s to all 1s and vice (1mV)

versa) and output change of another DAC. It is expressed in µV. NEGATIVE

OFFSET
ERROR
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being Figure 2. Transfer Function with Negative Offset
updated. It is expressed in dBs.

MAJOR-CODE TRANSITION GLITCH ENERGY

GAIN ERROR
Major-code transition glitch energy is the energy of the impulse PLUS
ACTUAL OFFSET ERROR
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the OUTPUT
glitch in nV-secs and is measured when the digital code is changed VOLTAGE
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).
IDEAL
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected into the POSITIVE
OFFSET
analog output of the DAC from the digital input pins of the device DAC CODE
when the DAC output is not being written to (SYNC held high). It
is specified in nV-secs and is measured with a worst-case change on Figure 3. Transfer Function with Positive Offset
the digital input pins, e.g., from all 0s to all 1s or vice versa.

REV. B –5–
AD5304/AD5314/AD5324
1.0 3 12
TA = 25ⴗC
TA = 25ⴗC TA = 25ⴗC
VDD = 5V
VDD = 5V 2 8 VDD = 5V

0.5

INL ERROR – LSBs

INL ERROR – LSBs

INL ERROR – LSBs

1 4

0 0 0

–1 –4
–0.5
–2 –8

–1.0 –3 –12
0 50 100 150 200 250 0 200 400 600 800 1000 0 1000 2000 3000 4000
CODE CODE CODE

Figure 4. AD5304 Typical INL Plot Figure 5. AD5314 Typical INL Plot Figure 6. AD5324 Typical INL Plot

0.3 0.6 1
TA = 25ⴗC TA = 25ⴗC TA = 25ⴗC
VDD = 5V VDD = 5V VDD = 5V
0.2 0.4
0.5

DNL ERROR – LSBs

DNL ERROR – LSBs

DNL ERROR – LSBs

0.1 0.2

0 0 0

–0.1 –0.2
–0.5
–0.2 –0.4

–0.3 –0.6 –1
0 50 100 150 200 250 0 200 400 600 800 1000 0 1000 2000 3000 4000
CODE CODE CODE

Figure 7. AD5304 Typical DNL Plot Figure 8. AD5314 Typical DNL Plot Figure 9. AD5324 Typical DNL Plot

0.5 0.5 1
VDD = 5V 0.4 VDD = 5V VDD = 5V
TA = 25ⴗC VREF = 3V VREF = 2V
MAX INL MAX INL
0.3
0.25 0.5
0.2
ERROR – LSBs

ERROR – LSBs

MAX DNL
MAX DNL
ERROR – %

0.1 GAIN ERROR

0 0 0
–0.1
MIN DNL MIN DNL OFFSET ERROR
–0.2
–0.25 –0.5
–0.3
MIN INL MIN INL
–0.4

–0.5 –0.5 –1
0 1 2 3 4 5 ⴚ40 0 40 80 120 ⴚ40 0 40 80 120
VREF – V TEMPERATURE – ⴰC TEMPERATURE – ⴰC

Figure 10. AD5304 INL and DNL Figure 11. AD5304 INL Error and Figure 12. AD5304 Offset Error and
Error vs. VREF DNL Error vs. Temperature Gain Error vs. Temperature

–6– REV. B
 AD5304/AD5314/AD5324
0.2 5 600
TA = 25ⴰC
0.1 TA = 25ⴰC VDD = 5V
VREF = 2V 5V SOURCE 500 VREF = 2V
4
0 GAIN ERROR
3V SOURCE 400

VOUT – Volts
–0.1
ERROR – %

IDD – ␮A
–0.2 300

2
–0.3
200
–0.4 OFFSET ERROR
1 3V SINK
100
–0.5 5V SINK

–0.6 0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6 ZERO – SCALE FULL – SCALE
VDD – Volts SINK/SOURCE CURRENT – mA CODE

Figure 13. Offset Error and Gain Figure 14. VOUT Source and Sink Figure 15. Supply Current vs. DAC
Error vs. VDD Current Capability Code

600 0.5 1000

ⴚ40ⴰC TA = 25ⴗC
500 900
0.4
+25ⴰC
400 +105ⴰC 800
0.3
IDD – ␮A

IDD – ␮A

IDD – ␮A
300 700
ⴚ40ⴰC
VDD = 5V
0.2
200 ⴙ25ⴰC 600

0.1 500
100
VDD = 3V
ⴙ105ⴰC

0 0 400
2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD – Volts VDD – Volts VLOGIC – Volts

Figure 16. Supply Current vs. Supply Figure 17. Power-Down Current vs. Figure 18. Supply Current vs. Logic
Voltage Supply Voltage Input Voltage

TA = 25ⴰC TA = 25ⴰC TA = 25ⴰC

5µs
VDD = 5V VDD = 5V VDD = 5V
VREF = 5V VREF = 2V VREF = 2V
CH1 CH1 CH1
VOUTA VDD VOUTA

SCLK
VOUTA
CH2 CH2 CH2 SCLK

CH1 1V, CH2 5V, TIME BASE= 1␮s/DIV CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV CH1 500mV, CH2 5V, TIME BASE= 1␮s/DIV

Figure 19. Half-Scale Settling (1/4 to Figure 20. Power-On Reset to 0 V Figure 21. Exiting Power-Down to
3/4 Scale Code Change) Midscale

REV. B –7–
AD5304/AD5314/AD5324
2.50 10

–10
VDD = 3V VDD = 5V 2.49
FREQUENCY

VOUT – Volts
–20

dB
–30
2.48
–40

–50

2.47 –60
300 350 400 450 500 550 600 1␮s/DIV 0.01 0.1 1 10 100 1k 10k
IDD – ␮A FREQUENCY – kHz

Figure 22. IDD Histogram with Figure 23. AD5324 Major-Code Figure 24. Multiplying Bandwidth
VDD = 3 V and VDD = 5 V Transition Glitch Energy (Small-Signal Frequency Response)

0.02
VDD = 5V
TA = 25ⴗC
FULL-SCALE ERROR – Volts

0.01
1mV/DIV

–0.01

–0.02
0 1 2 3 4 5 6
150ns/DIV
VREF – Volts

Figure 25. Full-Scale Error vs. VREF Figure 26. DAC-to-DAC Crosstalk

–8– REV. B
 AD5304/AD5314/AD5324
FUNCTIONAL DESCRIPTION DAC Reference Inputs
The AD5304/AD5314/AD5324 are quad resistor-string DACs There is a single reference input pin for the four DACs. The
fabricated on a CMOS process with resolutions of 8, 10, and 12 reference input is unbuffered. The user can have a reference
bits respectively. Each contains four output buffer amplifiers and voltage as low as 0.25 V and as high as VDD since there is no
is written to via a 3-wire serial interface. They operate from restriction due to headroom and footroom of any reference
single supplies of 2.5 V to 5.5 V and the output buffer amplifiers amplifier.
provide rail-to-rail output swing with a slew rate of 0.7 V/µs. The It is recommended to use a buffered reference in the external
four DACs share a single reference input pin. The devices have circuit (e.g., REF192). The input impedance is typically 45 kΩ.
programmable power-down modes, in which all DACs may be
turned off completely with a high-impedance output. Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail
Digital-to-Analog Section voltages on its output, which gives an output range of 0 V to VDD
The architecture of one DAC channel consists of a resistor-string when the reference is VDD. It is capable of driving a load of
DAC followed by an output buffer amplifier. The voltage at the 2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD.
REFIN pin provides the reference voltage for the DAC. Figure The source and sink capabilities of the output amplifier can be
27 shows a block diagram of the DAC architecture. Since the seen in the plot in Figure 14.
input coding to the DAC is straight binary, the ideal output
voltage is given by: The slew rate is 0.7 V/µs with a half-scale settling time to
± 0.5 LSB (at 8 bits) of 6 µs.
VREF × D
VOUT =
2N POWER-ON RESET
where The AD5304/AD5314/AD5324 are provided with a power-on
reset function, so that they power up in a defined state. The
D = decimal equivalent of the binary code, which is loaded to the
power-on state is:
DAC register;
– Normal operation.
0–255 for AD5304 (8 Bits)
– Output voltage set to 0 V.
0–1023 for AD5314 (10 Bits)
0–4095 for AD5324 (12 Bits) Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
N = DAC resolution
REFIN
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.

SERIAL INTERFACE
INPUT DAC RESISTOR VOUTA
The AD5304/AD5314/AD5324 are controlled over a versatile,
REGISTER REGISTER STRING
3-wire serial interface, which operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
OUTPUT BUFFER interface standards.
AMPLIFIER

Figure 27. DAC Channel Architecture Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the
Resistor String device as a 16-bit word under the control of a serial clock input,
The resistor string section is shown in Figure 28. It is simply a SCLK. The timing diagram for this operation is shown in Figure 1.
string of resistors, each of value R. The digital code loaded to the The 16-bit word consists of four control bits followed by 8, 10,
DAC register determines at which node on the string the voltage or 12 bits of DAC data, depending on the device type. Data
is tapped off to be fed into the output amplifier. The voltage is is loaded MSB first (Bit 15) and the first two bits determine
tapped off by closing one of the switches connecting the string to whether the data is for DAC A, DAC B, DAC C, or DAC D.
the amplifier. Because it is a string of resistors, it is guaranteed Bits 13 and 12 control the operating mode of the DAC. Bit 13 is
monotonic. PD, which determines whether the part is in normal or power-
R
down mode. Bit 12 is LDAC, which controls when DAC registers
and outputs are updated.
R
Table I. Address Bits for the AD53x4
TO OUTPUT
R AMPLIFIER
A1 A0 DAC Addressed
0 0 DAC A
0 1 DAC B
R
1 0 DAC C
1 1 DAC D
R

Figure 28. Resistor String

REV. B –9–
AD5304/AD5314/AD5324
BIT15 BIT0
(MSB) (LSB)
A1 A0 PD LDAC D7 D6 D5 D4 D3 D2 D1 D0 X X X X

DATA BITS

Figure 29. AD5304 Input Shift Register Contents

BIT15 BIT0
(MSB) (LSB)
A1 A0 PD LDAC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

DATA BITS

Figure 30. AD5314 Input Shift Register Contents

BIT15 BIT0
(MSB) (LSB)
A1 A0 PD LDAC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

Figure 31. AD5324 Input Shift Register Contents

Address and Control Bits Low-Power Serial Interface

PD: 0: All four DACs go into power-down mode consuming To reduce the power consumption of the device even further, the
only 200 nA @ 5 V. The DAC outputs enter a high- interface only powers up fully when the device is being written
impedance state. to, i.e., on the falling edge of SYNC. As soon as the 16-bit control
1: Normal operation. word has been written to the part, the SCLK and DIN input
LDAC: 0: All four DAC registers and hence all DAC outputs buffers are powered down. They only power up again following
updated simultaneously on completion of the write a falling edge of SYNC.
sequence. Double-Buffered Interface
1: Addressed input register only is updated. There is The AD5304/AD5314/AD5324 DACs all have double-buffered
no change in the content of the DAC registers. interfaces consisting of two banks of registers—input registers
The AD5324 uses all 12 bits of DAC data, the AD5314 uses and DAC registers. The input register is directly connected to
10 bits and ignores the two LSBs. The AD5304 uses eight bits the input shift register and the digital code is transferred to the
and ignores the last four bits. The data format is straight binary, relevant input register on completion of a valid write sequence.
with all zeros corresponding to 0 V output and all ones corre- The DAC register contains the digital code used by the resis-
sponding to full-scale output (VREF –1 LSB). tor string.

The SYNC input is a level-triggered input that acts as a frame Access to the DAC register is controlled by the LDAC bit. When
synchronization signal and chip enable. Data can only be trans- the LDAC bit is set high, the DAC register is latched and hence
ferred into the device while SYNC is low. To start the serial data the input register may change state without affecting the contents
transfer, SYNC should be taken low, observing the minimum of the DAC register. However, when the LDAC bit is set low,
SYNC to SCLK active edge setup time, t4. After SYNC goes low, all DAC registers are updated after a complete write sequence.
serial data will be shifted into the device's input shift register on This is useful if the user requires simultaneous updating of all DAC
the falling edges of SCLK for sixteen clock pulses. Any data and outputs. The user may write to three of the input registers indi-
clock pulses after the sixteenth falling edge of SCLK will be vidually and then, by setting the LDAC bit low when writing
ignored because the SCLK and DIN input buffers are powered to the remaining DAC input register, all outputs will update
down. No further serial data transfer will occur until SYNC is simultaneously.
taken high and low again. These parts contain an extra feature whereby the DAC register
SYNC may be taken high after the falling edge of the sixteenth is not updated unless its input register has been updated since
SCLK pulse, observing the minimum SCLK falling edge to the last time that LDAC was brought low. Normally, when LDAC
SYNC rising edge time, t7. is brought low, the DAC registers are filled with the contents of
After the end of serial data transfer, data will automatically be the input registers. In the case of the AD5304/AD5314/AD5324,
transferred from the input shift register to the input register of the part will only update the DAC register if the input register
the selected DAC. If SYNC is taken high before the sixteenth has been changed since the last time the DAC register was
falling edge of SCLK, the data transfer will be aborted and the updated, thereby removing unnecessary digital crosstalk.
DAC input registers will not be updated.
POWER-DOWN MODE
When data has been transferred into three of the DAC input The AD5304/AD5314/AD5324 have low power consumption,
registers, all DAC registers and all DAC outputs may simulta- dissipating only 1.5 mW with a 3 V supply and 3 mW with a 5 V
neously be updated by setting LDAC low when writing to the supply. Power consumption can be further reduced when the
remaining DAC input register. DACs are not in use by putting them into power-down mode,
which is selected by a zero on Bit 13 (PD) of the control word.

–10– REV. B
 AD5304/AD5314/AD5324
When the PD bit is set to 1, all DACs work normally with a AD5304/AD5314/AD5324 to 68HC11/68L11 Interface
typical power consumption of 600 µA at 5 V (500 µA at 3 V). Figure 34 shows a serial interface between the AD5304/AD5314/
However, in power-down mode, the supply current falls to 200 nA AD5324 and the 68HC11/68L11 microcontroller. SCK of the
at 5 V (80 nA at 3 V) when all DACs are powered down. Not 68HC11/68L11 drives the SCLK of the AD5304/AD5314/
only does the supply current drop, but the output stage is also AD5324, while the MOSI output drives the serial data line (DIN)
internally switched from the output of the amplifier making it of the DAC. The SYNC signal is derived from a port line (PC7).
open-circuit. This has the advantage that the output is three- The setup conditions for correct operation of this interface are
stated while the part is in power-down mode, and provides a as follows: the 68HC11/68L11 should be configured so that its
defined input condition for whatever is connected to the output CPOL bit is a 0 and its CPHA bit is a 1. When data is being
of the DAC amplifier. The output stage is illustrated in Figure 32. transmitted to the DAC, the SYNC line is taken low (PC7).
The bias generator, the output amplifier, the resistor string, and When the 68HC11/68L11 is configured as above, data appearing
all other associated linear circuitry are all shut down when the on the MOSI output is valid on the falling edge of SCK. Serial
power-down mode is activated. However, the contents of the data from the 68HC11/68L11 is transmitted in 8-bit bytes with
registers are unaffected when in power-down. The time to exit only eight falling clock edges occurring in the transmit cycle. Data
power-down is typically 2.5 µs for VDD = 5 V and 5 µs when is transmitted MSB first. In order to load data to the AD5304/
VDD = 3 V. This is the time from the falling edge of the sixteenth AD5314/AD5324, PC7 is left low after the first eight bits are
SCLK pulse to when the output voltage deviates from its power- transferred, a second serial write operation is performed to the
down voltage. See Figure 21 for a plot. DAC, and PC7 is taken high at the end of this procedure.

68HC11/68L11* AD5304/
AD5314/
RESISTOR
AMPLIFIER VOUT
AD5324*
STRING DAC
PC7 SYNC

SCK SCLK

MOSI DIN
POWER-DOWN
CIRCUITRY
*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 32. Output Stage During Power-Down Figure 34. AD5304/AD5314/AD5324 to 68HC11/68L11
Interface
MICROPROCESSOR INTERFACING
AD5304/AD5314/AD5324 to 80C51/80L51 Interface
AD5304/AD5314/AD5324 to ADSP-2101/ADSP-2103 Interface
Figure 35 shows a serial interface between the AD5304/AD5314/
Figure 33 shows a serial interface between the AD5304/AD5314/
AD5324 and the 80C51/80L51 microcontroller. The setup for
AD5324 and the ADSP-2101/ADSP-2103. The ADSP-2101/
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
ADSP-2103 should be set up to operate in the SPORT Transmit
of the AD5304/AD5314/AD5324, while RxD drives the serial
Alternate Framing Mode. The ADSP-2101/ADSP-2103 SPORT
data line of the part. The SYNC signal is again derived from a
is programmed through the SPORT control register and should
bit-programmable pin on the port. In this case port line P3.3 is
be configured as follows: Internal Clock Operation, Active-Low
used. When data is to be transmitted to the AD5304/AD5314/
Framing, 16-Bit Word Length. Transmission is initiated by writing
AD5324, P3.3 is taken low. The 80C51/80L51 transmits data
a word to the Tx register after the SPORT has been enabled.
only in 8-bit bytes; thus only eight falling clock edges occur in
The data is clocked out on each rising edge of the DSP’s serial
the transmit cycle. To load data to the DAC, P3.3 is left low
clock and clocked into the AD5304/AD5314/AD5324 on the
after the first eight bits are transmitted, and a second write cycle
falling edge of the DAC’s SCLK.
is initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
ADSP-2101/ AD5304/ the serial data in a format which has the LSB first. The AD5304/
ADSP-2103* AD5314/
AD5324* AD5314/AD5324 requires its data with the MSB as the first bit
received. The 80C51/80L51 transmit routine should take this
TFS SYNC
into account.
DT DIN

SCLK SCLK
80C51/80L51* AD5304/
AD5314/
*ADDITIONAL PINS OMITTED FOR CLARITY. AD5324*
Figure 33. AD5304/AD5314/AD5324 to ADSP-2101/ P3.3 SYNC
ADSP-2103 Interface TxD SCLK

RxD DIN

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 35. AD5304/AD5314/AD5324 to 80C51/80L51

Interface

REV. B –11–
AD5304/AD5314/AD5324
AD5304/AD5314/AD5324 to MICROWIRE Interface The load regulation of the REF195 is typically 2 ppm/mA, which
Figure 36 shows an interface between the AD5304/AD5314/ results in an error of 5.4 ppm (27 µV) for the 2.7 mA current
AD5324 and any MICROWIRE-compatible device. Serial data is drawn from it. This corresponds to a 0.0014 LSB error at 8 bits
shifted out on the falling edge of the serial clock, SK and is and 0.022 LSB error at 12 bits.
clocked into the AD5304/AD5314/AD5324 on the rising edge Bipolar Operation Using the AD5304/AD5314/AD5324
of SK, which corresponds to the falling edge of the DAC’s SCLK. The AD5304/AD5314/AD5324 have been designed for single-
supply operation, but a bipolar output range is also possible
MICROWIRE* AD5304/ using the circuit in Figure 38. This circuit will give an output
AD5314/ voltage range of ±5 V. Rail-to-rail operation at the amplifier output
AD5324*
is achievable using an AD820 or an OP295 as the output amplifier.
CS SYNC

SK SCLK
R2 = 10k⍀
SO DIN
+5V
6V TO 16V R1 = 10k⍀
*ADDITIONAL PINS OMITTED FOR CLARITY.
10␮F 0.1␮F AD820/ ⴞ5V
Figure 36. AD5304/AD5314/AD5324 to MICROWIRE 5V OP295
VDD VOUTA
Interface
REF195 AD5304 –5V
APPLICATIONS VIN VOUTB
VOUT REFIN
Typical Application Circuit
GND 1␮F VOUTC
The AD5304/AD5314/AD5324 can be used with a wide range
of reference voltages where the devices offer full, one-quadrant VOUTD
multiplying capability over a reference range of 0 V to VDD. GND
More typically, these devices are used with a fixed, precision DIN SCLK SYNC

reference voltage. Suitable references for 5 V operation are the

AD780 and REF192 (2.5 V references). For 2.5 V operation, a SERIAL
suitable external reference would be the AD589, a 1.23 V band- INTERFACE

gap reference. Figure 37 shows a typical setup for the AD5304/

AD5314/AD5324 when using an external reference.
Figure 38. Bipolar Operation with the AD5304
VDD = 2.5V TO 5.5V The output voltage for any input code can be calculated as
follows:
0.1␮F 10␮F
AD5304/ VOUT = [(REFIN × D/2N) × (R1+R2)/R1 – REFIN × (R2/R1)]
AD5314/
AD5324
where:
VIN VOUTA D is the decimal equivalent of the code loaded to the DAC.
VOUT REFIN
EXT VOUTB N is the DAC resolution.
1␮F
REF
SCLK VOUTC
REFIN is the reference voltage input.
AD780/REF192 DIN
WITH VDD = 5V with:
OR AD589 WITH SYNC VOUTD
VDD = 2.5V REFIN = 5 V, R1 = R2 = 10 kΩ:
A0 GND
VOUT = (10 × D/2N) – 5 V
SERIAL Opto-Isolated Interface for Process Control Applications
INTERFACE
The AD5304/AD5314/AD5324 have a versatile 3-wire serial
Figure 37. AD5304/AD5314/AD5324 Using External interface making them ideal for generating accurate voltages
Reference in process control and industrial applications. Due to noise,
If an output range of 0 V to VDD is required, the simplest solu- safety requirements or distance, it may be necessary to isolate
tion is to connect the reference input to VDD. As this supply may the AD5304/AD5314/AD5324 from the controller. This can easily
not be very accurate and may be noisy, the AD5304/AD5314/ be achieved by using opto-isolators, which will provide isolation in
AD5324 may be powered from the reference voltage; for example, excess of 3 kV. The actual data rate achieved may be limited by
using a 5 V reference such as the REF195. The REF195 will the type of optocouplers chosen. The serial loading structure
output a steady supply voltage for the AD5304/AD5314/AD5324. of the AD5304/AD5314/ AD5324 makes them ideally suited for
The current required from the REF195 is 600 µA supply current use in opto-isolated applications. Figure 39 shows an opto-iso-
and approximately 112 µA into the reference input. This is with no lated interface to the AD5304 where DIN, SCLK, and SYNC
load on the DAC outputs. When the DAC outputs are loaded, the are driven from optocouplers. The power supply to the part
REF195 also needs to supply the current to the loads. The total also needs to be isolated. This is done by using a transformer. On
current required (with a 10 kΩ load on each output) is: the DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5304.
712 µA + 4(5 V/10 kΩ) = 2.70 mA

–12– REV. B
 AD5304/AD5314/AD5324
AD5304/AD5314/AD5324 as a Digitally Programmable
5V
REGULATOR Window Detector
POWER 10␮F 0.1␮F
A digitally programmable upper/lower limit detector using two
VDD of the DACs in the AD5304/AD5314/AD5324 is shown in
Figure 41. The upper and lower limits for the test are loaded to
10k⍀ VDD
SCLK
DACs A and B which, in turn, set the limits on the CMP04. If
SCLK
the signal at the VIN input is not within the programmed window,
REFIN an LED will indicate the fail condition. Similarly, DACs C and
D can be used for window detection on a second VIN signal.
VDD AD5304
10k⍀ 5V
VOUTA
SYNC 0.1␮F 10␮F 1k⍀ 1k⍀
SYNC VOUTB VIN
VOUTC
FAIL PASS
VOUTD
VDD
VREF REFIN
VDD
VOUTA
10k⍀
1/2
DIN DIN AD5304/ 1/2
PASS/FAIL
SYNC SYNC AD5314/ CMP04
GND
DIN
AD5324*
DIN
SCLK SCLK VOUTB
1/6 74HC05
GND
Figure 39. AD5304 in an Opto-Isolated Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Decoding Multiple AD5304/AD5314/AD5324s
The SYNC pin on the AD5304/AD5314/AD5324 can be used Figure 41. Window Detection
in applications to decode a number of DACs. In this application,
all the DACs in the system receive the same serial clock and POWER SUPPLY BYPASSING AND GROUNDING
serial data, but the SYNC to only one of the devices will be active In any circuit where accuracy is important, careful consideration
at any one time, allowing access to four channels in this 16- of the power supply and ground return layout helps to ensure the
channel system. The 74HC139 is used as a 2-to-4-line decoder rated performance. The printed circuit board on which the
to address any of the DACs in the system. To prevent timing AD5304/AD5314/AD5324 is mounted should be designed so
errors, the enable input should be brought to its inactive state that the analog and digital sections are separated, and confined
while the coded address inputs are changing state. Figure 40 to certain areas of the board. If the AD5304/AD5314/AD5324
shows a diagram of a typical setup for decoding multiple is in a system where multiple devices require an AGND-to-DGND
AD5304 devices in a system. connection, the connection should be made at one point only.
The star ground point should be established as close as possible
SCLK AD5304
to the device. The AD5304/AD5314/AD5324 should have ample
DIN SYNC VOUTA supply bypassing of 10 µF in parallel with 0.1 µF on the supply
VDD VOUTB located as close to the package as possible, ideally right up against
DIN VOUTC
VOUTD the device. The 10 µF capacitors are the tantalum bead type. The
SCLK
VCC
0.1 µF capacitor should have low Effective Series Resistance
ENABLE 1G 1Y0 (ESR) and Effective Series Inductance (ESI), like the common
AD5304
CODED
1A 1Y1 SYNC VOUTA ceramic types that provide a low impedance path to ground at
VOUTB
ADDRESS 1B 74HC139 1Y2 DIN VOUTC
high frequencies, to handle transient currents due to internal logic
1Y3 SCLK VOUTD switching.
DGND
The power supply lines of the AD5304/AD5314/AD5324 should
AD5304
SYNC VOUTA
use as large a trace as possible to provide low impedance paths
VOUTB and reduce the effects of glitches on the power supply line. Fast
DIN VOUTC
VOUTD
switching signals such as clocks should be shielded with digital
SCLK
ground to avoid radiating noise to other parts of the board, and
AD5304 should never be run near the reference inputs. Avoid crossover
SYNC VOUTA of digital and analog signals. Traces on opposite sides of the
DIN
VOUTB board should run at right angles to each other. This reduces the
VOUTC
VOUTD effects of feedthrough through the board. A microstrip technique is
SCLK
by far the best, but not always possible with a double-sided
Figure 40. Decoding Multiple AD5304 Devices in a System board. In this technique, the component side of the board is
dedicated to ground plane while signal traces are placed on the
solder side.

REV. B –13–
AD5304/AD5314/AD5324
Table II. Overview of All AD53xx Serial Devices

No. of Settling
Part No. Resolution DACs DNL Interface Time Package Pins
SINGLES
AD5300 8 1 ± 0.25 SPI 4 µs SOT-23, microSOIC 6, 8
AD5310 10 1 ± 0.5 SPI 6 µs SOT-23, microSOIC 6, 8
AD5320 12 1 ± 1.0 SPI 8 µs SOT-23, microSOIC 6, 8
AD5301 8 1 ± 0.25 2-Wire 6 µs SOT-23, microSOIC 6, 8
AD5311 10 1 ± 0.5 2-Wire 7 µs SOT-23, microSOIC 6, 8
AD5321 12 1 ± 1.0 2-Wire 8 µs SOT-23, microSOIC 6, 8
DUALS
AD5302 8 2 ± 0.25 SPI 6 µs microSOIC 8
AD5312 10 2 ± 0.5 SPI 7 µs microSOIC 8
AD5322 12 2 ± 1.0 SPI 8 µs microSOIC 8
AD5303 8 2 ± 0.25 SPI 6 µs TSSOP 16
AD5313 10 2 ± 0.5 SPI 7 µs TSSOP 16
AD5323 12 2 ± 1.0 SPI 8 µs TSSOP 16
QUADS
AD5304 8 4 ± 0.25 SPI 6 µs microSOIC 10
AD5314 10 4 ± 0.5 SPI 7 µs microSOIC 10
AD5324 12 4 ± 1.0 SPI 8 µs microSOIC 10
AD5305 8 4 ± 0.25 2-Wire 6 µs microSOIC 10
AD5315 10 4 ± 0.5 2-Wire 7 µs microSOIC 10
AD5325 12 4 ± 1.0 2-Wire 8 µs microSOIC 10
AD5306 8 4 ± 0.25 2-Wire 6 µs TSSOP 16
AD5316 10 4 ± 0.5 2-Wire 7 µs TSSOP 16
AD5326 12 4 ± 1.0 2-Wire 8 µs TSSOP 16
AD5307 8 4 ± 0.25 SPI 6 µs TSSOP 16
AD5317 10 4 ± 0.5 SPI 7 µs TSSOP 16
AD5327 12 4 ± 1.0 SPI 8 µs TSSOP 16
Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html

–14– REV. B
 AD5304/AD5314/AD5324
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

10-Lead microSOIC
(RM-10)

C3721a–2.5–6/00 (rev. B) 00929

0.122 (3.10)
0.114 (2.90)

10 6
0.122 (3.10) 0.199 (5.05)
0.114 (2.90) 0.187 (4.75)
1 5

PIN 1
0.0197 (0.50) BSC
0.120 (3.05) 0.120 (3.05)
0.112 (2.85) 0.112 (2.85)
0.037 (0.94) 0.043 (1.10)
0.031 (0.78) MAX
6ⴗ
0.006 (0.15) 0.012 (0.30) SEATING 0ⴗ 0.028 (0.70)
PLANE 0.009 (0.23)
0.002 (0.05) 0.006 (0.15) 0.016 (0.40)
0.005 (0.13)

PRINTED IN U.S.A.

REV. B –15–