a +3 V, Dual, Serial Input

12-/10-Bit DACs
AD7394/AD7395
FEATURES FUNCTIONAL BLOCK DIAGRAM
Micropower: 100 mA/DAC
0.1 mA Typical Power Shutdown VDD VREF

Single-Supply +2.7 V to +5.5 V Operation

OP
Compact 1.1 mm Height TSSOP-14 Package R
E AMP A
CS EN D G
AD7394/12-Bit Resolution A I
C S DAC A VOUTA
AD7395/10-Bit Resolution CLK
T
A E
Serial Interface with Schmitt Trigger Inputs R
D
SDI
APPLICATIONS (DATA) R P R
S E
Automotive Output Span Voltage H G 12
I I
Portable Communications F S
T
AD7394/AD7395
T
Digitally Controlled Calibration E
R R
PC Peripherals D E
D G
A I
C S OP
T AMP B
B E
LDA R
DAC B VOUTB
LDB P R
GENERAL DESCRIPTION
The AD7394/AD7395 family of dual, 12-/10-bit, voltage output
digital-to-analog converters is designed to operate from a single
+3 V supply. Built using a CBCMOS process, this monolithic DGND MSB RS AGND SHDN
DAC offers the user low cost and ease of use in single-supply
+3 V systems. Operation is guaranteed over the supply voltage
range of +2.7 V to +5.5 V making this device ideal for battery The AD7394/AD7395 is specified over the extended industrial
operated applications. (–40°C to +85°C) temperature range. Packages available in-
clude plastic DIP and low profile 1.75 mm height SO-14 surface
The full-scale output voltage is determined by the applied exter-
mount packages. The AD7395ARU is available for ultracompact
nal reference input voltage, VREF. The rail-to-rail VREF input
applications in a thin 1.1 mm TSSOP-14 package. For automotive
to VOUT outputs allows for a full-scale voltage set equal to the
applications the AD7395AR is specified for operation over the
positive supply VDD or any value in between.
(–40°C to +125°C) temperature range.
A doubled-buffered serial data interface offers high speed,
microcontroller compatible inputs using serial-data-in (SDI), 1
VDD = 3V
clock (CLK) and load strobe (LDA + LDB) pins. A chip-select 0.8 VREF = 2.5V
(CS) pin simplifies connection of multiple DAC packages by
0.6
enabling the clock input when active low. Additionally, an RS
input sets the output to zero scale or to 1/2 scale based on the 0.4

logic level applied to the MSB pin. The power shutdown pin, 0.2
DNL – LSB

SHDN, reduces power dissipation to nanoamp current levels.

0
All digital inputs contain Schmitt-triggered logic levels to mini-
mize power dissipation and prevent false triggering on the clock –0.2

input. –0.4

Both parts are offered in the same pinout to allow users to select –0.6
the amount of resolution appropriate for their application with- –0.8
TA = –558C, +258C, +858C
SUPERIMPOSED
out circuit card redesign.
–1
0 500 1000 1500 2000 2500 3000 3500 4000
CODE – Decimal

Figure 1. Differential Nonlinearity Error vs. Code

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998
AD7394/AD7395–SPECIFICATIONS
AD7394 12-BIT RAIL-TO-RAIL VOLTAGE OUT DAC
ELECTRICAL CHARACTERISTICS (@ V = 2.5 V, –408C < T < +858C, unless otherwise noted)
REF IN A

Parameter Symbol Conditions 3 V 6 10% 5 V 6 10% Units

STATIC PERFORMANCE
Resolution1 N 12 12 Bits
Relative Accuracy2 INL TA = +25°C ± 1.5 ± 1.5 LSB max
Relative Accuracy2 INL TA = –40°C, +85°C ± 2.0 ± 2.0 LSB max
Differential Nonlinearity2 DNL TA = +25°C, Monotonic ± 0.9 ± 0.9 LSB max
Differential Nonlinearity2 DNL Monotonic ±1 ±1 LSB max
Zero-Scale Error VZSE Data = 000H 4.0 4.0 mV max
Full-Scale Voltage Error VFSE TA = +25°C, +85°C, Data = FFFH ±8 ±8 mV max
Full-Scale Voltage Error VFSE TA = –40°C, Data = FFFH ± 20 ± 20 mV max
Full-Scale Tempco3 TCVFS –30 –30 ppm/°C typ
REFERENCE INPUT
VREF IN Range VREF 0/VDD 0/VDD V min/max
Input Resistance RREF 2.5 2.5 MΩ typ4
Input Capacitance3 CREF 5 5 pF typ
ANALOG OUTPUT
Output Current (Source) IOUT Data = 800H, ∆VOUT = 5 LSB 1 1 mA typ
Output Current (Sink) IOUT Data = 800H, ∆VOUT = 5 LSB 3 3 mA typ
Capacitive Load3 CL No Oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage VIL 0.5 0.8 V max
Logic Input High Voltage VIH VDD–0.6 4.0 V min
Input Leakage Current IIL 10 10 µA max
Input Capacitance3 CIL 10 10 pF max
INTERFACE TIMING3, 5
Clock Width High tCH 50 30 ns min
Clock Width Low tCL 50 30 ns min
Load Pulsewidth tLDW 30 20 ns min
Data Setup tDS 10 10 ns min
Data Hold tDH 30 15 ns min
Clear Pulsewidth tCLRW 15 15 ns min
Load Setup tLD1 30 15 ns min
Load Hold tLD2 40 20 ns min
AC CHARACTERISTICS
Output Slew Rate SR Data = 000H to FFFH to 000H 0.05 0.05 V/µs typ
Settling Time6 tS To ± 0.1% of Full Scale 70 60 µs typ
DAC Glitch Q Code 7FFH to 800H to 7FFH 65 65 nV/s typ
Digital Feedthrough Q 15 15 nV/s typ
Feedthrough VOUT/VREF VREF = 1.5 VDC +1 V p-p,
Data = 000H, f = 100 kHz –63 –63 dB typ
SUPPLY CHARACTERISTICS
Power Supply Range VDD RANGE DNL < ± 1 LSB 2.7/5.5 2.7/5.5 V min/max
Shutdown Supply Current IDD_SD SHDN = 0, VIL = 0 V, No Load 0.1/1.5 0.1/1.5 µA typ/max
Positive Supply Current IDD VIL = 0 V, No Load 125/200 125/200 µA typ/max
Power Dissipation PDISS VIL = 0 V, No Load 600 1000 µW max
Power Supply Sensitivity PSS ∆VDD = ± 5% 0.006 0.006 %/% max
NOTES
1
One LSB = V REF/4096 V for the 12-bit AD7394.
2
The first two codes (000 H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with t R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last three LSBs of ground.
Specifications subject to change without notice.

–2– REV. 0
 AD7394/AD7395
AD7395 10-BIT RAIL-TO-RAIL VOLTAGE OUT DAC
ELECTRICAL CHARACTERISTICS (@ V = 2.5 V, –408C < T < +858C/+1258C, unless otherwise noted)
REF IN A

Parameter Symbol Conditions 3 V 6 10% 5 V 6 10% Units

STATIC PERFORMANCE
Resolution1 N 10 10 Bits
Relative Accuracy2 INL TA = +25°C ± 1.5 ± 1.5 LSB max
Relative Accuracy2 INL TA = –40°C, +85°C, +125°C ± 2.0 ± 2.0 LSB max
Differential Nonlinearity2 DNL Monotonic ±1 ±1 LSB max
Zero-Scale Error VZSE Data = 000H 9.0 9.0 mV max
Full-Scale Voltage Error VFSE TA = +25°C, +85°C, +125°C
Data = FFFH ± 42 ± 42 mV max
Full-Scale Voltage Error VFSE TA = –40°C, Data = FFFH ± 48 ± 48 mV max
Full-Scale Tempco3 TCVFS –35 –35 ppm/°C typ
REFERENCE INPUT
VREF IN Range VREF 0/VDD 0/VDD V min/max
Input Resistance RREF 2.5 2.5 MΩ typ4
Input Capacitance3 CREF 5 5 pF typ
ANALOG OUTPUT
Output Current (Source) IOUT Data = 200H, ∆VOUT = 5 LSB 1 1 mA typ
Output Current (Sink) IOUT Data = 200H, ∆VOUT = 5 LSB 3 3 mA typ
Capacitive Load3 CL No Oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage VIL 0.5 0.8 V max
Logic Input High Voltage VIH VDD–0.6 4.0 V min
Input Leakage Current IIL 10 10 µA max
Input Capacitance3 CIL 10 10 pF max
INTERFACE TIMING3, 5
Clock Width High tCH 50 30 ns min
Clock Width Low tCL 50 30 ns min
Load Pulsewidth tLDW 30 20 ns min
Data Setup tDS 10 10 ns min
Data Hold tDH 30 15 ns min
Clear Pulsewidth tCLRW 15 15 ns min
Load Setup tLD1 30 15 ns min
Load Hold tLD2 40 20 ns min
AC CHARACTERISTICS
Output Slew Rate SR Data = 000H to 3FFH to 000H 0.05 0.05 V/µs typ
Settling Time6 tS To ± 0.1% of Full Scale 70 60 µs typ
DAC Glitch Q Code 7FFH to 800H to 7FFH 65 65 nV/s typ
Digital Feedthrough Q 15 15 nV/s typ
Feedthrough VOUT/VREF VREF = 1.5 VDC +1 V p-p,
Data = 000H, f = 100 kHz –63 –63 dB typ
SUPPLY CHARACTERISTICS
Power Supply Range VDD RANGE DNL < ± 1 LSB 2.7/5.5 2.7/5.5 V min/max
Shutdown Supply Current IDD_SD SHDN = 0, VIL = 0 V, No Load 0.1/1.5 0.1/1.5 µA typ/max
Positive Supply Current IDD VIL = 0 V, No Load 125/200 125/200 µA typ/max
Power Dissipation PDISS VIL = 0 V, No Load 600 1000 µW max
Power Supply Sensitivity PSS ∆VDD = ± 5% 0.006 0.006 %/% max
NOTES
1
One LSB = VREF/4096 V for the 10-bit AD7395.
2
The first two codes (000 H, 001H) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with t R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last three LSBs of ground.
Specifications subject to change without notice.

REV. 0 –3–
AD7394/AD7395
SDI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CLK
tCSH
tCSS
CS
tLD2
LDA,B tLD1

tDS tDH
SDI

tCL
CLK
tCH
LDA,B tLDW

tCLRW
RS
tS
FS
VOUT
ZS
tS
61 LSB
ERROR BAND

Figure 2. Timing Diagram

SHDN
tSDR

IDD

Figure 3. Timing Diagram

Table I. Control Logic Truth Table

CS CLK RS MSB SHDN LDA/B Serial Shift Register Function DAC Register Function

H X H X H H No Effect Latched
L L H X H H No Effect Latched
L H H X H H No Effect Latched
L ↑+ H X H H Shift-Register-Data Advanced One Bit Latched
L ↑+ H X H L Shift-Register-Data Advanced One Bit Transparent
L H H X H L No Effect Transparent
↑+ L H X H H No Effect Latched
H X H X H ↓– No Effect Updated with Current Shift Register
Contents
H X H X H L No Effect Transparent
X X L H H X No Effect Loaded with 800H
X X ↑+ H H H No Effect Latched with 800H
X X L L H X No Effect Loaded with All Zeros
X X ↑+ L H H No Effect Latched All Zeros
X X X X L X No Effect No Affect
NOTES
1. ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care
2. Do not clock in serial data while level sensitive inputs LDA or LDB are logic LOW.

–4– REV. 0
 AD7394/AD7395
Table II. AD7394 Serial Input Register Data Format, Data Is Loaded in MSB-First Format
MSB LSB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7394 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table III. AD7395 Serial Input Register Data Format, Data Is Loaded in MSB-First Format
MSB LSB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
AD7395 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ABSOLUTE MAXIMUM RATINGS* Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V AD7395AR and AD7395AN Only . . . . . . –40°C to +125°C
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V Lead Temperature
VOUT to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V ␣ ␣ N-14 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . . +300°C
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA ␣ ␣ R-14 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . . . +215°C
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA ␣ ␣ RU-14 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . . . +224°C
Thermal Resistance θJA *Stresses above those listed under Absolute Maximum Ratings may cause
14-Lead Plastic DIP Package (N-14) . . . . . . . . . . 103°C/W permanent damage to the device. This is a stress rating only; functional operation
14-Lead SOIC Package (R-14) . . . . . . . . . . . . . . . 158°C/W of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
14-Lead Thin Shrink Surface Mount (RU-14) . . . 180°C/W maximum rating conditions for extended periods may affect device reliability.
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C

ORDERING GUIDE

Res Temperature Package Package

Model (LSB) Range Description Options
AD7394AN 12 –40°C to +85°C 14-Lead P-DIP N-14
AD7394AR 12 –40°C to +85°C 14-Lead SOIC R-14
AD7395AN 10 –40°C to +125°C 14-Lead P-DIP N-14
AD7395AR 10 –40°C to +125°C 14-Lead SOIC R-14
AD7395ARU 10 –40°C to +85°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
The AD7394/AD7395 contains 709 transistors. The die size measures 70 mil × 99 mil.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD7394/AD7395 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD SENSITIVE DEVICE
ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0 –5–
AD7394/AD7395
PIN FUNCTION DESCRIPTIONS
Pin
No. Name Function
1 AGND Analog Ground.
2 VOUTA DAC A Voltage Output.
3 VREF DAC Reference voltage input terminal. Establishes DAC full-scale output voltage. Pin can be tied to VDD pin.
4 DGND Digital Ground. Should be tied to analog GND.
5 CS Chip Select, active low input. Disables shift register loading when high. Does not effect LDA or LDB operation.
6 CLK Clock input, positive edge clocks data into shift register, MSB data bit first.
7 SDI Serial Data Input, input data loads directly into the shift register.
8 LDA Load DAC register strobe, level sensitive active low. Transfers shift register data to DAC A register. Asyn-
chronous active low input. See Control Logic Truth Table for operation.
9 RS Resets DAC register to zero condition or half-scale, depending on MSB pin logic level. Asynchronous active
low input.
10 LDB Load DAC register strobe, level-sensitive active low. Transfers shift register data to DAC B register. Asyn-
chronous active low input. See Control Logic Truth Table for operation.
11 MSB Digital Input: Logic High presets DAC registers to half-scale 800H (sets MSB bit to one) when the RS pin is
strobed; Logic Low clears all DAC registers to zero (000H) when the RS pin is strobed.
12 SHDN Active low shutdown control input. Does not affect register contents as long as power is present on VDD. New
data can be loaded into the shift register and DAC register during shutdown. When device is powered up the
most recent data loaded into the DAC register will control the DAC output.
13 VDD Positive power supply input. Specified range of operation +2.7 V to +5.5 V
14 VOUTB DAC B Voltage Output.

PIN CONFIGURATIONS

AGND 1 14 VOUTB

VOUTA 2 13 VDD

VREF 3 AD7394 12 SHDN

AD7395
DGND 4 TOP VIEW 11 MSB
CS 5 (Not to Scale) 10 LDB

CLK 6 9 RS
SDI 7 8 LDA

–6– REV. 0
 Typical Performance Characteristics– AD7394/AD7395
1.5 25 50
VDD = 3V SS = 200 UNITS AD7395
TA = –558C VREF = 2.5V SS = 200 UNITS AD7394
TA = +258C TA = +258C
1 VDD = 2.7V
20 VDD = 2.7V 40
VREF = 2.5V VREF = 2.5V
0.5

FREQEUENCY
FREQUENCY
INL – LSB

15 30
0

10 20
–0.5
TA = +258C, +858C
5 10
–1

–1.5 0 0
0 500 1000 1500 2000 2500 3000 3500 4000 23 22 21 0 1 –5 0 5 10 15
CODE – Decimal TOTAL UNADJUSTED ERROR – LSB TOTAL UNAJUSTED ERROR – LSB

Figure 4. AD7394 Integral Nonlinear- Figure 5. Total Unadjusted Error Figure 6. Total Unadjusted Error
ity Error vs. Code Histogram Histogram

35 0.6 30
AD7395 SS = 200, AD7394 AD7394
VDD = 2.7V 25
30 VREF = 2.5V 0.5 TA = +258C
TA = +858C TO –408C 20
25 VDD = 5.0V
0.4 TA = +258C 15
FREQUENCY

FSE – LSB
CODE = 768H
INL – LSB

20 10 TOTAL UNADJUSTED
0.3 FULL SCALE ERROR
15 5

0.2 0
10
25
0.1
5 FULL SCALE ERROR
210

0 0 215
26 28 30 32 34 36 38 40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
TEMPCO – ppm/8C VREF – Volts VREF – Volts

Figure 7. Full-Scale Output Tempco Figure 8. Integral Nonlinearity Error Figure 9. Full-Scale Error vs. VREF
Histogram vs. VREF

10 140 5
VDD = 5V VDD = 3V AD7394 AD7394
VREF = 2.5V
OUTPUT NOISE DENSITY – mV/ Hz

135 4.5
8 TA = +258C
LOGIC THRESHOLD – V

130 4

125 VIN 3V TO 0V VIN 0V TO 3V 3.5 VLOGIC FROM LOW TO HIGH

6
IDD – mA

120 3

4 2.5
115

110 2
2
105 1.5 VLOGIC FROM HIGH TO LOW

0 100 1
1 10 100 1k 10k 100k 0 0.5 1 1.5 2 2.5 3 2 3 4 5 6 7
FREQUENCY – Hz VIN – Volts VDD – Volts

Figure 10. AD7394 Output Noise Figure 11. Supply Current vs. Logic Figure 12. Logic Threshold vs. Sup-
Density vs. Frequency Input Voltage ply Voltage

REV. 0 –7–
AD7394/AD7395
1800 80 20
AD7394 TA = +258C VREF = 2.5V
18 CODE = 800H
1600 70
A: IDD = 2.7V, CODE = 555H 16
VDD = 5V

CURRENT SINKING – mA
1400 B: IDD = 2.7V, CODE = 3FFH 60
C: VDD = 5.5V, CODE = 155H VDD = 5.0V, 65% 14
1200 D: VDD = 5.5V, CODE = 3FFH 50 12

PSRR – dB
D
IDD – mA

1000
40 10
800 C VDD = 3V
8
30 VDD = 3.0V, 65%
600 B 6
20
400 A 4

200 10 2

0 0 0
1k 10k 100k 1M 10M 1 10 100 1k 10k 0 1 2 3 4 5 6 7 8 9 10
CLOCK FREQUENCY – Hz FREQUENCY – Hz D VOUT – LSB

Figure 13. Supply Current vs. Clock Figure 14. AD7394 Power Supply Figure 15. AD7394 IOUT Sink Current
Frequency Rejection vs. Frequency vs. ∆VOUT

0
10 1.262
VREF = 2.5V VDD = +5V 25
9 CODE = 800H VREF = 2.5V VDD = 5V
TA = +258C 210 CODE = FFFH
CURRENT SOURCING – mA

8 1.257
VDD = 5V CODE = 800H TO 7FFH 215
7 5mV/DIV
220

GAIN – dB
VOUT – Volts

6 1.252
VDD = 3V
225
5
230
4 1.247
235
3
240
2 1.242
245
1
250
0 1.237 100 1k 10k 100k
210 29 28 27 26 25 24 23 22 21 0 TIME – 2ms/DIV FREQUENCY – Hz
D VOUT – LSB

Figure 16. AD7394 IOUT Source Cur- Figure 17. Midscale Transition Figure 18. AD7395 Reference Multi-
rent vs. ∆VOUT Performance plying Bandwidth

1.4
AD7394
NOMINAL CHANGE IN VOUT – mV

1.2

1
CODE = FFFH
0.8

0.6
CODE = 000H
0.4

0.2

0
0 100 200 300 400 500 600
HOURS OF OPERATION – 1508C

Figure 19. Long-Term Drift Acceler-

ated by Burn-In

–8– REV. 0
 AD7394/AD7395
OPERATION AMPLIFIER SECTION
The AD7394 and AD7395 are a set of pin compatible, dual, The internal DAC’s output is buffered by a low power con-
12-bit/10-bit digital-to-analog converters. These single-supply sumption precision amplifier. The op amp has a 60 µs typical
operation devices consume less than 200 microamps of current settling time to 0.1% of full scale. There are slight differences in
while operating from power supplies in the +2.7 V to +5.5 V settling time for negative slewing signals versus positive. Also,
range, making them ideal for battery operated applications. negative transition settling time to within the last 6 LSBs of zero
They contain a voltage-switched, 12-bit/10-bit, laser trimmed volts has an extended settling time. The rail-to-rail output stage
digital-to-analog converter, rail-to-rail output op amps, two of this amplifier has been designed to provide precision perfor-
DAC registers and a serial input shift register. The external mance while operating near either power supply. Figure 20
reference input has constant input resistance independent of the shows an equivalent output schematic of the rail-to-rail-ampli-
digital code setting of the DAC. In addition, the reference input fier with its N-channel pull-down FETs that will pull an output
can be tied to the same supply voltage as VDD, resulting in a load directly to GND. The output sourcing current is provided
maximum output voltage span of 0 to VDD. The serial interface by a P-channel pull-up device that can source current to GND
consists of a serial data input (SDI), clock (CLK) and chip terminated loads.
select pin (CS) and two load DAC Register pins (LDA and
LDB). A reset (RS) pin is available to reset the DAC register to VDD
zero scale or midscale, depending on the digital level applied to P-CH
the MSB pin. This function is useful for power-on reset or
system failure recovery to a known state. Additional power
savings are accomplished by activating the SHDN pin resulting
in a 1.5 µA maximum consumption sleep mode. VOUT

N-CH

D/A CONVERTER SECTION

The voltage switched R-2R DAC generates an output voltage
dependent on the external reference voltage connected to the AGND
REF pin according to the following equation:
Figure 20. Equivalent Analog Output Circuit
V REF × D The rail-to-rail output stage provides more than ± 1 mA of out-
V OUT = (1)
2N put current. The N-channel output pull-down MOSFET shown
where D is the decimal data word loaded into the DAC register in Figure 20 has a 35 Ω ON resistance, which sets the sink cur-
and N is the number of bits of DAC resolution. In the case of rent capability near ground. In addition to resistive load driving
the 10-bit AD7395 using a 2.5 V reference, Equation 1 simpli- capability, the amplifier has also been carefully designed and
fies to: characterized for up to 100 pF capacitive load driving capability.

2.5 × D REFERENCE INPUT

V OUT = (2) The reference input terminal has a constant input resistance
1024
independent of digital code which results in reduced glitches on
Using Equation 2 the nominal midscale voltage at VOUT is the external reference voltage source. The high 2.5 MΩ input
1.25 V for D = 512; full-scale voltage is 2.497 V. The LSB step resistance minimizes power dissipation within the AD7394/
size is = 2.5 × 1/1024 = 0.0024 V. AD7395 D/A converters. The VREF input accepts input voltages
For the 12-bit AD7394 operating from a 5.0 V reference Equa- ranging from ground to the positive supply voltage VDD. One of
tion 1 becomes: the simplest applications, which saves an external reference
voltage source, is connection of the VREF terminal to the positive
5.0 × D VDD supply. This connection results in a rail-to-rail voltage
V OUT = (3)
4096 output span maximizing the programmed range. The reference
input will accept ac signals as long as they are kept within the
Using Equation 3 the AD7394 provides a nominal midscale
supply voltage range, 0 < VREF < VDD. The reference bandwidth
voltage of 2.50 V for D = 2048, and a full-scale output of and integral nonlinearity error performance are plotted in the
4.998 V. The LSB step size is = 5.0 × 1/4096 = 0.0012 V. Typical Performance Characteristics section (see Figures 8 and
18). The ratiometric reference feature makes the AD7394/AD7395
an ideal companion to ratiometric analog-to-digital converters
such as the AD7896.

REV. 0 –9–
AD7394/AD7395
POWER SUPPLY logic transitions when a standard CMOS logic interface or opto
The very low power consumption of the AD7394/AD7395 is a isolators are used. The logic inputs SDI, CLK, CS, LDA, LDB,
direct result of a circuit design optimizing the use of a CBCMOS RS, SHDN all contain the Schmitt trigger circuits.
process. By using the low power characteristics of CMOS for
the logic, and the low noise, tight matching of the complemen- CS EN
tary bipolar transistors, excellent analog accuracy is achieved. CLK
One advantage of the rail-to-rail output amplifiers used in the DAC A REGISTER
AD7394/AD7395 is the wide range of usable supply voltage. SDI D P R
The part is fully specified and tested for operation from +2.7 V
to +5.5 V.
SHIFT
REGISTER
POWER SUPPLY BYPASSING AND GROUNDING DAC B REGISTER
Local supply bypassing consisting of a 10 µF tantalum electro- Q D P R
lytic in parallel with a 0.1 µF ceramic capacitor is recommended
in all applications (Figure 21).

+2.7V TO +5.5V

* C
0.1mF LDA LDB RS MSB
10mF
REF VDD
Figure 23. Equivalent Digital Interface Logic
CS
AD7394
LDA, B OR VOUTA DIGITAL INTERFACE
CLK AD7395 The AD7394/AD7395 has a serial data input. A functional
VOUTB
SDI block diagram of the digital section is shown in Figure 23, while
RS Table I contains the truth table for the logic control inputs.
DGND AGND
Three pins control the serial data input register loading. Two
*OPTIONAL EXTERNAL
REFERENCE BYPASS additional pins determine which DAC will receive the data
loaded into the input shift register. Data at the SDI is clocked
Figure 21. Recommended Supply Bypassing for the into the shift register on the rising edge of the CLK. Data is
AD7394/AD7395 entered in the MSB-first format. The active low chip select (CS)
pin enables loading of data into the shift register from the SDI
INPUT LOGIC LEVELS pin. Twelve clock pulses are required to load the 12-bit AD7390
All digital inputs are protected with a Zener-type ESD protec- DAC shift register. If additional bits are clocked into the shift
tion structure (Figure 22) that allows logic input voltages to register, for example, when a microcontroller sends two 8-bit
exceed the VDD supply voltage. This feature can be useful if the bytes, the MSBs are ignored (Table IV). The lowest resolution
user is driving one or more of the digital inputs with a 5 V CMOS AD7395 is also loaded MSB-first with 10 bits of data. Again, if
logic input-voltage level while operating the AD7394/AD7395 additional bits are clocked into the shift register only the last 10
on a +3 V power supply. If this mode of interface is used, make bits clocked in are used. When CS returns to logic high, shift-
sure that the VOL of the 5 V CMOS meets the VIL input re- register loading is disabled. The load pins LDA and LDB con-
quirement of the AD7394/AD7395 operating at 3 V. See Figure trol the flow of data from the shift register to the DAC register.
12 for a graph of digital logic input threshold versus operating After a new value is clocked into the serial-input register, it will
VDD supply voltage. be transferred to the DAC register associated with its LDA or
LDB logic control line. Note, if the user wants to load both
VDD DAC registers with the current contents of the shift register,
LOGIC
both control lines LDA and LDB should be strobed together.
IN The LDA and LDB pins are level-sensitive and should be re-
GND
turned to logic high prior to any new data being sent to the
input shift register to avoid changing the DAC register values.
See Truth Table for complete set of conditions.
Figure 22. Equivalent Digital Input ESD Protection
In order to minimize power dissipation from input logic levels RESET (RS) PIN
that are near the VIH and VIL logic input voltage specifications, Forcing the asynchronous RS pin low will set the DAC register
a Schmitt trigger design was used that minimizes the input- to all zeros, or midscale, depending on the logic level applied to
buffer current consumption compared to traditional CMOS the MSB pin. When the MSB pin is set to logic high, both DAC
input stages. Figure 11 is a plot of incremental input voltage registers will be reset to midscale (i.e., the DAC Register’s MSB
versus supply current showing that negligible current consump- bit will be set to Logic 1 followed by all zeros). The reset func-
tion takes place when logic levels are in their quiescent state. tion is useful for setting the DAC outputs to zero at power-up or
The normal crossover current still occurs during logic transi- after a power supply interruption. Test systems and motor
tions. A secondary advantage of this Schmitt trigger is the pre- controllers are two of many applications that benefit from
vention of false triggers that would occur with slow moving powering up to a known state. The external reset pulse can be

–10– REV. 0
 AD7394/AD7395
Table IV. Typical Microcontroller Interface Formats

MSB BYTE 1 LSB MSB BYTE 0 LSB

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D11–D0: 12-bit AD7394 DAC data; D9–D0: 10-bit AD7395 DAC data; X = Don’t Care; The MSB of byte 1 is the first bit that is loaded into the SDI input.

generated by the microprocessor’s power-on RESET signal, by Table V. Unipolar Code Table
an output from the microprocessor, or by an external resistor
and capacitor. RESET has a Schmitt trigger input which results Hexadecimal Decimal Output
in a clean reset function when using external resistor/capacitor Number Number Voltage (V)
generated pulses. See the Control-Logic Truth Table I. in DAC Register in DAC Register [VREF = 2.5 V]
FFF 4095 2.4994
POWER SHUTDOWN (SHDN) 801 2049 1.2506
Maximum power savings can be achieved by using the power 800 2048 1.2500
shutdown control function. This hardware activated feature is 7FF 2047 1.2494
controlled by the active low input SHDN pin. This pin has a 000 0 0
Schmitt trigger input which helps to desensitize it to slowly
changing inputs. By placing a logic low on this pin the internal The circuit can be configured with an external reference plus
consumption of the device is reduced to nano amp levels, guar- power supply, or powered from a single dedicated regulator or
anteed to 1.5 µA maximum over the operating temperature reference depending on the application performance requirements.
range. When the AD7394/AD7395 has been programmed into
the power shutdown state, the present DAC register data is BIPOLAR OUTPUT OPERATION
maintained as long as VDD remains greater than 2.7 V. Once a Although the AD7395 has been designed for single-supply op-
wake-up command SHDN = 1 is given, the DAC voltage out- eration, the output can easily be configured for bipolar opera-
puts will return to their previous values. It typically takes tion. A typical circuit is shown in Figure 25. This circuit uses a
80 microseconds for the output voltage to fully stabilize. In the clean regulated +5 V supply for power, which also provides the
shutdown state the DAC output amplifier exhibits an open- circuit’s reference voltage. Since the AD7395 output span swings
circuit with a nominal output resistance of 500 kΩ to ground. If from ground to very near +5 V, it is necessary to choose an
the power shutdown feature is not needed, then the user should external amplifier with a common-mode input voltage range that
tie the SHDN pin to the VDD voltage thereby disabling this extends to its positive supply rail. The micropower consumption
function. OP196 has been designed just for this purpose and results in
only 50 microamps of maximum current consumption. Connec-
UNIPOLAR OUTPUT OPERATION tion of the equally valued 470 kΩ resistors results in a differen-
This is the basic mode of operation for the AD7394. As shown tial amplifier mode of operation with a voltage gain of two,
in Figure 24, the AD7394 has been designed to drive loads as which produces a circuit output span of ten volts, that is, –5 V to
low as 5 kΩ in parallel with 100 pF. The code table for this +5 V. As the DAC is programmed from zero code 000H to mid-
operation is shown in Table V. scale 200H to full-scale 3FFH, the circuit output voltage VO is
set at –5 V, 0 V and +5 V (–1 LSB). The output voltage VO is
+2.7V TO +5.5V coded in offset binary according to Equation 4.
R

0.01mF 0.1mF 10mF  D  

VDD V OUT =   –1 × 5 (4)
VREF  512  
DAC A VOUTA
75kV 100pF where D is the decimal code loaded in the AD7395 DAC regis-
EXT
REF ter. Note that the LSB step size is 10/1024 = 10 mV. This cir-
DAC B VOUTB cuit has been optimized for micropower consumption including
5
mC DIGITAL 75kV 100pF the 470 kΩ gain setting resistors, which should have low tem-
perature coefficients to maintain accuracy and matching (prefer-
DGND AGND
DIGITAL INTERFACE ably the same resistor material, such as metal film). If better
CIRCUITRY OMITTED
FOR CLARITY. stability is required, the power supply could be substituted with
a precision reference voltage such as the low dropout REF195,
Figure 24. AD7394 Unipolar Output Operation which can easily supply the circuit’s 262 microamps of current,
and still provide additional power for the load connected to
VOUT. The micropower REF195 is guaranteed to source 10 mA

REV. 0 –11–
AD7394/AD7395
output drive current, but consumes only 50 microamps inter- Table VI. Bipolar Code Table
nally. If higher resolution is required, the AD7394 can be used
with the addition of two more bits of data inserted into the Hexadecimal Number Decimal Number Analog Output
software coding, which would result in a 2.5 mV LSB step size. in DAC Register in DAC Register Voltage (V)
Table VI shows examples of nominal output voltages, VO, pro- 3FF 1023 4.9902
vided by the Bipolar Operation circuit application. 201 513 0.0097
200 512 0.0000

C3323–8–4/98
ISY < 262mA
1FF 511 –0.0097
+5V 000 0 –5.0000
470kV 470kV

200mA < 50mA

+5V
REF VDD VO BIPOLAR
OP196 OUTPUT
VOUTA SWING
AD7395
C –5V

GND 25V

ONLY ONE CHANNEL SHOWN.

DIGITAL INTERFACE CIRCUITRY
OMITTED FOR CLARITY.

Figure 25. Bipolar Output Operation

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

Plastic DIP Package Thin Surface Mount TSSOP Package

(N-14) (RU-14)
0.795 (20.19) 0.201 (5.10)
0.725 (18.42) 0.193 (4.90)

14 8
0.280 (7.11) 14 8
1 7 0.240 (6.10) 0.325 (8.25)
0.300 (7.62) 0.195 (4.95) 0.177 (4.50) 0.256 (6.50)
PIN 1 0.060 (1.52) 0.115 (2.93) 0.169 (4.30) 0.246 (6.25)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
1
7
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381)
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204)
PIN 1
0.014 (0.356) (2.54) 0.045 (1.15) PLANE 0.006 (0.15)
BSC
0.002 (0.05) 0.0433
(1.10)
MAX
88 0.028 (0.70)
SOIC Package 0.0256 0.0118 (0.30) 08 0.020 (0.50)
SEATING 0.0079 (0.20)
PLANE (0.65) 0.0075 (0.19)
(R-14) BSC 0.0035 (0.090)

0.3444 (8.75)
0.3367 (8.55)

PRINTED IN U.S.A.
14 8
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 7 0.2284 (5.80)

PIN 1 0.0688 (1.75) 0.0196 (0.50)

0.0098 (0.25) 0.0532 (1.35) 3 458
0.0099 (0.25)
0.0040 (0.10)

88
0.0500 0.0192 (0.49) 08
SEATING (1.27) 0.0099 (0.25) 0.0500 (1.27)
PLANE BSC 0.0138 (0.35)
0.0075 (0.19) 0.0160 (0.41)

–12– REV. 0