LC2MOS

a Complete, 8-Bit Analog I/0 Systems

AD7569/AD7669
FEATURES AD7569 FUNCTIONAL BLOCK DIAGRAM
2 ms ADC with Track/Hold
1 ms DAC with Output Amplifier
AD7569, Single DAC Output
AD7669, Dual DAC Output
On-Chip Bandgap Reference
Fast Bus Interface
Single or Dual 5 V Supplies

GENERAL DESCRIPTION
The AD7569/AD7669 is a complete, 8-bit, analog I/O system
on a single monolithic chip. The AD7569 contains a high speed
successive approximation ADC with 2 µs conversion time, a track/ AD7669 FUNCTIONAL BLOCK DIAGRAM
hold with 200 kHz bandwidth, a DAC and an output buffer ampli-
fier with 1 µs settling time. A temperature-compensated 1.25 V
bandgap reference provides a precision reference voltage for the
ADC and the DAC. The AD7669 is similar, but contains two
DACs with output buffer amplifiers.
A choice of analog input/output ranges is available. Using a sup-
ply voltage of +5 V, input and output ranges of zero to 1.25 V
and zero to 2.5 volts may be programmed using the RANGE in-
put pin. Using a ± 5 V supply, bipolar ranges of ± 1.25 V or
± 2.5 V may be programmed.
Digital interfacing is via an 8-bit I/O port and standard micro-
processor control lines. Bus interface timing is extremely fast, al-
lowing easy connection to all popular 8-bit microprocessors. A
separate start convert line controls the track/hold and ADC to
give precise control of the sampling period. PRODUCT HIGHLIGHTS
The AD7569/AD7669 is fabricated in Linear-Compatible 1. Complete Analog I/O on a Single Chip.
CMOS (LC2MOS), an advanced, mixed technology process The AD7569/AD7669 provides everything necessary to
combining precision bipolar circuits with low power CMOS interface a microprocessor to the analog world. No external
logic. The AD7569 is packaged in a 24-pin, 0.3" wide “skinny” components or user trims are required and the overall accu-
DIP, a 24-terminal SOIC and 28-terminal PLCC and LCCC racy of the system is tightly specified, eliminating the need
packages. The AD7669 is available in a 28-pin, 0.6" plastic to calculate error budgets from individual component
DIP, 28-terminal SOIC and 28-terminal PLCC package. specifications.
2. Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications,
the AD7569/AD7669 is specified for ac parameters, includ-
ing signal-to-noise ratio, distortion and input bandwidth.
3. Fast Microprocessor Interface.
The AD7569/AD7669 has bus interface timing compatible
with all modern microprocessors, with bus access and relin-
quish times less than 75 ns and write pulse width less than
80 ns.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 617/326-8703 © Analog Devices, Inc., 1996
AD7569/AD7669–SPECIFICATIONS
(V = +5 V 6 5%; V = RANGE = AGND 2
1 DD SS DAC = AGNDADC = DGND = 0 V; RL = 2 kV, CL = 100 pF to AGNDDAC
DAC SPECIFICATIONS unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
AD7569
J, A Versions3 AD7569
AD7669 K, B AD7569 AD7569
Parameter J Version Versions S Version T Version Units Conditions/Comments
STATIC PERFORMANCE
Resolution 4 8 8 8 8 Bits
Total Unadjusted Error 5 ±2 ±2 ±3 ±3 LSB typ
Relative Accuracy 5 ±1 ± 1/2 ±1 ± 1/2 LSB max
Differential Nonlinearity 5 ±1 ± 3/4 ±1 ± 3/4 LSB max Guaranteed Monotonic
Unipolar Offset Error DAC data is all 0s; VSS = 0 V
@ +25°C ±2 ± 1.5 ±2 ± 1.5 LSB max Typical tempco is 10 µV/°C for +1.25 V range
TMIN to TMAX ± 2.5 ±2 ± 2.5 ±2 LSB max
Bipolar Zero Offset Error DAC data is all 0s; V SS = –5 V
@ +25°C ±2 ±1 5 ±2 ± 1.5 LSB max Typical tempco is 20 µV/°C for ± 1.25 V range
TMIN to TMAX ± 2.5 ±2 ± 2.5 ±2 LSB max
Full-Scale Error 6 (AD7569 Only) VDD = 5 V
@ +25°C ±2 ±1 ±2 ±1 LSB max
TMIN to TMAX ±3 ±2 ±4 ±3 LSB max
Full-Scale Error 6 (AD7669 Only) VDD = 5 V
@ +25°C ±3 LSB max
TMIN to TMAX ± 4.5 LSB max
DACA/DACB Full-Scale Error Match 6
(AD7669 Only) ± 2.5 LSB max VDD = 5 V
∆Full Scale/∆VDD, TA = +25°C 0.5 0.5 0.5 0.5 LSB max VOUT = 2.5 V; ∆VDD = ± 5%
∆Full Scale/∆VSS, TA = +25°C 0.5 0.5 0.5 0.5 LSB max VOUT = –2.5 V; ∆V SS = ± 5%
Load Regulation at Full Scale 0.2 0.2 0.2 0.2 LSB max RL = 2 kΩ to °/C
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio 5 (SNR) 44 46 44 46 dB min VOUT = 20 kHz full-scale sine wave with f SAMPLING = 400 kHz
Total Harmonic Distortion 5 (THD) 48 48 48 48 dB max VOUT = 20 kHz full-scale sine wave with f SAMPLING = 400 kHz
Intermodulation Distortion 5 (IMD) 55 55 55 55 dB typ fa = 18.4 kHz, fb = 14.5 kHz with f SAMPLING = 400 kHz
ANALOG OUTPUT
Output Voltage Ranges
Unipolar 0 to +1.25/2.5 Volts VDD = +5 V, VSS = 0 V
Bipolar ± 1.25/± 2.5 Volts VDD = +5 V, VSS = –5 V
LOGIC INPUTS
CS, X/B,WR, RANGE, RESET, DB0–DB7
Input Low Voltage, V INL 0.8 0.8 0.8 0.8 V max
Input High Voltage, V INH 2.4 2.4 2.4 2.4 V min
Input Leakage Current 10 10 10 10 µA max VIN = 0 to VDD
Input Capacitance 7 10 10 10 10 pF max
DB0–DB7
Input Coding (Single Supply) Binary
Input Coding (Dual Supply) 2s Complement
AC CHARACTERlSTICS 7
Voltage Output Settling Time Settling time to within ± 1/2 LSB of final value
Positive Full-Scale Change 2 2 2 2 µs max Typically 1 µs
Negative Full-Scale Change (Single Supply) 4 4 4 4 µs max Typically 2 µs
Negative Full-Scale Change (Dual Supply) 2 2 2 2 µs max Typically 1 µs
Digital-to-Analog Glitch Impulse 5 15 15 15 15 nV secs typ
Digital Feedthrough 5 1 1 1 1 nV secs typ
VIN to VOUT Isolation 60 60 60 60 dB typ VIN = ± 2.5 V, 50 kHz Sine Wave
DAC to DAC Crosstalk 5 (AD7669 Only) 1 nV secs typ
DACA to DACB Isolation 5 (AD7669 Only) –70 dB max
POWER REQUIREMENTS
VDD Range 4.75/5.25 4.75/5.25 4.75/5.25 4.75/5.25 V min/V max For Specified Performance
VSS Range (Dual Supplies) –4.75/–5.25 –4.75/–5.25 –4.75/–5.25 –4.75/–5.25 V min/V max Specified Performance also applies to V SS = 0 V
for unipolar ranges.
IDD VOUT = VIN = 2.5 V; Logic Inputs = 2.4 V; CLK = 0.8 V
(AD7569) 13 13 13 13 mA max Output unloaded
(AD7669) 18 mA max Outputs unloaded
ISS (Dual Supplies) VOUT = VIN = –2.5 V; Logic Inputs = 2.4 V; CLK = 0.8 V
(AD7569) 4 4 4 4 mA max Output unloaded
(AD7669) 6 mA max Outputs unloaded
DAC/ADC MATCHING
Gain Matching 6 VIN to VOUT match with VIN = ± 2.5 V,
@ +25°C 1 1 1 1 % typ 20 kHz sine wave
TMIN to TMAX 1 1 1 1 % typ
NOTES
1
Specifications apply to both DACs in the AD7669. VOUT applies to both VOUTA and VOUTB of the AD7669.
2
Except where noted, specifications apply for all output ranges including bipolar ranges with dual supply operation.
3
Temperature ranges as follows: J, K versions; 0°C to +70°C
A, B versions; –40°C to +85°C
S, T versions; –55°C to +125°C
4
1 LSB = 4.88 mV for 0 V to +1.25 V output range, 9.76 mV for 0 V to +2.5 V and ± 1.25 V ranges and 19.5 mV for ± 2.5 V range.
5
See Terminology.
6
Includes internal voltage reference error and is calculated after offset error has been adjusted out. Ideal unipolar full-scale voltage is (FS – 1 LSB); ideal bipolar positive full-scale voltage is (FS/2 – 1 LSB)
and ideal bipolar negative full-scale voltage is –FS/2.
7
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.

–2– REV. B
 AD7569/AD7669
ADC SPECIFICATIONS (VDD = +5 V 6 5%; VSS1 = RANGE = AGNDDAC = AGNDDAC = DGND = 0 V; fCLK = 5 MHz external unless other-
wise noted. All specifications TMIN to TMAX unless otherwise noted.) Specifications apply to Mode 1 interface.

AD7569
J, A Versions3 AD7569
AD7669 K, B AD7569 AD7569
Parameter J Version Versions S Version T Version Units Conditions/Comments

DC ACCURACY
Resolution3 8 8 8 8 Bits
Total Unadjusted Error4 ±3 ±3 ±4 ±4 LSB typ
Relative Accuracy4 ±1 ± 1/2 ±1 ± 1/2 LSB max
Differential Nonlinearity4 ±1 ± 3/4 ±1 ± 3/4 LSB max No Missing Codes
Unipolar Offset Error Typical tempco is 10 µV/°C for +1.25 V range; VSS = 0 V
@ +25°C ±2 ± 1.5 ±2 ± 1.5 LSB max
TMIN to TMAX ±3 ± 2.5 ±3 ± 2.5 LSB max
Bipolar Zero Offset Error Typical tempco is 20 µV/°C for + 1.25 V range; VSS = –5 V
@ +25°C ±3 ± 2.5 ±3 ± 2.5 LSB max
TMIN to TMAX ± 3.5 ±3 ±4 ± 3.5 LSB max
Full-Scale Error5 VDD = 5 V
@ +25°C –4, +0 –4, +0 –4, +0 –4, +0 LSB max
TMIN to TMAX –5.5, +1.5 –5.5, +1.5 –7.5, +2 –7.5, +2 LSB max
∆Full Scale/∆VDD, TA = +25°C 0.5 0.5 0.5 0.5 LSB max VIN = +2.5 V; ∆VDD = ± 5%
∆Full Scale/∆VSS, TA = +25°C 0.5 0.5 0.5 0.5 LSB max VIN = –2.5 V; ∆VSS = ± 5%

DYNAMIC PERFORMANCE
Signal-to-Noise Ratio4 (SNR) 44 46 44 45 dB min VIN = 100 kHz full-scale sine wave with fSAMPLING = 400 kHz6
Total Harmonic Distortion4 (THD) 48 48 48 48 dB max VIN = 100 kHz full-scale sine wave with fSAMPLING = 400 kHz6
Intermodulation Distortion4 (IMD) 60 60 60 60 dB typ fa = 99 kHz, fb = 96.7 kHz with fSAMPLING = 400 kHz
Frequency Response 0.1 0.1 0.1 0.1 dB typ VIN = ± 2.5 V, dc to 200 kHz sine wave
Track/Hold Acquisition Time7 200 200 300 300 ns typ

ANALOG INPUT
Input Voltage Ranges
Unipolar 0 to +1.25/ +2.5 Volts VDD = +5 V; VSS = 0 V
Bipolar ± 1.25/± 2.5 Volts VDD = +5 V; VSS = –5 V
Input Current ± 300 ± 300 ± 300 ± 300 µA max See equivalent circuit Figure 5
Input Capacitance 10 10 10 10 pF typ

LOGIC INPUTS
CS, RD, ST, CLK, RESET, RANGE
Input Low Voltage, VINL 0.8 0.8 0.8 0.8 V max
Input High Voltage, VINH 2.4 2.4 2.4 2.4 V min
Input Capacitance8 10 10 10 10 pF max
CS, RD, ST, RANGE, RESET
Input Leakage Current 10 10 10 10 µA max V IN = 0 to VDD
CLK
Input Current
IINL –1.6 –1.6 –1.6 –1.6 mA max VIN = 0 V
IINH 40 40 40 40 µA max VIN = VDD

LOGIC OUTPUTS
DB0–DB7, INT, BUSY
VOL, Output Low Voltage 0.4 0.4 0.4 0.4 V max ISINK = 1.6 mA
VOH, Output High Voltage 4.0 4.0 4.0 4.0 V min ISOURCE = 200 µA
DB0–DB7
Floating State Leakage Current 10 10 10 10 µA max
Floating State Output Capacitance8 10 10 10 10 pF max
Output Coding (Single Supply) Binary
Output Coding (Dual Supply) 2s Complement

CONVERSION TIME
With External Clock 2 2 2 2 µs max fCLK = 5 MHz
With Internal Clock, TA = +25°C 1.6 1.6 1.6 1.6 µs min Using recommended clock components shown in Figure 21.
2.6 2.6 2.6 2.6 µs max Clock frequency can be adjusted by varying RCLK.

POWER REQUIREMENTS As per DAC Specifications

NOTES
1
Except where noted, specifications apply for all ranges including bipolar ranges with dual supply operation.
2
Temperature ranges are as follows: J, K versions; 0°C to +70°C
A, B versions; –40°C to +85°C
S, T versions; –55°C to +125°C
3
1 LSB = 4.88 mV for 0 V to +1.25 V range, 9.76 mV for 0 V to +2.5 V and ± 1.25 V ranges and 19.5 mV for +2.5 V range.
4
See Terminology.
5
Includes internal voltage reference error and is calculated after offset error has been adjusted out. Ideal unipolar last code transition occurs at (FS – 3/2 LSB). Ideal bipolar last code transition occurs at
(FS/2 – 3/2 LSB).
6
Exact frequencies are 101 kHz and 384 kHz to avoid harmonics coinciding with sampling frequency.
7
Rising edge of BUSY to falling edge of ST. The time given refers to the acquisition time, which gives a 3 dB degradation in SNR from the tested figure.
8
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.

REV. B –3–
AD7569/AD7669–TIMING CHARACTERISTICS1 (See Figures 8, 10, 12; V DD = 5 V 6 5%; VSS = 0 V or –5 V 6 5%)
Limit at Limit at
Limit at TMIN, TMAX TMIN, TMAX
Parameter 258C (All Grades) (J, K, A, B Grades) (S, T Grades) Units Test Conditions/Comments
DAC Timing
t1 80 80 90 ns min WR Pulse Width
t2 0 0 0 ns min CS, A/B to WR Setup Time
t3 0 0 0 ns min CS, A/B to WR Hold Time
t4 60 70 80 ns min Data Valid to WR Setup Time
t5 10 10 10 ns min Data Valid to WR Hold Time
ADC Timing
t6 50 50 50 ns min ST Pulse Width
t7 110 130 150 ns max ST to BUSY Delay
t8 20 30 30 ns max BUSY to INT Delay
t9 0 0 0 ns min BUSY to CS Delay
t10 0 0 0 ns min CS to RD Setup Time
t11 60 75 90 ns min RD Pulse Width Determined by t 13.
t12 0 0 0 ns min CS to RD Hold Time
t132 60 75 90 ns max Data Access Time after RD; CL = 20 pF
95 120 135 ns max Data Access Time after RD; CL = 100 pF
t143 10 10 10 ns min Bus Relinquish Time after RD
60 75 85 ns max
t15 65 75 85 ns max RD to INT Delay
t16 120 140 160 ns max RD to BUSY Delay
t172 60 75 90 ns max Data Valid Time after BUSY; CL = 20 pF
90 115 135 ns max Data Valid Time after BUSY; CL = 100 pF
NOTES
1
Sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
t13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.
3
tl4 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.
Specifications subject to change without notice.

a. High-Z to VOH b. High-Z to VOL a. VOH to High-Z b. VOL to High-Z

Figure 1. Load Circuits for Data Access Time Test Figure 2. Load Circuits for Bus Relinquish Time Test

ABSOLUTE MAXIMUM RATINGS

VDD to AGNDDAC or AGNDADC . . . . . . . . . . . . . –0.3 V, +7 V Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +14 V Operating Temperature Range
AGNDDAC or AGNDADC to DGND . . . . –0.3 V, VDD + 0.3 V Commercial (J, K) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AGNDDAC to AGNDADC . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 V Industrial (A, B) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Logic Voltage to DGND . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V Extended (S, T) . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
CLK Input Voltage to DGND . . . . . . . . . –0.3 V, VDD + 0.3 V Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
VOUT (VOUTA, VOUTB) to Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
AGND1DAC . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V *Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
VIN to AGNDADC . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V of the device at these or any other condition above those indicated in the
NOTE
1 operational sections of this specification is not implied. Exposure to absolute
Output may be shorted to any voltage in the range V SS to VDD provided that the
maximum rating conditions for extended periods may affect device reliability.
power dissipation of the package is not exceeded. Typical short circuit current for
a short to AGND or V SS is 50 mA.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD7569/AD7669 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD SENSITIVE DEVICE
ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. B
 AD7569/AD7669
NOTE: Digital Feedthrough
The term DAC (Digital-to-Analog Converter) throughout the Digital Feedthrough is also a measure of the impulse injected to
data sheet applies equally to the dual DACs in the AD7669 as the analog output from the digital inputs, but is measured when
well as to the single DAC of the AD7569 unless otherwise the DAC is not selected. It is essentially feedthrough across the
stated. It follows that the term VOUT applies to both VOUTA and die and package. It is also a measure of the glitch impulse trans-
VOUTB of the AD7669 also. ferred to the analog output when data is read from the internal
TERMINOLOGY ADC. It is specified in nV secs and is measured with WR high
Total Unadjusted Error and a digital code change from all 0s to all 1s.
Total unadjusted error is a comprehensive specification that in- DAC-to-DAC Crosstalk (AD7669 Only)
cludes internal voltage reference error, relative accuracy, gain The glitch energy transferred to the output of one DAC due to
and offset errors. an update at the output of the second DAC. The figure given is
Relative Accuracy (DAC) the worst case and is expressed in nV secs. It is measured with
Relative Accuracy or endpoint nonlinearity is a measure of the an update voltage of full scale.
maximum deviation from a straight line passing through the DAC-to-DAC Isolation (AD7669 Only)
endpoints of the DAC transfer function. It is measured after al- DAC-to-DAC Isolation is the proportion of a digitized sine
lowing for offset and gain errors. For the bipolar output ranges, wave from the output of one DAC, which appears at the output
the endpoints of the DAC transfer function are defined as those of the second DAC (loaded with all 1s). The figure given is the
voltages that correspond to negative full-scale and positive full- worst case for the second DAC output and is expressed as a ra-
scale codes. For the unipolar output ranges, the endpoints are tio in dBs. It is measured with a digitized sine wave (fSAMPLING =
code 1 and code 255. Code 1 is chosen because the amplifier is 100 kHz) of 20 kHz at 2.5 V pk-pk.
now working in single supply and, in cases where the true offset Signal-to-Noise Ratio
of the amplifier is negative, it cannot be seen at code 0. If the Signal-to-Noise Ratio (SNR) is the measured signal to noise at
relative accuracy were calculated between code 0 and code 255, the output of the converter. The signal is the rms magnitude of
the “negative offset” would appear as a linearity error. If the off- the fundamental. Noise is the rms sum of all the nonfundamen-
set is negative and less than 1 LSB, it will appear at code 1, and tal signals (excluding dc) up to half the sampling frequency.
hence the true linearity of the converter is seen between code 1 SNR is dependent on the number of quantization levels used in
and code 255. the digitization process; the more levels, the smaller the quanti-
Relative Accuracy (ADC) zation noise. The theoretical SNR for a sine wave is given by
Relative Accuracy is the deviation of the ADC’s actual code SNR = (6.02N + 1.76) dB
transition points from a straight line drawn between the end- where N is the number of bits. Thus for an ideal 8-bit converter,
points of the ADC transfer function. For the bipolar input SNR = 50 dB.
ranges, these points are the measured, negative, full-scale transi-
tion point and the measured, positive, full-scale transition point. Harmonic Distortion
For the unipolar ranges, the straight line is drawn between the Harmonic Distortion is the ratio of the rms sum of harmonics to
measured first LSB transition point and the measured full-scale the fundamental. For the AD7569/AD7669, Total Harmonic
transition point. Distortion (THD) is defined as
Differential Nonlinearity 2 2 2 2 2
V 2 +V 3 +V 4 +V 5 +V 6
Differential Nonlinearity is the difference between the measured 20 log
V1
change and an ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max en- where V1 is the rms amplitude of the fundamental and V2, V3,
sures monotonicity (DAC) or no missed codes (ADC). A differ- V4, V5 and V6 are the rms amplitudes of the individual
ential nonlinearity of ± 3/4 LSB max ensures that the minimum harmonics.
step size (DAC) or code width (ADC) is 1/4 LSB, and the maxi- Intermodulation Distortion
mum step size or code width is 3/4 LSB. With inputs consisting of sine waves at two frequencies, fa and
Digital-to-Analog Glitch Impulse fb, any active device with nonlinearities will create distortion
Digital-to-Analog Glitch Impulse is the impulse injected into the products, of order (m + n), at sum and difference frequencies of
analog output when the digital inputs change state with the mfa ± nfb where m, n = 0, l, 2, 3,… . Intermodulation terms
DAC selected. It is normally specified as the area of the glitch in are those for which m or n is not equal to zero. For example,
nV secs and is measured when the digital input code is changed the second order terms include (fa + fb) and (fa – fb) and the
by 1 LSB at the major carry transition. third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).

REV. B –5–
AD7569/AD7669
AD7569 PIN CONFIGURATIONS
DIP, SOIC PLCC LCCC

AD7669 PIN CONFIGURATIONS

DIP, SOIC
ORDERING GUIDE

Relative
Temperature Accuracy Package
Model Range TMIN –TMAX Option1
AD7569JN 0°C to +70°C ± 1 LSB N-24
AD7569JR 0°C to +70°C ± 1 LSB R-24
AD7569AQ –40°C to +85°C ± 1 LSB Q-24
AD7569SQ2 –55°C to +125°C ± 1 LSB Q-24
AD7569BN –40°C to +85°C ± 0.5 LSB N-24
AD7569KN 0°C to +70°C ± 0.5 LSB N-24
AD7569BR –40°C to +85°C ± 0.5 LSB R-24
AD7569BQ –40°C to +85°C ± 0.5 LSB Q-24
AD7569TQ2 –55°C to +125°C ± 1/2 LSB Q-24
AD7569JP 0°C to +70°C ± 1 LSB P-28A
AD7569SE2 –55°C to +125°C ± 1 LSB E-28A
AD7569KP 0°C to +70°C ± 1/2 LSB P-28A
AD7569TE2 –55°C to +125°C ± 1/2 LSB E-28A
AD7669AN –40°C to +85°C ± 1 LSB N-28
PLCC AD7669JN 0°C to +70°C ± 1 LSB N-28
AD7669JP 0°C to +70°C ± 1 LSB P-28A
AD7669AR –40°C to +85°C ± 1 LSB R-28
AD7669JR 0°C to +70°C ± 1 LSB R-28
NOTES
1
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = Small Outline SOIC.
2
To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact your local sales office for military data sheet.

–6– REV. B
 AD7569/AD7669
PIN FUNCTION DESCRIPTION
(Applies to the AD7569 and AD7669 unless otherwise stated.)

Pin Pin
Mnemonic Description Mnemonic Description

AGNDDAC Analog Ground for the DAC(s). Separate CS Chip Select Input (Active Low). The device is
ground return paths are provided for the selected when this input is active.
DAC(s) and ADC to minimize crosstalk.
RD READ Input (Active Low). This input must
VOUT Output Voltage. VOUT is the buffered output be active to access data from the part. In the
(VOUTA, VOUTB) voltage from the AD7569 DAC. VOUTA and Mode 2 interface, RD going low starts con-
VOUTB are the buffered DAC output voltages version. It is used in conjunction with the CS
from the AD7669. Four different output volt- input (see Digital Interface Section).
age ranges can be achieved (see Table I).
ST Start Conversion (Edge triggered). This is
VSS Negative Supply Voltage (–5 V for dual sup- used when precise sampling is required. The
ply or 0 V for single supply). This pin is also falling edge of ST starts conversion and drives
used with the RANGE pin to select the differ- BUSY low. The ST signal is not gated with
ent input/output ranges and changes the data CS.
format from binary (VSS = 0 V) to 2s comple-
BUSY BUSY Status Output (Active Low). When
ment (VSS = –5 V) (see Table I).
this pin is active, the ADC is performing a
RANGE Range Selection Input. This is used with the conversion. The input signal is held prior to
VSS input to select the different ranges as per the falling edge of BUSY (see Digital Inter-
Table I. The range selected applies to both face Section).
the analog input voltage of the ADC and the
INT INTERRUPT Output (Active Low). INT go-
output voltage from the DAC(s).
ing low indicates that the conversion is com-
RESET Reset Input (Active Low). This is an asyn- plete. INT goes high on the rising edge of CS
chronous system reset that clears the DAC or RD and is also set high by a low pulse on
register(s) to all 0s and clears the INT line of RESET (see Digital Interface Section).
the ADC (i.e., makes the ADC ready for new
A/B (AD7669 DAC Select Input. This input selects which
conversion). In unipolar operation, this input
Only) DAC register data is written to under control
sets the output voltage to 0 V; in bipolar
of CS and WR. With this input low, data is
operation, it sets the output to negative full
written to the DACA register; with this input
scale.
high, data is written to the DACB register.
DB7 Data Bit 7. Most Significant Bit (MSB).
CLK A TTL compatible clock signal may be used
DB6–DB2 Data Bit 6 to Data Bit 2. to determine the ADC conversion time. Inter-
DGND Digital Ground. nal clock operation is achieved by connecting
a resistor and capacitor to ground.
DB1 Data Bit 1.
AGNDADC Analog Ground for the ADC.
DB0 Data Bit 0. Least Significant Bit (LSB).
VIN Analog Input. Various input ranges can be se-
WR Write Input (Edge triggered). This is used in lected (see Table I).
conjunction with CS to write data into the
AD7569 DAC register. It is used in conjunc- VDD Positive Supply Voltage (+5 V).
tion with CS and A/B to write data into the
selected DAC register of the AD7669. Data is
transferred on the rising edge of WR.

Table I. Input/Output Ranges

Input/Output DB0–DB7
Range VSS Voltage Range Data Format
0 0V 0 V to +1.25 V Binary
1 0V 0 V to +2.5 V Binary
0 –5 V ± 1.25 V 2s Complement
1 –5 V ± 2.5 V 2s Complement

REV. B –7–
AD7569/AD7669—Typical Performance Graphs

Noise Spectral Density vs. Frequency Power Supply Rejection Ratio vs. Frequency

Positive-Going Settling Time (± 2.5 V Range) Negative-Going Settling Time (± 2.5 V Range)

DAC/ADC Full-Scale Temperature Coefficient IMD Plot for ADC

–8– REV. B
 AD7569/AD7669
CIRCUIT DESCRIPTION supply, a transistor on the output acts as a passive pull-down
D/A SECTION with output voltages near 0 V with VSS = 0 V. This means that
The AD7569 contains an 8-bit, voltage-mode, D/A converter the sink capability of the amplifier is reduced as the output volt-
that uses eight equally weighted current sources switched into age nears 0 V in single supply. In dual supply operation the full
an R-2R ladder network to give a direct but unbuffered 0 V to sink capability of 1.25 mA is maintained over the entire output
+1.25 V output range. The AD7669 is similar, but contains two voltage range.
D/A converters. The current sources are fabricated using PNP
For all other parameters, the single and dual supply perfor-
transistors. These transistors allow current sources that are
mances of the amplifier are essentially identical. The output
driven from positive voltage logic and give a zero-based output
noise from the amplifier, with full scale on the DAC, is 200 µV
range. The output voltage from the voltage switching R-2R lad-
peak-to-peak. The spot noise at 1 kHz is 35 nV/√Hz with all 0s
der network has the same positive polarity as the reference;
on the DAC. A noise spectral density versus frequency plot for
therefore, the D/A converter can be operated from a single
the amplifier is shown in the typical performance graphs.
power supply rail.
VOLTAGE REFERENCE
The PNP current sources are generated using the on-chip
The AD7569/AD7669 contains an on-chip bandgap reference
bandgap reference and a control amplifier. The current sources
that provides a low noise, temperature compensated reference
are switched to either the ladder or AGNDDAC by high speed
voltage for both the DAC and the ADC. The reference is
p-channel switches. These high-speed switches ensure a fast set-
trimmed for absolute accuracy and temperature coefficient. The
tling time for the output voltage of the DAC. The R-2R ladder
bandgap reference is generated with respect to VDD. It is buff-
network of the DAC consists of highly stable, thin-film resistors.
ered by a separate control amplifier for both the DAC and the
A simplified circuit diagram for the D/A converter section is
ADC reference. This can be seen in the DAC ladder network
shown in Figure 3. An identical D/A converter is used as part of
configuration in Figure 3.
the A/D converter, which is discussed later.
DIGITAL SECTION
The data pins on the AD7569/AD7669 provide a connection
between the external bus and DAC data inputs and ADC data
outputs. The threshold levels of all digital inputs and outputs
are compatible with either TTL or 5 V CMOS levels. Internal
input protection of all digital pins is achieved by on-chip distrib-
uted diodes.
The data format is straight binary when the part is used in single
supply (VSS = 0 V). However, when a VSS of –5 V is applied, the
data format becomes twos complement. This data format ap-
plies to the digital inputs of the DAC and the digital outputs of
the ADC.
ADC SECTION
The analog-to-digital converter on the AD7569/AD7669 uses
Figure 3. DAC Simplified Circuit Diagram the successive approximation technique to achieve a fast conver-
OP AMP SECTION
sion time of 2 µs and provides an 8-bit parallel digital output.
The output from the D/A converter is buffered by a high speed, The reference for the ADC is provided by the on-chip bandgap
noninverting op amp. This op amp is capable of developing reference.
± 2.5 V across a 2 kΩ and 100 pF load to AGNDDAC. The am- Conversion start is controlled by ST or by CS and RD. Once a
plifier can be operated from a single +5 V supply to give two conversion has been started, another conversion start should not
unipolar output ranges, or from dual supplies (± 5 V) to allow be attempted until the conversion in progress is completed.
two bipolar output ranges. Exercising the RESET input does not affect conversion; the
The feedback path of the amplifier contains a gain/offset net- RESET input resets the INT line high, which is useful in inter-
work that provides four voltage ranges at the output of the op rupt driven systems where a READ has not been performed at
amp. The output voltage range is determined by the RANGE the end of the previous conversion. The INT line does not have
and VSS inputs. (See Table I in the Pin Function Description to be cleared at the end of conversion. The ADC will continue
section.) The four possible output ranges are: 0 V to +1.25 V, to convert correctly, but the function of the INT line will be
0 V to +2.5 V, ± 1.25 V and ± 2.5 V. It should be noted that affected.
whichever range is selected for the output amplifier also applies Figure 4 shows the operating waveforms for a conversion cycle.
to the input voltage range of the A/D converter. The analog input voltage, VIN, is held 50 ns typical after the fall-
The output amplifier settles to within 1/2 LSB of its final value ing edge of ST or (CS & RD). The MSB decision is made ap-
in typically less than 500 ns. Operating the part from single or proximately 50 ns after the second falling edge of the input
dual supplies has no effect on the positive-going settling time. CLK following a conversion start. If t1 in Figure 4 is greater
However, the negative-going output settling time to voltages than 50 ns, then the falling edge of the input CLK will be seen
near 0 V in single supply will be slightly longer than the settling as the first falling clock edge. If t1 is less than 50 ns, the first fall-
time to negative full scale for dual supply operation. Addition- ing clock edge of the conversion will not occur until one clock
ally, to ensure that the output voltage can go to 0 V in single cycle later. The succeeding bit decisions are made approxi-
mately 50 ns after a CLK edge until conversion is complete.

REV. B –9–
AD7569/AD7669
At the end of conversion, the SAR contents are transferred to INTERNAL CLOCK
the output latch, and the SAR is reset in readiness for a new Clock pulses are generated by the action of an internal current
conversion. A single conversion lasts for 8 input clock cycles. source charging the external capacitor (CCLK) and this external
capacitor discharging through the external resistor (RCLK).
When a conversion is complete, this internal clock stops operat-
ing and the CLK pin goes to the DGND potential. Connections
for RCLK and CCLK are shown in the operating diagram of Fig-
ure 21. The nominal conversion time versus temperature for the
recommended RCLK and CCLK combination is shown in Figure
6. The internal clock provides a convenient clock source for the
AD7569/AD7669. Due to process variations, the actual operat-
ing frequency for this RCLK/CCLK combination can vary from
device to device by up to ± 25%.
Figure 4. Operating Waveforms Using External Clock
ANALOG INPUT
The analog input of the AD7569/AD7669 feeds into an on-chip
track-and-hold amplifier. To accommodate different full-scale
ranges, the analog input signal is conditioned by a gain/offset
network that conditions all input ranges so the internal ADC al-
ways works with a 0 V to +1.25 V signal. As a result, the input
current on the VIN input varies with the input range selected as
shown in Figure 5.

Figure 6. Conversion Time vs. Temperature for Internal

Clock Operation

DIGITAL INTERFACE
Figure 5. Equivalent VIN Circuit
DAC Timing and Control—AD7569
TRACK-AND-HOLD Table II shows the truth table for DAC operation for the
The track-and-hold (T/H) amplifier on the analog input of the AD7569. The part contains an 8-bit DAC register, which is
AD7569/AD7669 allows the ADC to accurately convert an in- loaded from the data bus under control of CS and WR. The
put sine wave of 2.5 V peak-to-peak amplitude up to a fre- data contained in the DAC register determines the analog out-
quency of 200 kHz, the Nyquist frequency of the ADC when put from the DAC. The WR input is an edge-triggered input,
operated at its maximum throughput rate of 400 kHz. This and data is transferred into the DAC register on the rising edge
maximum rate of conversion includes conversion time and time of WR. Holding CS and WR low does not make the DAC regis-
between conversions. Because the input bandwidth of the T/H ter transparent.
amplifier is much larger than 200 kHz, the input signal should
be band-limited to avoid converting high-frequency noise Table II. AD7569 DAC Truth Table
components.
CS WR RESET DAC Function
The operation of this T/H amplifier is essentially transparent to
the user. The T/H amplifier goes from its tracking mode to its H H H DAC Register Unaffected
hold mode at the start of conversion. This occurs when the L L H DAC Register Unaffected
ADC receives a conversion start command from either ST or L g H DAC Register Updated
CS & RD. At the end of conversion (BUSY going high), the g L H DAC Register Updated
T/H reverts back to tracking the input signal. X X L DAC Register Loaded with All Zeros
EXTERNAL CLOCK L = Low State, H = High State, X = Don’t Care
The AD7569/AD7669 ADC can be used with its on-chip clock
or with an externally applied clock. When using an external The contents of the DAC register are reset to all 0s by an active
clock, the CLK input of the AD7569/AD7669 may be driven low pulse on the RESET line, and for the unipolar output ranges,
directly from 74HC, 4000B series buffers (such as 4049) or the output remains at 0 V after RESET returns high. For the bi-
from TTL buffers. When conversion is complete, the internal polar output ranges, a low pulse on RESET causes the output to
clock is disabled. The external clock can continue to run be- go to negative full scale. In unipolar applications, the RESET line
tween conversions without being disabled. The mark/space ratio can be used to ensure power-up to 0 V on the AD7569 DAC out-
of the external clock can vary from 70/30 to 30/70. put and is also useful when used as a zero override in system cali-
bration cycles. If the RESET input is connected to the system

–10– REV. B
 AD7569/AD7669
RESET line, the DAC output resets to 0 V when the entire The contents of the DAC registers are reset to all 0s by an active
system is reset. Figure 7 shows the input control logic for the low pulse on the RESET line, and for the unipolar output
AD7569 DAC; the write cycle timing diagram is shown in ranges, the outputs remain at 0 V after RESET returns high.
Figure 8. For the bipolar output ranges, a low pulse on RESET causes the
outputs to go to negative full scale. In unipolar applications, the
RESET line can be used to ensure power-up to 0 V on the
AD7669 DAC outputs and is also useful when used as a zero
override in system calibration cycles. If the RESET input is con-
nected to the system RESET line, then the DAC outputs reset
to 0 V when the entire system is reset. Figure 9 shows the DAC
input control logic for the AD7669, and the write cycle timing
diagram is shown in Figure 8.

Figure 7. AD7569 DAC Input Control Logic

Figure 9. AD7669 DAC Control Logic

ADC Timing and Control

The ADC on the AD7569/AD7669 is capable of two basic oper-
ating modes. In the first mode, the ST line is used to start con-
version and drive the track-and-hold into hold mode. At the end
of conversion, the track-and-hold returns to its tracking mode.
The second mode is achieved by hard-wiring the ST line high.
In this case, CS and RD start conversion, and the microproces-
Figure 8. AD7569/AD7669 Write Cycle Timing Diagram
sor is driven into a WAIT state for the duration of conversion by
DAC Timing and Control—AD7669 BUSY.
Table III shows the truth table for the dual DAC operation of
the AD7669. The part contains two 8-bit DAC registers that are
loaded from the data bus under the control of CS, A/B and WR.
Address line A/B selects which DAC register the data is
loaded to. The data contained in the DAC registers determines
the analog output from the respective DACs. The WR input is
an edge-triggered input, and data is transferred into the selected
DAC register on the rising edge of WR. Holding CS and WR
low does not make the selected DAC register transparent. The
A/B input should not be changed while CS and WR are low.

Table III. AD7669 DAC Truth Table

CS WR A/B RESET DAC Function

H H X H DAC Registers Unaffected
L g L H DACA Register Updated
g L L H DACA Register Updated
L g H H DACB Register Updated
g L H H DACB Register Updated
X X X L DAC Registers Loaded with
All Zeros Figure 10. ADC Mode 1 Interface Timing
L = Low State, H = High State, X = Don’t Care

REV. B –11–
AD7569/AD7669
MODE 1 INTERFACE MODE 2 INTERFACE
The timing diagram for the first mode is shown in Figure 10. It The second interface mode is intended for use with micropro-
can be used in digital signal processing and other applications cessors, which can be forced into a WAIT state for at least 2 µs.
where precise sampling in time is required. In these applica- The ST line of the AD7569/AD7669 must be hardwired high to
tions, it is important that the signal sampling occurs at exactly achieve this mode. The microprocessor starts a conversion and
equal intervals to minimize errors due to sampling uncertainty is halted until the result of the conversion is read from the con-
or jitter. In these cases, the ST line is driven by a timer or some verter. Conversion is initiated by executing a memory READ to
precise clock source. the AD7569/AD7669 address, bringing CS and RD low. BUSY
The falling edge of the ST pulse starts conversion and drives the subsequently goes low (forcing the microprocessor READY or
AD7569/AD7669 track-and-hold amplifier into its hold mode. WAIT input low), placing the microprocessor into a WAIT
BUSY stays low for the duration of conversion and returns high state. The input signal is held on the falling edge of RD (assum-
at the end of conversion and the track-and hold amplifier reverts ing CS is already low or is coincident with RD). When the con-
to its tracking mode on this rising edge of BUSY. The INT line version is complete (BUSY goes high), the processor completes
can be used to interrupt the microprocessor. A READ to the the memory READ and acquires the newly converted data.
AD7569/AD7669 address accesses the data, and the INT line is While conversion is in progress, the ADC places old data (from
reset on the rising edge of CS or RD. Alternatively, the INT can the previous conversion) on the data bus. The timing diagram
be used to trigger a pulse that drives the CS and RD and places for this interface is shown in Figure 12.
the data into a FIFO or buffer memory. The microprocessor can
then read a batch of data from the FIFO or buffer memory at
some convenient time. The ST input should not be high when
RD is brought low; otherwise, the part will not operate correctly
in this mode.
It is important, especially in systems where the conversion start
(ST pulse) is asynchronous to the microprocessor, that a READ
does not occur during a conversion. Trying to read data from
the device during a conversion can cause errors to the conver-
sion in progress. Also, pulsing the ST line a second time before
conversion ends should be avoided since it too can cause errors
in the conversion result. In applications where precise sampling
is not critical, the ST pulse can be generated from a micropro-
cessor WR or RD line gated with a decoded address (different
from AD7569/AD7669 CS address).
Figure 12. ADC Mode 2 Interface Timing
The major advantage of this interface is that it allows the micro-
processor to start conversion, WAIT, and then READ data with
a single READ instruction. The user does not have to worry
about servicing interrupts or ensuring that software delays are
long enough to avoid reading during conversion. The fast con-
version time of the ADC ensures that for many microprocessors,
the processor is not placed in a WAIT state for an excessive
amount of time.
DIGITAL SIGNAL PROCESSING APPLICATIONS
In Digital Signal Processing (DSP) application areas such as
voice recognition, echo cancellation and adaptive filtering, the
Figure 11. Multichannel Inputs dynamic characteristics (SNR, Harmonic Distortion, Intermod-
ulation Distortion) of both the ADC and DAC are critical. The
This interface mode is also useful in applications where a num-
AD7569/AD7669 is specified dynamically as well as with stan-
ber of input channels are required to be converted by the ADC.
dard dc specifications. Because the track/hold amplifier has a
Figure 11 shows the circuit configuration for such an applica-
wide bandwidth, an antialiasing filter should be placed on the
tion. The signal that drives the ST input of the AD7569/
VIN input to avoid aliasing of high-frequency noise back into the
AD7669 is also used to drive the ENABLE input of the multi-
band of interest.
plexer. The multiplexer is enabled on the rising edge of the ST
pulse while the input signal is held on the falling edge; therefore, The dynamic performance of the ADC is evaluated by applying a
the signal must have settled to within 8 bits over the duration of sine-wave signal of very low distortion to the VIN input, which is
this ST pulse. The settling time, including tON (ENABLE) of sampled at a 409.6 kHz sampling rate. A Fast Fourier Transform
the multiplexer plus the T/H acquisition time (typically 200 ns), (FFT) plot or Histogram plot is then generated from which SNR,
thus determines the width of the ST pulse. This is suited to ap- harmonic distortion and dynamic differential nonlinearity data
plications where a number of input channels needs to be succes- can be obtained. For the DAC, the codes for an ideal sine wave
sively sampled or scanned. are stored in PROM and loaded down to the DAC. The output
spectrum is analyzed, using a spectrum analyzer to evaluate SNR

–12– REV. B
 AD7569/AD7669
and harmonic distortion performance. Similarly, for inter-
modulation distortion, an input (either to VIN or DAC code)
consisting of pure sine waves at two frequencies is applied to the
AD7569/AD7669.

Figure 15. DAC Output Spectrum

HISTOGRAM PLOT
When a sine wave of specified frequency is applied to the VIN in-
put of the AD7569/AD7669 and several thousand samples are
taken, it is possible to plot a histogram showing the frequency of
occurrence of each of the 256 ADC codes. If a particular step is
wider than the ideal 1 LSB width, the code associated with that
step will accumulate more counts than for the code for an ideal
Figure 13. ADC FFT Plot step. Likewise, a step narrower than ideal width will have fewer
counts. Missing codes are easily seen because a missing code
means zero counts for a particular code. The absence of large
Figure 13 shows a 2048 point FFT plot of the ADC with an in-
spikes in the plot indicates small differential nonlinearity.
put signal of 130 kHz. The SNR is 48.4 dB. It can be seen that
most of the harmonics are buried in the noise floor. It should be Figure 16 shows a histogram plot for the ADC indicating very
noted that the harmonics are taken into account when calculat- small differential nonlinearity and no missing codes for an input
ing the SNR. The relationship between SNR and resolution (N) frequency of 204 kHz. For a sine-wave input, a perfect ADC
is expressed by the following equation: would produce a cusp probability density function described by
the equation
SNR = (6.02N + 1.76) dB
1
This is for an ideal part with no differential or integral linearity p(V ) =
π( A2 − V 2 )1/2
errors. These errors will cause a degradation in SNR. By work-
ing backward from the above equation, it is possible to get a where A is the peak amplitude of the sine wave and p(V) the
measure of ADC performance expressed in effective number of probability of occurrence at a voltage V.
bits (N). This effective number of bits is plotted versus fre- The histogram plot of Figure 16 corresponds very well with this
quency in Figure 14. The effective number of bits typically falls cusp shape.
between 7.7 and 7.8, corresponding to SNR figures of 48.1 dB
Further typical plots of the performance of the AD7569/AD7669
and 48.7 dB.
are shown in the Typical Performance Graphs section of the data
Figure 15 shows a spectrum analyzer plot of the output spec- sheet.
trum from the DAC with an ideal sine-wave table loaded to the
data inputs of the DAC. In this case, the SNR is 46 dB.

Figure 14. Effective Number of Bits vs. Frequency

Figure 16. ADC Histogram Plot

REV. B –13–
AD7569/AD7669
INTERFACING THE AD7569/AD7669 AD7569/AD7669—ADSP-2100 INTERFACE
AD7569/AD7669—Z80 INTERFACE Figure 19 shows a typical interface to the DSP processor, the
Figure 17 shows a typical interface to the Z80 microprocessor. ADSP-2100. The ADC is in the Mode 2 interface mode, which
The ADC is configured for operation in the Mode 1 interface means that the ADSP-2100 is halted during conversion. This is
mode. A precise timer or clock source starts conversion in appli- achieved using the decoded address output. This is gated with
cations requiring equidistant sampling intervals. The scheme DMWR to ensure that it halts the processor for READ instruc-
used, whereby INT of the AD7569/AD7669 generates an inter- tions only. INT going low at the end of conversion releases the
rupt on the Z80, is limited in that it does not allow the ADC to processor and allows it to finish off the READ instruction.
be sampled at the maximum rate. This is because the time be-
tween samples has to be long enough to allow the Z80 to service
its interrupt and read data from the ADC. To overcome this,
some buffer memory or FIFO could be placed between the
AD7569/AD7669 and the Z80. Writing data to the relevant
AD7569/AD7669 DAC simply consists of a <LD (nn), A> in-
struction where nn is the decoded address for that DAC. Read-
ing data from the ADC, after an INT has been received,
consists of a < LDA, (nn)> instruction.

Figure 19. AD7569/AD7669 to ADSP-2100 Interface

Because the instruction cycle of the ADSP-2100 is so fast
(125 ns cycle), the DMWR pulse also has to be stretched also
for write cycles. This is achieved using the 74121, which gener-
ates a pulse that is fed back to DMACK. The duration of this
pulse determines how long the ADSP-2100 write cycle is
stretched. The buffers driving the DMACK line must have
Figure 17. AD7569/AD7669 to Z80 Interface open-collector outputs. Writing data to the relevant AD7569/
AD7569/AD7669—68008 INTERFACE AD7669 DAC is achieved using a single instruction, <DM
A typical interface to the 68008 is shown in Figure 18. In this (addr) = MRO>, where addr is the decoded address of that
case, the ADC is configured in the Mode 2 interface mode. This DAC, and MRO contains the data to be loaded to the DAC reg-
means that the one read instruction starts conversion and reads ister. Data is read from the ADC also, using a single instruction
the data. The read cycle is stretched out over the entire conver- <MRO = DM (addr)>, where the conversion result is placed in
sion period by taking the INT line back into the DTACK input the MRO data register.
of the 68008. The additional gates are required so the 68008 AD7569/AD7669—IBM PC* INTERFACE
receives a DTACK when the processor is writing data to the The AD7569/AD7669 is ideal for implementing an analog in-
AD7569/AD7669. In this case, there are no wait states intro- put/output port for the IBM PC. Figure 20 shows an interface
duced into the write cycle. Writing data to the relevant AD7569/ that realizes this function. The ADC is configured in the Mode
AD7669 DAC consists of a <MOVE.B Dn, addr> where Dn is 1 interface mode, and conversions are initiated using a precise
the data register, which contains the data to be loaded to that clock source for equidistant sampling intervals. At the end of
DAC, and addr is the decoded address for the DAC. Data is conversion, the INT line goes low, and the 74121 generates
read from the ADC using a <MOVE.B addr,Dn> with the con-
version result placed in register Dn.

Figure 20. AD7569/AD7669 to IBM PC Interface

Figure 18. AD7569/AD7669 to 68008 Interface
*IBM PC is a trademark of International Business Machines Corp.

–14– REV. B
 AD7569/AD7669
an RD pulse for the AD7569/AD7669. This RD pulse accesses UNIPOLAR (0 V to +2.5 V) CONFIGURATION
data from the ADC and places the conversion result into a regis- The 0 V to +2.5 V output voltage range is achieved by tying VSS
ter on the 74646. The rising edge of this pulse generates an in- to AGNDDAC(= 0 V) and the RANGE input to VDD. The table
terrupt request to the processor. The conversion result is read for output voltage versus digital code is as in Table IV with
from the 74646 register by performing an I/O read to the 2.VREF replacing VREF. Note that for this range
decoded address of the 74646. Writing data to the relevant
1
AD7569/AD7669 DAC involves an I/O write to the 74646, 1 LSB = 2.V REF (2−8 ) = V REF
which transfers the data to the data inputs of the AD7569/ 128
AD7669. Data is latched into the selected DAC register on the
BIPOLAR (–1.25 V to +1.25 V) CONFIGURATION
rising edge of IOW.
The first of the bipolar configurations is achieved by tying the
APPLYING THE AD7569/AD7669 DAC RANGE input to AGNDDAC(= 0 V) and VSS to –5 V. The VSS
An internal gain/offset network on the AD7569/AD7669 allows voltage level at which the AD7569/AD7669 changes to bipolar
several output voltage ranges. The part can produce unipolar operation is approximately –1 V. When the part is configured
output ranges of 0 V to +1.25 V or 0 V to +2.5 V and bipolar for bipolar outputs, the input coding becomes twos comple-
output ranges of –1.25 V to +1.25 V or –2.5 V to +2.5 V. Con- ment. The table for output voltage versus the digital code in the
nections for these various output ranges are outlined below.
DAC register is shown in Table V. Note as with the unipolar
UNIPOLAR (0 V to +1.25 V) CONFIGURATION configuration, a digital input code of all 0s produces an output
The first of the configurations provides an output voltage range of 0 V. It should be noted, however, that a low pulse on the
of 0 V to +1.25 V. This is achieved by tying the VSS and RESET line for the bipolar ranges sets the output voltage to
RANGE inputs to AGNDDAC(= 0 V). Figure 21 shows the con- negative full scale.
figuration of the AD7569 to achieve this output range. A similar
configuration of the AD7669 gives the same output range. The Table V. Bipolar (–1.25 V to +1.25 V) Code Table
table for output voltage versus the digital code in the DAC regis-
DAC Register Contents
ter is shown in Table IV.
MSB LSB Analog Output, VOUT

 127 
0111 1111 +VREF  
 128 
 1 
0000 0001 +VREF  
 128 

0000 0000 0V

 1 
1111 1111 –VREF  
 128 
 127 
1000 0001 –VREF  
 128 
Figure 21. AD7569 Unipolar (0 V to +1.25 V) Operation
 128 
1000 0000 –VREF   = –VREF
Table IV. Unipolar (0 V to +1.25 V) Code Table  128 
NOTE: 1 LSB = (V REF)(2–7) = VREF (1/128)
DAC Register Contents
MSB LSB Analog Output, VOUT BIPOLAR (–2.5 V to +2.5 V) CONFIGURATION
The –2.5 V to +2.5 V bipolar output range is achieved by tying
 255  the RANGE input to VDD and the VSS input to –5 V. Once
1111 1111 +VREF  256 
  again, the input coding is 2s complement. The table for output
 129 
voltage versus digital code is as in Table V with 2.VREF replacing
1000 0001 +VREF   VREF. Note that for this range
 256 
1
 128  1 LSB = 4.V REF (2−8 ) = V REF
64
1000 0000 +VREF  256  = +VREF/2
 
 127 
0111 1111 +VREF  
 256 
 1 
0000 0001 +VREF  
 256 

0000 0000 0V

NOTE: 1 LSB = (V REF) (2–8) = VREF (1/256); V REF = +1.25 V Nominal

REV. B –15–
AD7569/AD7669
APPLYING THE AD7569/AD7669 ADC
The analog input on the AD7569/AD7669 accepts the same
four input ranges as the output ranges on the DAC. Whatever
output range is selected for the DAC also applies to the input
range of the ADC.
Although separate AGNDs exist for both the DAC and ADC to
minimize crosstalk, writing data to the DAC while the ADC is
performing a conversion may result in an incorrect conversion
from the ADC due to an interaction of currents between the
DAC and ADC. Therefore, to ensure correct operation of the
ADC, the DAC register should not be updated while the ADC
is converting.

UNIPOLAR OPERATION
The circuit of Figure 21 shows the AD7569 configured for both
an input and output range of 0 V to +1.25 V (the AD7669 con-
figuration is similar). The nominal transfer characteristic for this
range is shown in Figure 22. The output code is Natural Binary Figure 23. Nominal Transfer Characteristic for Bipolar
with 1 LSB = (1.25/256)V = 4.88 mV. (–1.25 V to +1.25 V) Operation
As before, to achieve the unipolar 0 V to +2.5 V input range, typical example is a digital filter where an ac analog signal is
VSS is connected to 0 V, and the RANGE input is tied to a logic quantized by the ADC, digitally processed and recreated using
high. The nominal transfer characteristic is as in Figure 22 but, the DAC. In these types of applications, the offset error can be
in this case, 1 LSB = (2.5/256)V = 9.76 mV. eliminated by ac coupling the recreated signal. Full-scale error
effect is linear and does not cause problems as long as the input
signal is within the full dynamic range of the ADC. An impor-
tant parameter in DSP applications is Differential Nonlinearity,
and this is not affected by either offset or full-scale error.
In applications where absolute accuracy is important ADC off-
set and full-scale error can be adjusted to zero. Figure 24 shows
the additional components required for offset and full-scale er-
ror adjustment. Offset error must be adjusted before full-scale
error. Zero offset is achieved by adjusting the offset of the op
amp driving VIN (i.e., A1 in Figure 23). In unipolar applica-
tions, for zero offset error, apply 1/2 LSB at the analog input
and adjust the op amp offset voltage until the ADC output code
flickers between 0000 0000 and 0000 0001. For zero full-scale
error, apply an analog input of FS – 3/2 LSBs and adjust R1 un-
til the ADC output code flickers between 1111 1110 and 1111
1111.
In bipolar applications, to adjust for bipolar zero offset, apply
–1/2 LSB at the analog input and adjust the op amp offset volt-
Figure 22. Nominal Transfer Characteristic for Unipolar age until the output code flickers between 1111 1111 and 0000
(0 V to +1.25 V) Operation 0000. For zero full-scale error, apply +FS/2 – 3/2 LSB at the
analog input and adjust R1 until the ADC output code flickers
BIPOLAR OPERATION between 0111 1110 and 0111 1111.
The analog input of the AD7569/AD7669 ADC is configured
for bipolar inputs when VSS = –5 V. The output code provided
by the part is twos complement. Figure 23 shows the transfer
function for bipolar (–1.25 V to +1.25 V) operation. The LSB
size for this range is (2.5/256)V = 9.76 mV.
The transfer function for the –2.5 V to +2.5 V range is identical
to that of Figure 23, but now FS = 5 V and the LSB size is
(5/256)V = 19.5 mV.

ADC OFFSET AND FULL-SCALE ERROR ADJUSTMENT

In most Digital Signal Processing (DSP) applications, offset and
full-scale error have little or no effect on system performance. A

Figure 24. ADC Error Adjust Circuit

–16– REV. B
 AD7569/AD7669

Figure 25. Peak-Reading A/D Converter

PEAK DETECTION—AD7569 head (or motor) is monitored. The closed-loop system allows an
The circuit of Figure 25 shows a peak-reading A/D converter, error between the desired position and the actual position to be
which is useful in such applications as monitoring flow rates, monitored and corrected. The correction is achieved by adjust-
temperature, pressure, etc. The circuit ensures that a peak will ing the ratio of the phase currents in the motor windings until
not be missed while at the same time does not require the mi- the required head position is reached.
croprocessor to frequently monitor the data. The peak value is The AD7669 is ideally suited for the closed-loop microstepping
stored in the A/D converter and can be read at any time. technique with its on-chip dual DACs for positioning the disk
The gain on the AD524 is adjusted to yield a 0 V to +2.5 V out- drive head, and onboard ADC for monitoring the position of the
put. When the input signal exceeds the current stored value, the head. A generalized circuit for a closed-loop microstepping sys-
output of the TL311 goes low, triggering the Q output of the tem is shown in Figure 26. The DAC waveforms are shown in
74121. This low-going pulse starts a conversion on the AD7569 Figure 27, along with the direction information for clockwise ro-
ADC, and at the end of conversion latches the result into the tation supplied by the controller.
DAC. This pulse must be at least 120 ns greater than the con-
version time of the ADC. The Q output is used to drive the
strobe input of the TL311, resetting the TL311 output high in
readiness for another conversion.
The additional gates on the RD and WR inputs are to allow the
data to be read by the microprocessor while at the same time
ensuring that the DAC is not updated when the microprocessor
reads the data. It may be necessary to monitor the AD7569
BUSY line to ensure that a processor READ is not attempted
while the AD7569 is in the middle of a conversion. The READ
pulse width from the processor must be less than 1 µs to ensure
correct data is read from the ADC. A low-going pulse on the
RESET line resets the DAC output to 0 V and starts a new “peak-
detection” period. This RESET pulse must also be less than 1 µs.
DISK DRIVE APPLICATION—AD7669
Closed-Loop Microstepping
Microstepping is a popular technique in low density disk drives Figure 26. Typical Closed-Loop Microstepping Circuit with
(both floppy and hard disk) that allows higher positional resolu- the AD7669
tion of the disk drive head over that obtainable from a full- step The AD7669 is used in the unipolar 0 V to +2.5 V configura-
driven stepper motor. Typically, a two-phase stepper motor has tion. This allows the circuit of Figure 26 to be completely uni-
its phase currents driven with a sine-cosine relationship. These polar (+5 V, +12 V supplies); no negative power supplies are
cosinusoidal signals are generated by two DACs driven with the required. The power output stage is a dual H-Bridge device
appropriate data. The resolution of the DACs determines the such as the UDN-2998W from Sprague Electric. The phase
number of microsteps into which each full step can be divided. currents in both windings are detected by means of the small
For example, with a 1.8° full-step motor and a 4-bit DAC, a value sense resistors, RSA and RSB, in series with the windings.
microstep size of 0.11° (1.8°/(2n)) is obtainable. The voltage developed across these resistors is amplified and
The microstepping technique improves the positioning resolu- compared with the respective DAC output voltage. The com-
tion possible in any control application; however, the positional parators in turn chop the phase winding current. The ADC
accuracy can be significantly worse than that offered by the completes the feedback path by converting information from a
original full-step accuracy specification due to load torque effects. suitable transducer for analysis by the controller.
To ensure that the increased resolution is usable, it is necessary
to use a closed-loop system where the position of the disk drive

REV. B –17–
AD7569/AD7669
On initial start-up, the output voltage, VO, will be invalid until
the length of the delay is reached (i.e., until the counter is re-
set). From this point forward, the delayed data is read from the
6116 and loaded to the DAC before the newly converted data is
written into the same memory location. The input clock to the
system can be a square wave of maximum input frequency 200
kHz
(assuming 2 µs conversion time for the ADC). The mark/space
ratio of the input clock can be varied to maximize the sampling
frequency if required. The clock low time has to be equal to the
conversion time and access time of the ADC plus the setup time
required for the 6116. The clock high time has only to be equal
to the setup time for the DAC plus the delay time through the
counter and the access time of the 6116.
The amount of memory used, as well as the sampling frequency,
determines the maximum possible delay. Using the HCT4040,
Figure 27. Typical DAC Output Voltages for Microstepping
and the 6116 with an input clock frequency of 200 kHz, the
and Direction Signals for Clockwise Rotation with the
maximum delay is 5 ms on a maximum input frequency of
UDN-2998W
100 kHz. Using 64K memory, with an 8 kHz input clock fre-
quency, the maximum delay is 8 seconds on a maximum input
ANALOG DELAY LINE—AD7569
frequency of 4 kHz.
In many applications, especially in audio systems, it is necessary
to provide a delay on the input signal. The circuit of Figure 28
TRANSIENT RECORDER—AD7569
shows how a simple analog delay line can be implemented,
The scheme just outlined can also form the basis for a transient
based on the AD7569. The input signal is sampled using the
recorder. In this case, transients on the input signal are con-
AD7569 ADC, and converted data is loaded into the 6116 (2K
verted and stored in memory. The transient can then be recalled
3 8 static ram). The inverted input clock drives a counter that
from memory at a later time, and the transient waveform can be
selects the address for the 6116. The delay is selected by choos-
recreated using the AD7569 DAC.
ing one of the output lines of the HCT4040 counter to reset the
coun-ter. This can be done using a simple switch in a manual
INFINITE SAMPLE-AND-HOLD—AD7569
system or by a multiplexer in a programmable delay application.
The AD7569 is ideal for implementing a single-chip infinite
Data is written to the DAC using the inverted input clock signal.
sample-and-hold function. Basically, the ADC samples and con-
verts the input signal into an 8-bit digital word. The 8 bits of
data are then loaded to the DAC and the sampled value is re-
stored to analog form. The sampled value is held until the DAC
register is updated. The full-scale matching between the ADC
and the DAC on the AD7569 ensures a typical error of less than
1% between the analog input voltage and the “held” output
voltage. Figure 29 shows the connections required on the
AD7569 to achieve this infinite sample-and-hold function.

Figure 29. Infinite Sample-and-Hold

Figure 28. Analog Delay Line

–18– REV. B
 AD7569/AD7669
TARE FUNCTION FOR WEIGH SCALE—AD7569 panel meter module that converts the signal for digital readout.
The infinite sample-and-hold just outlined can also form the ba- The input signal to the panel meter is also applied to the analog
sis of a circuit to provide a tare function for a weigh scale sys- input of the AD7569 for the tare function. When the tare switch
tem. Figure 30 shows a circuit for a weigh scale system. It (S1) is closed, a tare cycle commences and VIN is sampled and
incorporates a tare function using a simple circuit based on the held infinitely at VOUT until the next tare cycle. VOUT drives the
AD7569. inverting input of the differential amplifier and forces its output
to zero. Thus, the tare function is used to give a readout of zero
The AD587, along with the 2N6285, provides a buffered +10 V for any undesired weight, such as a box, when only the item
reference to supply the low impedance load cell transducer. The placed in it is to be weighed. The tare function can also be used
load cell output is amplified by the AD624 precision instrumen- in calibrating the system, to cancel out offset errors due to the
tation amplifier with gain adjustment provided by R1. The out- load cell, AD624 and differential amplifier.
put of the AD624 is applied to the noninverting input of a unity
gain differential summing amplifier that uses the AD707, a high The AD7569 offers many advantages in the system outlined,
precision op amp with low drift. The AD707 feeds a 3 1/2 digit such as: simple, low cost circuit—no need for microprocessor,
software, etc.—and low power consumption.

Figure 30. Weigh Scale System with Tare Function

REV. B –19–
AD7569/AD7669
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

24-Pin Plastic (N-24) 24-Pin Cerdip (Q-24)

C1214–10–8/88
28-Terminal Leadless Ceramic Chip Carrier 28-Terminal Plastic Leaded Chip Carrier
(E-28A) (P-28A)

28-Pin Plastic DIP (N-28) 28-Lead Small Outline (SO)

(R-28)

PRINTED IN U.S.A.

–20– REV. B
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.