a LC2MOS

Complete, 14-Bit Analog I/O System

AD7869
FEATURES FUNCTIONAL BLOCK DIAGRAM
Complete 14-Bit l/O System, Comprising
VDD
14-Bit ADC with Track/Hold Amplifier
83 kHz Throughput Rate
RI DAC
14-Bit DAC with Output Amplifier
R
3.5 ms Settling Time R

On-Chip Voltage Reference

Operates from 65 V Supplies VOUT
14 - BIT
Low Power—130 mW typ DAC
LDAC
Small 0.3" Wide DIP
TFS DAC DAC 3V
APPLICATIONS TCLK SERIAL REFERENCE
RO DAC
Digital Signal Processing DT INTERFACE
ADC 3V
Speech Recognition and Synthesis CONTROL
REFERENCE
Spectrum Analysis RFS
ADC SERIAL
RCLK RO ADC
High Speed Modems INTERFACE
DR
DSP Servo Control R
CLK CLOCK R
14 - BIT VIN
CONVST ADC

GENERAL DESCRIPTION AD7869 TRACK/HOLD

The AD7869 is a complete 14-bit I/O system containing a DAC
and an ADC. The ADC is a successive approximation type with DGND VSS AGND

a track-and-hold amplifier, having a combined throughput rate

of 83 kHz. The DAC has an output buffer amplifier with a set- PRODUCT HIGHLIGHTS
tling time of 4 µs to 14 bits. Temperature compensated 3 V bur- 1. Complete 14-Bit I/O System.
ied Zener references provide precision references for the DAC The AD7869 contains a 14-bit ADC with a track-and-hold
and ADC. amplifier and a 14-bit DAC with output amplifier. Also in
Interfacing to both the DAC and ADC is serial, minimizing pin cluded are separate on-chip voltage references for the DAC
count and giving a small 24-pin package size. Standard control and the ADC.
signals allow serial interfacing to most DSP machines. 2. Dynamic Specifications for DSP Users.
Asynchronous ADC conversion control and DAC updating is In addition to traditional dc specifications, the AD7869 is
made possible with the CONVST and LDAC logic inputs. specified for ac parameters, including signal-to-noise ratio
and harmonic distortion. These parameters, along with im-
The AD7869 operates from ± 5 V power supplies; the analog in-
portant timing parameters, are tested on every device.
put/output range of the ADC/DAC is ± 3 V. The part is fully
specified for dynamic parameters such as signal-to-noise ratio 3. Small Package.
and harmonic distortion as well as traditional dc specifications. The AD7869 is available in a 24-pin DIP and a 28-pin SOIC
package.
The part is available in a 24-pin, 0.3 inch wide, plastic or her-
metic dual-in-line package (DIP) and in a 28-pin, plastic SOIC
package.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781.329.4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1996–2010 Analog Devices, Inc. All rights reserved.
AD7869–SPECIFICATIONS
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, fCLK = 2.0 MHz external.
ADC SECTION All specifications TMIN to TMAX unless otherwise noted.)
Parameter J Version1 A Version1 Units Test Conditions/Comments

DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3, 4 (SNR) @ +25°C 78 78 dB min VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
TMIN to TMAX 78 77 dB min
Total Harmonic Distortion (THD) –86 –86 dB typ VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
Peak Harmonic or Spurious Noise –86 –86 dB typ VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
Intermodulation Distortion (IMD)
Second Order Terms –86 –86 dB typ fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
Third Order Terms –88 –88 dB typ fa = 9 kHz, fb = 9.5 kHz, f SAMPLE = 50 kHz
Track/Hold Acquisition Time 2 2 µs max
DC ACCURACY
Resolution 14 14 Bits
Minimum Resolution 14 14 Bits No Missing Codes Are Guaranteed
Integral Nonlinearity ±2 ±2 LSB max
Differential Nonlinearity ±1 ±1 LSB max
Bipolar Zero Error ± 20 ± 20 LSB max
Positive Gain Error5 ± 20 ± 20 LSB max
Negative Gain Error5 ± 20 ± 20 LSB max
ANALOG INPUT
Input Voltage Range ±3 ±3 Volts
Input Current ±1 ±1 mA max
REFERENCE OUTPUT6
RO ADC @ +25°C 2.99/3.01 2.99/3.01 V min/ V max
RO ADC TC ± 25 ± 25 ppm/°C typ
± 40 ± ppm/°C max
Reference Load Sensitivity
(∆RO ADC vs. ∆I) –1.5 –1.5 mV max Reference Load Current Change (0–500 µA),
Reference Load Should Not Be Changed
During Conversion
LOGIC INPUTS
(CONVST, CLK, CONTROL)
Input High Voltage, VINH 2.4 2.4 V min VDD = 5 V ± 5%
Input Low Voltage, VINL 0.8 0.8 V max VDD = 5 V ± 5%
Input Current, IIN ± 10 ± 10 µA max VIN = 0 V to VDD
Input Current7 (CONTROL & CLK) ± 10 ± 10 µA max VIN = VSS to DGND
Input Capacitance, CIN8 10 10 pF max
LOGIC OUTPUTS
DR, RFS Outputs
Output Low Voltage, VOL 0.4 0.4 V max ISINK = 1.6 mA, Pull-Up Resistor = 4.7 kΩ
RCLK Output
Output Low Voltage, VOL 0.4 0.4 V max ISINK = 2.6 mA, Pull-Up Resistor = 2 kΩ
DR, RFS, RCLK Outputs
Floating-State Leakage Current ± 10 ± 10 µA max
Floating-State Output Capacitance8 15 15 pF max
CONVERSION TIME
External Clock 10 10 µs max
Internal Clock 10 10 µs max The Internal Clock Has a Nominal Value of 2.0 MHz
POWER REQUIREMENTS For Both DAC and ADC
VDD +5 +5 V nom ± 5% for Specified Performance
VSS –5 –5 V nom ± 5% for Specified Performance
IDD 22 22 mA max Cumulative Current from the Two VDD Pins
ISS 12 12 mA max Cumulative Current from the Two VSS Pins
Total Power Dissipation 170 170 mW max Typically 130 mW
NOTES
1
Temperature ranges are as follows: J Version, 0°C to +70°C; A Version, –40°C to +85°C.
2
VIN = ± 3 V.
3
SNR calculation includes distortion and noise components.
4
SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.
5
Measured with respect to internal reference.
6
For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
7
Tying the CONTROL input to V DD places the device in a factory test mode where normal operation is not exhibited.
8
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.

–2– REV. B
 AD7869
(VDD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V, Rl DAC = +3 V and decoupled as shown in Figure 2,
DAC SECTION VOUT Load to AGND; = 2 kV, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
Parameter J Versions1 A Version1 Units Test Conditions/Comments

DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3 (SNR) @ +25°C 78 78 dB min VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz
TMIN to TMAX 78 77 dB min Typically 82 dB at +25°C for 0 < VOUT < 20 kHz4
Total Harmonic Distortion (THD) –86 –86 dB typ VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz
Typically –84 dB at +25°C for 0 < VOUT < 20 kHz4
Peak Harmonic or Spurious Noise –86 –86 dB typ VOUT = 1 kHz, fSAMPLE = 83 kHz
Typically –84 dB at +25°C for 0 < VOUT < 20 kHz4
DC ACCURACY
Resolution 14 14 Bits
Integral Nonlinearity ±2 ±2 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed Monotonic
Bipolar Zero Error ± 10 ± 10 LSB max
Positive Full-Scale Error 5 ± 10 ± 10 LSB max
Negative Full-Scale Error 5 ± 10 ± 10 LSB max
REFERENCE OUTPUT6
RO DAC @ +25°C 2.99/3.01 2.99/3.01 V min/V max
RO DAC TC ± 25 ± 25 ppm/°C typ
± 40 ppm/°C max
Reference Load Change
(∆RO DAC vs. ∆I) –1.5 –1.5 mV max Reference Load Current Change (0 µA–500 µA)
REFERENCE INPUT
RI DAC Input Range 2.85/3.15 2.85/3.15 V min/V max 3 V ± 5%
Input Current 1 1 µA max
LOGIC INPUTS
(LDAC, TFS, TCLK, DT)
Input High Voltage, VINH 2.4 2.4 V min VDD = 5 V ± 5%
Input Low Voltage, VINL 0.8 0.8 V max VDD = 5 V ± 5%
Input Current, IIN ± 10 ± 10 µA max VIN = 0 V to VDD
Input Capacitance, C IN7 10 10 pF max
ANALOG OUTPUT
Output Voltage Range ±3 ±3 V nom
DC Output Impedance 0.3 0.3 Ω typ
Short-Circuit Current 20 20 mA typ
AC CHARACTERISTICS7
Voltage Output Settling-Time Settling Time to Within ± 1/2 LSB of Final Value
Positive Full-Scale Change 4 4 µs max Typically 3 µs
Negative Full-Scale Change 4 4 µs max Typically 3.5 µs
Digital-to-Analog Glitch Impulse 10 10 nV secs typ DAC Code Change All 1s to All 0s
Digital Feedthrough 2 2 nV secs typ
VIN to VOUT Isolation 100 100 dB typ VIN = ± 3 V, 41.5 kHz Sine Wave
POWER REQUIREMENTS As per ADC Section
NOTES
1
Temperature ranges are as follows: J Version, 0°C to +70°C; A Version, –40°C to +85°C.
2
VOUT (p-p) = ± 3 V.
3
SNR calculation includes distortion and noise components.
4
Using external sample and hold, see Figures 13 to 15.
5
Measured with respect to REF IN and includes bipolar offset error.
6
For capacitive loads greater than 50 pF a series resistor is required (see Internal Reference section).
7
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice

REV. B –3–
AD7869
TIMING SPECIFICATIONS1, 2 (V DD = +5 V 6 5%, VSS = –5 V 6 5%, AGND = DGND = 0 V)
Limit at TMIN, TMAX
Parameter (All Versions) Units Conditions/Comments
ADC TIMING
t1 50 ns min CONVST Pulse Width
t2 3 440 ns min RCLK Cycle Time, Internal Clock
t3 100 ns min RFS to RCLK Falling Edge Setup Time
t4 20 ns min RCLK Rising Edge to RFS
100 ns max
t5 4 155 ns max RCLK to Valid Data Delay, CL = 35 pF
t6 4 ns min Bus Relinquish Time after RCLK
100 ns max
t135 2 RCLK + 200 to ns typ CONVST to RFS Delay
3 RCLK + 200
DAC TIMING
t7 50 ns min TFS to TCLK Falling Edge
t8 75 ns min TCLK Falling Edge to TFS
t9 150 ns min TCLK Cycle Time
t10 30 ns min Data Valid to TCLK Setup Time
t11 75 ns min Data Valid to TCLK Hold Time
tl2 40 ns min LDAC Pulse Width
NOTES
1
Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.
2
Serial timing is measured with a 4.7 kΩ pull-up resistor on DR and RFS and a 2 kΩ pull-up resistor on RCLK. The capacitance on all three outputs is 35 pF.
3
When using internal clock, RCLK mark/space ratio (measured form a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space
ratio = external clock mark/space ratio.
4
DR will drive higher capacitance loads but this will add to t 5 since it increases the external RC time constant (4.7 kΩ//CL) and hence the time to reach 2.4 V.
5
Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.
6
TCLK mark/space ratio is 40/60 to 60/40.

ABSOLUTE MAXIMUM RATINGS* Operating Temperature Range

(TA = + 25°C unless otherwise noted) J Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V A Version . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD Power Dissipation (Any Package) to +75°C . . . . . . . 1000 mW
VIN to AGND . . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V *Stresses above those listed under “Absolute Maximum Ratings” may cause
RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V permanent damage to the device. This is a stress rating only; functional operation
RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V of the device at these or any other conditions above those listed in the operational
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V sections of this specification is not implied. Exposure to absolute maximum rating
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V conditions for extended periods may affect device reliability.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD7869 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. B
 AD7869
AD7869 PIN FUNCTION DESCRIPTION

DIP Pin
Number Mnemonic Function
POWER SUPPLY
7 & 23 VDD Positive Power Supply, 5 V ± 5%. Both VDD pins must be tied together.
10 & 22 VSS Negative Power Supply, –5 V ± 5%. Both VSS pins must be tied together.
8 & 19 AGND Analog Ground. Both AGND pins must be tied together.
6 & 17 DGND Digital Ground. Both DGND pins must be tied together.
ANALOG SIGNAL AND REFERENCE
21 VIN ADC Analog Input. The ADC input range is ± 3 V.
9 VOUT Analog Output Voltage from DAC. This output comes from a buffer amplifier. The range is bipolar, ± 3 V
with RI DAC = +3 V.
20 RO ADC Voltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be used as a
reference for the DAC by connecting it to the RI DAC input. The external load capability of this reference is 500 μA.
11 RO DAC DAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC with this
internal reference, RO DAC should be connected to RI DAC. The external load capability of the reference is 500 μA.
12 RI DAC DAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is internally
buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7869 is 3 V.
ADC INTERFACE AND CONTROL
2 CLK Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying this pin to VSS
enables the internal laser-trimmed oscillator.
3 RFS Receive Frame Synchronization, Logic Output. This is an active low open-drain output that provides a framing
pulse for serial data. An external 4.7 kΩ pull-up resistor is required on RFS.
4 RCLK Receive Clock, Logic Output. RCLK is the gated serial clock output that is derived from the internal or external
ADC clock. If the CONTROL input is at VSS, the clock runs continuously. With the CONTROL input at DGND,
the RCLK output is gated off (three-state) after serial transmission is complete. RCLK is an open-drain output and
requires an external 2 kΩ pull-up resistor.
5 DR Receive Data, Logic Output. This is an open-drain data output used in conjunction with RFS and RCLK to transmit
data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is low. An external 4.7 kΩ resistor is
required on the DR output.
1 CONVST Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into the hold
mode and starts an ADC conversion. This input is asynchronous to the CLK input.
24 CONTROL Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the RCLK is contin-
uous. Note, tying this pin to VDD places the part in a factory test mode where normal operation is not exhibited.
DAC INTERFACE AND CONTROL
14 TFS Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC with serial
data expected after the falling edge of this signal.
15 DT Transmit Data, Logic Input. This is the data input that is used in conjunction with TFS and TCLK to transfer
serial data to the input latch.
16 TCLK Transmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when TFS is low.
13 LDAC Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the falling edge
of this signal.
18 NC No Connect.

PIN CONFIGURATIONS
DIP SOIC
CONVST 1 24 CONTROL CONVST 1 28 CONTROL
CLK 2 23 VDD CLK 2 27 VDD
RFS 3 22 VSS RFS 3 26 VSS
RCLK 4 21 VIN NC 4 25 NC
DR 5
AD7869 20 RO ADC RCLK 5
AD7869 24 VIN
TOP VIEW TOP VIEW
DGND 6 (Not to Scale) 19 AGND DR 6 (Not to Scale) 23 RO ADC
VDD 7 18 NC DGND 7 22 AGND
AGND 8 17 DGND VDD 8 21 DGND
VOUT 9 16 TCLK AGND 9 20 TCLK
VSS 10 15 DT VOUT 10 19 NC
RO DAC 11 14 TFS NC 11 18 NC
RI DAC 12 13 LDAC VSS 12 17 DT

NC = NO CONNECT RO DAC 13 16 TFS

RI DAC 14 15 LDAC

NC = NO CONNECT

REV. B –5–
AD7869
CONVERTER DETAILS The operation of the track/hold amplifier is essentially transpar-
The AD7869 is a complete 14-bit I/O port; the only external ent to the user. The track/hold amplifier goes from its track
components required for normal operation are pull-up resistors mode to its hold mode at the start of conversion on the rising
for the ADC data outputs, and power supply decoupling capaci- edge of CONVST.
tors. The AD7869 is comprised of a 14-bit successive approxi-
mation ADC with a track/hold amplifier, a 14-bit DAC with a INTERNAL REFERENCES
buffered output and two 3 V buried Zener references, a clock os- The AD7869 has two on-chip temperature compensated buried
cillator and control logic. Zener references that are factory trimmed to 3 V ± 10 mV. One
reference provides the appropriate biasing for the ADC, while
ADC CLOCK the other is available as a reference for the DAC. Both reference
The AD7869 has an internal clock oscillator that can be used for outputs are available (labelled RO DAC and RO ADC) and are
the ADC conversion procedure. The oscillator is enabled by ty- capable of providing up to 500 µA to an external load.
ing the CLK input to VSS. The oscillator is laser trimmed at the The DAC input reference (RI DAC) can be sourced externally
factory to give a maximum conversion time of 10 µs. The mark/ or connected to any of the two on-chip references. Applications
space ratio can vary from 40/60 to 60/40. Alternatively, an exter- requiring good full-scale error matching between the DAC and
nal TTL compatible clock may be applied to this input. The al- the ADC should use the ADC reference as shown in Figure 4.
lowable mark/space ratio of an external clock is 40/60 to 60/40.
The maximum recommended capacitance on either of the refer-
RCLK is a clock output, used for the serial interface. This out- ence output pins for normal operation is 50 pF. If either of the
put is derived directly from the ADC clock source and can be reference outputs is required to drive a capacitive load greater
switched off at the end of conversion with the CONTROL than 50 pF, then a 200 Ω resistor must be placed in series with
input. the capacitive load. The addition of decoupling capacitors,
10 µF in parallel with 0.1 µF as shown in Figure 2, improves
ADC CONVERSION TIMING noise performance. The improvement in noise performance can
The conversion time for both external clock and continuous in- be seen from the graph in Figure 3. Note: this applies for the
ternal clock can vary from 19 to 20 rising clock edges, depending DAC output only; reference decoupling components do not af-
on the conversion start to ADC clock synchronization. If a con- fect ADC performance. Consequently, a typical application will
version is initiated within 30 ns prior to a rising edge of the ADC have just the DAC reference decoupled with the other one open
clock, the conversion time will consist of 20 rising clock edges, circuited.
i.e., 9.5 µs conversion time. For noncontinuous internal clock,
the conversion time always consists of 19 rising clock edges.

ADC TRACK-AND-HOLD AMPLIFIER RI DAC

The track-and-hold amplifier on the analog input of the AD7869
allows the ADC to accurately convert an input sine wave of 6 V RO DAC 200Ω EXT LOAD
peak–peak amplitude to 14-bit accuracy. The input impedance is or
GREATER THAN 50pF
RO ADC*
typically 9 kΩ; an equivalent circuit is shown in Figure 1. The
10µF 0.1µF
input bandwidth of the track/hold amplifier is much greater
than the Nyquist rate of the ADC even when the ADC is oper-
ated at its maximum throughput rate. The 0.1 dB cutoff fre-
quency occurs typically at 500 kHz. The track/hold amplifier
acquires an input signal to 14-bit accuracy in less than 2 µs. The *RO DAC/RO ADC CAN BE LEFT
OPEN CIRCUIT IF NOT USED
overall throughput rate is equal to the conversion time plus the
track/hold amplifier acquisition time. For a 2.0 MHz input clock,
the throughput time is 12 µs max. Figure 2. Reference Decoupling Components

DAC OUTPUT AMPLIFIER

TRACK/HOLD
The output from the voltage mode DAC is buffered by a non-
AMPLIFIER inverting amplifier. The buffer amplifier is capable of developing
4.5kΩ
TO INTERNAL ± 3 V across 2 kΩ and 100 pF load to ground and can produce
VIN
COMPARATOR 6 V peak-to-peak sine wave signals to a frequency of 20 kHz.
The output is updated on the falling edge of the LDAC input.
4.5kΩ
The output voltage settling time, to within 1/2 LSB of its final
AD7869* value, is typically less than 3.5 µs.
The small signal (200 mV p–p) bandwidth of the output buffer
TO INTERNAL
3V REFERENCE
amplifier is typically 1 MHz. The output noise from the ampli-
fier is low with a figure of 30 nV/√Hz at a frequency of 1 kHz.
The broadband noise from the amplifier exhibits a typical peak-
*ADDITIONAL PINS OMITTED FOR CLARITY
to-peak figure of 150 µV for a 1 MHz output bandwidth. Figure
3 shows a typical plot of noise spectral density versus frequency
Figure 1. ADC Analog Input
for the output buffer amplifier and for either of the on-chip
references.

–6– REV. B
 AD7869
500
ADC ADJUSTMENT
TA = +25°C
Figure 6 has signal conditioning at the input and output of the
VDD = +5V AD7869 for trimming the endpoints of the transfer functions of
200 VSS = –5V
both the ADC and the DAC. Offset error must be adjusted be-
REF OUT
fore full-scale error. For the ADC, this is achieved by trimming
100
the offset of A1 while the input voltage, V1, is 1/2 LSB below
nV – √Hz

ground. The trim procedure is as follows: apply a voltage of

50
OUTPUT WITH
–183 µV (–1/2 LSB) at V1 in Figure 6 and adjust the offset volt-
ALL 0s LOADED age of A1 until the ADC output code flickers between 11 1111
REF OUT DECOUPLED
AS SHOWN IN
1111 1111 (3FFF HEX) and 00 0000 0000 0000 (0000 HEX).
20
FIGURE 2
V1
INPUT VOLTAGE
10
50 100 200 1k 2k 10k 20k 100k RANGE = ±3V
FREQUENCY – Hz

R1
Figure 3. Noise Spectral Density vs. Frequency 10k

INPUT/OUTPUT TRANSFER FUNCTIONS R2

500 A1 VIN VOUT
A bipolar circuit for the AD7869 is shown in Figure 4.
The analog input/output voltage range of the AD7869 is ± 3 V.
R3
10k
R4 R6
The designed code transitions for the ADC occur midway be- R5 10k
AD7869* 10k V0
10k
tween successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB, R7
OUTPUT VOLTAGE
RANGE = ± 3V
5/2 LSB . . . FS –3/2 LSBs). The input/output code is 2s AGND 500 A2

Complement Binary with 1 LSB = FS/16384 = 366 µV. The R8

10k
ideal transfer function is shown in Figure 5. R9
R10 10k
*ADDITIONAL PINS 10k
OMITTED FOR
AD7869* CLARITY
ANALOG OUTPUT
VIN
RANGE = ±3V
VOUT
ANALOG INPUT
RANGE = ±3V
R1
RI DAC Figure 6. AD7869 with Input/Output Adjustment
200
RO ADC ADC gain error can be adjusted at either the first code transi-
C1 C2 tion (ADC negative full scale) or the last code transition (ADC
10µF 0.1µF
positive full scale). The trim procedures for both cases are as
AGND
follows (see Figure 6).
*ADDITIONAL PINS OMITTED FOR CLARITY
ADC Positive Full-Scale Adjustment
Apply a voltage of 2.99945 V (FS/2 – 3/2 LSBs) at V1. Adjust
Figure 4. Basic Bipolar Operation R2 until the ADC output code flickers between 01 1111 1111
1110 (1FFE HEX) and 01 1111 1111 1111 (1FFF HEX).
OUTPUT
CODE
ADC Negative Full-Scale Adjustment
011...111

011...110 Apply a voltage of –2.99982 V (–FS/2 + 1/2 LSB) at V1 and ad-

just R2 until the ADC output code flickers between 10 0000
000...010 0000 0000 (2000 HEX) and 10 0000 0000 0001 (2001 HEX).
-FS
000...001
2
000...000 DAC ADJUSTMENT
+ FS
111...111 2
-1LSB
Op amp A2 is included in Figure 6 for the DAC transfer func-
111...110 FS = 6V tion adjustment. Again, offset must be adjusted before full scale.
1LSB =
FS
16384
To adjust offset, load the DAC with 00 0000 0000 0000 (0000
100...001
HEX) and trim the offset of A2 to 0 V. As with the ADC adjust-
100...000
ment, gain error can be adjusted at either the first code transi-
0V tion (DAC negative full scale) or the last code transition (DAC
INPUT VOLTAGE
positive full scale). The trim procedures for both cases are as
follows:
Figure 5. Input/Output Transfer Function
DAC Positive Full-Scale Adjustment
OFFSET AND FULL SCALE ADJUSTMENT Load the DAC with 01 1111 1111 1111 (1FFF HEX) and ad-
In most digital signal processing (DSP) applications, offset and just R7 until the op amp output voltage is equal to 2.99963 V
full-scale errors have little or no effect on system performance. (FS/2 – 1 LSB).
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale errors do not cause problems as long as DAC Negative Full-Scale Adjustment
the input signal is within the full dynamic range of the ADC. Load the DAC with 10 0000 0000 0000 (2000 HEX) and adjust
For applications requiring that the input signal range match the R7 until the op amp output voltage is equal to –3 V (–FS/2).
full analog input dynamic range of the ADC, offset and full-
scale errors have to be adjusted to zero.

REV. B –7–
AD7869
TIMING AND CONTROL DAC TIMING
Communication with the AD7869 is managed by six dedicated The AD7869 DAC contains two latches, an input latch and a
pins. These consist of separate serial clocks, word framing or DAC latch. Data must be loaded to the input latch under the
strobe pulses, and data signals for both receiving and transmit- control of the TCLK, TFS and DT serial logic inputs. Data is
ting data. Conversion starts and DAC updating are controlled then transferred from the input latch to the DAC latch under
by two digital inputs, CONVST and LDAC. These inputs can the control of the LDAC signal. Only the data in the DAC latch
be asserted independently of the microprocessor by an external determines the analog output of the AD7869.
timer when precise sampling intervals are required. Alterna-
Data is loaded to the input latch under control of TCLK, TFS
tively, the LDAC and CONVST can be driven from a decoded
and DT. The AD7869 DAC expects a 16-bit stream of serial
address bus, allowing the microprocessor control over conver-
data on its DT input. Data must be valid on the falling edge of
sion start and DAC updating as well as data communication to
TCLK. The TFS input provides the frame synchronization sig-
the AD7869.
nal, which tells the AD7869 DAC that valid serial data will be
ADC Timing available for the next 16 falling edges of TCLK. Figure 8 shows
Conversion control is provided by the CONVST input. A low to the timing diagram for the serial data format.
high transition on CONVST input starts conversion and drives
the track/hold amplifier into its hold mode. Serial data then be- t7 t8

comes available while conversion is in progress. The corre- TFS

sponding timing diagram is shown in Figure 7. The word length t9

is 16 bits, two leading zeros followed by the 14-bit conversion TCLK

result starting with the MSB. The data is synchronized to the t11
t10
serial clock output (RCLK) and is framed by the serial strobe DON'T DON'T
DT DB13 DB12 DB11 DB10 DB1 DB0
(RFS). Data is clocked out on a low to high transition of the se- CARE CARE

rial clock and is valid on the falling edge of this clock while the
RFS output is low. RFS goes low at the start of conversion, and Figure 8. DAC Control Timing Diagram
the first serial data bit (which is the first leading zero) is valid on Although 16 bits of data are clocked into the input latch, only
the first falling edge of RCLK. All the ADC serial lines are 14 bits are transferred into the DAC latch. Therefore, two bits
open-drain outputs and require external pull-up resistors. in the stream are don’t cares since their value does not affect the
DAC latch data. The bit positions are two don’t cares, followed
t1
CONVERSION TIME by the 14-bit DAC data starting with the MSB.
CONVST The LDAC signal controls the transfer of data to the DAC
t13
latch. Normally, data is loaded to the DAC latch on the falling
1
RFS
edge of LDAC. However, if LDAC is held low, then serial data
t3 t2 t4
is loaded to the DAC latch on the sixteenth falling edge of
2,3
RCLK
TCLK. If LDAC goes low during the loading of serial data to
t5 t6
the input latch, no DAC latch update takes place on the falling
1 DB13 DB12 DB11 DB1 DB0
DR edge of LDAC. If LDAC stays low until the serial transfer is
completed, the update takes place on the sixteenth falling edge
Figure 7. ADC Control Timing Diagram of TCLK. If LDAC returns high before the serial data transfer
The serial clock out is derived from the ADC master clock is completed, no DAC latch update takes place.
source, which may be internal or external. Normally, RCLK is
required during the serial transmission only. In these cases, it
can be shut down (i.e., placed into three-state) at the end of
conversion to allow multiple ADCs to share a common serial
bus. However, some serial systems (e.g., TMS32020) require a
serial clock that runs continuously. Both options are available
on the AD7869 ADC. With the CONTROL input at 0 V,
RCLK is noncontinuous; when it is at –5 V, RCLK is
continuous.

–8– REV. B
 AD7869
AD7869 DYNAMIC SPECIFICATIONS
The AD7869 is specified and 100% tested for dynamic perfor-
mance specifications as well as traditional dc specifications such
as Integral and Differential Nonlinearity. These ac specifications
are required for signal processing applications such as speech
recognition, spectrum analysis and high speed modems. These
applications require information on the converter’s effect on the
spectral content of the input signal. Hence, the parameters for
which the AD7869 is specified include SNR, harmonic distor-
tion and peak harmonics. These terms are discussed in more de-
tail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC or DAC. The signal is the rms magnitude of the funda-
mental. Noise is the rms sum of all the nonfundamental signals
up to half the sampling frequency (fSAMPLE/2), excluding dc.
SNR is dependent upon the number of levels used in the quanti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal-to-noise ratio for a sine wave input
is given by
Figure 9. ADC FFT Plot
SNR = (6.02N + 1.76) dB (1)
where N is the number of bits. Thus for an ideal 14-bit con- Figure 10 shows a typical plot of effective number of bits versus
verter, SNR = 86 dB. frequency for an AD7869AQ with a sampling frequency of
Effective Number of Bits 60 kHz. The effective number of bits typically falls between 12.7
The formula given in Equation (1) relates the SNR to the num- and 13.1, corresponding to SNR figures of 79 dB and 80.4 dB.
ber of bits. Rewriting the formula, as in Equation (2), it is pos-
sible to obtain a measure of performance expressed in effective
number of bits (N).
SNR –1.76
N= (2)
6.02
The effective number of bits for a device can be calculated di-
rectly from its measured SNR.
Harmonic Distortion
Harmonic Distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7869, total harmonic distortion
(THD) is defined as: Figure 10. Effective Number of Bits vs. Frequency for the
ADC
V 2 2 +V 3 2 +V 4 2 +V5 2 +V 6 2
THD = 20 log DAC Testing
V1 A simplified diagram of the method used to test the dynamic
where V1 is the rms amplitude of the fundamental and V2, V3, performance specifications of the DAC is outlined in Figure 11.
V4, V5 and V6 are the rms amplitudes of the second through to Data is loaded to the DAC under control of the microcontroller
the sixth harmonic. The THD is also derived from the FFT plot and associated logic. The output of the DAC is applied to a 9th
of the ADC or DAC output spectrum. order low pass filter whose cutoff frequency corresponds to the
Nyquist limit. The output of the filter is, in turn, applied to a
ADC Testing
16-bit accurate digitizer. This digitizes the signal and the micro-
The output spectrum from the ADC is evaluated by applying a
controller generates an FFT plot from which the dynamic per-
sine wave signal of very low distortion to the VIN input while
formance of the DAC can be evaluated.
reading multiple conversion results. A Fast Fourier Transform
(FFT) plot is generated from which the SNR data can be ob- LOW-PASS
16-BIT
tained. Figure 9 shows a typical 2048 point FFT plot of the MICRO- AD7869
DIGITIZER
CONTROLLER DAC
AD7869AQ ADC with an input signal of 10 kHz and a sam- FILTER

pling frequency of 60 kHz. The SNR obtained from this graph

is 80 dB. It should be noted that the harmonics are taken into
account when calculating the SNR.
Figure 11. DAC Dynamic Performance Test Circuit

REV. B –9–
AD7869
The digitizer sampling is synchronized with the DAC update Performance versus Frequency
rate to ease FFT calculations. The digitizer samples the DAC The typical performance plots of Figures 14 and 15 show the
output after the output has settled to its new value. Therefore, if AD7869 DAC performance over a wide range of input frequen-
the digitizer were to directly sample the output, it would effec- cies at an update rate of 83 kHz. The plot of Figure 14 is with-
tively be sampling a dc value each time. As a result, the dynamic out a sample-and-hold on the DAC output while the plot of
performance of the DAC would not be measured correctly. Us- Figure 15 is generated with a sample-and-hold on the output.
ing the digitizer directly on the DAC output would give better
results than the actual performance of the DAC. Using a filter
between the DAC and the digitizer means that the digitizer
samples a continuously moving signal, and the true dynamic
performance of the AD7869 DAC output is measured.
Figure 12 shows a typical 2048 point Fast Fourier Transform
plot for the AD7869 DAC with an update rate of 83 kHz and an
output frequency of 1 kHz. The SNR obtained from the graph is
82 dBs.

Figure 14. DAC Performance vs. Frequency (No

Sample-and-Hold)

Figure 12. DAC FFT Plot

Some applications will require improved performance versus fre-
quency from the AD7869 DAC. In these applications, a simple
sample-and-hold circuit such as that outlined in Figure 13 will
extend the very good performance of the DAC to 20 kHz. Other
applications will already have an inherent sample-and-hold
function following the AD7869 DAC output. An example of
this type of application is driving a switched capacitor filter
where the updating of the DAC is synchronized with the
switched capacitor filter. This inherent sample-and-hold func-
tion also extends the frequency range performance.
R2
2k2

C9
Figure 15. DAC Performance vs. Frequency (Sample-and-
ADG201HS 330pF Hold)
R1
2k2
V OUT
AD7869* S1 D1

AD711
LDAC
IN1

1µs
LDAC ONE SHOT Q
DELAY

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 13. DAC Sample-and-Hold Circuit

–10– REV. B
 AD7869
MICROPROCESSOR INTERFACING AD7869–DSP56000 Interface
Microprocessor interfacing to the AD7869 is via a serial bus that Figure 16 shows a typical interface between the AD7869 and
uses standard protocol compatible with DSP machines. The DSP56000. The interface arrangement is synchronous with a
communication interface consists of separate transmit (DAC) gated clock requiring only three lines of interconnect. The
and receive (ADC) sections whose operations can be either syn- DSP56000 internal serial control registers have to be configured
chronous or asynchronous with respect to each other. Each sec- for a 16-bit data word with valid data on the first falling clock
tion has a clock signal, a data signal and a frame or strobe pulse. edge. Conversion starts and DAC updating are controlled by an
Synchronous operation means that data is transmitted from the external timer. Data transfers, which occur during ADC conver-
ADC and to the DAC at the same time. In this mode, only one sions, are between the processor receive and transmit shift regis-
interface clock is needed, and this has to be the ADC clock out; ters and the AD7869’s ADC and DAC. At the end of each
RCLK must be connected to TCLK. For asynchronous opera- 16-bit transfer, the DSP56000 receives an internal interrupt in-
tion, DAC and ADC data transfers are independent of each dicating the transmit register is empty, and the receive register is
other; the ADC provides the receive clock (RCLK) while the full.
transmit clock (TCLK) may be provided by the processor or the
ADC or some other external clock source. TIMER CONVST

Another option to be considered with serial interfacing is the use LDAC

of a gated clock. A gated clock means that the device sending CONTROL
the data switches on the clock when data is ready to be transmit-
ted and three states the clock output when transmission is com-
plete. Only 16 clock pulses are transmitted with the first data bit + 5V AD7869*
being latched into the receiving device on the first falling clock DSP56000 4.7kΩ 2kΩ 4.7kΩ
edge. Ideally, there is no need for frame pulses, however the
RFS
AD7869 DAC frame input (TFS) has to be driven high between SC0
TFS
data transmissions. The easiest method is to use RFS to drive
SCK RCLK
TFS and use only synchronous interfacing. This avoids the use
SRD DR
of interconnects between the processor and AD7869 frame sig-
nals. Not all processors have a gated clock facility; Figure 16 STD DT

shows an example with the DSP56000. TCLK

Table I below shows the number of interconnect lines between

the processor and the AD7869 for the different interfacing
*ADDITIONAL PINS OMITTED FOR CLARITY
options.
The AD7869 has the ability to use different clocks for transmit- Figure 16. AD7869–DSP56000 Interface
ting and receiving data. This option, however, exists only on AD7869–ADSP-2101/2102 Interface
some processors and normally just one clock (ADC clock) is An interface that is suitable for the ADSP-2101 or the ADSP-
used for all communication with the AD7869. For simplicity, all 2102 is shown in Figure 17. The interface is configured for syn-
the interface examples in this data sheet use synchronous inter- chronous, continuous clock operation. The LDAC is tied low so
facing and use the ADC clock (RCLK) as an input for the DAC the DAC gets updated on the sixteenth falling clock after TFS
clock (TCLK). For a better understanding of each of these in- goes low. Alternatively, LDAC may be driven from a timer as
terfaces, consult the relevant processor data sheet. shown in Figure 16. As with the previous interface, the proces-
sor receives an interrupt after reading or writing to the AD7869
and updates its own internal registers in preparation for the next
Table I. Interconnect Lines for Different Interfacing Options
data transfer.
Number of
Configuration Interconnects Signals TIMER CONVST

Synchronous 4 RCLK, DR, DT and RFS CONTROL

(TCLK = RCLK, TFS = RFS) – 5V

+ 5V
Asynchronous* 5 or 6 RCLK, DR, RFS, DT, TFS ADSP-2101/2
AD7869*
(TCLK = RCLK or 4.7kΩ 2kΩ 4.7kΩ

µP serial CLK) RFS RFS

RCLK
Synchronous 3 RCLK, DR and DT SCLK

DR DR
Gated Clock (TCLK = RCLK, TFS = RFS)
*5 LINES OF INTERCONNECT WHEN TCLK = RCLK TFS TFS

6 LINES OF INTERCONNECT WHEN TCLK = µP SERIAL CLK TCLK

DT DT

LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 17. AD7869–ADSP-2101/ADSP-2102 Interface

REV. B –11–
AD7869
AD7869–TMS32020 Interface tween the source and the ADC. Reduce the ground circuit im-
Figure 18 shows an interface that is suitable for the TMS32020/ pedance as much as possible since any potential difference in
TMS320C25 processors. This interface is configured for syn- grounds between the signal source and the ADC appears as an
chronous, continuous clock operation. Note the AD7869 will error voltage in series with the input signal.
not correctly interface to these processors if the AD7869 is con-
figured for a noncontinuous clock. Conversion starts and DAC INPUT/OUTPUT BOARD
updating are controlled by an external timer. Figure 19 shows an analog I/O board based on the AD7869.
The corresponding printed circuit (PC) board layout and
silkscreen are shown in Figures 21 to 23.
TIMER CONVST

LDAC The analog input to the AD7869 is buffered with an AD711 op

– 5V CONTROL amp. There is a component grid provided near the analog input
on the PC board that may be used for an antialiasing filter for
TMS32020/ + 5V
AD7869* the ADC or a reconstruction filter for the DAC or any other
TMS320C25
4.7kΩ 2kΩ 4.7kΩ
conditioning circuitry. To facilitate this option, there are two
FSR
wire links (labeled LK1 and LK2) required on the analog input
RFS

CLKR RCLK
and output tracks.
DR
DR
The board contains a SHA circuit that can be used on the out-
FSX TFS put of the AD7869 DAC to extend the very good performance
CLKX TCLK of the part over a wider frequency range. The increased perfor-
DX DT mance from the SHA can be seen from Figures 14 and 15 of
this data sheet. A wire link (labeled LK3) connects the board
output to either the SHA output or directly to the AD7869
*ADDITIONAL PINS OMITTED FOR CLARITY
DAC output .
Figure 18. AD7869–TMS32020/TMS32025 Interface
There are three LDAC link options on the board; LDAC can be
APPLICATION HINTS driven from an external source independent of CONVST,
Good printed circuit board (PCB) layout is as important as the LDAC can be tied to CONVST or LDAC can be tied to GND.
circuit design itself in achieving high speed A/D performance. Choosing the latter option disables the SHA operation and
The AD7869’s comparator is required to make bit decisions on places the SHA permanently in the track mode.
an LSB size of 366 µV. To achieve this, the designer has to be Microprocessor connections to the board are made by a 9-way
conscious of noise both in the ADC itself and in the preceding D-type connector. The pinout is shown in Figure 20. The
analog circuitry. Switching mode power supplies are not recom- ADC’s digital outputs are buffered with 74HC4050s. These
mended as the switching spikes will feed through to the com- buffers provide a higher current output capability for high
parator causing noisy code transitions. Other causes of concern capacitance loads or cables. Normally, these buffers are not re-
are ground loops and digital feedthrough from microprocessors. quired as the AD7869 will be sitting on the same board as the
These are factors that influence any ADC, and a proper PCB processor.
layout that minimizes these effects is essential for best
performance. POWER SUPPLY CONNECTIONS
The PC board requires two analog power supplies and one 5 V
LAYOUT HINTS digital supply. Connections to the analog supply are made di-
Ensure that the layout for the printed circuit board has the digi- rectly to the PC board as shown on the silkscreen in Figure 21.
tal and analog signal lines separated as much as possible. Take The connections are labeled V+ and V–, and the range for both
care not to run any digital track alongside an analog signal track. of these supplies is 12 V to 15 V. Connections to the 5 V digital
Guard (screen) the analog input with AGND. supply are made through the D-type connector SKT6. The
Establish a single point analog ground (star ground), separate ± 5 V analog supply required by the AD7869 is generated from
from the logic system ground, as close as possible to the two voltage regulators on the V+ and V– supplies.
AD7869 AGND pins. Connect all other grounds and the
AD7869 DGND to this single analog ground point. Do not WIRE LINK OPTIONS
connect any other digital grounds to this analog ground point. LK1, Analog Input Link
LK1 connects the analog input to a component grid or to a
Low impedance analog and digital power supply common re- buffer amplifier which drives the ADC input.
turns are essential to low noise operation of the ADC, so make
the foil width for these tracks as wide as possible. The use of LK2, Analog Output Link
ground planes minimizes impedance paths and also guards the LK2 connects the analog output to the component grid or to ei-
analog circuitry from digital noise. The circuit layout of Figures ther the SHA or DAC output (see LK3).
22 and 23 have both analog and digital ground planes that are LK3, SHA or DAC Select
kept separated and only joined together at the AD7869 AGND The analog output may be taken directly from the DAC or from
pins. a SHA at the output of the DAC.

NOISE LK4, DAC Reference Selection

Keep the input signal leads to VIN and signal return leads from The DAC reference may be connected to either the ADC refer-
AGND as short as possible to minimize input noise coupling. In ence output (RO ADC) or to the DAC reference (RO DAC).
applications where this is not possible, use a shielded cable be-

–12– REV. B
 AD7869
V+ 5V
IN OUT
C2 C1
IC5
0.1µF 10µF
V+ 78L05
GND
C5 C6
10µF 0.1µF

ANALOG INPUT V DD
V DD
±3V RANGE LK1 R7
A B 200
+ AD711
IC2 V IN RO ADC
SKT1 C C24
C23
V– A 0.1µF
10µF
B
COMPONENT RI DAC LK4
GRID C7 C8 C
10µF 0.1µF RO DAC

IC1 – 5V
A
AD7869
B
CONTROL LK5
C
COMPONENT
GRID AGND

B SKT6
LK2 C AGND 9-WAY D-TYPE
SKT2 B
A 5V CONNECTOR
A IC7 1/2
ANALOG OUTPUT C DGND 74HC4050 5V
R3 R4 R5
±3V RANGE V+ LK3 4.7k Ω 2k Ω 4.7k Ω
DR
DGND
DR
C10 C9
0.1µF 10µF RCLK
RCLK
IC4
RFS
AD711 ADG201HS RFS
+ R1
IC3 2k Ω
LK9
V OUT
V– LK8

TFS
C12 C11
TFS
0.1µF 10µF
TCLK
TCLK
C21
330pF DT
DT

R2 DGND
2k Ω
CLK
5V

LDAC
R6 V CC
Q CONVST
15k
REXT /C EXT V SS V SS
C22 B
68pF A A C
CEXT – 5V V–
B 5V OUT IN
LK7
C4 IC6 – 5V
IC8 1/2 CLR C3
74HC221 0.1µF 10µF 79L05

A B C GND
GND
LK6

SKT3 SKT4 SKT5

LDAC CONVST EXT CLK

Figure 19. Input/Output Circuit Based on the AD7869

LK5, ADC Internal Clock Selection LK9 Transmit/Receive Clock Option

This link configures the ADC for continuous or noncontinuous LK9 provides the option to connect the ADC RCLK to the
internal clock operation. DAC TCLK.
LK6, DAC Updating
RCLK
TCLK

RFS

DR
DT

The DAC, LDAC input may asserted independently of the

ADC CONVST signal or it may be tied to CONVST or it may
1 2 3 4 5
tied to GND.
LK7, ADC Clock Source 6 7 8 9
This link provides the option for the ADC to use its own inter-
DGND

TFS

NC

5V

nal clock oscillator or an external TTL compatible clock.

LK8 Frame Synchronous Option NC = NO CONNECT
LK8 provides the option of tying the ADC RFS output to the
DAC TFS input. Figure 20. SKT6, D-Type Connector Pinout

REV. B –13–
AD7869
COMPONENT LIST C21 330 pF Capacitor
IC1 AD7869 C22 68 pF Capacitor
IC2, IC3 2X AD711 R1, R2, R4 2 kΩ Resistor
IC4, ADG201HS R3, R5 4.7 kΩ Resistor
IC5, MC78L05 R6 15 kΩ Resistor
IC6, MC79L05 R7 200 Ω Resistor
IC7, 74HC4050
IC8, 74HC221 LK1, LK2, LK3,
LK4, LK5, LK6,
C1, C3, C5, C7 LK7, LK8, LK9 Shorting Plugs
C9, C11, C13, C15 10 µF Capacitor
C17, C19, C23 SKT1, SKT2, SKT3,
SKT4, SKT5 BNC Sockets
C2, C4, C6, C8
C10, C12, C14, C16 0.1 µF Capacitor SKT6 9-Contact D-Type Connector
C18, C20, C24

Figure 21. Silkscreen for the Circuit Diagram of Figure 19

–14– REV. B
 AD7869

Figure 22. Component Side Layout for the Circuit Diagram of Figure 19

Figure 23. Solder Side Layout for the Circuit Diagram of Figure 19

REV. B –15–
AD7869
Outline Dimensions
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)

24 13 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
12
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC
0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38)0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING 0.010 (0.25)
PLANE
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

071006-A
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 24. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
18.10 (0.7126)
17.70 (0.6969)

28 15
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
14
10.00 (0.3937)

0.75 (0.0295)
45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 1.27 (0.0500) 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
BSC 0.31 (0.0122) 0.40 (0.0157)
0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AE

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
060706-A

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 25. 28-Lead Standard Small Outline Package [SOIC_W]

Wide Body
(RW-28)

ORDERING GUIDE
Model 1 Temperature Range Signal-to-Noise Ratio (SNR) Relative Accuracy Package Description Package Option
AD7869JNZ 0°C to +70°C 78 dB ±2 LSB max 24-Lead PDIP N-24-1
AD7869JRZ 0°C to +70°C 78 dB ±2 LSB max 28-Lead SOIC_W RW-28
1
Z = RoHS Compliant Part.

REVISION HISTORY
10/10—Rev. A to Rev. B
Added SOIC Pin Configuration......................................................5

-16-