Product specification

12-Bit 20MSPS Sampling

Analog-to-Digital Converter IP Core nAD1220
TSMC 0.35µ 2P3M
FEATURES APPLICATIONS
• 2.8-3.6V power supply • Imaging
• SINAD typ. 59dB for (fin = 5MHz) • Test equipment
• Very low power (70mW@3.0V) • Computer scanners
• Sample rate: > 20MSPS • Communications
• Internal Sample/Hold • Set top boxes
• Differential input
• Low input capacitance

GENERAL DESCRIPTION
The nAD1220 is a compact, high-speed, very low power 12-bit monolithic analog-to-
digital converter, implemented in a 0.35µm CMOS process. It has 12-bit resolution
with close to 10 effective bits, and more than 10 bit dynamic range for video signals.
The converter includes sample and hold. The full-scale range can be set between
±0.6V and ±1.7V using external references. It operates from a single 2.8-3.6V supply
- compatible with modern digital systems. Most converters in this performance range
demand at least a +5V supply. Its low distortion and high dynamic range offers the
performance needed for demanding imaging, multimedia, telecommunications and
instrumentation applications. The conversion rate can be increased to 40MHz while
keeping SINAD higher than 50dB. An evaluation kit is available, see ordering
information below.

QUICK REFERENCE DATA

Symbol Parameter Conditions Min. Typ. Max. Unit
VDD supply voltage 2.8 3.3 3.6 V
PD power dissipation Ex. references 76 mW
DNL differential nonlinearity fIN=0.9991MHz ±0.4 LSB(10bit)
differential nonlinearity fIN=0.9991MHz ±1 LSB(12bit)
INL integral nonlinearity fIN=0.9991MHz ±1 LSB(10bit)
integral nonlinearity fIN=0.9991MHz ±3 LSB(12it)
fS conversion rate 20 MHz
N resolution 12 bit
Table 1. Quick reference data

ORDERING INFORMATION
Type number Name Description Version
nAD1220-CORE CORE nAD1220 hard-core; layout available in 0.35µm CMOS c-1
nAD1220-KIT KIT nAD1220 evaluation kit with the nAD1220 on board k-1
Table 2. Ordering information

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099
Revision: 3.3 Page 1 of 12 February 27th 2001
Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

GENERAL DESCRIPTION (Continued)

The nAD1220 has a pipelined architecture - resulting in low input capacitance. Digital
error correction of the 11 most significant bits ensures good linearity for input
frequencies approaching Nyquist. The excellent linearity at the color subcarrier
frequency makes the converter ideally suited for video. It is also well suited for
demanding ultrasonic imaging and flow measurements. The nAD1220 is very
compact - occupying less than 3.2mm2 of die area in a standard dual poly 0.35µm
CMOS process. The fully differential architecture makes it insensitive to substrate
noise. Thus it is ideal as a mixed signal ASIC macro cell. The modular architecture of
the converter and the flexible external biasing scheme means that scaling in number of
bits and sampling rate is easily achieved. Power consumption is roughly proportional
to the number of bits and to the maximum sampling rate. Thus, nAD1220 is an
excellent choice as the core of a product family of very low power high speed
converters with resolutions ranging from 8 - 12 bits and sampling rates ranging from
1-40MHz.

BLOCK DIAGRAM

BGAP BIAS0 BIAS1 CM

REFBUFF
BGREF BIASCELL
REFBUFF
EXTREF

REFN
REFP
STAGE_LAST
INP STAGE1 STAGE2 STAGE3 STAGE10 (2-bit flash)
INN

CLOCK CLOCKDR DIGITAL DELAYS, ERROR CORRECTION AND OUTPUT REGISTER

OR BIT<11..0>

Figure 1. Block diagram nAD1220

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
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Revision: 3.3 Page 2 of 12 February 27th 2001
Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

ELECTRICAL SPECIFICATIONS
(At TA = 25°C, VDD = 3.3V, Sampling Rate = 20MHz, Differential input, Input frequency =
4.4995MHz with a 50% duty cycle clock unless otherwise noted )
Symbol Parameter (condition) Test Min. Typ. Max. Units
Level
DC Accuracy
DNL Differential Nonlinearity
fIN = 0.9991 MHz VI ±0.4 LSB (10 bit)
±0.6 LSB (12bit)
INL Integral Nonlinearity
fIN = 0.9991 MHz VI ±1.0 LSB (10 bit)
±3.0 LSB (12bit)
No Missing Codes VI Guaranteed (12 bit)
VOS Midscale offset V ±1 % FSR
CMRR Common Mode Rejection Ratio V 55 DB
εG Gain Error V 0.3 % FSR
Dynamic Performance
SINAD Signal to Noise and Distortion Ratio
fIN = 5 MHz VI 55 59 dB
fIN = 10 MHz V 54 dB
SNR Signal to Noise Ratio (without harmonics)
fIN = 5 MHz VI 57 60 dB
fIN = 10 MHz V 56 dB
SFDR Spurious Free Dynamic Range
fIN = 5 MHz VI 60 65 dB
fIN = 10 MHz V 59 dB
DP Differential Phase V 0.2 degrees
DG Differential Gain V 0.5 %
PSRR Power Supply Rejection Ratio V 63 dB
Analog Input
VFSR Input Voltage Range (Differential) IV ±0.6 ±1 ±1.7 V
VCMI Common mode input voltage IV 1.2 1.65 1.9 V
CINA Input Capacitance (from each input to V 1.4 pF
ground)
Reference Voltages
VREFNO Negative Input Voltage IV 1.15 V
VREFPO Positive Input Voltage IV 2.15 V
VREFP-VREFN Reference input voltage range IV 0.6 1.0 1.7 V
VCM Common mode output voltage (Io=-1µA) VI 1.3 1.65 1.8 V
Digital Inputs
VIL Logic “0” voltage VI 20% VDD
VIH Logic “1” voltage VI 80% VDD
IIL Logic “0” current (VI=VSS) VI ±1 µA
IIH Logic “1” current (VI=VDD) VI ±1 µA
CIND Input Capacitance V 1.8 pF
Digital Outputs
VOL Logic “0” voltage (I = + 2 mA) VI 0.1 0.4 V
VOH Logic “1” voltage (I = - 2 mA) VI 85% VDD 95% VDD V
tH Output hold time IV 6 ns
tD Output delay time IV 4 8 12 ns
(table continued on next page)

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
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Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

Switching Performance
fS Conversion Rate VI 20 TBD MSPS
Pipeline Delay (see timing diagram) IV 7.5 Clocks
σAP Aperture jitter V 10 ps
tAP Aperture delay V 5 ns
Power Supply
VDD supply voltage IV 2.8 3.3 3.6 V
IDD supply current 1) VI 24 30 mA
IDD supply current (sleep mode, EXTREF "0") VI 6.6 mA
IDD supply current (sleep mode, EXTREF "1") VI 1.8 mA
VSS supply voltage GND
AVDD- analog power - digital power pins V -0.2 +0.2 V
DVDD1
DVDD1- digital power - output driver power V -0.2 +0.2 V
DVDD2
PD Power dissipation VI 79 100 mW
Table 3. Electrical specifications

1) Power down ("zero") power consumption available for IP core.

Test Levels

Test Level I: 100% production tested at +25°C

Test Level II: 100% production tested at +25°C and sample tested at specified
temperatures
Test Level III: Sample tested only
Test Level IV: Parameter is guaranteed by design and characterization testing
Test Level V: Parameter is typical value only
Test Level VI: 100% production tested at +25°C. Guaranteed by design and
characterization testing for industrial temterature range

ABSOLUTE MAXIMUM RATINGS

Supply voltages Temperatures
AVDD ...............................- 0.5V to +6V Operating Temperature….-55°C to +95°C
DVDD1 ..................- 0.5V to VDD + 0.5V Storage Temperature..- 65°C to +125°C
DVDD2 ..................- 0.5V to VDD + 0.5V

Input voltages
Analog In.......... - 0.5V to AVDD + 0.5V
Digital In..............- 0.5V to VDD + 0.5V
REFP ................. - 0.5V to AVDD + 0.5V
REFN................. - 0.5V to AVDD + 0.5V
CLOCK ...............- 0.5V to VDD + 0.5V

Note: Stress above one or more of the limiting values may cause permanent damage
to the device.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099
Revision: 3.3 Page 4 of 12 February 27th 2001
Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

PIN FUNCTIONS
Pin Name Description
INP INN Differential input signal pins. Common mode voltage: 1.65V
REFP REFN Reference pins. Bypass with 100nF capacitors close to the pins. See Application
Information below.
EXTREF Digital input: Reference select.
EXTREF=1: Internal reference powered down, use external reference
EXTREF=0: Internal reference is used
BIAS0, BIAS1 Digital inputs for max. sampling rate programming.
BIAS1=0, BIAS0=0: Sleep mode (power save)
BIAS1=0, BIAS0=1: Max. 5MHz sampling
BIAS1=1, BIAS0=0: Max. 20MHz sampling
BIAS1=1, BIAS0=1: Max. 30MHz sampling
CLOCK Clock input
CM Common mode voltage output.
BIT11 - BIT0 Digital outputs ( MSB to LSB)
BGAP Band gap reference input / output voltage, nominally 2.413V
QI, S Scan inputs. Connect to ground.
AVDD Analog power pins. Should be connected to VDD
DVDD1 Digital power pins. Should be connected to VDD
DVDD2 Power pins for output drivers. Should be connected to VDD
Table 4. Pin functions.
PIN ASSIGNMENT
CLOCK
DVDD1

DVDD1

DVDD2
REFN
REFP

AVDD

AVDD

AVDD

VSS

VSS

11 10 9 8 7 6 5 4 3 2 1

NC 12 44 DVDD2

EXTREF 13 43 BIT0 (LSB)

BGAP 14 42 BIT1

VSS 15 41 BIT2

BIAS0 16 40 BIT3

BIAS1 17 39 BIT4

CM 18 38 BIT5

VSS 19 37 BIT6
nAD1220
INP 20 36 BIT7

INN 21 44 PIN QFP 35 BIT8

VSS 22 34 BIT9

23 24 25 26 27 28 29 30 31 32 33
VSS

VSS

VSS

VSS

VSS

VSS

VSS

QI

BIT11

BIT10

Figure 2. Pin assignment

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
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Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

TIMING DIAGRAM

CLOCK

S S S S
A A A A
M N-1 M N M N+1 tAP M n+2 th td
P P P 2 P 6 8
L L L ns L ns ns
E E E E
ANALOG INPUT

Data Data Data

DATA
N-1 N N+1

Figure 3. Timing diagram

PACKAGE OUTLINE

All dimensions are in inches and

paranthetically in millimeters.

Figure 5. Package outline

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099
Revision: 3.3 Page 6 of 12 February 27th 2001
Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

DEFINITIONS
Data sheet status
Objective product specification This datasheet contains target specifications for product development.
Preliminary product This datasheet contains preliminary data; supplementary data may be
specification published from Nordic VLSI ASA later.
Product specification This datasheet contains final product specifications.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or at any other conditions above those given in the
Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may
affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Table 5. Definitions

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Nordic VLSI ASA customers using or selling these products for use in such
applications do so at their own risk and agree fully indemnify Nordic VLSI ASA for
any damages resulting from such improper use or sale.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099
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Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

APPLICATION INFORMATION

References
The nAD1220 has a differential analog input. The input range is determined by the
voltages VP and VN applied to reference pins REFP and REFN respectively, and is
equal to ±(VP-VN). Externally generated reference voltages connected to REFP and
REFN should be symmetric around 1.5V. The input range can be defined between
±0.6V and ±1.5V. Internal reference buffers exists – providing reference voltages at
pins REFP and REFN equal to +2.00V (VREFP) and +1.00V (VREFN). These can be
connected to REFP and REFN by connecting pin EXTREF to VSS. The references
should be bypassed as close to the converter pins as possible using 100nF capacitors
in parallel with smaller capacitors (e.g. 220pF) (to ground).

Series resistance from IP reference pins to pad window should be in the range 1 - 5
ohms.

Analog input
The input of the nAD1220 can be configured in various ways - dependent upon
whether a single ended or differential, AC- or DC-coupled input is wanted.

AC-coupled input is most conveniently implemented using a transformer with a center

tapped secondary winding. The center tap is connected to the CM-node, as shown in
Figure 1. In order to obtain low distortion, it is important that the selected transformer
does not exhibit core saturation at full-scale. Excellent results are obtained with the
Mini Circuits T1-6T or T1-1T. Proper termination of the input is important for input
signal purity. A small capacitor (typ. 68pF) across the inputs attenuates kickback-
noise from the sample and hold. A small capacitor (1nF) between CM and ground has
also been proven to be advantageous.

68pF
Mini Circuits ADC
T1-6T
Vin INP
51Ω
CM

INN

Figure 6. AC coupled input using transformer

If a DC-coupled single ended input is wanted, a solution based on operational

amplifiers - as shown in Figure 7, is usually preferred. The AD826 is suggested for
low distortion and video bandwidth. Lower cost operational amplifiers may be used if
the demands are less strict.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099
Revision: 3.3 Page 8 of 12 February 27th 2001
Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

51Ω

470Ω

AD826
Input 470Ω
offset ADC
51Ω
100Ω AD826 INP
Video
in
15pF

100Ω
INN

51Ω
51Ω
470Ω AD826

470Ω 470Ω

Figure 7. DC-coupled single ended to differential conversion (power supplies and

bypassing not shown)

Clock
The nAD1220 accepts a CMOS logic level clock at the CLK-node. The duty cycle of
the clock should be close to 50%. Consecutive pipeline stages in the ADC are clocked
in antiphase. With a 50% duty cycle, every stage has the same time for settling. If the
duty cycle deviates from 50%, every second stage has a shorter time for settling - thus
it operates less accurately, potentially causing degradation of SNR.

In order to preserve accuracy at high input frequency, it is important that the clock has
low jitter and steep edges. Rise/fall times should be kept shorter than 2ns whenever
possible. Overshoot should be avoided. Low jitter is especially important when
converting high frequency input signals. Jitter causes the noise floor to rise
proportionally to input signal frequency. Jitter may be caused by crosstalk on the PCB.
It is therefore recommended that the clock trace on the PCB is made as short as
possible.

Digital outputs
The digital output data appears in offset binary code at CMOS logic levels. Full-scale
negative input results in output code 000...0. Full-scale positive input results in output
code 111...1. Output data are available 7.5 clock cycles after the data are sampled. The
analog input is sampled one aperture delay (tAP) after the high to low clock transition.
Output data should be sampled on the low to high clock transition, as shown in the
timing diagram. Output data are invalid for the first 20 clock cycles after wake-up
from power down mode.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
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Revision: 3.3 Page 9 of 12 February 27th 2001
Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

PCB layout and decoupling

A well designed PCB is necessary to get good spectral purity from any high
performance ADC. A multilayer PCB with a solid ground plane is recommended for
optimum performance. If the system has a split analog and digital ground plane, it is
recommended that all ground pins on the ADC are connected to the analog ground
plane. It is our experience that this gives the best performance. The power supply pins
should be bypassed using 100nF surface mounted capacitors as close to the package
pins as possible. Analog and digital supply pins should be separately filtered. One
should make sure that the analog and digital supply voltages are equal.

Dynamic testing
Careful testing using high quality instrumentation is necessary to achieve accurate test
results on high speed A/D-converters. It is important that the clock source and signal
source has low jitter. A spectrally pure, low noise RF signal generator - such as the
HP8662A or HP 8644B is recommended for the test signal. Low pass filtering or band
pass filtering of the input signal is usually necessary to obtain the required spectral
purity (SFDR > 75dB). The clock signal can be obtained from either a crystal
oscillator or a low-jitter pulse generator. Alternatively, a low-jitter RF-generator can
be used as a clock source. At Nordic VLSI, the Marconi Instruments 2041A is used.
The sinewave clock must then be applied to an ultra high speed comparator (e.g.
AD9696) and a TTL to CMOS level shifter (e.g. 74LV04) before application to the
converter. The most consistent results are obtained if the clock signal is phase locked
to the input signal. Phase locking allows testing without windowing of output data. A
logic analyzer with deep memory - such as the HP16500-series, is recommended for
test data acquisition.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099
Revision: 3.3 Page 10 of 12 February 27th 2001
Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

YOUR NOTES

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099
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Product Specification
nAD1220 12-Bit 20MSPS Sampling ADC

DESIGN CENTER

Main office: Branch office:

Nordic VLSI ASA Nordic VLSI ASA
Vestre Rosten 81 Drammensveien 165
N-7075 TILLER P.O.Box 436 Skøyen, N-0212 OSLO
NORWAY NORWAY
Telephone: +47 72898900 Telephone: +47 22511050
Telefax: +47 72898989 Telefax: +47 22511099

E-mail: For further information regarding datasheets, please send mail to

datasheet@nvlsi.no

World Wide Web/Internet: Visit our site at http://www.nvlsi.no

Product specification. Revision Date: February 27th, 2001

All rights reserved ®. Reproduction in whole or in part is prohibited without the prior
written permission of the copyright holder. Company and product names referred to in
this datasheet belong to their respective copyright/trademark holders.

Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989
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